JP4870403B2 - Thin film transistor manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a thin film transistor. More specifically, in a thin film transistor having an oxide mainly composed of zinc oxide (ZnO) as a semiconductor thin film layer (active layer), the manufacturing process is greatly reduced, and the semiconductor thin film By purifying the interface between the layer and the interface-controlled gate insulating film formed on the semiconductor thin film layer, application to liquid crystal display devices and organic electroluminescence elements (OLEDs) formed on plastic substrates The present invention relates to a method for manufacturing a high-performance thin film transistor that has been made possible.

  It has long been known that oxides related to ZnO such as zinc oxide (ZnO) or magnesium zinc oxide (ZnMgO) exhibit excellent semiconductor (active layer) properties, and in recent years thin film transistors (hereinafter abbreviated as TFT), Research and development of thin-film semiconductors using oxides related to ZnO are becoming active with the aim of applying electronic devices such as light-emitting devices and transparent conductive films. In particular, TFTs using zinc oxide (ZnO) as a semiconductor thin film have higher electron mobility than amorphous silicon (a-Si: H) TFTs that are mainly used in conventional liquid crystal displays, and excellent TFT characteristics. Active development is underway because of the possibility of low-temperature processes.

  Currently, the mainstream of thin film transistors (TFTs) used in mobile displays is amorphous Si-TFT, and a glass substrate is used as the substrate. On the other hand, the plastic substrate is about 1/2 thick, about 1/3 the weight, and about 10 times the drop strength compared to the glass substrate, and it is superior to the glass in terms of thinness, light weight, and impact resistance. It is a substrate material suitable for mobile displays that are lightweight, tough and flexible.

  Glass substrates have a heat resistance temperature of about 400 to 600 ° C, whereas general plastic substrates have low heat resistance of 200 ° C or less, so if a high temperature process is included in the manufacturing process, Can not withstand, stretch and deteriorate. Therefore, for the application of the plastic substrate, it is indispensable to significantly lower the temperature of the entire manufacturing process of the thin film transistor.

The inventors of the present application have obtained the following knowledge regarding the temperature-programmed desorption characteristics of single crystal ZnO and ZnO thin films.
Zn desorption from ZnO is detected at a low level from around 100 ° C., and increases with increasing temperature. In particular, a sharp increase is observed from around 220 ° C. In addition, the desorption of H ₂ O, OH, O, which seems to be due to the adsorbed moisture on the zinc oxide surface, rises from around 100 ° C and is noticeable at 150-200 ° C. It has become clear that a temperature exceeding 200 ° C. is required for removal. When the gate insulating film is formed in a state where moisture is adsorbed on the surface of the zinc oxide thin film, the zinc oxide is reduced by the adsorbed OH group, which causes a leakage current.
In view of these characteristics, in order to realize a good thin film transistor at a heat resistant temperature of 200 ° C. or less of the plastic substrate, moisture adsorption to the zinc oxide thin film is suppressed, and a good interface between the semiconductor thin film and the insulating film is formed. Need to form.

  In view of the applicability of the plastic substrate as described above, prevention of low resistance of the semiconductor thin film layer, and suppression of moisture adsorption at the interface between the zinc oxide thin film and the insulating film, a thin film transistor (ZnO) using zinc oxide ZnO as the semiconductor thin film layer -TFT) on a plastic substrate requires a technique to prevent moisture and organic contamination from adsorbing to the zinc oxide thin film at the same time as lowering the manufacturing process.

  As the structure of the ZnO-TFT, a top gate type structure in which the gate electrode is located at the upper part of the semiconductor thin film and a bottom gate type structure in which the gate electrode is located at the lower part can be considered.

FIG. 6 shows an example of a conventional structure of a top gate type TFT (ZnO-TFT) using zinc oxide (ZnO) as a semiconductor thin film.
This top gate structure is configured by stacking a source / drain electrode 117, a semiconductor thin film 118, a gate insulating film 119, and a gate electrode 120 in this order on a substrate 116.
The gate insulating film 119 is often formed with a thickness of 200 to 500 nm by a chemical vapor deposition (CVD) method.

  On the other hand, Patent Document 1, Patent Document 2, and the like can be exemplified as those that disclose bottom gate type ZnO-TFTs.

  As shown in FIG. 7, a bottom gate type ZnO-TFT disclosed in Patent Document 1 includes a substrate 102, a gate electrode 103, a gate insulating film 104, a zinc oxide semiconductor thin film 105, a source electrode 106, a drain electrode 107, and a protective film 108. These components are stacked in this order.

  As shown in FIG. 8A, the bottom gate type ZnO-TFT disclosed in Patent Document 2 includes a substrate 109, a gate electrode 110, a gate insulating film 111, a source electrode 112, a drain electrode 113, and a zinc oxide semiconductor thin film 114. Each of these components is stacked in this order. Actually, in the final manufacturing process, as shown in FIG. 8B, the protective film 115 is formed by covering the zinc oxide semiconductor thin film 114.

  In the top gate type ZnO-TFT as shown above, a gate insulating film on zinc oxide is formed, and in the manufacturing method of the bottom gate type ZnO-TFT, a protective film on zinc oxide is usually formed at a temperature of 250 ° C. or more. It is common to be done.

  In the conventional method of forming a gate insulating film under such temperature conditions, a plastic substrate cannot be used for the reasons described above, and zinc oxide is decomposed and desorbed due to an increase in temperature. There is a problem of increased current.

In the conventional top gate TFT manufacturing method, the process of forming the semiconductor thin film and the gate insulating film is performed discontinuously. During this process, the surface of the semiconductor thin film is exposed to moisture, organic matter, alkali metals such as Na and K, boron, etc. Etc. are adsorbed, and there is a problem that a good interface cannot be formed between the gate insulating film and the semiconductor thin film stacked in a later step.
In order to solve such a problem, various cleaning methods are used for cleaning the interface in the silicon semiconductor. For example, wet cleaning using an acid such as RCA cleaning is used to remove metal impurities, ionic impurities, and particulate impurities, and wet cleaning using hydrofluoric acid (HF) is used to remove surface oxides to remove organic substances. It is conceivable to use dry cleaning such as UV or ozone treatment throughout the manufacturing process.

  Even in the manufacturing process of the conventional bottom gate type ZnO-TFT, the formation of the semiconductor thin film performed after the formation of the gate insulating film and the formation of the protective film performed thereafter are the same as the manufacturing process of the top gate type TFT described above. It is performed in a discontinuous process.

  Therefore, there is a possibility that impurities adhere to the surface of the semiconductor thin film before forming the gate insulating film before the semiconductor thin film and the protective film covering the surface of the semiconductor thin film, and it is considered that a cleaning process is necessary.

  As described above, it is considered that a cleaning process is required from the viewpoint of forming a good interface in any of the manufacturing processes of the top gate type structure and the bottom gate type structure.

  However, the ZnO semiconductor thin film has low acid resistance, and when wet cleaning using acid is performed in the same manner as the silicon semiconductor described above, the film disappears or the grain boundaries are selectively etched. It becomes difficult to form a good interface with the gate insulating film. Furthermore, when dry cleaning using UV or ozone is used, the removal efficiency of substances other than organic substances (for example, metals, ionic impurities, particulate impurities) becomes insufficient.

  Patent Document 3 listed below discloses that an interface treatment by UV is performed on an oxide semiconductor thin film in a manufacturing process of a top gate type TFT using an oxide semiconductor thin film containing zinc oxide as a main component. .

JP 2005-033172 A Japanese Patent Laid-Open No. 2004-349583 JP 2003-298062 A

  However, in the transistor manufacturing method disclosed in Patent Document 3, UV irradiation is intended to flatten the interface, and organic substances cannot be completely removed. It was not possible to provide a transistor with

  In top-gate and bottom-gate thin film transistors using an oxide semiconductor thin film containing zinc oxide (ZnO) as a main component, if the interface between the oxide semiconductor thin film and the gate insulating film is not good, an increase in leakage current or drain The deterioration of the current rising (subthreshold) characteristic becomes large, and a good TFT characteristic is not exhibited.

  An object of the present invention is to provide an interface between a gate insulating film and an oxide semiconductor thin film layer containing zinc oxide (ZnO) as a main component in a thin film transistor (TFT) using an oxide containing zinc oxide (ZnO) as a main component as a semiconductor. Can be formed cleanly and satisfactorily at a low temperature, and it is possible to use a plastic having excellent performance as a substrate and to produce a high-quality semiconductor thin film transistor with high TFT characteristics. It is to provide a method.

The invention according to claim 1 is a method of manufacturing a thin film transistor having a semiconductor thin film made of an oxide mainly composed of zinc oxide ZnO and a gate insulating film made of a silicon-based insulating film and in contact with the semiconductor thin film. The gate insulating film is formed in a continuous process in a vacuum, and the gate insulating film is formed by inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) or electron cyclotron resonance chemical vapor deposition (ECR- CVD) method, and the entire manufacturing process is performed under a temperature condition of 200 ° C. or less ,
The thin film transistor is a bottom-gate thin film transistor, and the gate insulating film, the semiconductor thin film, and the insulating film on the semiconductor thin film are formed in a continuous process in a vacuum, and then the semiconductor thin film and the insulating film are formed in the shape of the active layer of the thin film transistor. After the processing, the surface treatment is performed in a plasma atmosphere using an oxidizing gas with at least a part of the semiconductor thin film exposed, and a protective film is continuously formed in vacuum following the surface treatment. The present invention relates to a method for manufacturing a thin film transistor.

  The invention according to claim 2 relates to the method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor thin film layer is formed by a sputtering method.

The invention according to claim 3 relates to a method of manufacturing a thin film transistor according to claim 1 or 2 , wherein oxygen or nitrous oxide (N ₂ O) is used as the oxidizing gas.

The invention according to claim 4, in the case of using oxygen as the oxidizing gas, the He, Ar, Xe, among Kr, according to claim 3, characterized in that in combination with oxygen at least one kind of gas The present invention relates to a method for manufacturing a thin film transistor.

  According to the first aspect of the present invention, in a method of manufacturing a thin film transistor having a semiconductor thin film made of an oxide mainly composed of zinc oxide ZnO and a gate insulating film made of a silicon-based insulating film and in contact with the semiconductor thin film, the semiconductor thin film And the formation of the gate insulating film in a continuous process in a vacuum, and as a method for manufacturing the gate insulating film, an inductively coupled plasma chemical vapor deposition (ICP-CVD) method or an electron cyclotron resonance chemical vapor phase is used. By using the growth (ECR-CVD) method, while preventing moisture adsorption on the surface of the semiconductor thin film and interfacial contamination due to organic matter, high-quality silicon-based insulating films and zinc oxide and gate insulating films A good interface can be obtained. Further, decomposition or desorption of zinc or oxygen components from the zinc oxide thin film due to temperature rise can be suppressed. As a result, a plastic that is inferior in heat resistance as compared with glass can be used as a substrate, and a high-performance thin film transistor in which leakage current is suppressed can be obtained on a flexible substrate.

  According to the invention of claim 2, by forming a semiconductor thin film made of an oxide containing zinc oxide as a main component by a sputtering method, a large number of substrates can be easily formed at a low temperature. A crystalline semiconductor thin film can be formed, and a method for manufacturing a thin film transistor with high performance and mass productivity can be provided.

According to the invention of claim 1 , after forming the gate insulating film, the semiconductor thin film, and the insulating film on the semiconductor thin film in a continuous process in a vacuum, the semiconductor thin film and the insulating film are processed into the shape of the active layer of the thin film transistor. Thereafter, a surface treatment is performed in a plasma atmosphere using an oxidizing gas with at least a part of the semiconductor thin film exposed, and a protective film is continuously formed in vacuum following the surface treatment. That is, after forming an insulating film that is a protective film on the upper surface of the semiconductor thin film, surface treatment is performed in a plasma atmosphere using an oxidizing gas as a pre-process of the first overcoat insulating film that is a protective film on the side surface, By forming the protective film in vacuum in succession to this surface treatment, it is possible to provide a method for producing a high-performance thin film transistor that has a good interface and suppresses the occurrence of leakage current.

According to the invention of claim 3 , by using oxygen or nitrous oxide (N ₂ O) as the oxidizing gas, the cleaning process is performed while the semiconductor thin film layer is placed in an oxidizing atmosphere, and leakage current is reduced. It is possible to obtain a highly applicable thin film transistor in which generation is suppressed.

According to the invention of claim 4 , the amount of oxygen radicals generated can be increased by using at least one kind of gas of He, Ar, Xe, and Kr together with oxygen in an oxidizing gas atmosphere. It becomes possible, and the effect of removing organic contamination on the surface of zinc oxide is improved at a lower temperature. Moreover, the sputter effect on the zinc oxide surface by the added gas makes it possible to remove metals and ionic impurities that could not be removed only by the oxidizing gas, and more excellent interface cleanliness, suppressing the occurrence of leakage current, and A thin film transistor with high current driving capability can be obtained.

  The structure of the top-gate thin film transistor 100 obtained by the manufacturing method according to the present invention will be described below with reference to FIG.

  A top gate type thin film transistor 100 obtained by a manufacturing method according to an embodiment of the present invention includes a substrate 1, a source / drain electrode 2, a semiconductor thin film 3, a first gate insulating film 4, a contact portion 5, a gate insulating film 6, and a gate. It has the electrode 7 and the display electrode 8, and these each structure is laminated | stacked and formed.

As shown in FIG. 1A, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO ₂ and Al ₂ O ₃ as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulating material such as plastic or metal foil coated with an insulating material.

A source / drain electrode 2 is stacked on the substrate 1. The source / drain electrodes 2 are arranged with a space in a part of the upper surface of the substrate 1.
The source / drain electrode 2 is formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n ⁺ ZnO, a metal, or a metal at least partially covered with the conductive oxide.
The metal used for the source and drain electrodes 2 is a single layer or laminate of Ti, Cr, Ta, Mo, W, Al, Cu, Ni, or an alloy, Ti, Cr, Ta, Mo, W, Al An alloy containing at least one of Cu, Si, and Ni is used. Specific examples of this alloy include alloys such as TiW, TaW, MoW, MoSi, AlCu, AlSi, and NiSi.
As an example of forming the source / drain electrode 2 with a metal at least partially covered with the conductive oxide, a structure as shown in FIG. A structure directly formed by an object is also conceivable.
The thickness of the source / drain electrode 2 is not particularly limited. For example, the source / drain electrode 2 is formed to have a thickness of 30 nm to 150 nm. In the structure 1 (b), the conductive oxide film is thinner than the semiconductor thin film 3 (for example, about 40 nm), and in the structure formed directly, the metal or conductive oxide film is thinner than the semiconductor thin film 3 (for example, About 40 nm) is desirable.

The semiconductor thin film 3 is laminated on the substrate 1 and the source / drain electrodes 2.
The semiconductor thin film 3 is disposed so as to form a channel between the source and drain electrodes 2, and a current is supplied from the source electrode and emitted from the drain electrode.
The semiconductor thin film 3 is formed from an oxide semiconductor thin film mainly composed of zinc oxide (ZnO).
Although the thickness of this semiconductor thin film 3 is not specifically limited, For example, it forms in about 25-200 nm, Preferably, it forms in about 50-100 nm.
FIG. 1B is a diagram showing an example of a junction portion between the source / drain electrode 2 and the semiconductor thin film 3, in which a wiring in which titanium (Ti) is laminated on aluminum (Al) is formed, and indium tin is formed. A structure is shown in which a portion of this stack is covered with oxide (ITO).
In FIG. 1B, the source / drain electrode 2 is formed of an aluminum layer 18, a titanium layer 19, and an indium tin oxide (ITO) layer 20, and the semiconductor thin film 3 is indicated by reference numeral 21.
An aluminum layer 18 is provided on the substrate 17, and at least an upper surface thereof is covered with a titanium layer 19, and an indium tin oxide (ITO) layer 20 exists so as to cover a part of the titanium layer 19 and a part on the substrate. A part of the indium tin oxide (ITO) layer 20 is in contact with the semiconductor thin film 21.

The first gate insulating film 4 is disposed so as to cover the upper surface of the semiconductor thin film 3. The first gate insulating film 4 also serves as a protective film that protects from the resist stripping solution in the manufacturing process of the semiconductor thin film 3.
The first gate insulating film 4 is formed of a silicon-based insulating film such as SiNx, SiOx, or SiON.
The thickness of the first gate insulating film 4 is not particularly limited, but is formed, for example, to about 20-100 nm, preferably about 50 nm.
As will be described later, the first gate insulating film 4 is formed by an inductively coupled plasma chemical vapor deposition (ICP-CVD) method or electron cyclotron resonance, which is a film forming method using inductively coupled plasma (ICP). It is formed by an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method, which is a film forming method using plasma generation by (Electron Cyclotron Resonance: ECR), and is laminated on the semiconductor thin film layer 3.
This is because the inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) method or electron cyclotron resonance chemical vapor deposition (ECR-CVD) method, which can generate high-density plasma, is performed at 200 ° C or lower. This is because a high-quality insulating film can be formed at a low temperature.

The second gate insulating film 6 is laminated so as to reliably cover the surfaces of the source / drain electrode 2, the semiconductor thin film 3 and the first gate insulating film 4. Thus, the semiconductor thin film 3 can be reliably covered by laminating the second gate insulating film 6.
The second gate insulating film 6 is formed of a silicon-based compound such as SiNx, SiOx, or SiON.
The thickness of the second gate insulating film 6 is not particularly limited, but is formed, for example, to about 200 to 400 nm, and preferably about 300 nm.
As will be described later, the second gate insulating film 6 is formed by an inductively coupled plasma (ICP-CVD) method or an electron cyclotron resonance, which is a film forming method using inductively coupled plasma (ICP). It is formed by an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method which is a film forming method using plasma generation by (Electron Cyclotron Resonance: ECR).
The reason for adopting these identification methods is as described above.

  The contact portion 5 is formed of the same material as that of a gate electrode 7 described later in a contact hole portion formed by photolithography and etching in order to take out the source / drain electrode 2 to the outside.

The gate electrode 7 is formed on the gate insulating film 6. The gate electrode 7 serves to control the electron density in the semiconductor thin film 3 by a gate voltage applied to the thin film transistor.
The gate electrode 7 is made of a metal such as Cr, Ti, Ta, Mo, W, or an alloy of these metals, and has a thickness of, for example, 50 to 100 nm.

The display electrode 8 is formed in order to apply a voltage to the liquid crystal used for the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, it is formed of indium tin oxide (ITO), which is an oxide conductive thin film.
Although the thickness of the display electrode 8 is not specifically limited, For example, it forms in about 50-100 nm.

  Next, a method for manufacturing a top gate type thin film transistor (TFT) according to an embodiment of the present invention will be described with reference to FIG.

  The manufacturing method of a top gate type thin film transistor according to an embodiment of the present invention includes three main steps. The first step is a step of forming a first gate insulating film 4 on a zinc oxide (ZnO) semiconductor thin film 3 provided so as to cover the source / drain electrodes 2 on the substrate 1. The second step is a step of forming the gate insulating film 6 on the first gate insulating film 4 by patterning the first gate insulating film with a resist and then processing the shape of the semiconductor thin film 3 by etching. is there. The third step is a step of forming the gate electrode 7, the contact portion 5 and the display electrode 8 in this order on the gate insulating film.

Hereinafter, a method for manufacturing a top gate type thin film transistor (TFT) according to the present invention will be described in detail.
As shown in FIG. 2 (1), a metal such as Ti, Cr, etc. with a thickness of, for example, 100 nm is formed on the entire surface of a glass substrate 1 or a plastic resin (for example, polycarbonate (PC) or polyethylene naphthalate (PEN) substrate) by magnetron sputtering. The source / drain electrodes 2 are formed by photolithography. Although not shown, a transparent conductive film such as n ⁺ ZnO or indium tin oxide (ITO) may be laminated on the source / drain metal film.

As shown in FIG. 2B, a zinc oxide (ZnO) semiconductor thin film 3 is formed on the entire surface of the glass substrate 1 and the source / drain electrodes 2 by a sputtering method with a film thickness of about 50 to 100 nm, for example. After the semiconductor thin film 3 is formed, the substrate is transferred to an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus in a vacuum.
At this time, in order to clean the surface of the semiconductor thin film 3, the substrate is placed in an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus in a vacuum. After the transfer, the semiconductor thin film 3 is preferably surface-treated in a plasma atmosphere using an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O). In particular, when oxygen is used as the oxidizing gas, the amount of oxygen radicals generated is increased and adsorbed on the surface of the semiconductor thin film by using a plasma in which a rare gas such as Ar, Xe, He, or Kr is added to oxygen. The cleaning efficiency for organic components and moisture is increased, and at the same time, metal impurities on the surface of the semiconductor thin film can be removed by the sputtering effect of the additive gas, which is more preferable. Furthermore, by performing the process of cleaning the surface of the semiconductor thin film in a state where the oxygen radical concentration is high, oxygen desorption from the semiconductor thin film can be prevented, and leakage current due to defects due to oxygen deficiency can be reduced.

After forming the semiconductor thin film 3, preferably further cleaning the surface, the first gate insulating film 4 is formed of a silicon-based insulating film such as SiNx, SiOx, or SiON as shown in FIG. .
The first gate insulating film 4 is formed by using an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus with SiH ₄ + N ₂ O gas. Is used to form SiOx with a thickness of about 20 to 50 nm.
An ECR plasma source used in an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus can generate a high-density plasma under a low pressure (high vacuum). Moreover, the ion energy in plasma is small, ion damage of the semiconductor thin film during the formation of the insulating film can be reduced, and a good interface between zinc oxide and the insulating film can be formed.
The same effect can be obtained when an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus is used.
For the above reason, the first gate insulating film 4 is formed by an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus. It is possible to form a high-quality insulating film under the condition of ℃ or lower and to form an interface between zinc oxide and the insulating film.
When SiOx is used as the first gate insulating film 4, it is preferable that plasma treatment is subsequently performed in a mixed atmosphere of a rare gas such as Ar and an oxidizing gas after the SiOx film is formed. This is because the plasma treatment promotes the oxidation of the SiOx film and further improves the withstand voltage.

2 (4), a photoresist is coated on the first gate insulating film 4, and the first gate insulating film 4 is made of CF ₄ + O ₂ or the like using the patterned photoresist 4a as a mask. Dry etching is performed using a gas, and then wet etching is performed on the semiconductor thin film 3 with a 0.2% HNO ₃ solution.

  FIG. 2 (5) shows a cross section in which the photoresist 4a is removed after wet etching of the semiconductor thin film 3, and the first gate insulating film 4 (SiNx) having the same shape as the semiconductor thin film 3 and having a thickness of about 20 to 50 nm. A TFT active layer region is formed. The first gate insulating film 4 having a thickness of about 20 to 50 nm simultaneously plays a role of protecting the semiconductor thin film 3 when patterning the active region in addition to forming an interface with the semiconductor thin film 3. That is, the resist stripping solution used when stripping the photoresist 4a after patterning of the active layer roughens the surface of the semiconductor thin film 3 by etching, but the first gate insulating film 4 is against the resist stripping solution on the surface of the semiconductor thin film 3. By serving as a protective film, surface roughness due to etching can be prevented.

After the patterning of the TFT active layer region, as shown in FIG. 2 (6), the substrate 1, the source / drain electrode 2, the ZnO thin film 3 so as to cover the first gate insulating film 4 and the source / drain electrode 2. The second gate insulating film 6 is formed on the entire surface of the first gate insulating film 4. The second gate insulating film 6 is composed of a silicon-based insulating film, and is preferably formed of SiNx having a high dielectric constant and also having a role of protecting the semiconductor thin film 3 from external moisture and the like.
The second gate insulating film 6 is formed by an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus. It is formed with a thickness of ˜400 nm.
Further, when SiOx is used as the second gate insulating film 6, it is preferable that plasma treatment is subsequently performed with a mixed gas of rare gas such as Ar and oxygen after the formation of SiOx. This is because the plasma treatment promotes the oxidation of the SiOx film and further improves the withstand voltage.
Thereafter, contact holes are opened on the source / drain electrodes by photolithography and etching.

  Finally, as shown in FIG. 2 (7), a gate electrode 7 made of a metal or alloy such as Cr, Ti, Ta, Mo, W is formed on the gate insulating film 6, and then the same material as the gate electrode 7 is formed. Then, a contact portion 5 which is an electrode for taking out the source / drain electrode 2 to the outside through the contact hole is formed. Thereafter, a display electrode 8 made of indium tin oxide (ITO) or the like is formed to complete a top gate type thin film transistor.

  In one embodiment of the method for manufacturing a top gate type thin film transistor according to the present invention, the entire manufacturing process is performed at 200 ° C. or lower. The reason why the temperature is set to 200 ° C. or lower is that most plastics (for example, polycarbonate (PC) or polyethylene naphthalate (PEN)) that are preferably used for substrates cause expansion and contraction and modification at temperatures exceeding 200 ° C. .

  The structure of the bottom-gate thin film transistor 101 obtained by the manufacturing method according to one embodiment of the present invention will be described below with reference to FIG.

  A bottom gate type thin film transistor 101 obtained by a manufacturing method according to an embodiment of the present invention includes a substrate 9, a gate electrode 10, a gate insulating film 11, a semiconductor thin film 12, an insulating film 13, a first overcoat insulating film 14, a source A drain electrode 15 and a second overcoat insulating film 16 are provided, and as shown in FIG.

The thin film transistor 101 is formed on the substrate 9 as shown in FIG.
The substrate 9 is provided as an insulator and is made of alkali-free glass or plastic resin (for example, polycarbonate (PC) or polyethylene naphthalate (PEN) substrate) containing SiO ₂ and Al ₂ O ₃ as components.

A gate electrode 10 is formed on the substrate 9. The gate electrode 10 is formed on a part of the substrate 9.
The gate electrode 10 is made of a metal film such as Cr, Ti, Al, Ta, W or an alloy thereof, and has a thickness of, for example, about 100 nm.

The gate insulating film 11 is laminated on the entire surface of the substrate 9 so as to cover the gate electrode 10.
As the gate insulating film 11, a silicon-based insulating film such as SiNx, SiOx, or SiON can be used, but SiNx is often used.
The gate insulating film 11 is formed to have a thickness of, for example, about 200 to 400 nm, preferably about 300 nm.

The semiconductor thin film 12 is formed so as to cover a part of the gate insulating film 11 including the upper part of the gate electrode 10.
The semiconductor thin film 12 is formed using zinc oxide (ZnO) as a component.
Although the thickness of this semiconductor thin film 12 is not specifically limited, For example, it forms in about 50-100 nm, Preferably, it is formed in about 60 nm.

The insulating film 13 is provided so as to cover the entire surface of the semiconductor thin film 12 in order to protect the semiconductor thin film 12 made of zinc oxide (ZnO) from damage and reductive desorption. It also plays a role as a protective film that protects against water.
As this insulating film 13, a silicon-based insulating film such as SiNx, SiOx, or SiON can be used. The thickness of this insulating film 13 is, for example, about 30 to 100 nm, preferably about 50 nm. The

The first overcoat insulating film 14 is provided for the purpose of protecting the thin film transistor 101 and is laminated so as to cover the entire surface of the insulating film 13 and the side surface of the semiconductor thin film 12.
By providing the first overcoat insulating film 14, the side surface of the zinc oxide semiconductor thin film 12 that is not covered with the insulating film 13 can be reliably covered.
As the first overcoat insulating film 14, a silicon insulating film such as SiNx, SiOx, or SiON can be used.
The thickness of the first overcoat insulating film 14 is, for example, about 150 to 300 nm, preferably about 200 nm.

The source / drain electrodes 15 are formed so as to be in contact with the semiconductor thin film 12 through contact hole portions opened in the insulating film 13 and the first overcoat insulating film 14.
The source / drain electrodes 15 are formed of a metal material such as Ti, Cr, Al, Mo, W, Ta, alloys thereof, or conductive oxide materials such as indium tin oxide (ITO) and n ⁺ ZnO. Is done. Moreover, the thickness of these electrodes 13 is not particularly limited, but is formed to about 50 to 300 nm, for example.

The second overcoat insulating film 16 is provided for the purpose of protecting the thin film transistor 101 and is laminated so as to cover the entire surface of the thin film transistor.
By providing the second overcoat insulating film 16, the entire thin film transistor 101 can be more reliably protected.
The second overcoat insulating film 16 is not particularly limited, but it is desirable to use, for example, a SiNx film having excellent protection against impurities.
The thickness of the second overcoat insulating film 16 is not particularly limited, but is formed, for example, to about 150 to 500 nm, preferably 300 nm.

  Next, a method for manufacturing a bottom gate type thin film transistor (TFT) according to the first embodiment of the present invention will be described with reference to FIG.

  A manufacturing method of a bottom gate type thin film transistor according to an embodiment of the present invention includes the following steps. The first step is a step of forming the gate electrode 10 on a part of the substrate 9. The second step is a step of covering the gate electrode 10 and forming the gate insulating film 11 on the entire surface of the substrate 9. The third step is a step of forming the semiconductor thin film 12 on the entire surface of the gate insulating film 11. The fourth step is a step of covering the entire surface of the semiconductor thin film 12 and forming the insulating film 13. The fifth step is a step of processing the shapes of the insulating film 13 and the semiconductor thin film 12. The sixth step is a step of forming the first overcoat insulating film 14 by covering the entire surface of the semiconductor thin film 12, the insulating film 13, and the gate insulating film 11. The seventh step is a step of forming contact holes for contacting the source / drain electrodes 15 and the semiconductor thin film 12 in the insulating film 13 and the first overcoat insulating film 14. The eighth step is a step of forming the source / drain electrode 15 through the contact hole portion formed in the seventh step. The ninth step is a step of forming the second overcoat insulating film 16 that covers the entire surface of the thin film transistor.

  Hereinafter, a method of manufacturing a bottom gate type thin film transistor (TFT) according to an embodiment of the present invention will be described in detail.

  As shown in FIG. 4 (1), Cr, Ti, Al, etc. are formed on the entire surface of the substrate 9 made of resin such as glass or plastic (for example, polycarbonate (PC) or polyethylene naphthalate (PEN) substrate) by magnetron sputtering or the like. A metal film such as Ta, W, or an alloy thereof is formed with a thickness of, for example, 100 nm, and the gate electrode 10 is formed by photolithography and etching.

As shown in FIG. 4B, a gate insulating film 11 is formed on the entire surface of the substrate 9 so as to cover the gate electrode 10. The gate insulating film 11 is formed using a silicon-based insulating film such as SiNx, SiOx, or SiON. The gate insulating film 11 is preferably SiNx having a high dielectric constant.
This gate insulating film 11 is formed by using an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) apparatus with SiH ₄ + N ₂ gas or SiH ₄ + NH. ₃ to form.
The ECR plasma source used in electron cyclotron resonance chemical vapor deposition (ECR-CVD) equipment is capable of generating high-density plasma under low pressure (high vacuum) and under 200 ° C or less. It is possible to form a high-quality insulating film. The same effect can be obtained when an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatus is used.
After the gate insulating film 11 is formed, the substrate surface is preferably surface-treated in a plasma atmosphere using an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O). In particular, when oxygen is used as the oxidizing gas, the amount of oxygen radicals generated is increased and adsorbed on the surface of the semiconductor thin film by using a plasma in which a rare gas such as Ar, Xe, He, or Kr is added to oxygen. The cleaning efficiency for organic components and moisture is increased, and at the same time, metal impurities on the surface of the semiconductor thin film can be removed by the sputtering effect of the additive gas, which is more preferable.

After forming the gate insulating film 11, preferably further cleaning the surface, the substrate is transferred to a sputtering apparatus in a vacuum, and as shown in FIG. 4 (3), zinc oxide is deposited on the entire surface of the gate insulating film 11. A semiconductor thin film 12 made of (ZnO) is formed to a thickness of about 50 to 100 nm.
In forming the semiconductor thin film 12, a sputtering method is preferably used. This is because a polycrystalline zinc oxide (ZnO) thin film can be formed over a large area by using a sputtering method without heating the substrate.

After the formation of the semiconductor thin film 12, as shown in FIG. 4 (4), an insulating film 13 covering the entire surface of the semiconductor thin film is formed. The insulating film 13 is formed of a silicon-based insulating film such as SiOx, SiNx, or SiON.
The insulating film 13 can be formed using various CVD methods.
In forming the insulating film 13, it is preferable to use an inductively coupled plasma chemical vapor deposition (ICP-CVD) method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method. The reason for this is that plasma processing and film formation of the insulating film 13 are made continuous by using inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) or electron cyclotron resonance chemical vapor deposition (ECR-CVD). This is because a good film can be formed at a low temperature.
The thickness of the insulating film 13 is, for example, about 30 to 70 nm, preferably about 50 nm.
Before the insulating film 13 is formed, the semiconductor thin film 12 is preferably surface-treated in a plasma atmosphere using an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O). In particular, when oxygen is used as the oxidizing gas, the amount of oxygen radicals generated is increased and adsorbed on the surface of the semiconductor thin film by using a plasma in which a rare gas such as Ar, Xe, He, or Kr is added to oxygen. The cleaning efficiency for organic components and moisture is increased, and at the same time, metal impurities on the surface of the semiconductor thin film can be removed by the sputtering effect of the additive gas, which is more preferable. Furthermore, by performing the process of cleaning the surface of the semiconductor thin film in a state where the oxygen radical concentration is high, oxygen desorption from the semiconductor thin film can be prevented, and leakage current due to defects due to oxygen deficiency can be reduced.

  After the formation of the insulating film 13, the insulating film 13 and the semiconductor thin film 12 are processed into a channel shape.

A photoresist is coated on the upper surface of the insulating film 13, the insulating film 13 is etched using the patterned photoresist as a mask, and then the semiconductor thin film 12 is wet etched using the patterned insulating film 13 as a mask.
The series of patterning for the insulating film 13 and the semiconductor thin film 12 is not particularly limited, and various etching methods can be used. For example, the insulating film 13 is dry-etched using a gas such as CF ₄ + O ₂ , Next, a method of performing wet etching on the semiconductor thin film 12 with a 0.2% HNO ₃ solution using the patterned insulating film 13 as a mask can be exemplified.

After the shape processing is performed on the semiconductor thin film 12 and the insulating film 13, the first overcoat insulation is performed so as to cover the entire surface of the insulating film 13, the semiconductor thin film 12 and the gate insulating film 11, as shown in FIG. A film 14 is formed.
The first overcoat insulating film 14 is not particularly limited. For example, the first overcoat insulating film 14 is made of a silicon-based insulating film such as SiNx, and more specifically, inductively coupled plasma chemical vapor deposition (ICP) using a gas such as SiH ₄ + NH _3. -SiNx is formed to a thickness of 200 nm using a CVD method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method. The components of the gas used for forming the inductive coupling method plasma chemical vapor deposition (ICP-CVD) method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method SiNx using tetra instead of silane SiH ₄ The same process can be performed using methylsilane (CH ₃ ) ₄ Si.
For the same reason as described above, as a process before forming the first overcoat insulating film, an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) with at least a part of the semiconductor thin film exposed. It is preferable to perform the surface treatment in a state where at least the side surface of the semiconductor thin film 12 is exposed in a plasma atmosphere using the above. By this surface treatment, a good interface can be formed not only on the upper surface of the semiconductor thin film 12 but also on the side surface.
Furthermore, by performing the process of cleaning the surface of the semiconductor thin film in a state where the oxygen radical concentration is high, oxygen desorption from the semiconductor thin film can be prevented, and leakage current due to defects due to oxygen deficiency can be reduced.

After the formation of the first overcoat insulating film 14, a contact hole portion is formed as a contact portion between a source / drain electrode 15 to be described later and the semiconductor thin film 12.
The contact hole is formed by photolithography and etching up to a portion that reaches the surface of the semiconductor thin film 12 through the first overcoat insulating film 14 and the insulating film 13.
The two contact hole portions are filled with a source electrode and a drain electrode constituting a source / drain electrode 15 described later.

After the contact hole portion is formed, the source / drain electrode 15 is formed.
As the source / drain electrodes 15, for example, Ti, Cr, Al, Mo, W, Ta, alloys thereof, or conductive oxide materials such as indium tin oxide (ITO) and n ⁺ ZnO are formed by magnetron sputtering. It is formed with a thickness of 100 nm.
The source / drain electrodes 15 are formed with a space between the two contact hole portions.

Finally, a second overcoat insulating film 16 is formed on the thin film transistor.
The second overcoat insulating film 16 is not particularly limited. For example, a SiNx film having excellent protection against impurities can be used. Specifically, inductively coupled plasma chemistry using a gas such as SiH ₄ + NH ₃ can be used. SiNx is formed to a thickness of 200 nm by using vapor deposition (ICP-CVD) or electron cyclotron resonance chemical vapor deposition (ECR-CVD). The components of the gas used for forming the inductive coupling method plasma chemical vapor deposition (ICP-CVD) method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method using a SiNx, tetra instead of silane SiH ₄ The same process can be performed using methylsilane (CH ₃ ) ₄ Si.

In the present invention, the step of forming the gate insulating film 11 and the step of forming the semiconductor thin film 12 are continuously performed in a vacuum.
This is because a good interface with few impurities can be formed between both layers by continuously performing the gate insulating film 11 and the semiconductor thin film 12 in a vacuum.
Further, in addition to the above-described step of forming the gate insulating film 11 and the step of forming the semiconductor thin film 12, it is preferable to continuously perform the step of forming the insulating film 13 in succession.
This is because a good interface with less impurities can be formed between the semiconductor thin film 12 and the insulating film 13, and the generation of fixed charges on the back channel side of the thin film transistor is reduced, and at the same time, zinc oxide (ZnO) from the semiconductor thin film 12 is reduced. This is because the occurrence of leakage current can be suppressed by preventing reductive desorption of the component.
When the zinc oxide semiconductor thin film 12 is subjected to plasma treatment, it is preferable that at least the plasma treatment and the formation process of the insulating film 13 are continuously performed in a vacuum.
This is because by forming a clean interface between the semiconductor thin film 12 and the insulating film 13, the generation of fixed charges on the back channel side of the thin film transistor can be reduced and good TFT characteristics can be obtained.

  In one embodiment of the manufacturing method of the bottom gate type thin film transistor according to the present invention, the entire manufacturing process is performed at 200 ° C. or lower. The reason why the temperature is set to 200 ° C. or lower is that most plastics preferably used for the substrate are stretched or denatured when the temperature exceeds 200 ° C.

  A bottom gate type thin film transistor (TFT) according to an embodiment of the present invention is completed through the series of steps as described above.

Test example

  Hereinafter, the effects of the present invention will be made clearer by comparing the characteristics of the transistor test example obtained by the manufacturing method according to the present invention and the characteristics of the comparative example.

(Test example)
A transistor (see FIG. 1) based on the manufacturing method according to the present invention was prepared by the following method (see FIG. 2).
First, a source / drain electrode 2 made of indium tin oxide (ITO) was formed to a thickness of 40 nm on a substrate 1 made of alkali-free glass mainly composed of SiO ₂ and Al ₂ O ₃ .
A zinc oxide (ZnO) semiconductor thin film having a thickness of 50 nm was formed on the entire surface of the substrate 1 and the source / drain electrodes 2 as a semiconductor thin film 3 by RF magnetron sputtering without heating the substrate.
Thereafter, the substrate on which zinc oxide was formed was transferred to an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) apparatus for forming an interface control type insulating film in vacuum.
After transporting the substrate to the ICP-CVD apparatus, the semiconductor thin film 3 was subjected to a surface treatment using a plasma containing oxygen (O ₂ ) and Ar. Thereby, a zinc oxide semiconductor film having a cleaned surface was obtained. After performing the plasma treatment, a SiO ₂ film to be the first gate insulating film 4 was continuously formed in a vacuum. The SiO ₂ film was formed by using an inductively coupled plasma chemical vapor deposition (ICP-CVD) method using SiH ₄ + N ₂ O gas without heating the substrate. The film thickness was set to 50 nm. Inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) equipment can generate high-density plasma, can form high-quality insulating films at low temperatures, and at the same time has low ion energy in the plasma and damages the zinc oxide semiconductor. And an excellent interface between zinc oxide and the gate insulating film can be formed.

Further, a photoresist was coated on the first gate insulating film 4, and the first gate insulating film 4 was dry-etched using CF ₄ + O ₂ gas using the patterned photoresist 4 a as a mask.
Next, wet etching was performed on the ZnO thin film with a 0.2% HNO ₃ solution. The photoresist is removed, and the entire surface of the substrate 1, the source / drain electrode 2, the ZnO semiconductor thin film 3, and the first gate insulating film 4 is covered so as to cover the first gate insulating film 4 and the source / drain electrode 2. A second gate insulating film 6 made of SiNx was formed to a thickness of 300 nm.
The second gate insulating film 6 was formed by inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) using SiH ₄ + NH ₃ + N ₂ gas and without heating the substrate. .

Further, contact holes were opened on the source / drain electrodes 2 by dry etching using photolithography and CF ₄ + O ₂ gas.
Next, a gate electrode 7 made of Cr is formed on the gate insulating film 6 with a thickness of 100 nm. Simultaneously with the formation of the gate electrode, the same material as the gate electrode 7 is used to form the contact portion 5 which is an electrode for taking out the source / drain electrode to the outside through the contact hole, and then from indium tin oxide (ITO) A display electrode 8 having a thickness of 100 nm was formed on a part of the display electrode 8 to form a transistor.

  All the above steps were performed at 200 ° C. or lower. Zinc oxide and insulating films are all formed without heating the substrate, and the maximum temperature is 150 ° C., which is the heat treatment temperature used for curing the photoresist in the photolithography process.

(Comparative example)
As a comparative example, in the above-described method, the zinc oxide semiconductor thin film was laminated in the same manner as in the test example, and then the zinc oxide semiconductor thin film layer was directly coated with a photoresist, and the zinc oxide semiconductor was 0.2% HNO ₃ solution. Wet etching was performed on the thin film. The photoresist was removed, and a second gate insulating film, a gate electrode portion, and a display electrode portion were stacked in the same manner as in the example to form a transistor.

(Transfer characteristics evaluation test)
Using the transistors of the test example and the comparative example, the magnitude of the drain current accompanying the change in the gate voltage was measured to evaluate the transfer characteristics.
The result is shown in FIG.

As is apparent from FIG. 5, the rising characteristics (Vg> 3 V) of the transistors in the test example are superior to the rising characteristics in the comparative example, and the drain current value at the gate voltage Vgs = 10 V is in the comparative example. Compared to two orders of magnitude improvement.
This is considered to be because the first gate insulating film and the second gate insulating film were formed continuously in vacuum in the transistor of the test example, so that adhesion of impurities was prevented and a good interface was formed. It is done.

On the other hand, regarding the off-state current (Vgs <0), the off-state current in the transistor of the test example was reduced to half or less than the off-state current in the comparative example.
The off-current improvement effect is the same as the above-mentioned improvement of the rise characteristic, because the first gate insulating film and the second gate insulating film are continuously formed in vacuum, so that the adhesion of impurities is prevented and the generation of leakage current is suppressed. This is thought to be due to this.

  As described above, a thin film transistor using zinc oxide obtained by the production method according to the present invention for a semiconductor layer has excellent performance and can be used as a driving element for a liquid crystal display device or the like.

  As described above, by using the present invention, it is possible to obtain a good gate insulating film-ZnO interface under a low temperature condition, and to form a high-performance thin film transistor on a flexible substrate such as a plastic. is there. Therefore, a flexible and lightweight display can be realized by using the TFT of the present invention as a driving element for a liquid crystal display or an organic EL display.

(A) is sectional drawing which shows one form of the top gate type thin-film transistor (TFT) obtained by the manufacturing method concerning this invention, (b) is the source-drain electrode in one Embodiment of the thin-film transistor (TFT) in this invention It is sectional drawing which showed an example of the junction part of a semiconductor thin film. It is sectional drawing which shows one form of the manufacturing method of the top gate type thin-film transistor (TFT) based on this invention. It is sectional drawing which shows one form of the bottom gate type thin-film transistor (TFT) obtained by the manufacturing method which concerns on this invention. It is sectional drawing which shows one form of the manufacturing method of the bottom gate type thin-film transistor (TFT) based on this invention. It is a figure which shows the transfer characteristic of the transistor of a test example and a comparative example. It is sectional drawing which shows the thin-film transistor (TFT) with the conventional top gate structure. It is sectional drawing which shows an example of the zinc oxide thin-film transistor (ZnO-TFT) with the conventional bottom gate structure. (A) is sectional drawing which shows the other example of the zinc oxide thin-film transistor (ZnO-TFT) with the conventional bottom gate structure, (b) is a cross section which shows the last process of manufacture of the ZnO-TFT of this other example FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Semiconductor thin film 4 First gate insulating film 4a Photoresist 5 Contact portion 6 Gate insulating film 7 Gate electrode 8 Display electrode 9 Substrate 10 Gate electrode 11 Gate insulating film 12 Semiconductor thin film 13 Insulating film 14 First Overcoat insulating film 15 Source / drain electrode 16 Second overcoat insulating film 17 Substrate 18 Aluminum layer 19 Titanium layer 20 Indium tin oxide (ITO) layer 21 Semiconductor thin film 100 Top gate thin film transistor 101 Bottom gate thin film transistor

Claims (4)

In a method of manufacturing a thin film transistor having a semiconductor thin film made of an oxide mainly composed of zinc oxide ZnO and a gate insulating film made of a silicon-based insulating film and in contact with the semiconductor thin film, the formation of the semiconductor thin film and the formation of the gate insulating film are performed. The gate insulating film is formed by an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method. The manufacturing process is performed under a temperature condition of 200 ° C. or lower ,
The thin film transistor is a bottom-gate thin film transistor, and the gate insulating film, the semiconductor thin film, and the insulating film on the semiconductor thin film are formed in a continuous process in a vacuum, and then the semiconductor thin film and the insulating film are formed in the shape of the active layer of the thin film transistor. After the processing, the surface treatment is performed in a plasma atmosphere using an oxidizing gas with at least a part of the semiconductor thin film exposed, and a protective film is continuously formed in vacuum following the surface treatment. A method for producing a thin film transistor, comprising:   2. The method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor thin film layer is formed by a sputtering method. Thin film transistor process according to claim 1 or 2, characterized by using oxygen or nitrous oxide (N 2 _O) as the oxidizing gas. 4. The method of manufacturing a thin film transistor according to claim 3 , wherein when oxygen is used as the oxidizing gas, at least one of He, Ar, Xe, and Kr is used in combination with oxygen.

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