JP4869911B2 - Logic BIST circuit and modulo circuit - Google Patents

Description

  The present invention relates to a BIST (built-in self test) circuit incorporated in a semiconductor integrated circuit device, and in particular, a logic BIST circuit for checking a functional circuit including an arithmetic unit and a modulo circuit used therein. About.

  With the high integration of LSI (large-scale integrated circuit), the importance of design for testability is increasing. BIST is known as one of testability design. Here, the BIST is a combination of a built-in test and a self-test, and generates a test pattern and determines an output inside the LSI. The BIST circuit incorporates a test sequence generation mechanism inside the circuit.

  Various prior art documents relating to design for testability are known. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2001-297598) discloses a “semiconductor integrated circuit device and a self-test method for a semiconductor integrated circuit device” that includes a programmable memory BIST without newly incorporating a BIST instruction memory. Is disclosed. In Patent Document 1, a scan path register in which flip-flops in an integrated circuit are connected in series is used as a BIST instruction memory, and a flip-flop is selected by an address command signal from an address decoder to read program data for BIST execution instructions. Yes. Then, a test pattern is generated based on the read program data, and the data read after the test target memory writes the test pattern data and the expected value pattern data corresponding to the test pattern are obtained. The memory BIST is performed by comparison.

  More specifically, Patent Document 1 discloses a semiconductor integrated circuit device incorporating a programmable memory BIST. The semiconductor integrated circuit device includes a system logic including a combinational circuit and a sequential circuit, a BIST control circuit, an address decoder, a test pattern generator, first and second multiplexers, and first and second target circuits. A test memory and a test result analyzer; A plurality of flip-flops constituting the sequential circuit are connected in series like a shift register to form a scan path register (BIST instruction memory). The BIST control circuit supplies an address decoder control signal to the address decoder. The address decoder applies an address command signal to the BIST instruction memory, and selectively reads out program data sequentially from the BIST instruction memory. The test pattern generator sequentially generates test pattern data corresponding to the program data in accordance with a control signal output from the BIST control circuit. The test pattern generator provides test pattern data to the test result analyzer. The first and second multiplexers switch between test pattern data generated from the test pattern generator and output data from the system logic, and select input data to the first and second test target memories. Data read from the first and second memory under test is output to the system logic via the data bus during normal system operation, and taken into the test analyzer during BIST operation. The test result analyzer compares the fetched memory output data with expected value pattern data corresponding to the test pattern data, and outputs a test analysis result (comparison result).

Patent Document 2 (Japanese Patent Laid-Open No. 63-145547) discloses a modulo W circuit used for checking an arithmetic circuit or the like. The modulo W circuit disclosed in Patent Document 2 is a modulo W circuit having w-bit (w ≧ 2) input and w-bit output, and 2 ^w binary ^values that can be expressed by w bits. Among the values, a code having all bits “1” is defined as an error code indicating that a failure has been detected, and the remaining W except for all bits “1” (= 2 ^w −1) is modulo W. When a failure occurs or a failure is detected and an error code is generated, the error code is propagated. Then, the modulo W circuit includes n-value w-bit data A ₁ = [a ₁₁ , a ₁₂ ,..., A _1w ], A ₂ = [a ₂₁ , a ₂₂ ,..., A _2w ] _,. When one or more of the inputs A _n = [a _n1 , a _n2 ,..., A _nw ] indicate the error code, w-bit data C = [c ₁ , c ₂ , .., C _n ], the error code is output.

  Specifically, Patent Document 2 discloses a case where W = 3, that is, a modulo-3 circuit as an example. Then, the arithmetic unit using the modulo 3 circuit inputs the first and second binary data and the first and second modulo 3 expected values, and receives the first binary data and the second binary data. An operation result with binary data and a modulo 3 value of the operation result are output. The arithmetic device using the modulo 3 circuit includes a modulo 3 circuit, which will be described later, in addition to a normal arithmetic device composed of first and second input registers, an arithmetic circuit, and an arithmetic result output register. The modulo 3 circuit includes first and second input modulo 3 generation circuits, first and second input modulo 3 coincidence circuits, first and second modulo 3 holding registers, an operation result modulo 3 generation circuit, and a modulo 3 circuit. 3 arithmetic circuits and an arithmetic result modulo 3 coincidence circuit.

  The first input modulo 3 generation circuit generates a modulo 3 value of the first binary data as a first input modulo 3 value. The second input modulo 3 generation circuit generates a modulo 3 value of the second binary data as a second input modulo 3 value. The calculation result modulo 3 generation circuit generates a modulo 3 value of the calculation result. The first input modulo 3 coincidence circuit checks whether or not the first input modulo 3 value matches the first modulo 3 expected value. The second input modulo 3 matching circuit checks whether or not the second modulo 3 value matches the second modulo 3 expected value. The first modulo 3 holding register holds the output modulo 3 value of the first input modulo 3 matching circuit. The second modulo 3 holding register holds the output modulo 3 value of the second input modulo 3 matching circuit. The modulo 3 arithmetic circuit performs a modulo 3 operation corresponding to the arithmetic circuit between the output modulo 3 value held in the first modulo 3 holding register and the output modulo 3 value held in the second modulo 3 holding register. The result is output as the modulo 3 expected value of the operation result. The calculation result modulo 3 coincidence circuit checks whether or not the modulo 3 value of the calculation result matches the modulo 3 expected value of the calculation result.

  Patent Document 3 (Japanese Patent Laid-Open No. 2002-342071) discloses a “divider failure detection circuit” that can significantly reduce the amount of hardware for division check and check the entire divider. Yes. The divider failure detection circuit disclosed in Patent Document 3 considers the quotient after the rounding process and the quotient addition instruction generated by the rounding process when performing division corresponding to the rounding process of the IEEE P754 standard. A circuit for generating modulo 3 is included. More specifically, in the divider failure detection circuit, the modulo 3 result generated by the modulo 3 generation circuit of the quotient from the rounding processing results by the rounding circuit and the rounding addition circuit, and the modulo of the divisor obtained by the modulo 3 generation circuit for divisor. The multiplication of the three results is performed by a product modulo-3 generator. The result of the product modulo 3 generation circuit and the result of the partial remainder modulo 3 obtained by the partial remainder modulo 3 generation circuit are added by the sum modulo 3 generation circuit. The added modulo 3 result is compared with the modulo 3 result of the dividend generated in advance by the modulo 3 generation circuit for the dividend by the comparison circuit, and whether or not there is an obstacle in the quotient generation unit, the rounding circuit, and the rounding addition circuit. judge.

Patent Document 4 (Japanese Patent Application Laid-Open No. 60-117332) discloses a “divider” that requires a small amount of hardware for division check and can check the entire division. The division device disclosed in Patent Document 4 is a division device that calculates division by a g-adic number. The division device includes an inverse table memory for obtaining an approximate inverse of a divisor, a divisor correction circuit for obtaining a corrected divisor from a product of the divisor and the approximate inverse, and a multiplication for obtaining a first partial remainder R ₁ by multiplying the dividend by the approximate inverse. A circuit, N provisional commercial addition circuits for rounding off the i th partial remainder R _i to obtain the i th provisional quotient P _i , and the i th partial remainder to the i th provisional quotient and the corrected divisor N partial division circuits for obtaining the (i + 1) th partial remainder R _{i + 1} by multiplying the difference obtained by subtracting the product of i and the i-th partial remainder R _{i + 1} according to the positive or negative of the (i + 1) th partial remainder R _{i + 1} N quotient correction circuit that uses the principal value of the modulus g obtained by subtracting 0 or 1 from the provisional quotient P _i of the quotient as the quotient digit of the i-th digit from the quotient, and the dividend for generating the modulo 3 of the dividend A modulo 3 generation circuit, a modulo 3 generation circuit for divisors for creating a modulo 3 of a divisor, An approximate inverse modulo 3 generating circuit for generating a modulo 3 of reciprocal similar, and commercial modulo 3 generating circuit for generating a modulo 3 of the quotient, and a circuit for generating a first (N + 1) th partial remainder R _{N + 1} modulo 3 Prepare.

  Patent Document 5 (Japanese Patent Application Laid-Open No. 2003-307551) enables logic BIST to be performed at an actual operation speed (At-speed) without increasing the test time even for a large-scale, high-performance logic circuit. As a result, a "semiconductor integrated circuit and a method for designing a semiconductor integrated circuit" are disclosed in which the test cost is reduced. In the semiconductor integrated circuit disclosed in Patent Document 5, the logic BIST controller is divided into two, the partial circuit that supplies the scan enable signal and the clock signal to the user circuit is driven by a clock with a small delay, and the test pattern is supplied to the user circuit. And the partial circuit for collecting the test results is driven by a clock signal having a large delay. In the semiconductor integrated circuit disclosed in Patent Document 5, after setting the input pattern to the scan FF in the scan operation, the test pattern is propagated from the scan FF to the combinational circuit, and the test result output from the combinational circuit is taken into the scan FF. The operation of collecting the results is performed.

  By the way, in order to realize BIST, it is necessary to realize generation of an input pattern, generation of an expected value pattern for the input pattern, and comparison between a response result of the test target circuit and the expected value pattern in the chip. That is, to realize the BIST circuit, it is necessary to automatically generate an input pattern, automatically generate an expected value pattern for the input pattern, and compare the result pattern with the expected value pattern.

  Among the BIST circuits, the memory BIST circuit can detect a failure by accessing all memory cells and reading a pattern of “0” or “1” and then reading it, so that an expected value can be easily generated. Since the memory BIST circuit is a circuit that checks all memory cells without omission, it is easy to realize the circuit.

  On the other hand, in order to realize the logic BIST circuit of four arithmetic operations, it is necessary to consider the carry-up of carry or the like, and therefore it is generally difficult to generate an expected value. Therefore, conventionally, the following method is adopted. The first method is a method of checking the parity accompanying the response result of the functional circuit. The second method is a method in which a test target circuit is duplicated instead of generating an expected value pattern, and a response result from the duplicated test target circuit is used as an expected value.

  A conventional logic BIST circuit 100 employing the second method will be described with reference to FIG. The conventional logic BIST circuit 100 includes a test control unit 11, a pattern generator 12, a first test target circuit 13, a second test target circuit 13 </ b> A, and a comparator 30.

  When the BIST activation instruction signal C is given to the test control unit 11, the test control unit 11 sends a pattern generation instruction signal D to the pattern generator 12. The pattern generator 2 generates an input pattern in which the test target circuit 13 is easily activated and easily detects a failure, and gives the generated input pattern to the first test target circuit 13. In this example, since an arithmetic unit is assumed for the test target circuit 13, the first input pattern data A and the second input pattern data B are set. In parallel, the pattern generator 12 sends the first input pattern data A and the second input pattern data B to the duplicated second test target circuit 13A. Here, each of the first and second input pattern data A and B is composed of n bits.

  The first test target circuit 13 executes a calculation of Y = A (calculation) B and outputs a first response result Y. The second test target circuit 13A performs a calculation of YA = A (calculation) B, and outputs a second response result YA. Here, each of the first and second response results Y and YA is also composed of n bits. The first response result Y and the second response result YA are supplied to the comparator 3. The comparator 30 compares the first response result Y and the second response result YA in response to the comparison instruction signal E from the test control unit 11. If the first response result Y matches the second response result YA, the comparator 30 determines that the test target circuit 13 is “no failure”. On the other hand, if the first response result Y and the second response result YA do not match, the comparator 30 determines that the first test target circuit 13 has “circuit failure”.

JP 2001-297598 A JP-A 63-145547 JP 2002-342071 A JP 60-117332 A JP 2003-307551 A

  However, the conventional logic BIST circuit 100 shown in FIG. 7 has the following problems.

  The first problem is that a large amount of hardware is required because the test target circuit is duplicated.

  The second problem is that the comparator 30 requires a large amount of hardware because the comparison of the response results of the test target circuits 13 and 13A is n bits. As another solution, there is a case in which the first method described above is adopted and the response results Y and YA of n bits are not compared, but the parity of the response results is used. In this case, the comparison circuit can be configured with small-scale hardware, but there are cases where parity prediction cannot be performed depending on the arithmetic processing. Therefore, there is a problem that parity cannot be added to all stages of the arithmetic unit of the test target circuit 13 and the failure propagation rate is inferior.

  Patent Document 1 only discloses a technical idea related to the memory BIST circuit, and does not disclose any logic BIST circuit of four arithmetic operations targeted by the present invention.

  Patent Document 2 discloses a modulo W circuit used for checking an arithmetic circuit or the like. However, Patent Document 2 only discloses a modulo W circuit, and does not disclose or suggest applying the modulo W circuit to a logic BIST system. Further, since the modulo W circuit disclosed in Patent Document 2 is premised on a check in normal operation, it is necessary to generate modulo values from two operand data, respectively. Therefore, there is a problem that the circuit configuration becomes complicated. Furthermore, the modulo W circuit disclosed in Patent Document 2 requires two modulo value holding registers, ie, a first modulo 3 holding register and a second modulo 3 holding register, which increases the hardware. is there.

  Further, Patent Document 3 discloses a divider failure detection circuit having a circuit that performs modulo 3 generation. Similarly to Patent Document 2, this Patent Document 3 only discloses the use of a modulo circuit for detecting a failure of a divider, and applies (adopts) the modulo circuit to the logic BIST system. There is no disclosure or suggestion.

  Further, Patent Document 4 only discloses a division device that can perform division check using a modulo circuit, and does not disclose or suggest applying the modulo circuit to the logic BIST system. Absent.

  In Patent Document 5, in the case of a large-scale logic circuit, there is a problem that the delay of the scan enable signal and the delay of the clock signal become so large that they cannot be ignored compared to the clock period, and cannot operate at the at speed (actual operation speed). is there.

  Accordingly, an object of the present invention is to provide a logic BIST circuit capable of realizing high fault propagation with a small amount of hardware.

  Another object of the present invention is to provide a logic BIST circuit that performs generation of an expected value of a circuit to be tested using a modulo circuit.

  Still another object of the present invention is to provide a logic BIST circuit capable of operating at an actual operation speed.

According to the first aspect of the present invention, in a logic BIST circuit of a circuit whose test target is an arithmetic unit, a modulo expected value generation circuit that generates an expected value modulo value of a response result from input data supplied to the test target circuit And a result modulo generation circuit for obtaining a modulo value of the response result output from the circuit to be tested , and a comparator for comparing the modulo value of the response result with the expected value modulo value. The target circuit is a circuit that performs an operation on one input pattern data and a fixed value and outputs the response result, and the modulo expectation value generation circuit generates an input modulo value from the input pattern data. The input modulo value generation circuit, the input modulo value, and the modulo fixed value are subjected to the same operation as that of the test target circuit, thereby calculating the operation Logic BIST circuit is obtained having a modulo calculator for outputting a value, the.

In the logic BIST circuit according to the first aspect of the present invention, logic BIST circuit may have an output means for outputting the arithmetic modulo value as the expected value modulo value. The logic BIST circuit may further include a modulo value rotation circuit that is inserted between the input modulo generation circuit and the modulo arithmetic unit and holds the input modulo value. The logic BIST circuit includes a selector that selects one of the arithmetic modulo value and the input modulo value held by the modulo value rotation circuit and outputs the selected value as the expected value modulo value. good.

According to the second aspect of the present invention, input data is supplied from a pattern generator to a circuit whose test target is an arithmetic unit, and the test target circuit fails based on a response result output from the test target circuit. A modulo circuit for determining whether the response result is an expected value modulo value from the input data; a result modulo generation circuit for obtaining a response result modulo value; A comparator that compares the modulo value of the response result and the expected value modulo value, and the circuit under test performs an operation on one input pattern data and a fixed value, and the response A modulo expectation value generation circuit, an input modulo value generation circuit for generating an input modulo value from the input pattern data, and the input module. It performs the same operation as the test target circuit with respect to the B value and modulo a fixed value, and a modulo calculator for outputting the arithmetic modulo value, modulo circuit having obtained.

In modulo circuit according to the second aspect of the present invention, modulo circuit may have an output means for outputting the arithmetic modulo value as the expected value modulo value. The modulo circuit may further include a modulo value rotation circuit that is inserted between the input modulo generation circuit and the modulo arithmetic unit and holds the input modulo value. The modulo circuit may include a selector that selects one of the arithmetic modulo value and the input modulo value held by the modulo value rotation circuit and outputs the selected value as the expected value modulo value. .

According to a third aspect of the present invention, there is provided a logic BIST method for a circuit whose test target is an arithmetic unit, the step of supplying input data to the test target circuit, and a response of the test target circuit from the input data. a generating a result of the expected value modulo value, determining a modulo value of the response result, and the step of comparing the expected value modulo value modulo value of the response result, and the test target circuit Is a circuit that performs an operation on one input pattern data and a fixed value and outputs the response result, and the step of generating the expected value modulo value generates an input modulo value from the input pattern data Performing the same operation as the circuit under test on the input modulo value and the modulo fixed value, and outputting the operation modulo value A step that the logic BIST method having obtained.

In the logic BIST method according to the third aspect of the present invention, the step of generating a pre-Symbol expected value modulo value may have a step of outputting the operation modulo value as the expected value modulo value. The step of generating the expected value modulo value may further include the step of holding the input modulo value inserted between the step of generating the input modulo value and the step of outputting the arithmetic modulo value. . The step of generating the expected value modulo value includes a step of selecting either the arithmetic modulo value or the held input modulo value and outputting the selected value as the expected value modulo value. Good.

  The present invention has the following effects.

  The first effect is that expected value data can be generated from input data by using a modulo circuit in a test test of a functional circuit, particularly an arithmetic unit, without using an intermediate result of the circuit to be tested. The entire device can be in the failure detection range, and a high failure detection rate can be realized. Specifically, in contrast to the calculation “Y = A (calculation) B”, the “ModY = ModA (calculation) ModB” calculation is also established for the modulo data. By using a modulo circuit for generating the expected value, it is possible to generate an expected value modulo value from the input data of the circuit under test.

  The second effect is that a modulo circuit can be configured with a significantly smaller amount of hardware compared to the duplication of a functional circuit because a modulo circuit is used to generate an expected value of the functional circuit. An expected value modulo value can be generated using a modulo generation circuit and a modulo calculator. When the functional circuit is an arithmetic unit, the larger the data width, the smaller the hardware amount of the modulo circuit compared to the dual functional circuit, so that the hardware reduction effect is greater. In addition, a hardware having a simple configuration can be realized by a pattern generator having no input data width limitation. Furthermore, it is easy to increase the speed by using a small comparator. This facilitates AT-SPEED (actual speed) testing.

  The features of the present invention will be described.

  A first feature of the present invention is a logic BIST circuit capable of realizing a high failure detection rate by generating an expected value pattern using a modulo circuit in a functional circuit of a data control system, particularly in a test test of an arithmetic unit. It is. The functional circuit includes a circuit capable of generating an expected value pattern by a modulo circuit in addition to the arithmetic unit.

  The first feature of the present invention will be described. A process of calculating the first input data A and the second input data B and generating the result data Y is described as “Y = A (calculation) B”. The modulo value of the first input data A is ModA, and the modulo value of the second input data B is ModB. In this case, since “ModY = ModA (calculation) ModB” is established with respect to the “Y = A (calculation) B” computation, the modulo value for the first input data A and the second input data B is obtained. “ModA” and “ModB” are created, and the same calculation as the test target circuit is performed on the modulo values “ModA” and “ModB” to generate the expected value modulo value “ModA (calculation) ModB”. The result modulo value “ModY” is generated from the result data Y from the test target circuit. In this way, the expected value modulo value “ModA (calculation) ModB” is created from the input data, so that a failure of the test target circuit can be easily detected.

  The second feature of the present invention is that the amount of hardware can be reduced by adopting a modulo circuit for generating an expected value of the logic BIST circuit.

  The second feature of the present invention will be described. By adopting a modulo circuit for the logic BIST circuit of the arithmetic unit, it is possible to generate a modulo value for expected value data only by a combination of the modulo generation circuit and the modulo arithmetic circuit. For example, assume that a modulo-3 operation, which is a remainder operation obtained by dividing n-bit data by an integer 3, is employed. In this case, n-bit data can be compressed into 2-bit data by a modulo circuit (modulo generation circuit, modulo arithmetic circuit). By performing the same operation as the test target circuit on the modulo data compressed to 2 bits, modulo data for the expected value pattern can be created. The hardware of the modulo generation circuit and the modulo arithmetic circuit is considerably smaller than the hardware amount of the redundant system of the circuit under test, so the comparison between the expected modulo value and the result modulo value should be done with a small amount of hardware. Is possible.

  Specifically, assume that the circuit under test is a 64-bit arithmetic unit. In this case, a circuit for compressing 64-bit data into modulo data of 2-bit data is required, but this circuit can be configured with hardware of several tens to several hundreds of gates. Since the modulo operation performs an operation between two bits, this circuit can be composed of several tens of gates. The amount of hardware is much smaller than that of a 64-bit arithmetic unit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A logic BIST circuit 10 according to a first embodiment of the present invention will be described with reference to FIG. The illustrated logic BIST circuit 10 includes a test control unit 11, a pattern generator 12, a test target circuit 13, and a modulo circuit 20.

  The modulo circuit 20 includes a modulo expected value generation circuit 22, a result modulo generation circuit 24, and a comparator 26.

  The test control unit 11 is a circuit that issues a test execution instruction in a test operation. The test control unit 11 receives the BIST activation instruction signal C for starting the BIST operation, and outputs a pattern generation instruction signal D and a comparison instruction signal E.

  In response to the pattern generation instruction signal D, the pattern generator 12 is a circuit that generates a pattern that can easily detect a failure of the test target circuit 13. In the illustrated example, the pattern generator 12 generates first input pattern data A and second input pattern data B. Here, each of the first and second input pattern data A and B is n-bit data. The first and second input pattern data A and B are sent to the modulo expected value generation circuit 22 and the test target circuit 13.

  The test target circuit 13 inputs the first and second input pattern data A and B, performs an operation (Y = A (calculation) B) on the data A and B, and obtains a response result Y. Generate. The response result Y is sent to the result modulo generation circuit 24.

  The modulo expected value generation circuit 22 receives the first and second input pattern data A and B, and generates an expected value modulo value G as described later. The result modulo generation circuit 24 receives the response result Y, and generates a remainder ModY obtained by dividing the response result Y by an integer m (m ≧ 3) as a result modulo value F. In response to the comparison instruction signal E, the comparator 26 compares the result modulo value F with the expected value modulo value G, and performs a match / mismatch determination.

  As described above, the test target circuit 13 generates a response result Y = A (calculation) B from the first input pattern data A and the second input pattern data B. The modulo value of the first input pattern data A is ModA, and the modulo value of the second input pattern data B is ModB. In contrast to the calculation “Y = A (calculation) B”, “ModY = ModA (calculation) ModB” is established.

  Therefore, the modulo expected value generation circuit 22 creates modulo values “ModA” and “ModB” for the first input pattern data A and the second input pattern data B, and performs the same operation as the test target circuit 13 with the modulo value “ Implementation on “ModA” and “ModB” generates an expected value modulo value “ModA (calculation) ModB”. The result modulo value “ModY” is generated from the response result data Y output from the test target circuit 13 by the result modulo generation circuit 24.

  As described above, the expected value modulo value “ModA (calculation) ModB” is created from the input pattern data A and B, so that the failure of the test target circuit 13 can be easily detected.

  A specific example of the modulo expected value generation circuit 22 shown in FIG. 1 will be described with reference to FIG.

  The modulo expected value generation circuit 22 includes first and second input modulo generation circuits 221 and 222, a modulo value rotation circuit 223, and a modulo arithmetic unit 225.

  The first input modulo generation circuit 221 generates a remainder obtained by dividing the first input pattern data A by the integer m as a first input modulo value ModA. The second input modulo generation circuit 222 generates a remainder obtained by dividing the second input pattern data B by the integer m as a second input modulo value ModB. The modulo arithmetic unit 225 receives the first and second input modulo values ModA and ModB generated from the first and second input modulo generation circuits 221 and 222, respectively, and outputs these modulo values ModA and ModB. Then, the same calculation as that of the test target circuit 13 is performed to generate an expected value modulo value G. The modulo value rotation circuit 223 holds the expected value modulo value G until the time required for the calculation of the test target circuit 13.

  By adopting the modulo circuit 20 in the logic BIST circuit 10 of the arithmetic unit, the modulo value for the expected value data can be generated only by the combination of the modulo generation circuits 221 and 222 and the modulo arithmetic unit 225. For example, assume that the integer m is 3. In this case, the n-bit data A and B can be compressed into 2-bit data by the modulo circuit 20 by adopting a modulo-3 operation that is a remainder operation obtained by dividing the n-bit data A and B by the integer 3. By performing the same operation as the test target circuit 13 on the modulo data ModA and ModB compressed to 2 bits, modulo data (operation modulo value) ModA (operation) ModB for the expected value pattern can be created.

  The hardware of the modulo generation circuits 221, 222, 24 and the modulo arithmetic unit 225 is considerably smaller than the hardware amount of the duplex system of the test target circuit 13. Therefore, the expected value modulo value G and the result modulo value F can be compared with a small amount of hardware.

  Further, in this embodiment, the modulo arithmetic is performed by the modulo arithmetic unit 225 before being held (carried around), so that only one modulo value rotation circuit 223 is required, and the hardware can be reduced.

  Assume that the test target circuit 13 is a 64-bit arithmetic unit. In this case, each of the modulo generation circuits 221, 222, and 24 compresses 64-bit data into modulo data of 2-bit data. Such a modulo generation circuit can be constituted by hardware of several tens of gates to several hundred gates. Since the modulo arithmetic unit 225 performs an arithmetic operation between two bits, the modulo arithmetic unit 225 can be composed of several tens of gates. These hardware amounts are significantly smaller than the hardware amount of a 64-bit arithmetic unit.

  Next, the operation of the logic BIST circuit 10 shown in FIG. 2 will be described with reference to FIG.

  The test control unit 11 receives the BIST activation instruction signal C at timing 1 and sends a pattern generation instruction signal D to the pattern generator 12 at timing 2. The pattern generator 12 generates a pattern that facilitates activation of the test target circuit 13 and easily detects a failure, and sends the pattern to the test target circuit 13 at timing 3.

  In this example, since an arithmetic unit is assumed for the test target circuit 13, the pattern generator 12 sets the first input pattern data A and the second input pattern data B. In parallel, the pattern generator 12 sends the first and second input pattern data A and B to the first and second input modulo generation circuits 221 and 222 at timing 3, respectively.

  The first input modulo generation circuit 221 generates a first input modulo value ModA at timing 3 and sends it to the modulo calculator 225. The second input modulo generation circuit 222 generates a second input modulo value ModB at timing 3 and sends it to the modulo calculator 225.

  The modulo calculator 225 performs the same calculation as the test target circuit 13 at the timing 4 on the first input modulo value ModA and the second input modulo value ModB, and calculates the calculation modulo value (ModA (calculation) ModB). Output as expected value modulo value G.

  The modulo value rotation circuit 223 holds the expected value modulo value G until timing 7, which is the timing at which the response result Y is output from the test target circuit 13.

  It is assumed that the test target circuit 13 executes A (calculation) B in four cycles. In this case, the first and second input pattern data A and B given to the test target circuit 13 at the timing 3 are calculated by the test target circuit 13, and the test target circuit 13 receives the response result at the timing 7. Returns Y.

  The result modulo generation circuit 24 generates a result modulo value “ModY” from the response result Y at timing 7 and holds it at timing 8.

  The comparator 26 compares the result modulo value F with the expected value modulo value G in response to the comparison instruction signal E from the test control unit 11 at timing 9 and outputs the comparison result H. If the comparison result H indicates a match, it is determined that the test target circuit 13 is “no failure”. On the other hand, if the comparison result H indicates a mismatch, it is determined that the test target circuit 13 is “failed”.

  The case of adding two 64-bit data A and B will be described with specific data presented. A case where A = 0010101010101010 (hex) and B = 0001010101010101 (hex) are input as the first and second input pattern data A and B will be described.

  At timing 3, A = 0010101010101010 (hex) and B = 0001010101010101 (hex) are sent to the test target circuit 13. Assuming that the operation between A and B is executed in 4 cycles, the test target circuit 13 performs an addition result of A + B at 4 timings, generates an addition result at timing 7, and Q = 0011111111111111 which is the addition result (hex) is sent out.

  At timing 3, the first and second input pattern data A and B are set in the first and second input modulo generation circuits 221 and 222, respectively. Here, it is assumed that the modulo generation circuit performs modulo 3 processing. In this case, the first input modulo generation circuit 221 generates 01 (bin) as the first input modulo value “ModA”, and the second input modulo generation circuit 222 uses the second input modulo value “ModB”. As a result, 01 (bin) is generated. At timing 7, the response result Q = 0011111111111111 (hex) from the test target circuit 13 is subjected to modulo 3 processing by the result modulo generation circuit 24 to obtain 10 (bin) as a result modulo value “ModQ”. In parallel with timing 4, the modulo arithmetic unit 225 performs addition of “ModA” = 01 (bin) and “ModB” = 01 (bin), and obtains the modulo addition result “ModA ( Add) ModB "= 10 (bin).

  Since the result modulo value “ModQ” and the expected value modulo value “ModA (addition) ModB” have obtained the same result, the test target circuit 13 indicates “no failure” for the input pattern data A and B described above. I can judge.

  When the test target circuit 13 fails, if input pattern data that can activate the failed circuit portion can be input, the response result Y from the test target circuit 13 is different, and the failure of the test target circuit 13 can be detected.

  For example, in the example in which A = 0010101010101010 (hex) and B = 0001010101010101 (hex) are used as the first and second input pattern data A and B, the response result is Q = In the case of 0011111111111110 (hex), the result modulo value generated from the result modulo generation circuit 24 is ModQ = 01 (bin). As a result, the modulo value ModQ = 01 (bin) is different from the expected value modulo value “ModA (addition) ModB”, and a failure of the test target circuit 13 can be detected.

  A logic BIST circuit 10A according to a second embodiment of the present invention will be described with reference to FIG. The illustrated logic BIST circuit 10A includes a test control unit 11, a pattern generator 12A, a test target circuit 13, first and second selectors 16 and 17, and a modulo circuit 20A.

  The test control unit 11 is a circuit that issues a test execution instruction by a test operation. In response to the BIST activation instruction signal C, the test control unit 11 outputs a pattern generation instruction signal D and a comparison instruction signal E. The pattern generator 12 </ b> A is a circuit that generates a pattern that easily detects a failure in the test target circuit 13. In response to the pattern generation instruction signal D, the pattern generator 12A generates one n-bit data (input pattern data) A. In this example, a fixed value is used as another bit data value.

  The first selector 16 selects either the input pattern data A or a fixed value, and outputs the first selected data. The second selector 17 selects one of the fixed value and the input pattern data A, and outputs the second selected data. That is, by switching the first and second selectors 16 and 17, the generation pattern and the fixed value are switched and input to the test target circuit 13.

  The test target circuit 13 inputs the n-bit data (input pattern data) A generated by the pattern generator 12A and the n-bit fixed value via the first and second selectors 16 and 17, And a response result Y is generated. That is, the test target circuit 13 executes any one of the fixed value (calculation) A, A (calculation) fixed value, and A (calculation) A.

  The modulo circuit 20A has the same configuration as that of the modulo circuit 20 shown in FIG. 2 except that the configuration of the modulo expectation value generation circuit is different from that shown in FIG. Therefore, the reference numeral 22A is assigned to the modulo expected value generation circuit. Components having the same functions as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted for the sake of simplicity.

  The modulo expected value generation circuit 22A is identical to the modulo expected value generation circuit 22 shown in FIG. 2 except that the second input modulo generation circuit 222 is omitted (deleted) and a selector 226 is added. It has the same configuration. In other words, the modulo expected value generation circuit 22A includes one input modulo generation circuit 221, one modulo value rotation circuit 223, a modulo calculator 225, and a selector 226.

  The input modulo generation circuit 221 is a circuit that generates a remainder obtained by dividing n-bit data (input pattern data) A by an integer m as an input modulo value ModA. The result modulo generation circuit 24 is a circuit that generates a remainder ModY obtained by dividing an n-bit response result Y by an integer m as a result modulo value F. The modulo value rotation circuit 223 holds the input modulo value ModA until the time required for the operation of the test target circuit 13. The modulo calculator 225 is a circuit that performs the same calculation as the test target circuit 13 on the remainder data (input modulo value) ModA generated by the input modulo generation circuit 221 and carried around by the modulo value rotation circuit. That is, the modulo calculator 225 calculates “Mod fixed value (calculation) ModA” and outputs it as a calculated modulo value.

  The selector 226 selects and selects either the input modulo value ModA held by the modulo value rotation circuit 223 or the operation modulo value “Mod fixed value (operation) ModA” generated by the modulo calculator 225. The obtained modulo value is output as an expected value modulo value G.

  The comparator 26 is a circuit that compares the result modulo value F generated by the result modulo generation circuit 24 with the expected value modulo value G selected by the selector 226 and outputs a comparison result H.

  As described above, in the logic BIST circuit 10A according to this embodiment, two independent n-bit patterns are converted into an arithmetic unit (test target circuit) as in the case of the logic BIST circuit 10 according to the first embodiment shown in FIGS. ) Instead of being supplied to 13, a combination of one n-bit pattern data A generated by the pattern generator 12A and a fixed value is input. For this reason, the modulo expected value generation circuit 22A can reduce the amount of hardware compared to the modulo expected value generation circuit 22 shown in FIG. Play.

  For example, it is assumed that the calculation in the test target circuit 13 is multiplication and the fixed value = “1”. In this case, the test target circuit 13 performs an operation of “1 (multiplication) A”, and the multiplication result as the response result is equal to A (multiplication result = A). In this case, since the input modulo value ModA generated by the input modulo generation circuit 221 can be used as the expected value modulo value G, the calculation by the modulo calculator 225 becomes unnecessary. Therefore, the input modulo value ModA held by the modulo value rotation circuit 223 can be used as the expected value modulo value G as it is switched by the selector 226.

  In the second embodiment of the present invention, the modulo expected value generation circuit 22A includes the selector 226. However, the selector 226 may be omitted. In this case, by connecting the output terminal of the modulo arithmetic unit 225 and one input terminal of the comparator 26 directly by a signal line (not shown), the arithmetic modulo value generated by the modulo arithmetic unit 225 is directly used as the expected value. What is necessary is just to output as the modulo value G.

  A logic BIST circuit 10B according to a third embodiment of the present invention will be described with reference to FIG. The illustrated logic BIST circuit 10B has the same configuration as that of the logic BIST circuit 10 shown in FIG. 2 except that the pattern generator and the modulo circuit are configured by circuits that can operate at an actual operation speed. Accordingly, reference numerals 12B and 20B are assigned to the pattern generator and the modulo circuit, respectively.

  The modulo circuit 20B includes a modulo expected value generation circuit 22B, a result modulo generation circuit 24A, and a comparator 26. The modulo expectation value generation circuit 22B includes first and second input modulo generation circuits 221A and 222A, a modulo value rotation circuit 223, and a modulo calculator 225.

  The illustrated logic BIST circuit 10B is a logic BIST circuit that can operate at an at-speed (actual operating speed).

  When the LSI tester is a middle end tester, the LSI is tested at a tester frequency of 100 MHz to 200 MHz. On the other hand, the number of circuits operating at an actual operating frequency of 200 MHz or more is increasing due to circuit miniaturization, and there are cases where the LSI can operate at an actual operating frequency of 500 MHz or 1 GHz. For this reason, AC operation verification tends to be insufficient at LSI test frequencies.

  Therefore, in this embodiment, a logic BIST circuit 10B operable at at speed is realized by incorporating a function operable at an actual operation speed (at speed) on the LSI tester.

  FIG. 6 shows a time chart for explaining the operation of the logic BIST circuit 10B shown in FIG.

  Hereinafter, a specific configuration of the logic BIST circuit 10B will be described with reference to FIGS. Here, it is assumed that the tester frequency is 200 MHz and the actual operating frequency is 600 MHz.

  Since the pattern generation instruction signal D from the test control unit 11 operating at the tester frequency has a signal cycle later than the actual operation frequency, the pattern generator 12B generates an actual operation speed timing signal using a differentiation circuit or the like. The pattern generation instruction signal D is captured.

  The internal signal of the pattern generator 12B needs to propagate from the rising edge of the clock signal that drives the register to the next rising edge of the clock signal that drives the register that receives the signal (setup time constraint). . In addition, the propagating internal signal must be propagated after the previous rising edge of the clock signal that drives the register that receives the signal (hold time constraint).

  Since the pattern generator 12B has no constraint for generating a pattern within a predetermined time, the circuit is adjusted by adjusting the latency (waiting time) so as to satisfy the above two constraints (setup time constraint and hold time constraint). Realize.

  The modulo circuit 20B can also operate at an actual operation speed if the circuit is realized by adjusting the latency (waiting time) so as to satisfy the above two constraints (setup time constraint and hold time constraint).

  When the test target circuit 13 is a computing unit, a computing unit that operates at high speed generally requires several cycles to calculate the result.

  The modulo calculator 225 is a 2-bit calculation and can be realized with a small amount of hardware. Therefore, the modulo arithmetic unit 225 can be realized by a circuit that can be easily increased in speed and can be operated in a short cycle. The expected value modulo value G and the result modulo value F are 2 bits, and the comparator 26 performs comparison of 2 bits width. Therefore, the comparator 26 becomes a small comparator, can be realized with a circuit that is easy to increase the speed and can operate in a short cycle.

  On the other hand, first and second input modulo generation circuits 221A for generating 2-bit first and second input modulo values ModA and ModB from n-bit first and second input pattern data A and B, Since 222A requires the number of logic stages, the number of logic stages between the registers is adjusted, and the circuit is adjusted so as to satisfy the above two constraints (setup time constraint and hold time constraint).

  The result modulo generation circuit 24A that generates the result modulo value ModY from the response result Y from the test target circuit 13 also adjusts the circuit so as to satisfy the above two constraints (setup time constraint and hold time constraint).

  As described above, when the circuit adjustment of the modulo circuit 20B is performed and the latency of the result modulo value ModY is increased, by extending the rotation time of the modulo value rotation circuit 223 that holds the expected value modulo value G, The result modulo value ModY and the expected value modulo value G can be input to the comparator 26 at the same timing. The comparator 26 compares these values in response to the comparison instruction signal E from the test control unit 11.

  In the case of the logic BIST circuit 10 illustrated in FIG. 2, the modulo generation circuits 221, 222, and 24 operate in two cycles in order to operate the logic BIST circuit 10 at a tester frequency as illustrated in FIG. 3. , And ModY are generated.

  On the other hand, in the case of the logic BIST circuit 10B shown in FIG. 5, the logic BIST circuit 10B is operated at the actual operating frequency (speed) as shown in FIG. Although the results G and H are output in one cycle, the modulo generation circuits 221A, 222A, and 24A generate the modulo values ModA, ModB, and ModY in five cycles, so that the register 4 is output as shown in FIG. Corresponding to add a step.

  In the logic BIST circuit 10B shown in FIG. 5, unlike the configuration of Patent Document 5, the pattern generation start signal of the pulse signal is applied to the combinational circuit (test circuit) by a scanning operation instead of a pattern. A start instruction is given by a circuit method, and it is observed whether or not a mismatch result occurs at the result output timing.

  The logic BIST circuit 10B illustrated in FIG. 5 is a circuit in which the logic BIST circuit 10 illustrated in FIG. 2 is changed so as to be able to operate at an at-speed (actual operation speed), but the logic BIST circuit 10B illustrated in FIG. On the other hand, those skilled in the art can easily understand that it can be changed so that it can be operated at an at-speed (actual operation speed).

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the spirit (subject) of the present invention. . For example, although the case where the test target circuit is an arithmetic unit has been described as an example in the above embodiment, the test target circuit may be a functional circuit other than a memory.

1 is a block diagram showing a logic BIST circuit according to a first embodiment of the present invention. FIG. FIG. 1 is a block diagram showing a specific example of a modulo expected value generation circuit of a logic BIST circuit. 3 is a time chart for explaining the operation of the logic BIST circuit shown in FIG. 2. FIG. 6 is a block diagram showing a logic BIST circuit according to a second embodiment of the present invention. FIG. 6 is a block diagram showing a logic BIST circuit according to a third embodiment of the present invention. 6 is a time chart for explaining the operation of the logic BIST circuit shown in FIG. 5. It is a block diagram which shows the conventional logic BIST circuit.

Explanation of symbols

10, 10A, 10B Logic BIST circuit 11 Test control unit 12, 12A, 12B Pattern generator 13 Test target circuit 16, 17 Selector 20, 20A, 20B Modulo circuit 22, 22A, 22B Modulo expected value generation circuit 221, 222 Input modulo Generation circuit 221A, 222A Input modulo generation circuit 223 Modulo value rotation circuit 225 Modulo operation unit 226 Selector 24 Result modulo generation circuit 24A Result modulo generation circuit 26 Comparator

Claims (12)

In the logic BIST circuit of a circuit whose test target is an arithmetic unit ,
A modulo expected value generation circuit that generates an expected value modulo value of a response result from input data supplied to the test target circuit;
A result modulo generation circuit for obtaining a modulo value of the response result output from the test target circuit;
A comparator for comparing the modulo value of the response result with the expected value modulo value;
Have
The test target circuit is a circuit that performs an operation on one input pattern data and a fixed value and outputs the response result,
The modulo expected value generation circuit includes:
An input modulo value generation circuit for generating an input modulo value from the input pattern data;
A modulo calculator that performs the same operation as the test target circuit on the input modulo value and the modulo fixed value, and outputs an operation modulo value;
Logic BIST circuit, characterized in that it comprises a. 2. The logic BIST circuit according to claim 1 , further comprising output means for outputting the arithmetic modulo value as the expected value modulo value. The logic BIST circuit according to claim 1 , further comprising a modulo value rotation circuit inserted between the input modulo generation circuit and the modulo arithmetic unit and holding the input modulo value. 4. The selector according to claim 3 , further comprising a selector that selects one of the arithmetic modulo value and the input modulo value held by the modulo value rotation circuit and outputs the selected value as the expected value modulo value. Logic BIST circuit. A modulo circuit for supplying input data from a pattern generator to a circuit to be tested as an arithmetic unit and determining whether or not the test target circuit is faulty from a response result output from the test target circuit Because
A modulo expected value generation circuit for generating an expected value modulo value of the response result from the input data;
A result modulo generation circuit for obtaining a modulo value of the response result;
A comparator for comparing the modulo value of the response result with the expected value modulo value;
Have
The test target circuit is a circuit that performs an operation on one input pattern data and a fixed value and outputs the response result,
The modulo expected value generation circuit includes:
An input modulo value generation circuit for generating an input modulo value from the input pattern data;
A modulo calculator that performs the same operation as the test target circuit on the input modulo value and the modulo fixed value, and outputs an operation modulo value;
Modulo circuit characterized in that it comprises a. 6. The modulo circuit according to claim 5 , further comprising output means for outputting the arithmetic modulo value as the expected value modulo value. The modulo circuit according to claim 5 , further comprising a modulo value rotation circuit inserted between the input modulo generation circuit and the modulo arithmetic unit to hold the input modulo value. The selector according to claim 7 , further comprising: a selector that selects one of the arithmetic modulo value and the input modulo value held by the modulo value rotation circuit and outputs the selected value as the expected value modulo value. Modulo circuit. A logic BIST method for a circuit for testing an arithmetic unit ,
Supplying input data to the circuit under test;
Generating an expected value modulo value of a response result of the circuit under test from the input data;
Obtaining a modulo value of the response result;
Comparing the modulo value of the response result with the expected value modulo value;
Have
The test target circuit is a circuit that performs an operation on one input pattern data and a fixed value and outputs the response result,
Generating the expected value modulo value comprises:
Generating an input modulo value from the input pattern data;
Performing the same operation as the test target circuit on the input modulo value and the modulo fixed value, and outputting an operation modulo value;
Logic BIST method characterized by having a. 10. The logic BIST method according to claim 9 , wherein the step of generating the expected value modulo value includes the step of outputting the operation modulo value as the expected value modulo value. Wherein generating the expected value modulo value further comprises the step of being inserted, to hold the input modulo value between the step of outputting the operation modulo value and the step of generating the input modulo value, claim 10. The logic BIST method according to 9 . The step of generating the expected value modulo value includes the step of selecting either the arithmetic modulo value or the held input modulo value and outputting the selected value as the expected value modulo value. The logic BIST method according to claim 11 .

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