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JP4863861B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4863861B2
JP4863861B2 JP2006341822A JP2006341822A JP4863861B2 JP 4863861 B2 JP4863861 B2 JP 4863861B2 JP 2006341822 A JP2006341822 A JP 2006341822A JP 2006341822 A JP2006341822 A JP 2006341822A JP 4863861 B2 JP4863861 B2 JP 4863861B2
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wiring board
semiconductor device
semiconductor element
alloy
adhesive layer
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JP2008153548A (en
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英二 堀越
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure including a semiconductor element, which employs a material with a low dielectric constant called a low-K material as a material constituting an interlayer insulation film of a multilayer wiring layer, flip-chip-mounted on a circuit board, with a highly reliable mounting structure by flexibly coping with a change in temperature to prevent breakdown of the interlayer insulation film. <P>SOLUTION: The semiconductor device including a structure in which a semiconductor element 50 is flip-chip-connected with a wiring board 60 with its face downward has a connecting member 53 for electrically connecting the semiconductor element 50 with the wiring board 60 and a semiconductor element adhesive layer 51 formed on a surface opposite to the board 60 among principal planes of the element 50, a wiring board adhesive layer 63 formed on the upper surface of the wiring board, and an elastic resin 64 provided between the adhesive layers 51 and 63. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、半導体装置に関し、より具体的には、Ｌｏｗ−Ｋ材料と呼ばれる誘電率の低い材料を多層配線層の層間絶縁膜を構成する材料として用いた半導体素子を、回路基板に実装した構造を備える半導体装置に関する。   The present invention relates to a semiconductor device, and more specifically, a structure in which a semiconductor element using a low dielectric constant material called Low-K material as a material constituting an interlayer insulating film of a multilayer wiring layer is mounted on a circuit board. The present invention relates to a semiconductor device comprising:

近年、半導体素子の多層配線層の層間絶縁膜を構成する材料として、有機樹脂、炭素を添加した酸化シリコン（ＳｉＯＣ）、フッ素がドープされたシリコンガラス（ＦＳＧ：Ｆｌｕｏｒｉｎｅ ｄｏｐｅｄ Ｓｉｌｉｃｏｎ Ｇｌａｓｓ）、ポーラスシリカ系Ｌｏｗ−ｋ材料ナノクラスタリングシリカ（ＮＣＳ： Ｎａｎｏ Ｃｌｕｓｔｅｒｉｎｇ Ｓｉｌｉｃａ）等の誘電率の低い材料（所謂Ｌｏｗ−Ｋ材料）が用いられ、配線間に形成される電気容量を低減し、電気信号の伝達の高速化が図られる。このようなＬｏｗ−Ｋ材料は、特に、次世代の高速処理用の半導体装置の多層配線層の層間絶縁膜を構成する材料として期待されている。   In recent years, organic resins, silicon oxide added with carbon (SiOC), fluorine-doped silicon glass (FSG: Fluorine doped Silicon Glass), and porous silica-based materials are used as materials constituting an interlayer insulating film of a multilayer wiring layer of a semiconductor element. Low-k material Nanoclustering Silica (NCS: Nano Clustering Silica) and other low dielectric constant materials (so-called Low-K materials) are used to reduce the electrical capacitance formed between the wires and to transmit electrical signals at high speed. Is achieved. Such a Low-K material is particularly expected as a material constituting an interlayer insulating film of a multilayer wiring layer of a semiconductor device for next-generation high-speed processing.

図１は、配線基板にフリップチップ実装してなる半導体装置における、前記半導体素子の構造を示す断面図である。また、図１において点線で囲まれた部分を拡大して図２に示す。   FIG. 1 is a cross-sectional view showing the structure of the semiconductor element in a semiconductor device that is flip-chip mounted on a wiring board. Further, FIG. 2 is an enlarged view of a portion surrounded by a dotted line in FIG.

図１及び図２に示すように、半導体素子にあっては、シリコン（Ｓｉ）からなる半導体基板１に所謂ウエハープロセスが適用されて、その一方の主面にトランジスタなどの能動素子、及び容量素子などの受動素子が形成され（図示せず）、更に当該半導体基板１の一方の主面上に、酸化シリコン（ＳｉＯ２）層２等の絶縁層を介して多層配線層３が配設されている。 As shown in FIGS. 1 and 2, in a semiconductor element, a so-called wafer process is applied to a semiconductor substrate 1 made of silicon (Si), and an active element such as a transistor and a capacitive element are provided on one main surface thereof. And a multilayer wiring layer 3 is disposed on one main surface of the semiconductor substrate 1 via an insulating layer such as a silicon oxide (SiO 2 ) layer 2. Yes.

かかる多層配線層３は、アルミニウム（Ａｌ）又は銅（Ｃｕ）等からなる配線層４が層間絶縁膜５を介して複数層積層されて形成されている。そして層間接続部を介して上下の配線層４間が適宜接続されている。   The multilayer wiring layer 3 is formed by laminating a plurality of wiring layers 4 made of aluminum (Al) or copper (Cu) with an interlayer insulating film 5 interposed therebetween. The upper and lower wiring layers 4 are appropriately connected through interlayer connection portions.

層間絶縁膜５を構成する材料としては、有機樹脂、炭素を添加した酸化シリコン（ＳｉＯＣ）、フッ素がドープされたシリコンガラス（ＦＳＧ：Ｆｌｕｏｒｉｎｅ ｄｏｐｅｄ Ｓｉｌｉｃｏｎ Ｇｌａｓｓ）、ポーラスシリカ系Ｌｏｗ−ｋ材料ナノクラスタリングシリカ（ＮＣＳ： Ｎａｎｏ Ｃｌｕｓｔｅｒｉｎｇ Ｓｉｌｉｃａ）等の誘電率の低い材料（所謂Ｌｏｗ−Ｋ材料）が用いられ、配線間に形成される電気容量を低減し、電気信号の伝達の高速化が図られる。   The material constituting the interlayer insulating film 5 includes organic resin, silicon-added silicon (SiOC) added with carbon, fluorine-doped silicon glass (FSG), porous silica-based low-k material nano-clustering silica A material having a low dielectric constant (so-called Low-K material) such as (NCS: Nano Clustering Silica) is used, and the electric capacity formed between the wirings is reduced, thereby speeding up the transmission of the electric signal.

半導体基板１に形成された能動素子、受動素子等の機能素子は、多層配線層３を介して相互に接続され、所望の機能を有する電子回路が形成される。   Functional elements such as active elements and passive elements formed on the semiconductor substrate 1 are connected to each other via the multilayer wiring layer 3 to form an electronic circuit having a desired function.

多層配線層３の上部には、アルミニウム（Ａｌ）からなる電極パッド１１が複数個選択的に配設され、多層配線層３を構成する配線４と適宜接続されている。また、多層配線層３上には、電極パッド１１の中央部を表出するよう選択的に開口を有して、例えば酸化シリコン（ＳｉＯ２）或いは窒化シリコン（ＳｉＮ）等の無機絶縁材料からなるパッシベーション層６が選択的に配設されている。 A plurality of electrode pads 11 made of aluminum (Al) are selectively disposed on the multilayer wiring layer 3 and are appropriately connected to the wiring 4 constituting the multilayer wiring layer 3. In addition, an opening is selectively formed on the multilayer wiring layer 3 so as to expose the central portion of the electrode pad 11 and is made of an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN). A passivation layer 6 is selectively provided.

更に、半導体素子の表面の保護を図るべく、無機絶縁層６の上面及び電極パッド１１の上における無機絶縁層６の端面を覆って、ポリイミド、ベンゾシクロブテン、フェノール樹脂、又はポリベンゾオキサゾール等の有機絶縁性材料からその材料が選択された有機絶縁膜７が配設されている。   Furthermore, in order to protect the surface of the semiconductor element, the upper surface of the inorganic insulating layer 6 and the end surface of the inorganic insulating layer 6 on the electrode pad 11 are covered, and polyimide, benzocyclobutene, phenol resin, polybenzoxazole, or the like An organic insulating film 7 in which the material is selected from organic insulating materials is disposed.

電極パッド１１の上面であって、無機絶縁層６及び有機絶縁膜７が設けられていない箇所から鉛直方向に、例えば、チタン（Ｔｉ）／銅（Ｃｕ）から成るバンプ下地金属８が、有機絶縁膜７の上面よりも僅かに上方に至るまで、当該有機絶縁膜７の端面を覆って配設されている。   A bump base metal 8 made of, for example, titanium (Ti) / copper (Cu) is organically insulated in a vertical direction from a position on the upper surface of the electrode pad 11 where the inorganic insulating layer 6 and the organic insulating film 7 are not provided. The organic insulating film 7 is disposed so as to cover the end surface of the organic insulating film 7 until slightly above the upper surface of the film 7.

バンプ下地金属８の上面には、略球状の外部接続用突起電極９が配設されている。当該外部接続用突起電極９は、錫（Ｓｎ）−銀（Ａｇ）、又は銅（Ｃｕ）を含む錫（Ｓｎ）−銀（Ａｇ）等の半田から構成され、半田バンプとも称される。   On the upper surface of the bump base metal 8, a substantially spherical external connection protruding electrode 9 is provided. The external connection protruding electrode 9 is made of solder such as tin (Sn) -silver (Ag) or tin (Sn) -silver (Ag) containing copper (Cu), and is also referred to as a solder bump.

上述の構造を有する半導体素子１０を配線基板にフリップチップ実装した状態を図３に示す。   FIG. 3 shows a state where the semiconductor element 10 having the above structure is flip-chip mounted on a wiring board.

図３を参照するに、半導体素子１０は、配線基板２０に対しフェイスダウンでフリップチップ方式にて実装されている。   Referring to FIG. 3, the semiconductor element 10 is mounted on the wiring board 20 by face-down flip-chip method.

なお、配線基板２０は、ガラスエポキシ材，ポリイミドテープ等、樹脂系材料から成る。配線基板２０の上面には、電極パッド２１が複数個選択的に配設され、当該電極パッド２１の中央部を表出するよう選択的に開口を有するソルダーレジスト２２が配設されている。   The wiring board 20 is made of a resin material such as a glass epoxy material or a polyimide tape. A plurality of electrode pads 21 are selectively disposed on the upper surface of the wiring board 20, and a solder resist 22 having an opening is selectively disposed so as to expose the central portion of the electrode pad 21.

また、配線基板２０上に配設された電極パッド２１に対して半導体素子１０の外部接続用突起電極９が接続されている。また、半導体素子１０と配線基板２０との間には、エポキシ系樹脂等から成るアンダーフィル材２３が配設されている。配線基板２０の下面には、半田から成る外部接続用突起電極２４が配設されている。   Further, the external connection protruding electrode 9 of the semiconductor element 10 is connected to the electrode pad 21 disposed on the wiring board 20. An underfill material 23 made of an epoxy resin or the like is disposed between the semiconductor element 10 and the wiring board 20. An external connection protruding electrode 24 made of solder is disposed on the lower surface of the wiring board 20.

このような構造を有する半導体装置は、以下の工程を経て完成される。   A semiconductor device having such a structure is completed through the following steps.

即ち、半導体素子１０を配線基板２０に対しフリップチップ（フェイスダウン）方式にて搭載した後に、リフロー加熱処理により、外部接続用突起電極９と予め配線基板２０の電極パッド２１上に設けられた予備半田（半田プリコート・図示を省略）とを溶融して、半導体素子１０の外部接続用突起電極９と配線基板２０とを接続する。   That is, after the semiconductor element 10 is mounted on the wiring board 20 by the flip chip (face-down) method, the external connection protruding electrode 9 and the spare provided in advance on the electrode pad 21 of the wiring board 20 by reflow heat treatment. Solder (solder precoat, not shown) is melted to connect the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し、硬化せしめる。最後に、配線基板２０の下面に半田ボールを搭載し、リフロー加熱工程及び冷却工程を経て、外部接続用突起電極２４を接続する。   Thereafter, an underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured. Finally, solder balls are mounted on the lower surface of the wiring board 20 and the external connection protruding electrodes 24 are connected through a reflow heating process and a cooling process.

そのほか、接続端子を備えた基板とパッドを具えた被実装物に挟まれたシート状の弾性体からなる絶縁体と、接続端子とパッドに対応した位置に局在して導通させ、絶縁体の厚さ方向に埋設された複数本の導電性のワイヤから構成されるワイヤ集合体と、を備えた異方導電性接続部材が提案されている。（特許文献１参照）
更に、接着剤組成物として、エポキシ樹脂、アクリルゴム、及び、潜在性硬化剤を含有する回路部材接続用の接着剤が提案されている。 In addition, an insulator made of a sheet-like elastic body sandwiched between a substrate having a connection terminal and a mounted object having a pad, and a localized connection at a position corresponding to the connection terminal and the pad. There has been proposed an anisotropic conductive connecting member including a wire assembly including a plurality of conductive wires embedded in a thickness direction. (See Patent Document 1)
Furthermore, an adhesive for connecting a circuit member containing an epoxy resin, an acrylic rubber, and a latent curing agent has been proposed as an adhesive composition.

また、ゴム状弾性樹脂に、多数の一軸方向に伸びた針形状導電性フィラーと、針形状導電性フィラーの径よりも直径が大きい球状フィラーを混在させた弾性導電接着剤により、部品接続部の周辺を封止する態様が提案されている。（特許文献３参照）
特開平５−６２７２７号公報 国際公開第００／０９６２３号パンフレット 特開２００６−３２４１２号公報 In addition, the elastic conductive adhesive in which a rubber-like elastic resin is mixed with a large number of needle-shaped conductive fillers extending in a uniaxial direction and a spherical filler having a diameter larger than the diameter of the needle-shaped conductive filler, An aspect of sealing the periphery has been proposed. (See Patent Document 3)
JP-A-5-62727 International Publication No. 00/09623 Pamphlet JP 2006-32412 A

しかしながら、層間絶縁膜５を構成する材料として、例えば、上述のポーラスシリカ系Ｌｏｗ−ｋ材料ナノクラスタリングシリカ（ＮＣＳ： Ｎａｎｏ Ｃｌｕｓｔｅｒｉｎｇ Ｓｉｌｉｃａ）を用いた場合、誘電率は２．２５と優れているものの、機械的強度は、約１０Ｐａ程度、即ち、層間絶縁膜５として従来用いられてきた材料の約１／３程度である。そのため、以下の問題が発生する。これについて、図４を参照して説明する。   However, when the above-described porous silica-based low-k material nano-clustering silica (NCS: Nano Clustering Silica) is used as a material constituting the interlayer insulating film 5, for example, although the dielectric constant is excellent at 2.25, The mechanical strength is about 10 Pa, that is, about 1/3 of the material conventionally used as the interlayer insulating film 5. Therefore, the following problems occur. This will be described with reference to FIG.

ここで、図４は、図３に示す半導体装置の問題点を説明するための概略模式図である。なお、図４では、図３に示す構造において前記問題点に関する部分のみ示して図を簡素化するとともに、説明を分かりやすくするために層間絶縁膜５を多層配線層３の代表として示している。図４（ｂ）は、図４（ａ）に示す半導体装置が温度変化がある環境におかれ、変形した状態を示す図である。   Here, FIG. 4 is a schematic diagram for explaining the problem of the semiconductor device shown in FIG. In FIG. 4, only the portion related to the problem is shown in the structure shown in FIG. 3 to simplify the drawing, and the interlayer insulating film 5 is shown as a representative of the multilayer wiring layer 3 for easy understanding. FIG. 4B is a diagram illustrating a deformed state in which the semiconductor device illustrated in FIG.

半導体素子１０が配線基板２０に対しフリップチップ（フェイスダウン）方式にて実装された半導体装置にあっては、当該半導体装置を構成する各部材の熱膨張係数は相違する。例えば、半導体素子１０として使用されるシリコン（Ｓｉ）の熱膨張係数は約３×１０−６／℃であり、樹脂系材料から成る配線基板２０の熱膨張係数は約１６×１０−６／℃である。 In a semiconductor device in which the semiconductor element 10 is mounted on the wiring substrate 20 by a flip chip (face-down) method, the thermal expansion coefficients of the members constituting the semiconductor device are different. For example, the thermal expansion coefficient of silicon (Si) used as the semiconductor element 10 is about 3 × 10 −6 / ° C., and the thermal expansion coefficient of the wiring board 20 made of a resin-based material is about 16 × 10 −6 / ° C. It is.

また、例えば、半導体素子１０を配線基板２０に実装する際の温度は、約１５０乃至２６０℃であり、特に、当該実装のためのリフロー工程においてリフロー炉内の温度は約２６０℃に達する。半導体装置の信頼性試験においても熱が加わる。更に、一般の使用においても、約７０乃至８０℃以上の環境に置かれる場合がある。   For example, the temperature at which the semiconductor element 10 is mounted on the wiring board 20 is about 150 to 260 ° C. In particular, the temperature in the reflow furnace reaches about 260 ° C. in the reflow process for the mounting. Heat is also applied in reliability testing of semiconductor devices. Further, even in general use, it may be placed in an environment of about 70 to 80 ° C. or higher.

従って、このような温度変化がある環境下においては、上記の熱膨張係数の相違に因り各部材が膨張又は収縮して、層間絶縁膜５に応力集中が発生してしまうおそれがある。   Therefore, in an environment where there is such a temperature change, each member may expand or contract due to the difference in thermal expansion coefficient, and stress concentration may occur in the interlayer insulating film 5.

その結果、図４（ｂ）に示すように、半導体装置にひずみが生じ、外部接続用突起電極９を介して配線基板２０に接合された半導体素子１０の層間絶縁膜５にクラックが発生し、当該層間絶縁膜５が破壊してしまい、半導体装置としての信頼性の低下を招来してしまうおそれがある。   As a result, as shown in FIG. 4B, the semiconductor device is distorted, and a crack is generated in the interlayer insulating film 5 of the semiconductor element 10 bonded to the wiring substrate 20 via the external connection protruding electrode 9. The interlayer insulating film 5 may be destroyed, leading to a decrease in reliability as a semiconductor device.

そこで、本発明は、上記の点に鑑みてなされたものであって、Ｌｏｗ−Ｋ材料と呼ばれる誘電率の低い材料を多層配線層の層間絶縁膜を構成する材料として用いた半導体素子が回路基板にフリップチップ実装された構造を有する半導体装置であって、温度変化に柔軟に対応して前記層間絶縁膜の破壊を防止することにより、信頼性の高い実装構造を備えた半導体装置を提供することを本発明の目的とする。   Therefore, the present invention has been made in view of the above points, and a semiconductor device using a low dielectric constant material called a Low-K material as a material for forming an interlayer insulating film of a multilayer wiring layer is a circuit board. A semiconductor device having a structure mounted in a flip-chip, and having a highly reliable mounting structure by flexibly responding to a temperature change and preventing breakdown of the interlayer insulating film Is an object of the present invention.

本発明の一観点によれば、半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材と、半導体素子接着剤層と、が形成され、前記配線基板の上面には、配線基板接着剤層が形成され、前記半導体素子接着剤層と前記配線基板接着剤層との間に、弾性体樹脂が設けられており、前記配線基板には、凹部が形成されており、前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置が提供される。 According to an aspect of the present invention, there is provided a semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face-down, on a surface of the main surface of the semiconductor element that faces the wiring board. Includes a connecting member for electrically connecting the semiconductor element and the wiring board, and a semiconductor element adhesive layer, and a wiring board adhesive layer is formed on an upper surface of the wiring board. An elastic resin is provided between the element adhesive layer and the wiring board adhesive layer, and a concave portion is formed in the wiring substrate. During operation of the semiconductor device, the concave portion is formed inside the concave portion. A semiconductor device is provided in which a molten metal or alloy is disposed, and the connection member has a portion located in the recess of the wiring board .

前記半導体素子接着剤層及び前記配線基板接着剤層は、エポキシ系、アクリル系、シリコン系、ウレタン系の樹脂から構成される群から選択された材料から成っていてもよい。   The semiconductor element adhesive layer and the wiring board adhesive layer may be made of a material selected from the group consisting of epoxy-based, acrylic-based, silicon-based, and urethane-based resins.

前記接続部材のうち、少なくとも前記配線基板の前記凹部内に位置している部分には、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）から構成される群から選択された材料から成る表面皮膜が形成されていてもよい。また、前記金属又は合金は、錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、ガリウム（Ｇａ）、ガリウム（Ｇａ）−銀（Ａｇ）系合金、ガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、ガリウム（Ｇａ）−錫（Ｓｎ）系合金から構成される群から選択された材料から成っていてもよい。   Of the connecting member, at least a portion of the wiring board located in the recess is made of nickel (Ni) / gold (Au) or titanium (Ti) / nickel (Ni) / gold (Au). A surface film made of a material selected from the group may be formed. The metal or alloy may be tin (Sn) -bismuth (Bi) -indium (In) alloy, gallium (Ga), gallium (Ga) -silver (Ag) alloy, gallium (Ga) -zinc ( It may be made of a material selected from the group consisting of a Zn) based alloy and a gallium (Ga) -tin (Sn) based alloy.

本発明の別の観点によれば、半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材が形成されており、前記配線基板には、凹部が形成されており、前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置が提供される。   According to another aspect of the present invention, there is provided a semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face down, and a surface of the main surface of the semiconductor element that faces the wiring board. A connection member for electrically connecting the semiconductor element and the wiring board is formed. The wiring board has a recess, and the recess is formed in the recess during operation of the semiconductor device. A semiconductor device is provided in which a molten metal or alloy is disposed, and the connection member has a portion located in the recess of the wiring board.

本発明によれば、Ｌｏｗ−Ｋ材料と呼ばれる誘電率の低い材料を多層配線層の層間絶縁膜を構成する材料として用いた半導体素子が回路基板にフリップチップ実装された構造を有する半導体装置であって、温度変化に柔軟に対応して前記層間絶縁膜の破壊を防止することにより、信頼性の高い実装構造を備えた半導体装置を提供することができる。   According to the present invention, there is provided a semiconductor device having a structure in which a semiconductor element using a low dielectric constant material called Low-K material as a material constituting an interlayer insulating film of a multilayer wiring layer is flip-chip mounted on a circuit board. Thus, it is possible to provide a semiconductor device having a highly reliable mounting structure by flexibly responding to a temperature change and preventing the breakdown of the interlayer insulating film.

以下、本発明の実施の形態について説明する。   Embodiments of the present invention will be described below.

まず、本発明の実施の形態にかかる半導体装置の構造について、図５を参照して説明する。ここで、図５は、本発明の実施の形態にかかる半導体装置の概略模式図である。   First, the structure of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG. Here, FIG. 5 is a schematic diagram of the semiconductor device according to the embodiment of the present invention.

上述のように、図１乃至図４に示す例においては、半導体素子１のバンプ下地金属８の上面に外部接続用突起電極９が配設され、配線基板２０の上面には電極パッド２１が配設され、かかる電極パッド２１に半導体素子１０の外部接続用突起電極９が接続され、半導体素子１０と配線基板２０との間にアンダーフィル材２３が配設されている。   As described above, in the example shown in FIGS. 1 to 4, the external connection protruding electrode 9 is disposed on the upper surface of the bump base metal 8 of the semiconductor element 1, and the electrode pad 21 is disposed on the upper surface of the wiring substrate 20. The external connection protruding electrode 9 of the semiconductor element 10 is connected to the electrode pad 21, and an underfill material 23 is disposed between the semiconductor element 10 and the wiring substrate 20.

本発明の実施の形態にかかる半導体装置にあっては、半導体素子の配線基板への接続（実装）構造が、図１乃至図４に示す例と相違し、他の構造については、図１乃至図４に示す例と基本的に同様である。   In the semiconductor device according to the embodiment of the present invention, the connection (mounting) structure of the semiconductor element to the wiring board is different from the example shown in FIGS. This is basically the same as the example shown in FIG.

そこで、図５では、本発明の実施の形態にかかる半導体装置における半導体素子の配線基板への接続（実装）構造を主として図示し、他の構造については、図示を簡素化して説明を省略するとともに、説明を分かりやすくするために層間絶縁膜５を多層配線層３の代表として示す。また、図５（ｂ）は、図５（ａ）に示す半導体装置を温度変化がある環境におき、変形した状態を示す図である。   Therefore, FIG. 5 mainly illustrates the connection (mounting) structure of the semiconductor element to the wiring board in the semiconductor device according to the embodiment of the present invention, and the other structures are simplified in illustration and the description is omitted. For easy understanding, the interlayer insulating film 5 is shown as a representative of the multilayer wiring layer 3. FIG. 5B is a diagram illustrating a deformed state of the semiconductor device illustrated in FIG. 5A in an environment where there is a temperature change.

図５を参照するに、本発明の実施の形態にかかる半導体装置にあっては、半導体素子５０が、配線基板６０に対しフェイスダウンでフリップチップ方式にて実装されている。   Referring to FIG. 5, in the semiconductor device according to the embodiment of the present invention, the semiconductor element 50 is mounted on the wiring substrate 60 by face-down flip-chip method.

半導体素子５０にあっては、シリコン（Ｓｉ）からなる半導体基板１に所謂ウエハープロセスが適用されて、その一方の主面にトランジスタなどの能動素子、及び容量素子などの受動素子が形成され（図示せず）、更に当該半導体基板１の一方の主面上に、酸化シリコン（ＳｉＯ２）層等の絶縁層を介して多層配線層が配設されている。 In the semiconductor element 50, a so-called wafer process is applied to the semiconductor substrate 1 made of silicon (Si), and an active element such as a transistor and a passive element such as a capacitor element are formed on one main surface thereof (FIG. Further, a multilayer wiring layer is disposed on one main surface of the semiconductor substrate 1 via an insulating layer such as a silicon oxide (SiO 2 ) layer.

かかる多層配線層は、アルミニウム（Ａｌ）又は銅（Ｃｕ）等からなる配線層が層間絶縁膜５を介して複数層積層されて形成されている。なお、図５では、層間絶縁膜５を多層配線層の代表として示している。   Such a multilayer wiring layer is formed by laminating a plurality of wiring layers made of aluminum (Al), copper (Cu), or the like via an interlayer insulating film 5. In FIG. 5, the interlayer insulating film 5 is shown as a representative of the multilayer wiring layer.

層間絶縁膜５を構成する材料としては、有機樹脂、炭素を添加した酸化シリコン（ＳｉＯＣ）、フッ素がドープされたシリコンガラス（ＦＳＧ：Ｆｌｕｏｒｉｎｅ ｄｏｐｅｄ Ｓｉｌｉｃｏｎ Ｇｌａｓｓ）、ポーラスシリカ系Ｌｏｗ−ｋ材料ナノクラスタリングシリカ（ＮＣＳ： Ｎａｎｏ Ｃｌｕｓｔｅｒｉｎｇ Ｓｉｌｉｃａ）等の誘電率の低い材料（所謂Ｌｏｗ−Ｋ材料）が用いられ、配線間に形成される電気容量を低減し、電気信号の伝達の高速化が図られる。   The material constituting the interlayer insulating film 5 includes organic resin, silicon-added silicon (SiOC) added with carbon, fluorine-doped silicon glass (FSG), porous silica-based low-k material nano-clustering silica A material having a low dielectric constant (so-called Low-K material) such as (NCS: Nano Clustering Silica) is used, and the electric capacity formed between the wirings is reduced, thereby speeding up the transmission of the electric signal.

層間絶縁膜５をその代表として示している多層配線層の上部には、図１乃至図４に示す例と同様に、アルミニウム（Ａｌ）からなる電極パッド１１が複数個選択的に配設され、多層配線層を構成する配線と適宜接続されている。   A plurality of electrode pads 11 made of aluminum (Al) are selectively disposed on the upper portion of the multilayer wiring layer showing the interlayer insulating film 5 as a representative, as in the example shown in FIGS. It is appropriately connected to the wiring constituting the multilayer wiring layer.

一方、配線基板６０は、ガラスエポキシ材，ポリイミドテープ等、樹脂系材料から成り、その上面であって、半導体素子５０を配線基板６０に実装したときに前記電極パッド１１と対応する箇所に、配線基板６０を貫通しないように凹部６１が選択的に形成されている。   On the other hand, the wiring board 60 is made of a resin-based material such as a glass epoxy material or a polyimide tape, and is on the upper surface of the wiring board 60 at a position corresponding to the electrode pad 11 when the semiconductor element 50 is mounted on the wiring board 60. A recess 61 is selectively formed so as not to penetrate the substrate 60.

凹部６１は、例えば、直径を約３０μｍ、深さを約１０μｍに設定することができ、その内側に、例えば、銅（Ｃｕ）、アルミニウム（Ａｌ）、又はニッケル（Ｎｉ）等のめっきを施してもよい。   For example, the recess 61 can be set to have a diameter of about 30 μm and a depth of about 10 μm, and the inside thereof can be plated with, for example, copper (Cu), aluminum (Al), or nickel (Ni). Also good.

凹部６１内には、低融点金属又は合金６２が充填されており、凹部６１はかかる金属又は合金の溜部として機能する。具体的には、半導体装置の動作時、例えば、約７０乃至８０℃のときに溶融状態となる金属又は合金が凹部６１内に充填されている。例えば、融点が約７８．８℃である錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、融点が約２９．８℃であるガリウム（Ｇａ）、融点が約２５℃であるガリウム（Ｇａ）−銀（Ａｇ）系合金、融点が約２５℃であるガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、融点が約２０℃であるガリウム（Ｇａ）−錫（Ｓｎ）系合金等が、凹部６１内に充填されている。   The recess 61 is filled with a low melting point metal or alloy 62, and the recess 61 functions as a reservoir for the metal or alloy. Specifically, during operation of the semiconductor device, for example, the recess 61 is filled with a metal or alloy that is in a molten state at about 70 to 80 ° C. For example, a tin (Sn) -bismuth (Bi) -indium (In) alloy having a melting point of about 78.8 ° C., gallium (Ga) having a melting point of about 29.8 ° C., and a melting point of about 25 ° C. Gallium (Ga) -silver (Ag) based alloy, gallium (Ga) -zinc (Zn) based alloy having a melting point of about 25 ° C., gallium (Ga) -tin (Sn) based alloy having a melting point of about 20 ° C., etc. Is filled in the recess 61.

更に、配線基板６０の上面のうち、凹部６１内に充填された低融点金属又は合金６２の上面を除いた箇所に、例えば、エポキシ系、アクリル系、シリコン系、ウレタン系等の樹脂から成る配線基板接着層６３が設けられている。なお、配線基板接着層６３の配設箇所は、凹部６１内に充填された低融点金属又は合金６２の上面を除いた箇所である限り、凹部６１の外周部分に設けられていてもよい。   Further, in the upper surface of the wiring substrate 60, the wiring made of, for example, an epoxy-based resin, an acrylic-based resin, a silicon-based resin, a urethane-based resin, or the like, except for the upper surface of the low melting point metal or alloy 62 filled in the recess 61. A substrate adhesive layer 63 is provided. In addition, the arrangement | positioning location of the wiring board contact bonding layer 63 may be provided in the outer peripheral part of the recessed part 61, as long as it is a location except the upper surface of the low melting metal or alloy 62 with which the recessed part 61 was filled.

なお、図示を省略するが、配線基板６０の下面には、半田から成る外部接続用突起電極がグリッド状に複数配設されている。   Although not shown, a plurality of external connection protruding electrodes made of solder are arranged in a grid on the lower surface of the wiring board 60.

このような構造を有する半導体素子５０は配線基板６０に以下のように実装されている。   The semiconductor element 50 having such a structure is mounted on the wiring board 60 as follows.

半導体素子５０において、層間絶縁膜５をその代表として示している多層配線層の上面には、例えば、エポキシ系、アクリル系、シリコン系、ウレタン系等の樹脂から成る半導体素子接着剤層５１が設けられている。なお、半導体素子接着剤層５１を構成する材料は、上述の配線基板６０の上面に設けられた配線基板接着層６３と同じ材料であっても、異なる材料であってもよい。   In the semiconductor element 50, a semiconductor element adhesive layer 51 made of, for example, an epoxy, acrylic, silicon, or urethane resin is provided on the upper surface of the multilayer wiring layer showing the interlayer insulating film 5 as a representative example. It has been. The material constituting the semiconductor element adhesive layer 51 may be the same material as or different from the wiring substrate adhesive layer 63 provided on the upper surface of the wiring substrate 60 described above.

また、かかる半導体素子接着剤層５１中において前記電極パッド１１に対応する箇所には、錫（Ｓｎ）を主体を主体とする半田層５２がそれぞれ設けられている。   Further, solder layers 52 mainly composed of tin (Sn) are provided at locations corresponding to the electrode pads 11 in the semiconductor element adhesive layer 51.

更に、各半田層５２上には、略二段構造になっている接続部材である接続ピン５３が例えば、約１００μｍピッチで設けられている。接続ピン５３は、例えば、電鋳法、放電加工等によって形成され、銅（Ｃｕ）、金（Ａｕ）、鉛（Ｐｄ）、又はこれらの合金から構成される。   Furthermore, on each solder layer 52, connection pins 53, which are connection members having a substantially two-stage structure, are provided at a pitch of about 100 μm, for example. The connection pin 53 is formed by, for example, electroforming, electric discharge machining, or the like, and is made of copper (Cu), gold (Au), lead (Pd), or an alloy thereof.

接続ピン５３は、例えば約２０乃至３０μｍの径を有する台座部５３−１上に、例えば径が約１０μｍで鉛直方向の長さが約４０μｍの接続部５３−２が設けられた略二段構造になっている。但し、本発明では、接続ピン５３の形状・大きさについてはこの例に限定されない。   The connection pin 53 has a substantially two-stage structure in which, for example, a connection part 53-2 having a diameter of about 10 μm and a vertical length of about 40 μm is provided on a pedestal part 53-1 having a diameter of about 20 to 30 μm. It has become. However, in the present invention, the shape and size of the connection pin 53 are not limited to this example.

接続ピン５３の接続部５３−２の端部側は、上述の低融点金属又は合金６２が充填された配線基板６０の凹部６１内に位置しており、低融点金属又は合金６２及び前記半田層５２と相俟って、半導体素子５０と配線基板６０とが電気的に接続されている。   The end side of the connection portion 53-2 of the connection pin 53 is located in the recess 61 of the wiring board 60 filled with the above-described low melting point metal or alloy 62, and the low melting point metal or alloy 62 and the solder layer. In combination with 52, the semiconductor element 50 and the wiring substrate 60 are electrically connected.

接続ピン５３にあっては、必要に応じ、少なくとも接続部５３−２の端部側のうち、配線基板６０の凹部６１内に充填された低融点金属又は合金６２と接触する箇所に、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）等の腐食防止用の表面皮膜が設けられていてもよい。   In the connection pin 53, if necessary, at least on the end side of the connection portion 53-2, nickel (in the place of contact with the low melting point metal or alloy 62 filled in the recess 61 of the wiring substrate 60 is provided. A surface film for preventing corrosion such as Ni) / gold (Au) or titanium (Ti) / nickel (Ni) / gold (Au) may be provided.

更に、半導体素子接着剤層５１と配線基板６０の上面に設けられた配線基板接着層６３との間には、例えば、シリコン系、ウレタンゴム系等のゴム系の樹脂から成る弾性体樹脂６４が設けられている。   Further, between the semiconductor element adhesive layer 51 and the wiring board adhesive layer 63 provided on the upper surface of the wiring board 60, for example, an elastic resin 64 made of a rubber-based resin such as silicon-based or urethane rubber-based resin. Is provided.

即ち、上述の接続ピン５３によって、半導体素子５０と配線基板６０とが電気的に接続されている一方、弾性体樹脂６４が、半導体素子５０の主面のうち配線基板６０に対向する面に設けられた半導体素子接着剤層５１と、配線基板６０の上面に設けられた配線基板接着層６３と、に挟持され接着されたサンドイッチ（三層）構造が形成され、弾性体樹脂６４により、半導体素子５０と配線基板６０とが機械的に柔軟に接続されている。   That is, the semiconductor element 50 and the wiring board 60 are electrically connected by the connection pins 53 described above, while the elastic resin 64 is provided on the surface of the semiconductor element 50 facing the wiring board 60. A sandwich (three-layer) structure sandwiched between and bonded to the semiconductor element adhesive layer 51 thus formed and the wiring board adhesive layer 63 provided on the upper surface of the wiring board 60 is formed. 50 and the wiring board 60 are mechanically flexibly connected.

上述のように半導体装置を構成する各部材の熱膨張係数は相違するが、かかる構造により、図５（ｂ）に示すように、温度変化がある環境下において熱膨張係数の相違に因って生ずる歪みを、柔軟なゴム系の樹脂から成る弾性体樹脂６４及び／又は配線基板６０の凹部６１内に充填され半導体装置の動作時に溶融状態となる低融点金属又は合金６２によって、吸収することができる。   As described above, the thermal expansion coefficients of the respective members constituting the semiconductor device are different, but due to such a structure, as shown in FIG. 5B, due to the difference in thermal expansion coefficient in an environment where there is a temperature change. The generated strain can be absorbed by the elastic resin 64 made of a flexible rubber-based resin and / or the low melting point metal or alloy 62 that is filled in the recess 61 of the wiring board 60 and is in a molten state when the semiconductor device is operated. it can.

本発明の発明者のシミュレーション結果によれば、図４に示す構造のように、半導体素子１０と配線基板２０との間にエポキシ系樹脂等から成るアンダーフィル材２３を配設した半田バンプ９によるフリップチップ接合の場合には、４０００端子のエリアアレイを有し１辺が２０ｍｍの矩形の半導体素子１０の略中央において約８乃至１０ＭＰａの応力が発生するところ、本実施の形態に示す弾性体樹脂６４が半導体素子接着剤層５１と配線基板接着層６３とに挟持された構造の場合、前記応力を約５乃至６ＭＰａに低減することが把握された。   According to the simulation result of the inventor of the present invention, as shown in FIG. 4, the solder bump 9 is provided with an underfill material 23 made of epoxy resin or the like between the semiconductor element 10 and the wiring board 20. In the case of flip chip bonding, a stress of about 8 to 10 MPa is generated in the approximate center of a rectangular semiconductor element 10 having an area array of 4000 terminals and a side of 20 mm. The elastic resin shown in the present embodiment In the case where the structure 64 is sandwiched between the semiconductor element adhesive layer 51 and the wiring board adhesive layer 63, it has been found that the stress is reduced to about 5 to 6 MPa.

また、半導体装置の動作時に溶融状態となる低融点金属又は合金６２を配線基板６０の凹部６１内に充填した構造の場合、前記応力は約０．８ＭＰａに低減することが把握された。   Further, it has been found that the stress is reduced to about 0.8 MPa in the case of a structure in which the low melting point metal or alloy 62 that is in a molten state during operation of the semiconductor device is filled in the recess 61 of the wiring board 60.

更に、本実施の形態のように、弾性体樹脂６４が半導体素子接着剤層５１と配線基板接着層６３とに挟持され、半導体装置の動作時に溶融状態となる低融点金属又は合金６２を配線基板６０の凹部６１内に充填した構造の場合、前記応力を約２乃至３ＭＰａに低減することが把握された。   Further, as in the present embodiment, the elastic resin 64 is sandwiched between the semiconductor element adhesive layer 51 and the wiring board adhesive layer 63, and the low melting point metal or alloy 62 that is in a molten state during the operation of the semiconductor device is used as the wiring board. In the case of a structure filled in 60 recesses 61, it was found that the stress was reduced to about 2 to 3 MPa.

このように、本実施の形態によれば、誘電率の低い材料（所謂Ｌｏｗ−Ｋ材料）から成り強度が低い層間絶縁膜５が半導体素子５０の半導体基板１の上面に設けられていても、温度変化に因りクラックが発生してしまうことを防止することができる。従って、温度変化に対しても柔軟に追随することができ、層間絶縁膜５の破壊を防止することができる。よって、信頼性の高い実装構造を提供することができる。   Thus, according to the present embodiment, even if the interlayer insulating film 5 made of a low dielectric constant material (so-called Low-K material) and having low strength is provided on the upper surface of the semiconductor substrate 1 of the semiconductor element 50, It is possible to prevent cracks from occurring due to temperature changes. Therefore, it is possible to flexibly follow the temperature change and prevent the interlayer insulating film 5 from being broken. Therefore, a highly reliable mounting structure can be provided.

次に、本発明の実施の形態にかかる半導体装置の製造方法を、図６を参照して説明する。ここで、図６は、図５に示す半導体装置の製造方法を説明するための図である。   Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. Here, FIG. 6 is a diagram for explaining a method of manufacturing the semiconductor device shown in FIG.

まず、図６（ａ）に示すように、キャリア電極（導電層）に、銅（Ｃｕ）、金（Ａｕ）、鉛（Ｐｄ）、又はこれらの合金から構成される接続ピン５３を約１００μｍピッチで形成する。   First, as shown in FIG. 6 (a), connection pins 53 made of copper (Cu), gold (Au), lead (Pd), or an alloy thereof are formed on the carrier electrode (conductive layer) at a pitch of about 100 μm. Form with.

接続ピン５３は、略二段構造に形成され、例えば約２０乃至３０μｍの径を有する台座部５３−１上に、例えば径が約１０μｍで鉛直方向の長さが約４０μｍの接続部５３−２が設けられた形状を有する。但し、本発明では、接続ピン５３の形状・大きさについてはこの例に限定されない。   The connection pin 53 is formed in a substantially two-stage structure, for example, on a pedestal portion 53-1 having a diameter of about 20 to 30 μm, for example, a connection portion 53-2 having a diameter of about 10 μm and a vertical length of about 40 μm. Is provided. However, in the present invention, the shape and size of the connection pin 53 are not limited to this example.

なお、少なくとも接続部５３−２の端部側のうち、配線基板６０の凹部６１内に充填された低融点金属又は合金６２と接触する箇所に、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）等の腐食防止用の表面皮膜が設けられていてもよい。   It should be noted that nickel (Ni) / gold (Au) or titanium (at least in the end portion side of the connection portion 53-2 is in contact with the low melting point metal or alloy 62 filled in the recess 61 of the wiring board 60. A surface coating for preventing corrosion such as Ti) / nickel (Ni) / gold (Au) may be provided.

次いで、図６（ｂ）に示すように、接続ピン５３が設けられたキャリア電極（導電層）上にシリコン系、ウレタンゴム系等のゴム系の樹脂から成り、例えば、厚さが約３０μｍの弾性体樹脂６４を形成する。更に、当該弾性体樹脂６４の上に、レジスト６０を形成する。   Next, as shown in FIG. 6B, the carrier electrode (conductive layer) provided with the connection pin 53 is made of a rubber-based resin such as silicon-based or urethane rubber-based, and has a thickness of about 30 μm, for example. An elastic resin 64 is formed. Further, a resist 60 is formed on the elastic resin 64.

次いで、図６（ｃ）に示すように、図６（ｂ）に示す構造を反転し、エッチングにより前記キャリア電極を除去するとともに、レジスト６０を剥離する。   Next, as shown in FIG. 6C, the structure shown in FIG. 6B is reversed, the carrier electrode is removed by etching, and the resist 60 is peeled off.

しかる後、図６（ｄ）に示すように、接続ピン５３の台座部５３−１の上面に、錫（Ｓｎ）を主体とする半田層５２をめっき法で形成する。ここで、半田層５２は、接続ピン５３の接続部５３−２よりも幅広の台座部５３−１に設けられるため、容易に半田層５２を形成することができる。   Thereafter, as shown in FIG. 6D, a solder layer 52 mainly composed of tin (Sn) is formed on the upper surface of the pedestal portion 53-1 of the connection pin 53 by a plating method. Here, since the solder layer 52 is provided on the base portion 53-1, which is wider than the connection portion 53-2 of the connection pin 53, the solder layer 52 can be easily formed.

更に、弾性体樹脂６４の上面であって、前記半田層５２が配設されていない箇所に、エポキシ系、アクリル系、シリコン系、ウレタン系等の樹脂から成る半導体素子接着剤層５１を形成する。   Further, a semiconductor element adhesive layer 51 made of an epoxy-based resin, an acrylic-based resin, a silicon-based resin, a urethane-based resin, or the like is formed on the upper surface of the elastic body resin 64 where the solder layer 52 is not disposed. .

次いで、図６（ｅ）に示すように、層間絶縁膜５をその代表として示している半導体素子５０の多層配線層の上部に設けられたアルミニウム（Ａｌ）から成る電極パッド１１が設けられた面を下向き（フェイスダウン）にして、当該電極パッド１１が半田層５２に接合するように、半導体素子５０を半導体素子接着剤層５１上に接着する。   Next, as shown in FIG. 6E, the surface provided with the electrode pad 11 made of aluminum (Al) provided on the upper part of the multilayer wiring layer of the semiconductor element 50 showing the interlayer insulating film 5 as a representative thereof. The semiconductor element 50 is bonded onto the semiconductor element adhesive layer 51 so that the electrode pad 11 is bonded to the solder layer 52 with face down.

一方、図６（ｆ）に示すように、例えばガラスエポキシ材，ポリイミドテープ等、樹脂系材料から成る配線基板６０にあっては、その上面に、半導体素子５０を配線基板６０に実装したときに接続ピン５３の接続部５３−２が内設できるように、例えば機械的手法等により、配線基板６０を貫通しない凹部６１を形成する。   On the other hand, as shown in FIG. 6F, for example, in the wiring board 60 made of a resin-based material such as glass epoxy material or polyimide tape, when the semiconductor element 50 is mounted on the wiring board 60 on the upper surface thereof. The concave portion 61 that does not penetrate the wiring board 60 is formed by, for example, a mechanical method so that the connection portion 53-2 of the connection pin 53 can be provided.

このとき、凹部６１を、例えば、直径が約３０μｍであり、深さが約１０μｍに設定することができ、その内側に、例えば、銅（Ｃｕ）、アルミニウム（Ａｌ）、又はニッケル（Ｎｉ）等のめっきを施してもよい。   At this time, for example, the recess 61 can be set to have a diameter of about 30 μm and a depth of about 10 μm, and inside thereof, for example, copper (Cu), aluminum (Al), nickel (Ni), or the like Plating may be performed.

次いで、図６（ｇ）に示すように、凹部６１内には、低融点金属又は合金６２をシリンジ等により充填する。   Next, as shown in FIG. 6G, the recess 61 is filled with a low melting point metal or alloy 62 with a syringe or the like.

具体的には、半導体装置の動作時、例えば、約７０乃至８０℃のときに溶融状態となる金属又は合金が凹部６１内に充填する。例えば、融点が約７８．８℃である錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、融点が約２９．８℃であるガリウム（Ｇａ）、融点が約２５℃であるガリウム（Ｇａ）−銀（Ａｇ）系合金、融点が約２５℃であるガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、融点が約２０℃であるガリウム（Ｇａ）−錫（Ｓｎ）系合金等を、凹部６１内に充填する。   Specifically, during operation of the semiconductor device, for example, a metal or alloy that is in a molten state at about 70 to 80 ° C. is filled in the recess 61. For example, a tin (Sn) -bismuth (Bi) -indium (In) alloy having a melting point of about 78.8 ° C., gallium (Ga) having a melting point of about 29.8 ° C., and a melting point of about 25 ° C. Gallium (Ga) -silver (Ag) based alloy, gallium (Ga) -zinc (Zn) based alloy having a melting point of about 25 ° C., gallium (Ga) -tin (Sn) based alloy having a melting point of about 20 ° C., etc. Is filled in the recess 61.

次いで、図６（ｈ）に示すように、配線基板６０の上面のうち、凹部６１内に充填された低融点金属又は合金６２の上面を除いた箇所に、例えば、エポキシ系、アクリル系、シリコン系、ウレタン系等の樹脂から成る配線基板接着層６３を塗布する。具体的には、マスクを施して印刷又は露光等の周知の方法により、配線基板接着層６３を選択的に形成する。   Next, as shown in FIG. 6 (h), in the upper surface of the wiring board 60, except for the upper surface of the low melting point metal or alloy 62 filled in the recess 61, for example, epoxy-based, acrylic-based, silicon A wiring substrate adhesive layer 63 made of a resin such as a urethane or urethane resin is applied. Specifically, the wiring board adhesive layer 63 is selectively formed by applying a mask and using a known method such as printing or exposure.

なお、配線基板接着層６３の配設箇所は、凹部６１内に充填された低融点金属又は合金６２の上面を除いた箇所である限り、凹部６１の外周部分に設けられていてもよい。   In addition, the arrangement | positioning location of the wiring board contact bonding layer 63 may be provided in the outer peripheral part of the recessed part 61, as long as it is a location except the upper surface of the low melting metal or alloy 62 with which the recessed part 61 was filled.

しかる後、図６（ｅ）に示す半導体素子５０と、図６（ｈ）に示す配線基板６０とを加熱接合し、半導体素子５０の配線基板６０への接続（実装）が完成となる。即ち、接続ピン５３によって、半導体素子５０と配線基板６０とが電気的に接続されている一方、弾性体樹脂６４が、半導体素子５０の主面のうち配線基板６０に対向する面に設けられた半導体素子接着剤層５１と、配線基板６０の上面に設けられた配線基板接着層６３と、に挟持され接着されたサンドイッチ構造が形成され、弾性体樹脂６４により、半導体素子５０と配線基板６０とが機械的に柔軟に接続された構造が形成される。   Thereafter, the semiconductor element 50 shown in FIG. 6 (e) and the wiring board 60 shown in FIG. 6 (h) are heat-bonded to complete the connection (mounting) of the semiconductor element 50 to the wiring board 60. That is, the semiconductor element 50 and the wiring board 60 are electrically connected by the connection pins 53, while the elastic resin 64 is provided on the surface of the main surface of the semiconductor element 50 that faces the wiring board 60. A sandwich structure sandwiched and bonded between the semiconductor element adhesive layer 51 and the wiring board adhesive layer 63 provided on the upper surface of the wiring board 60 is formed. The elastic resin 64 allows the semiconductor element 50 and the wiring board 60 to be bonded together. Are mechanically and flexibly connected.

最後に、図示を省略するが、配線基板６０の下面に半田ボールをグリッド状に複数搭載し、リフロー加熱工程及び冷却工程を経て、外部接続用突起電極を接続し、半導体装置が完成となる。   Finally, although not shown in the drawing, a plurality of solder balls are mounted on the lower surface of the wiring board 60 in a grid shape, and through the reflow heating process and the cooling process, the external connection protruding electrodes are connected, and the semiconductor device is completed.

以上、本発明の実施の形態について詳述したが、本発明は特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形及び変更が可能である。   Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are within the scope of the gist of the present invention described in the claims. It can be changed.

以上の説明に関し、更に以下の項を開示する。
（付記１） 半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、
前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材と、半導体素子接着剤層と、が形成され、
前記配線基板の上面には、配線基板接着剤層が形成され、
前記半導体素子接着剤層と前記配線基板接着剤層との間に、弾性体樹脂が設けられていることを特徴とする半導体装置。
（付記２） 付記１記載の半導体装置であって、
前記弾性体樹脂は、ゴム系樹脂から成ることを特徴とする半導体装置。
（付記３） 付記１又は２記載の半導体装置であって、
前記半導体素子接着剤層及び前記配線基板接着剤層は、エポキシ系、アクリル系、シリコン系、ウレタン系の樹脂から構成される群から選択された材料から成ることを特徴とする半導体装置。
（付記４） 付記１乃至３いずれか一項記載の半導体装置であって、
前記接続部材は、前記半導体素子の電極上に設けられていることを特徴とする半導体装置。
（付記５） 付記１乃至４いずれか一項記載の半導体装置であって、
前記接続部材は、銅（Ｃｕ）、金（Ａｕ）、鉛（Ｐｄ）、又はこれらの合金から構成される群から選択された材料から成ることを特徴とする半導体装置。
（付記６） 付記５記載の半導体装置であって、
前記接続部材は、電鋳法又は放電加工により形成されることを特徴とする半導体装置。
（付記７） 付記１乃至６いずれか一項記載の半導体装置であって、
前記配線基板には、凹部が形成されており、
前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、
前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置。
（付記８） 付記７記載の半導体装置であって、
前記接続部材のうち、少なくとも前記配線基板の前記凹部内に位置している部分には、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）から構成される群から選択された材料から成る表面皮膜が形成されていることを特徴とする半導体装置。
（付記９） 付記７又は８記載の半導体装置であって、
前記金属又は合金は、錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、ガリウム（Ｇａ）、ガリウム（Ｇａ）−銀（Ａｇ）系合金、ガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、ガリウム（Ｇａ）−錫（Ｓｎ）系合金から構成される群から選択された材料から成ることを特徴とする半導体装置。
（付記１０） 半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、
前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材が形成されており、
前記配線基板には、凹部が形成されており、
前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、
前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置。
（付記１１） 付記１０記載の半導体装置であって、
前記金属又は合金は、錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、ガリウム（Ｇａ）、ガリウム（Ｇａ）−銀（Ａｇ）系合金、ガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、ガリウム（Ｇａ）−錫（Ｓｎ）系合金から構成される群から選択された材料から成ることを特徴とする半導体装置。
（付記１２） 付記１０又は１１記載の半導体装置であって、
前記接続部材は、前記半導体素子の電極上に設けられていることを特徴とする半導体装置。
（付記１３） 付記１０乃至１２いずれか一項記載の半導体装置であって、
前記接続部材は、銅（Ｃｕ）、金（Ａｕ）、鉛（Ｐｄ）、又はこれらの合金から構成される群から選択された材料から成ることを特徴とする半導体装置。
（付記１４） 付記１３記載の半導体装置であって、
前記接続部材は、電鋳法又は放電加工により形成されることを特徴とする半導体装置。
（付記１５） 付記１０乃至１４記載の半導体装置であって、
前記接続部材のうち、少なくとも前記配線基板の前記凹部内に位置している部分には、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）から構成される群から選択された材料から成る表面皮膜が形成されていることを特徴とする半導体装置。 Regarding the above description, the following items are further disclosed.
(Appendix 1) A semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face down,
Of the main surface of the semiconductor element, a surface facing the wiring board is formed with a connection member for electrically connecting the semiconductor element and the wiring board, and a semiconductor element adhesive layer,
A wiring board adhesive layer is formed on the upper surface of the wiring board,
An elastic resin is provided between the semiconductor element adhesive layer and the wiring board adhesive layer.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein
The semiconductor device, wherein the elastic resin is made of a rubber-based resin.
(Additional remark 3) It is a semiconductor device of Additional remark 1 or 2, Comprising:
The semiconductor device adhesive layer and the wiring board adhesive layer are made of a material selected from the group consisting of epoxy-based, acrylic-based, silicon-based, and urethane-based resins.
(Appendix 4) A semiconductor device according to any one of appendices 1 to 3,
The semiconductor device, wherein the connection member is provided on an electrode of the semiconductor element.
(Appendix 5) A semiconductor device according to any one of appendices 1 to 4,
The connection member is made of a material selected from the group consisting of copper (Cu), gold (Au), lead (Pd), or an alloy thereof.
(Supplementary note 6) The semiconductor device according to supplementary note 5, wherein
The connection member is formed by electroforming or electric discharge machining.
(Appendix 7) A semiconductor device according to any one of appendices 1 to 6,
The wiring board has a recess,
A metal or alloy that is in a molten state during operation of the semiconductor device is disposed inside the recess,
The semiconductor device according to claim 1, wherein the connection member has a portion located in the recess of the wiring board.
(Appendix 8) A semiconductor device according to appendix 7,
Of the connecting member, at least a portion of the wiring board located in the recess is made of nickel (Ni) / gold (Au) or titanium (Ti) / nickel (Ni) / gold (Au). A semiconductor device characterized in that a surface film made of a material selected from the group is formed.
(Supplementary note 9) The semiconductor device according to supplementary note 7 or 8, wherein
The metal or alloy includes tin (Sn) -bismuth (Bi) -indium (In) alloy, gallium (Ga), gallium (Ga) -silver (Ag) alloy, gallium (Ga) -zinc (Zn). A semiconductor device comprising a material selected from the group consisting of a gallium-based alloy and a gallium (Ga) -tin (Sn) -based alloy.
(Supplementary Note 10) A semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face down,
A connection member that electrically connects the semiconductor element and the wiring board is formed on a surface of the main surface of the semiconductor element that faces the wiring board.
The wiring board has a recess,
A metal or alloy that is in a molten state during operation of the semiconductor device is disposed inside the recess,
The semiconductor device according to claim 1, wherein the connection member has a portion located in the recess of the wiring board.
(Supplementary note 11) The semiconductor device according to supplementary note 10,
The metal or alloy includes tin (Sn) -bismuth (Bi) -indium (In) alloy, gallium (Ga), gallium (Ga) -silver (Ag) alloy, gallium (Ga) -zinc (Zn). A semiconductor device comprising a material selected from the group consisting of a gallium-based alloy and a gallium (Ga) -tin (Sn) -based alloy.
(Supplementary note 12) The semiconductor device according to supplementary note 10 or 11, wherein
The semiconductor device, wherein the connection member is provided on an electrode of the semiconductor element.
(Supplementary note 13) The semiconductor device according to any one of supplementary notes 10 to 12,
The connection member is made of a material selected from the group consisting of copper (Cu), gold (Au), lead (Pd), or an alloy thereof.
(Supplementary note 14) The semiconductor device according to supplementary note 13, wherein
The connection member is formed by electroforming or electric discharge machining.
(Supplementary note 15) The semiconductor device according to supplementary notes 10 to 14,
Of the connecting member, at least a portion of the wiring board located in the recess is made of nickel (Ni) / gold (Au) or titanium (Ti) / nickel (Ni) / gold (Au). A semiconductor device characterized in that a surface film made of a material selected from the group is formed.

半導体素子の構造を示す断面図である。It is sectional drawing which shows the structure of a semiconductor element. 図１において点線で囲まれた箇所の拡大図である。FIG. 2 is an enlarged view of a portion surrounded by a dotted line in FIG. 1. 図１に示す半導体素子を配線基板にフリップチップ実装した状態を示す図である。It is a figure which shows the state which carried out the flip chip mounting of the semiconductor element shown in FIG. 図３に示す半導体装置の問題点を説明するための概略模式図である。FIG. 4 is a schematic diagram for explaining problems of the semiconductor device shown in FIG. 3. 本発明の実施の形態にかかる半導体装置における半導体素子の配線基板への接続（実装）構造を示す図である。It is a figure which shows the connection (mounting) structure to the wiring board of the semiconductor element in the semiconductor device concerning embodiment of this invention. 図５に示す半導体装置の製造方法を説明するための図である。FIG. 6 is a diagram for explaining a manufacturing method of the semiconductor device shown in FIG. 5.

符号の説明Explanation of symbols

１１ 電極パッド
５０ 半導体素子
５１ 半導体素子接着剤層
５２ 半田層
５３ 接続ピン
６０ 配線基板
６１ 凹部
６２ 低融点金属又は合金
６３ 配線基板接着剤層
６４ 弾性体樹脂 11 Electrode Pad 50 Semiconductor Element 51 Semiconductor Element Adhesive Layer 52 Solder Layer 53 Connection Pin 60 Wiring Board 61 Recess 62 Low Melting Point Metal or Alloy 63 Wiring Board Adhesive Layer 64 Elastic Body Resin

Claims (5)

半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、
前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材と、半導体素子接着剤層と、が形成され、
前記配線基板の上面には、配線基板接着剤層が形成され、
前記半導体素子接着剤層と前記配線基板接着剤層との間に、弾性体樹脂が設けられており、
前記配線基板には、凹部が形成されており、
前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、
前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置。 A semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face down,
Of the main surface of the semiconductor element, a surface facing the wiring board is formed with a connection member for electrically connecting the semiconductor element and the wiring board, and a semiconductor element adhesive layer,
A wiring board adhesive layer is formed on the upper surface of the wiring board,
An elastic resin is provided between the semiconductor element adhesive layer and the wiring board adhesive layer ,
The wiring board has a recess,
A metal or alloy that is in a molten state during operation of the semiconductor device is disposed inside the recess,
The semiconductor device according to claim 1, wherein the connection member has a portion located in the recess of the wiring board . 請求項１記載の半導体装置であって、
前記半導体素子接着剤層及び前記配線基板接着剤層は、エポキシ系、アクリル系、シリコン系、ウレタン系の樹脂から構成される群から選択された材料から成ることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device adhesive layer and the wiring board adhesive layer are made of a material selected from the group consisting of epoxy-based, acrylic-based, silicon-based, and urethane-based resins. 請求項１又は２記載の半導体装置であって、
前記接続部材のうち、少なくとも前記配線基板の前記凹部内に位置している部分には、ニッケル（Ｎｉ）／金（Ａｕ）又はチタン（Ｔｉ）／ニッケル（Ｎｉ）／金（Ａｕ）から構成される群から選択された材料から成る表面皮膜が形成されていることを特徴とする半導体装置。 A semiconductor device according to claim 1 or 2 ,
Of the connecting member, at least a portion of the wiring board located in the recess is made of nickel (Ni) / gold (Au) or titanium (Ti) / nickel (Ni) / gold (Au). A semiconductor device characterized in that a surface film made of a material selected from the group is formed. 請求項１乃至３のいずれか一項記載の半導体装置であって、
前記金属又は合金は、錫（Ｓｎ）−ビスマス（Ｂｉ）−インジウム（Ｉｎ）系の合金、ガリウム（Ｇａ）、ガリウム（Ｇａ）−銀（Ａｇ）系合金、ガリウム（Ｇａ）−亜鉛（Ｚｎ）系合金、ガリウム（Ｇａ）−錫（Ｓｎ）系合金から構成される群から選択された材料から成ることを特徴とする半導体装置。 A semiconductor device according to any one of claims 1 to 3 ,
The metal or alloy includes tin (Sn) -bismuth (Bi) -indium (In) alloy, gallium (Ga), gallium (Ga) -silver (Ag) alloy, gallium (Ga) -zinc (Zn). A semiconductor device comprising a material selected from the group consisting of a gallium-based alloy and a gallium (Ga) -tin (Sn) -based alloy. 半導体素子がフェイスダウンで配線基板にフリップチップ接続された構造を備えた半導体装置であって、
前記半導体素子の主面のうち、前記配線基板に対向する面には、前記半導体素子と前記配線基板とを電気的に接続する接続部材が形成されており、
前記配線基板には、凹部が形成されており、
前記凹部の内部に、当該半導体装置の動作時に溶融状態となる金属又は合金が配設され、
前記接続部材は、前記配線基板の前記凹部内に位置している部分を有することを特徴とする半導体装置。 A semiconductor device having a structure in which a semiconductor element is flip-chip connected to a wiring board face down,
A connection member that electrically connects the semiconductor element and the wiring board is formed on a surface of the main surface of the semiconductor element that faces the wiring board.
The wiring board has a recess,
A metal or alloy that is in a molten state during operation of the semiconductor device is disposed inside the recess,
The semiconductor device according to claim 1, wherein the connection member has a portion located in the recess of the wiring board.
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