JP4846834B2 - Capacitive touch panel - Google Patents

Description

  The present invention relates to a capacitive touch panel that detects an input operation position from an arrangement position of a detection electrode in which stray capacitance increases when an input operation body such as a finger approaches, and more specifically, while waiting for an input operation. The present invention also relates to a capacitive touch panel that operates in a sleep mode with low power consumption.

  As a pointing device for pointing and inputting icons, etc. displayed on the display of electronic devices, the input operation position is detected in a non-contact manner using the change in capacitance caused by the input operation body such as a finger approaching the input operation surface. However, a capacitive touch panel that can detect an input operation even if it is arranged on the back side of the display is used.

  In the conventional capacitive touch panel, a large number of X-side electrodes and Y-side electrodes are formed in a matrix shape so as to intersect each other on the front and back of the insulating substrate, and each of the intersections in the vicinity where an input operation body such as a finger is brought close Since the capacitance between the X-side electrode and the Y-side electrode changes, the operation position on the insulating substrate by the input operation body has been detected (Patent Document 1).

  In this capacitive touch panel 100, as shown in FIG. 7, scanning is performed by sequentially applying a predetermined pulse voltage to a large number of Y-side electrodes 101, and a pulse voltage is being applied to each Y-side electrode 101. In addition, the voltage of each X-side electrode 102 that intersects the Y-side electrode 101 to which the pulse voltage is applied is detected. When an input operation body such as a finger is brought close to the insulating substrate, the electrostatic capacity between the X-side electrode 102 and the Y-side electrode 101 that intersect at the position where the input operation body approaches is changed. The input operation position on the insulating substrate of the input operation body is detected by the arrangement position of the X-side electrode 102 whose voltage has changed due to the change in capacitance and the Y-side electrode 101 to which the pulse voltage is applied at that time.

  However, in order to detect an input operation from a change in capacitance, it is necessary to sequentially apply a predetermined pulse voltage to a large number of Y-side electrodes 101, and even during standby when no input operation is performed, Since the pulse voltage is continuously generated, the power consumption is large and the battery is consumed quickly. Therefore, it cannot be used as a pointing device for portable equipment such as a mobile phone.

  Therefore, when there is no input operation for a certain period, the operation shifts to the sleep mode in which the operation of the input operation position detection means for detecting the input operation position is stopped, and in the sleep mode, only the input determination means for detecting the input operation is operated and input There is provided a capacitance type sensor that returns to a normal mode in which an input operation position detecting means is operated again when an operation is detected (Patent Document 2).

  The capacitance sensor 200 will be described with reference to FIG. 8. A displacement electrode 202 is fixed to the bottom side of the operation button 201 for performing an input operation, and a fan-shaped capacitance is formed on the insulating substrate 203 facing the displacement electrode 202. The device electrodes E1 to E4 (only E1 and E2 are shown) are arranged at intervals of 90 degrees, and the return switch electrodes E11 and E12 are arranged in a ring shape around the device electrodes.

  In the normal mode in which the input operation position is detected, a periodic signal is input to the capacitive element electrodes E1 to E4, and the operation button 201 is inclined and pushed down in the direction of the input operation position, so that the displacement electrode 202 and the capacitive element electrode Changes in the capacitance values of the capacitive elements C1 to C4 configured between E1 and E4 are detected, and an input operation position indicating the direction of the force applied to the operation button 31 is detected.

  In addition, when the capacitance values of the capacitive elements C1 to C4 do not change for a certain period, it is assumed that the input operation to the operation button 201 has not been performed, and the periodic signal is input to the capacitive element electrodes E1 to E4. Stops and shifts to a sleep mode in which only the contact between the return switch electrodes E11 and E12 is detected. Therefore, power consumption in this sleep mode is reduced. When there is an input operation for depressing the operation button 201 in the sleep mode waiting for an input operation, the return switch electrodes E11 and E12 are formed in a ring shape in the periphery regardless of the direction in which the operation button 201 is inclined and depressed. Are connected via the displacement electrode 202, the input operation is detected, and the normal mode is restored.

JP 2005-337773 A (Items 0017 to 0031 of the specification, FIG. 1) JP 2004-20210 A (Items 0047 to 60 of the specification, FIG. 5)

  The capacitive touch panel 100 disclosed in Patent Document 1 requires scanning that sequentially applies a predetermined pulse voltage to a large number of electrodes in order to detect an input operation body such as a finger from a change in capacitance. In addition, power consumption is large, and it cannot be provided in a portable device that operates with a limited battery capacity.

  In sleep mode waiting for input operation, it is conceivable to perform a scan to apply a pulse voltage to a large number of electrodes in an intermittent operation to reduce power consumption, but apply a pulse voltage to a large number of electrodes in order, For each electrode to which an individual pulse voltage is applied, it is necessary to detect a change in electrostatic capacitance with the electrode intersecting with the electrode, so the input operation cannot be detected in a short time. For example, a sufficient pause time could not be taken within a period of 100 msec for reliable detection, and power consumption could not be reduced.

  In order to detect an input operation in the sleep mode, the capacitive sensor 200 disclosed in Patent Document 2 is provided with a mechanical switch that connects the return switch electrodes E11 and E12 by depressing the operation button 201. Therefore, the non-contact input operation cannot be detected, so that it cannot be arranged below the display element or the like.

  In addition to the capacitive element electrodes E1 to E4 for detecting the input operation position, return switch electrodes E11 and E12 for detecting the input operation need to be separately arranged, and any input of the operation button 201 is required. Since the operation position must be detected even if it is an input operation, the return switch electrodes E11 and E12 are disposed so as to surround the capacitive element electrodes E1 to E4 in a ring shape. There was a problem.

  Therefore, a capacitive touch panel that detects an input operation in a non-contact manner is in a non-contact state in a short time even though it is desired to use a sleep mode during standby when no input operation is performed to prevent battery consumption. Since there is no means for detecting the input operation, a capacitive touch panel that waits for the input operation in the low power consumption sleep mode cannot be realized.

  The present invention has been made in consideration of such conventional problems, and can detect a non-contact input operation in a short time, and therefore can operate in a low power consumption sleep mode while waiting for the input operation. An object is to provide a capacitive touch panel.

  It is another object of the present invention to provide a capacitive touch panel that detects an input operation in a sleep mode using detection electrodes for detecting an input operation position in a normal mode.

In order to achieve the above-described object, a capacitive touch panel according to claim 1 includes a plurality of detection electrodes arranged on an insulating panel so as to be insulated from each other, and a stray capacitance of at least one detection electrode of the plurality of detection electrodes. from increasing, compared with the input determination means determines that the input operation input operation body has approached is performed, the variation in the stray capacitance of each sensing electrode of the plurality of detection electrodes, the input operation member to a specific detection electrode There an input position detecting means for detecting an input position in close proximity, a normal mode in which the input operation position detecting means for continuous operation, the input operation position detecting means at rest, and the input determination unit intermittent operation Capacitive touch panel that transitions between sleep mode and
Further, for each detection electrode, a constant determined by a resistance connected in series or in parallel with the stray capacitance of each detection electrode, a resistance value of the resistance, and a stray capacitance of each detection electrode, and a predetermined reference time ( a charge / discharge circuit that charges or discharges the stray capacitance from t0) and raises or lowers the potential of each detection electrode between a first potential and a second potential higher than the first potential; and the potential of each detection electrode; The reference potential set between the first potential and the second potential is compared, and the potential of each detection electrode at the reference time (t0) exceeds the reference potential as it is pulled up or pulled down by the charge / discharge circuit. A comparison circuit that outputs a binary signal that is inverted at the time, and for each of the binary signals output from the comparison circuit for each detection electrode, a reference for not performing an input operation to each detection electrode, respectively Time (t0) The first elapsed time until the binary signal is inverted, and the time from the reference time (t0) when the input operation body approaches by the input operation to each detection electrode until the binary signal is inverted. A second elapsed time is detected in advance, and the input determining means detects, for each of the detection electrodes, after the passage of the first elapsed time from the reference time (t0) and before the passage of the second elapsed time. A predetermined time is defined as a determination time for determining the inversion state of the binary signal, and it is determined that an input operation has been performed when the binary signal output from any of the comparison circuits is not inverted at the time of determination. The input operation position detecting means compares each elapsed time from the reference time (t0) until the binary signal is inverted based on the binary signal output from the comparison circuit for each detection electrode. An input operation in which the input operating body is close to a specific detection electrode When the position is detected and the input operation position detection means does not detect that the input operation has been performed for a predetermined period sufficiently longer than the detection cycle in which the input operation position is detected. When the discharge circuit and the comparison circuit and the input determination unit shift to a sleep mode where the input determination unit operates intermittently and the input determination unit determines that an input operation has been performed during the sleep mode, all the charge / discharge circuits and the The comparison circuit and the input operation position detecting means shift to a normal mode in which the operation is continuous .

The potential of the detection electrode gradually increases or decreases as the constant determined by the resistance value of the resistance and the floating capacitance of the detection electrode increases after charging or discharging the floating capacitance of the detection electrode from the reference time t0. The time until the reference potential is exceeded becomes longer, and the comparison circuit for each detection electrode generates a binary signal whose elapsed time from the reference time t0 to the inversion changes according to the size of the stray capacitance of the detection electrode. Output.

Since the binary signal is inverted from the reference time (t0) to each first elapsed time while the input operation is not performed on the detection electrodes , the binary signals output from all the comparison circuits are Inverted when determined . On the other hand, when the input operation body by an input operation approaches the one of the detection electrodes, increasing the stray capacitance of the detection electrode, the binary signal output from the comparison circuit for the detection electrodes, each of the post when determining the 2 is inverted at the elapsed time, and when the binary signal output from any of the comparison circuits is not inverted at the time of determination, it is determined that the input operation has been performed by the input determination means, and the normal mode is entered.

The stray capacitance of the respective detection electrodes, using a comparison circuit and the charge-discharge circuit provided for each of the detection electrodes can detect the variation in the stray capacitance independently, with overlapping detection time, to all the detection electrodes Can be detected in a short time.

The capacitive touch panel according to claim 2, wherein the first elapsed time is adjusted to be substantially the same for each detection electrode , and the circuit constants for each detection electrode are adjusted, and all the charge / discharge circuits synchronize time reference (t0) of the input determination means for the binary signal output from all of the comparator circuit, upon determination that defines the same time, it determines the inverted state of the binary signal It is characterized by.

While no input operation is performed on each detection electrode, the binary signals output from all the comparison circuits are inverted when each first elapsed time at the same time elapses. On the other hand, when the input operation body approaches any one of the detection electrodes by the input operation, the stray capacitance of the detection electrode increases, and the binary signal is not inverted by the time of determination common to each detection electrode. The input operation is detected with and shifts to the normal mode.

Capacitive touch panel of claim 3, wherein the input operation position detecting means, wherein in a sufficiently short cycle than the second elapsed time, the logical value of the binary signals output from a plurality of said comparator circuit a parallel input register for temporarily storing the parallel data of a plurality of bits to one of said binary signal is inverted, to monitor the parallel data stored in the parallel input register, one of the binary signal is inverted at least the register value monitoring means for detecting a change in any of the bit data, a counter for counting the elapsed time from the reference that is synchronized (t0), the register value monitoring means said parallel input register parallel data by each time detecting a change in the parallel data stored in the counter value at the time of detection, the parallel input register during the detection Further comprising a storage means for storing in association with the parallel data stored in the data, after the binary signal output from all of the comparison circuit is inverted, stored counter value in the storage means and the parallel data From the above, it is characterized in that an input operation position where an input operation body approaches a specific detection electrode is detected.

Since the reference times t0 are synchronized and the first elapsed times are substantially the same, the plurality of comparison circuits output binary signals that are inverted in ascending order of the stray capacitance of each detection electrode, and output from any of the comparison circuits Each time the binary signal is inverted , parallel data obtained by changing the bit data of the bit corresponding to the comparison circuit that has output the inverted binary signal is stored in the parallel input register. Since the parallel data stored in the storage means is stored in association with the counter value indicating the elapsed time from the reference time t0, it represents a change history in which any bit data of the parallel data changes, and is obtained from the counter value. By comparing with the immediately preceding parallel data, the changed bit data and the elapsed time until the inversion of the binary signal output from the comparison circuit corresponding to the bit can be obtained.

The elapsed time from the reference time t0 when the bit data changes is the elapsed time until the binary signal of the comparison circuit corresponding to the bit is inverted , and the size of the stray capacitance of the detection electrode provided with the comparison circuit Therefore, the elapsed time from the reference time t0 is compared for each bit data, and the input operation position of the input operation is detected from the arrangement position of the detection electrode having a large stray capacitance as the specific detection electrode that the input operation body approaches. Is done.

According to the first aspect of the present invention, the charge / discharge circuit, the comparison circuit, and the detection electrode for detecting the input operation position in the normal mode are used without separately providing a detection switch dedicated for detecting the input operation in the sleep mode. Therefore, a non-contact input operation can be detected in the sleep mode without making the configuration complicated and large.

  In the sleep mode, since the input operation position is not detected, the power consumption is small, and it can be used as an instruction input device mounted on a portable device.

  In addition, non-contact input operation can be detected in sleep mode, so it is placed on the back side of the display element, and the normal operation mode is detected to detect the input operation position even if the input operation is just to approach the display element. Can be migrated.

Further, a change in the stray capacitance of the detection electrode can be detected with a simple configuration of the time constant circuit without using a generating means for generating a detection signal such as a pulse voltage.

  Since the change in the stray capacitance of each detection electrode can be detected in a short time by overlapping the detection time, the pause period Trs during which the intermittent operation is performed during the sleep mode can be increased, and the power consumption can be reduced.

According to the invention of claim 2, the input operation can be simultaneously detected for all the detection electrodes, and the input operation can be detected by setting the charge / discharge time to a short time during the sleep mode.

Further, at the time of determination at the same time, it is possible to determine the presence or absence of a non-contact input operation only by determining whether or not the binary signals output from all the comparison circuits are inverted .

According to the third aspect of the invention, using a single counter and parallel input register that are common for a plurality of detection electrodes, it can detect changes in any of the stray capacitance of the plurality of detection electrodes, thereby the stray capacitance up The input operation position can be detected from the arrangement position of the detection electrodes.

1 is a circuit diagram showing a plurality of capacitance-time conversion circuits 2 of a capacitive touch panel 1 according to a first embodiment of the present invention. FIG. 2 is a block diagram of the main part of the capacitive touch panel 1. FIG. It is a wave form diagram which shows the waveform of a and c of each capacity | capacitance-time conversion circuit 2 in sleep mode. 3 is a waveform diagram showing waveforms a, b, and c of each capacitance-time conversion circuit 2. FIG. It is a wave form diagram which shows the charging / discharging time and rest time in sleep mode and normal mode. It is a wave form diagram which shows the waveform of a, c of each capacity | capacitance-time conversion circuit 30 in the sleep mode which concerns on 2nd Embodiment. It is a block diagram which shows the conventional electrostatic capacitance type touch panel. It is a longitudinal cross-sectional view which shows the conventional electrostatic capacitance type sensor 200. FIG.

Hereinafter, a capacitive touch panel (hereinafter referred to as a touch panel) 1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 5. In the touch panel 1, a plurality of detection electrodes 3 ₁ , 3 ₂ , 3 ₃ , 3 ₄ are arranged on an insulating panel (not shown) so as to be insulated from each other at intervals of, for example, several mm. The stray capacitance Cs of each detection electrode 3 is represented by the sum of the capacitance formed between the surrounding conductive pattern, the shield case that shields the device, and the ground, but the other capacitance is substantially constant. Thus, it increases when an input operation body such as an operator's finger approaches. Therefore, the stray capacitances Cs ₁ , Cs ₂ , Cs ₃ , and Cs ₄ of each detection electrode 3 are compared, and when the stray capacitance Cs of any of the detection electrodes 3 increases, an input operation is performed on the detection electrode 3. It is determined that the input operation body is approaching, and the input operation is determined, and the mode shifts from the sleep mode that detects only the input operation with low power consumption to the normal mode that detects the input operation position.

Here, an input operation from the convenience of description, either the touch panel 1 is a four detection electrodes _{3 1,} 3 _2, 3 3, _{3 4} of the stray capacitance _{Cs 1,} Cs _2, Cs 3, Cs ₄ is increased This will be described as detecting this. In order to monitor the magnitudes of the stray capacitances Cs ₁ , Cs ₂ , Cs ₃ , and Cs ₄ of each detection electrode 3, as shown in FIG. A capacitance-time conversion circuit 2 that outputs the time width is connected.

Each capacitance-time conversion circuit 2 is connected in series between the charge / discharge switch 4 for switching the common terminal between the reference charge voltage Vdd and the ground potential GND, and between the common terminal of the charge / discharge switch 4 and the detection electrode 3. A comparator having the stray capacitance Cs of the electrode 3 and detection resistors R1 and R2 forming a time constant circuit, a non-inverting input connected to a connection point of the detection resistors R1 and R2, and an inverting input as a reference potential V _SH potential And 5. The reference potential V _SH is a predetermined potential between the reference charging voltage Vdd and the ground potential GND, and is set to 70% of Vdd here, whereby the charge / discharge switch 4 is changed from the ground potential GND to the reference charging voltage Vdd. Is switched to the side, the stray capacitance Cs is charged with a time constant determined from the resistance values of the detection resistors R1 and R2 and the stray capacitance Cs, and when the potential of the detection electrode 3 rising from the ground potential GND exceeds the reference potential _VSH , The output c of the comparator 5 is inverted. Further, when the charge / discharge switch 4 is switched from the reference charge voltage Vdd to the ground potential GND side, the charges accumulated in the stray capacitance Cs are discharged, and when the potential of the descending detection electrode 3 becomes less than the reference potential V _SH , As long as the output c of the comparator 5 is inverted again and the charge / discharge switch 4 is not switched, the potential of the detection electrode 3 drops to the ground potential GND.

In the present embodiment, the resistance values of the detection resistors R1 and R2 of the capacitance-time conversion circuit 2, the circuit constants of the comparator 5, etc., and the potential of the reference potential V _SH are the same for each capacitance-time conversion circuit 2. The charging / discharging switches 4 are simultaneously switched by a switching control signal a from the microcomputer 20 shown in FIG. 2 so that the reference charging voltage Vdd is applied at the same reference time t0. Therefore, the rising speed of the potential of the detection electrode 3 when the above-described stray capacitance Cs (for convenience, the capacitor of the stray capacitance Cs is referred to as the stray capacitance Cs) is charged with the reference charging voltage Vdd is the resistance of the detection resistors R1 and R2. The value is determined by a time constant obtained by multiplying the value by the stray capacitance Cs. However, it depends exclusively on the stray capacitance Cs, and as the stray capacitance Cs increases, the voltage rises more slowly and the output c of the comparator 5 is inverted from the reference time t0. The time to do is also longer. In general, the stray capacitance Cs of the detection electrode 3 is about 10 pF, and the amount of change of the stray capacitance Cs that changes due to the approach of an input operation body such as a finger is about 1 to 3 pF. In order to discriminate from the time until inversion, the resistance values of the detection resistors R1 and R2 are set to 10 MΩ here.

  The microcomputer 20 that controls switching to the charge / discharge switch 4 of each capacity-time conversion circuit 2 receives a clock signal of 50 MHz here from the clock transmission circuit 9, operates in the sleep mode and the normal mode shown in FIG. The switching control signal a generated from the clock signal is output to the charge / discharge switch 4. In the sleep mode, the first register (T) 6 shown in FIG. 2 for detecting the input operation position, leaving the capacity-time conversion circuit 2, the microcomputer 20, the clock oscillation circuit 9 and the like necessary for detecting the input operation, The operations of the second register (T-1) 7, the register value comparison circuit 8, the counter 11, and the RAM 10 are stopped, and the power consumption is reduced by stopping the power supply to these circuit elements.

  As shown in FIG. 2, the outputs c1, c2, c3, and c4 of the comparator 5 of each capacitance-time conversion circuit 2 are a first register that is a microcomputer 20 and a 4-bit PIPO (parallel input parallel output type) register, respectively. (T) 6 is connected to the input port of the microcomputer 20 in the sleep mode, and is input in parallel to the first register (T) 6 as 4-bit parallel data in the normal mode.

  In the present embodiment, the circuit constants of the circuit elements constituting each capacitance-time conversion circuit 2 are set, and the stray capacitance Cs of the detection electrode 3 is charged with the reference charge voltage Vdd having the same potential at the same reference time t0. The first elapsed time from the reference time t0 to the inversion of the outputs c1, c2, c3, and c4 of the comparator 5 is the same for each output c1, c2, c3, and c4 when no operation is performed. . On the other hand, when an input operating body such as a finger approaches one of the detection electrodes 3, the stray capacitance Cs of the detection electrode 3 increases, and the output c of the comparator 5 has a second elapsed time longer than the first elapsed time. Therefore, the input operation can be determined based on whether or not the output c of the comparator 5 is inverted at the determination time tj after the first elapsed time has elapsed from the reference time t0 and before the second elapsed time has elapsed. .

  Therefore, the microcomputer 20 operating in the sleep mode determines the binary data of the outputs c1, c2, c3, and c4 of each comparator 5 as the reference time t0 when each charge / discharge switch 4 is switched to the reference charge voltage Vdd side and the above determination. Comparison is made at time tj, and if the binary data at any reference time t0 is not reversed even at the determination time tj, it is determined that an input operation has been performed and the normal mode is entered.

In the normal mode, each bit of the parallel data input to the first register (T) 6 corresponds to each output c1, c2, c3, c4, and when the output c of the binary signal is “H”, Bit data of “0” is stored when “1” and “L”. The parallel output of the first register (T) 6 is connected to the parallel input of the second register (T-1) 7 which is a 4-bit PIPO register similarly configured. The first register (T) 6 and the second register (T-1) 7 are connected to a common shift clock terminal (SFT) and reset output terminal (RESET) of the microcomputer 20, and a shift clock is transmitted from the clock terminal (SFT). A 4-bit register value is input / output each time it is input, and when a reset signal is input from the reset output terminal (RESET), the stored 4-bit register value is reset. That is, the first register (T) 6 stores the binary data of the outputs c1, c2, c3, and c4 stored as 4-bit register values when the shift clock is input until the next shift clock is input. Similarly, the second register (T-1) 7 stores the 4-bit register value output from the first register (T) 6 until the next shift clock is input. Further, when a trigger signal is input from a register value comparison circuit 8 described later, the first register (T) 6 stores the register value stored at that time in the RAM 10.

Each time a new 4-bit register value of outputs c1, c2, c3, and c4 is stored in the first register (T) 6, the register value comparison circuit 8 and the second register (T-1). The register value stored in the register 7 is compared, and if any bit data of at least 4 bits is different, a trigger signal is output from the register value comparison circuit 8 to the first register (T) 6 and the counter 11. Since the register value stored in the second register (T-1) 7 is the register value stored in the first register (T) 6 immediately before the latest shift clock is input, the trigger signal is output c1. , C2, c3, and c4 are output when the binary data changes.

  The microcomputer 20 operating in the normal mode outputs the switching control signal a to switch the charge / discharge switch 4 and controls the operations of the registers 6 and 7 by the shift clock having a frequency obtained by dividing the clock frequency of 50 MHz. . Here, since the time difference until the binary data of the output c is inverted by the input operation is about 10 to 30 μsec, the frequency of the shift clock is at least 1 MHz or more in order to detect the time difference reliably. . In the normal mode, the microcomputer 20 specifies the detection electrode 3 to which the input operation body approaches from the combination of the counter value and the register value stored in association with the RAM 10 for each detection cycle Tpn in FIG. The detection process which detects the input operation to the arrangement position of is performed.

The counter 11 counts up the counter value at a frequency obtained by dividing the frequency of the clock signal output from the clock oscillation circuit 9. The counter value of the counter 11 is reset by a reset signal output from the microcomputer 20, and when a trigger signal is input from the register value comparison circuit 8, the counter value at that time is output to the RAM 10, as shown in FIG. .

The RAM 10, which is a temporary storage device, is stored in the counter value of the counter 11 and the first register (T) 6 each time a trigger signal is output from the register value comparison circuit 8, as shown in FIG. The register values are stored in association with each other, and each combination associated with the counter value is stored until a register value in which all bit data is “1” is input. The data of each combination stored in the RAM 10 is cleared by control from the microcomputer 20 before the reference time t0 for each detection cycle Tpn in the normal mode.

  The touch panel 1 configured as described above operates in accordance with two types of operation modes, that is, a sleep mode and a normal mode of the microcomputer 20, and the operation will be described below in the order of the sleep mode and the normal mode shown in FIG.

  Immediately after the touch panel 1 is activated, the microcomputer 20 operates in a sleep mode in which an input operation is detected. As shown in FIGS. 3 and 5, the charge time Tc and the discharge time for charging and discharging the stray capacitance Cs of each detection electrode 3. The detection of the input operation is repeated at the sleep mode detection cycle Tps obtained by adding the pause time Trs to Td.

The charging time Tc is the time from the reference time t0 when the charge / discharge switch 4 is switched to the reference charging voltage Vdd side to the switching time tg when the charging / discharging switch 4 is switched to the ground potential GND, and the switching time tg is the reference time regardless of whether or not an input operation is performed. It is set at a time after the second elapsed time when the potentials of all the detection electrodes 3 exceed the reference potential V _SH from t0. The maximum value of the stray capacitance Cs is about 10 pF. In this embodiment, the stray capacitance Cs is charged via the detection resistors R1 and R2 connected in series of 10 MΩ, so that the potential of the detection electrode 3 is substantially the reference. The time until the charging voltage Vdd is reached is about 100 μsec, and the charging time Tc until the switching time tg is 100 μsec.

  The discharge time Td is set to 100 μsec, which is the same as the charge time Tc. After the discharge time Td has elapsed from the switching time tg, the potentials of all the detection electrodes 3 are equal to the ground potential GND, which is the potential at the reference time t0. Become.

  The pause time Trs is a time obtained by excluding the charge time Tc and the discharge time Td from the sleep mode detection cycle Tps that can reliably detect a non-contact input operation. Here, the sleep mode detection cycle Tps is set to 100 msec. Trs is set to 99 msec or more. As a result, in the sleep mode, only the capacity-time conversion circuit 2, the microcomputer 20, the clock oscillation circuit 9, and the like necessary for detecting the input operation operate, but the operation period is also 1 during the period waiting for the input operation. The input operation can be detected with extremely low power consumption.

At the reference time t0 when all the charge / discharge switches 4 are switched to the reference charge voltage Vdd side, the potential of each detection electrode 3 is the ground potential GND less than the reference potential V _SH , so that the comparator 5 input to the microcomputer 20 The outputs c1, c2, c3, and c4 are “L” as shown in FIG. If the input operation is not performed, the stray capacitance Cs of each detection electrode 3 does not increase, and the potential of each detection electrode 3 becomes the reference potential V _SH when the first elapsed time Tf has elapsed from the reference time t0. Beyond that, each output c1, c2, c3, c4 is inverted to “H”. Accordingly, the microcomputer 20 determines that all the binary data of the outputs c1, c2, c3, and c4 input at the determination time tj after the first elapsed time from the reference time t0 is “L” from the reference time t0 to “L”. Since it is reversed to “H”, it is determined that the input operation is not performed, and the sleep mode is continued. Before and after the determination of the microcomputer 20, the microcomputer 20 outputs a switching control signal a for switching the charge / discharge switch 4 to the ground potential GND side, and sets the potential of the detection electrode 3 to the ground potential GND during the discharge time Td. After the pause time Trs for stopping the operation, the operation of the next sleep mode detection cycle Tps is started.

During sleep mode, for example, detecting the electrode 3 and the ₂ to the input operation member used to be input operation to close, as shown in FIG. 3, the output c2 is the reference time t0 from the second comparator 5 during the charging time Tc Inverted after the elapsed time Ts has elapsed. That is, the output c2 of the comparator 5 input to the microcomputer 20 at the determination time tj after the elapse of the first elapsed time from the reference time t0 and before the second elapsed time elapses is the same binary data as the reference time t0. Since it is “L” and there is an output c2 in which the binary data is not inverted from the reference time t0 even at the determination time tj, the microcomputer 20 determines that the operation is an input operation, and after the discharge time Td and the rest time Trs have elapsed. , Transition to the normal mode for detecting the input operation position.

  When shifting to the normal mode, in addition to the circuit elements operating in the sleep mode, the first register (T) 6, the second register (T-1) 7, the register value comparison circuit 8, the counter 11 and the RAM 10 are also displayed. Power is supplied and these circuit elements are activated. In the normal mode, as shown in FIG. 5, the input operation position is detected at the normal mode detection cycle Tpn obtained by adding the pause time Trn to the charge time Tc and the discharge time Td for charging and discharging the stray capacitance Cs of each detection electrode 3. repeat. Even in the normal mode, the microcomputer 20 outputs the switching control signal a from the reference time t0 at the same timing as in the sleep mode. Therefore, the stray capacitance Cs of each detection electrode 3 has the same charging time Tc and discharging time as in the sleep mode. Charge and discharge at Td.

  In order to increase the detection frequency of the input operation position, it is not always necessary to provide the rest time Trn in the normal mode detection cycle Tpn with the time when the discharge time Td has passed as the reference time t0. A pause time Trn of .8 msec is provided, and the normal mode detection period Tpn is set to 2 msec. The microcomputer 20 performs a detection process for calculating the input operation position from the data stored in the RAM 10 from the discharge time Td to the rest time Tr.

  As described above, according to the present embodiment, charge and discharge are simultaneously performed on the stray capacitance Cs of a large number of capacitance-time conversion circuits 2, so that the charge time Tc and the discharge time Td depend on the number of capacitance-time conversion circuits 2. Even if a sufficiently long pause time Trn is provided, an input operation can be detected with a short detection cycle Tp. Therefore, even in the normal mode in which the microcomputer 20 detects the input operation position, the non-contact input operation position can be detected with low power consumption.

The microcomputer 20 in the normal mode outputs a reset signal from the reset output terminal (RESET) at the reference time t0 when the normal mode detection cycle Tpn starts, and the first register (T) 6 and the second register (T-1) 7 It resets the counter value of the register value and the counter 11 to clear the data stored in the RAM 10. Here, as will be described later, in order to store the register value of the first register (T) 6 at the reference time t0 in the RAM 10, the first register (T) 6 and the second register (T-1) 7 are reset. All the registered values are set to “1”, but when the detection period Tpn elapses, the register values of the first register (T) 6 and the second register (T−1) 7 are “1”. Therefore, it is not always necessary to reset.

Further, the microcomputer 20 outputs a switching control signal a for switching the charge / discharge switches 4 to the reference charging voltage Vdd side at the same reference time t0, and charges the stray capacitance Cs of the detection electrode 3 with the reference charging voltage Vdd. Since the charge and discharge switches 4 to the reference time t0, the potential of the sensing electrode 3 which has been switched to the ground potential GND are the following ground potential GND reference potential _{V SH,} the output of the comparator 5 of the reference time t0 c1, c2, Both c3 and c4 are “L”, and the 4-bit “0000” parallel data of the first register (T) 6 is stored.

Since the register value is different from the register value “1111” stored in the second register (T−1) 7 by the reset, the register value comparison circuit 8 sends a trigger signal to the counter 11 and the first register (T) 6. As shown in FIG. 2, the RAM 10 stores the counter value Ct0 representing the reference time t0 and the register value “0000” stored in the first register (T) 6 in association with the reference time t0.

Away from the position of the detection electrode 3 _2, stray capacitance Cs ₄ of the detection electrode 3 ₄ not affected by the input operation of the input operation is minimal, as shown in FIG. 4, the resistance value of the detection resistor R1, R2 when the earliest potential of the detection electrode 3 ₄ rises at a constant between, exceeds the reference potential V _SH at time t1 from the reference time t0 is first elapsed time Tf has elapsed. As a result, the output c4 of the comparator 5 is inverted from “L” to “H”, and the first register (T) 6 stores the parallel data “0001” in which the least significant bit is “1”. The register value comparison circuit 8 outputs a trigger signal to the counter 11 and the first register (T) 6 because the register value is different from the register value “0000” stored in the second register (T−1) 7. The RAM 10 stores the counter value C (t1) representing the time t1 and the register value “0001” newly stored in the first register (T) 6 in association with each other.

Subsequently disposed on both sides of the detection electrodes 3 _2, stray capacitance Cs _1, Cs ₃ of the detection electrode 3 sensing electrode 3 ₁ arranged equidistant substantially with respect to the input operation body that approaches ₂ to the detection electrode 3 ₃ greater than the stray capacitance Cs _4, the sensing electrode ₃ exceeds the reference voltage _{V SH} 1, _{3 3} of potential at time t2, the inverted output c1, c3 of the comparator 5 from "L" to "H", the first register ( T) 6 stores parallel data “1011”. The register value comparison circuit 8 is different from the register value “0001” stored in the second register (T−1) 7 because the first and third bits of the register value are different from the counter 11 and the first register (T ) 6, the trigger signal is output to the RAM 10, and the register value “1011” newly stored in the first register (T) 6 is stored in the RAM 10 in association with the counter value C (t 2) representing the time t 2.

Since the stray capacitance Cs ₂ of the input operation position to the closest detector electrode 3 ₂ is maximized in comparison to other, as shown in FIG. 4, the potential of the sensing electrode 3 _2, second elapsed time from the reference time t0 It exceeds the reference voltage V _SH to the end of the time t ₃ when Ts has elapsed, the output c3 of the comparator 5 is inverted from "L" to "H". As a result, the parallel data “1111” is stored in the first register (T) 6 at time t ₃ , and the register value comparison circuit 8 stores this register value in the second register (T−1) 7. Since this is different from the register value “1011”, a trigger signal is output to the counter 11 and the first register (T) 6, and as shown in FIG. 2, the counter value C (t 3) representing the time t 3 is The register value “1111” stored in one register (T) 6 is associated and stored.

  The microcomputer 20 switches each charge / discharge switch 4 from the reference charge voltage Vdd side to the ground potential GND at the switching time tg when the charging time Tc has elapsed from the reference time t0, and is stored in each floating capacitance Cs during the discharging time Td. The electric charges are discharged, and the potentials of all the detection electrodes 3 are set to the ground potential GND.

Since the potentials of all the detection electrodes 3 exceed the reference potential V _SH at the switching time tg, the register value “1111” stored in the first register (T) 6 does not change until the switching time tg. The microcomputer 20 reads a combination of each counter value C (t) and the register value stored in the RAM 10 at the switching time tg. The counter value C (t) represents an elapsed time from the reference time t0 when charging is started, and the register value indicates a bit whose bit data has changed compared to the register value of the immediately preceding combination. The bit of each register value corresponds to the stray capacitance Cs of each detection electrode 3, and the elapsed time from the reference time t0 becomes longer depending on the size of the stray capacitance Cs. Therefore, the microcomputer 20 stores each bit stored in the RAM 10. From the combination data, the magnitude of the stray capacitance Cs of the detection electrode 3 can be compared.

Here, as shown in FIG. 2, since the bit data of 4 bits changes in the order of the fourth bit (LSB), the first bit (MSB), the third bit, and the second bit, the stray capacitance Cs is Cs ₄ , Cs ₁ , Cs ₃ , and Cs ₂ are detected to increase in this order. Thus, the microcomputer 20, the stray capacitance Cs ₂ can be determined that the maximum of the detection electrode 3 ₂ input operation member to the position of the approaches, an input operation to input position the arrangement position of the detection electrode 3 ₂ To detect.

  The input operation position is detected by comparing the stray capacitances Cs of the plurality of detection electrodes 3 and inputting the positions between the arrangement positions of the plurality of detection electrodes 3 obtained from a ratio obtained by dividing the plurality of stray capacitances Cs. It may be an operation position.

  Further, the microcomputer 20 detects an input operation to the input operation position every detection cycle Tp, but the data of each combination stored in the RAM 10 is left for a plurality of detection cycles Tpn, and is detected at each detection cycle Tpn. The input operation position may be calculated from the correlation of a plurality of input operation positions, excluding the stray capacitance Cs and the abnormal value of the input operation position.

Further, since the elapsed time from the reference time t0 of the capacitance-time conversion circuit 2 corresponding to the bit to the inversion of the output c is known from the combination of the bit whose bit data has changed and the counter value C (t), the reference When the elapsed time from time t0 is equal to or longer than the second elapsed time Ts, the input operation position can be detected from the position where the detection electrode 3 of the capacitance-time conversion circuit 2 is disposed. For example, since the time elapsed from the reference time t0 shown in FIG. 4 to time t ₃ is a second elapsed time Ts or more, it is also possible to detect the position of the detection electrode 3 ₂ as the input operation position.

  The microcomputer 20 outputs the input operation position detected in this way to an external control circuit that controls cursor movement control on the display screen and the operation of the electronic device, and executes predetermined processing corresponding to the input operation position.

  The microcomputer 20 executes the input operation position and input operation detection process between the discharge time Td and the subsequent rest time Trn, and after detecting the input operation, the reference time t0 when the next detection cycle Tpn is started. Before, the data stored in the RAM 10 is cleared.

  While operating in the normal mode, the microcomputer 20 repeats the detection of the input operation position at the normal mode detection cycle Tpn. The input operation in the normal mode means that the stray capacitance Cs of the plurality of detection electrodes 3 arranged adjacent to the detection electrode 3 detected as the input operation position increases, or the second lapse from the reference time t0. After the time Ts elapses, all bit data change can be detected, and in normal mode, for example, when no input operation is detected for a certain period of 20 seconds, the mode shifts to the sleep mode, and the sleep mode Repeat the process.

In the first embodiment, the capacity - circuit constants such as a resistance value of the detection resistor R1, R2 of the time conversion circuit 2, as the same potential or the like of the reference potential V _SH to comparator compares each capacitance - time conversion circuit Although the first elapsed time Tf is substantially the same for 2, the circuit constant, the reference potential V _{SH and the} like are not necessarily the same, but in the sleep mode, the charge time Tc or the discharge time Td is within one time. Input operations can be detected.

  The capacitance type touch panel according to the second embodiment is different from each other in the resistance values of the detection resistors R1 and R2 of each capacitance-time conversion circuit 2 shown in FIG. Since it is the same as the form, the description thereof is omitted. FIG. 6 is output from each comparator 5 when the charge / discharge switch 4 of each capacity-time conversion circuit 2 according to the second embodiment is controlled to be switched during the sleep mode at the same timing as in the first embodiment. It is the wave form diagram which showed the waveform of output c1, c2, c3, c4.

In the first sleep mode detection period Tps shown on the left side of the figure, the input operation is not performed, the reference time t0 is synchronized, despite the same reference charging voltage Vdd and the reference potential V _SH, detection resistor R1, The first elapsed time Tf from the reference time t0 differs depending on the resistance value of R2. Therefore, in the second embodiment, as in the first embodiment, the input operation cannot be determined from the binary data of the outputs c1, c2, c3, and c4 at the common determination time tj. A different determination time tj is determined for each capacity-time conversion circuit 2 in advance. That is, for each capacitance-time conversion circuit 2, the first elapsed time Tf from the reference time t 0 until the output c of the comparator 5 is inverted in the state where the input operation is not performed on the detection electrode 3, and the detection electrode 3, the second elapsed time Ts from the reference time t0 until the output c of the comparator 5 is inverted is detected in advance, and the first time is set for each capacitance-time conversion circuit 2. A determination time tj is set until the second elapsed time Ts elapses after the elapsed time Tf has elapsed.

  The microcomputer 20 operating in the sleep mode detects each inversion time when the binary data of the outputs c1, c2, c3, and c4 input to the input port after the reference time t0 is inverted every sleep mode detection period Tps, Comparison is made with the outputs c1, c2, c3, c4, that is, the determination time tj set for each capacitance-time conversion circuit 2. As a result, for any output c, when the detected inversion time is after the determination time tj, it indicates that the binary data at the reference time t0 is not inverted at the determination time tj. Judge as operation. On the other hand, for all the outputs c, when the detected inversion time is before the determination time tj, it indicates that the binary data at the reference time t0 is inverted at the determination time tj. Judge that it is not.

In the second sleep mode detection period Tps shown on the right side of FIG. 6, the case where there input operation for approximating the input operation member to the detection electrode 3 _2, capacitor connected to the sensing electrode 3 ₂ - time converter 2 when reversing the output c2 is the capacitance - is after the determination time tj set for time conversion circuit 2, the microcomputer 20 detects an input operation as if there is an input operation to the detection electrode 3 _2.

  The detection of the input operation in the microcomputer 20 is performed by the first register (T) 6, the second register (T-1) 7, the register value comparison circuit 8, and the counter according to the first embodiment that are suspended in the sleep mode. 11. The RAM 10 may be operated at least during the charging time Tc and may be detected from the data of each combination stored in the RAM 10 at the switching time tg. That is, when the bit data changes and when the bit data changes, that is, when the binary data is inverted, is obtained from each combination of data stored in the RAM 10, the microcomputer 20 If the bit data changes after the determination time tj set for the capacity-time conversion circuit 2 corresponding to the bit, the input operation can be detected as having been input.

  Thus, when detecting an input operation using the circuit element for detecting the input operation position, a processing time of several milliseconds is required as compared with the first embodiment, and a pause at the sleep mode detection cycle Tps is required. Although the period Tpn is shortened, unlike in the normal mode in which it is desired to detect the input operation position with a cycle as short as possible, for example, several milliseconds, in the sleep mode, at least one input operation is performed. Since the input operation only needs to be detected, the sleep mode detection cycle Tps can be set to a long cycle of about 100 msec as described above, and a sufficiently long pause period Tpn can be taken.

In the second embodiment, if the first elapsed time Tf from the reference time t0 and the second elapsed time Ts are obtained for each capacity-time conversion circuit 2, the determination time tj between them is also the capacity-time conversion circuit 2. Therefore, the potential on the switching terminal side for switching the charge / discharge switch 4, the reference potential _{VSH, and the} like may be different for each capacitance-time conversion circuit 2.

  In the above embodiments, circuit elements such as the register value comparison circuit 8, the first register (T) 6, and the second register (T-1) 7 may be incorporated in the microcomputer 20.

The capacitance in each of the above embodiments - time conversion circuit 2, the charging time Tc, but the detection electrode 3 represents the variation in the stray capacitance Cs at time elapsed exceeds the reference voltage V _SH, the discharge time Td It may represent a change in the stray capacitance Cs at the elapsed time until the potential of the sensing electrode 3, which had been the same potential for each detection electrode 3 is less than the reference potential V _SH.

  The present invention is suitable for a capacitive touch panel that is mounted on a portable device that operates with a limited battery and detects a non-contact input operation.

1 Capacitive Touch Panel According to First Embodiment 2 Capacitance-Time Conversion Circuit (Capacitance-Time Conversion Unit)
3 Detection electrode 4 Charge / discharge switch (charge / discharge circuit)
5 Comparator (comparison circuit)
6 First register (T) (parallel input register)
8 Register value comparison circuit (register value monitoring means)
10 RAM (storage means)
11 Counter 20 Microcomputer R1, R2 Resistance

Claims (3)

A plurality of detection electrodes disposed on the insulating panel so as to be insulated from each other;
Input determination means for determining that an input operation in which the input operation body approaches is performed from an increase in stray capacitance of at least one detection electrode of the plurality of detection electrodes ;
The variation in the stray capacitance of each sensing electrode of a plurality of detection electrodes are compared, and an input operation position detecting means for detecting the input operation position input operation member approaches the particular detection electrodes,
A capacitive touch panel that transitions between a normal mode in which the input operation position detection means continuously operates and a sleep mode in which the input operation position detection means is paused and the input determination means is intermittently operated,
For each of the detection electrodes,
A resistor connected in series or in parallel with the stray capacitance of each detection electrode;
A constant determined by the resistance value of the resistor and the stray capacitance of each detection electrode, and the stray capacitance is charged or discharged from a predetermined reference time (t0), and the potential of each detection electrode is determined by the first potential and the first potential. A charge / discharge circuit that raises or lowers it between a high second potential;
The potential of each detection electrode is compared with the reference potential set between the first potential and the second potential, and the potential of each detection electrode at the reference time (t0) is raised or lowered by the charge / discharge circuit. And a comparator circuit that outputs a binary signal that inverts when the reference potential is exceeded.
With respect to the binary signal output from the comparison circuit for each detection electrode, each of the binary signals from the reference time (t0) when the input operation to each detection electrode is not performed until the binary signal is inverted is performed. 1 elapsed time and each second elapsed time from the reference time (t0) when the input operating body approaches by the input operation to each detection electrode until the binary signal is inverted,
The input determination means sets the inversion state of the binary signal for each detection electrode for a predetermined time after the elapse of each first elapsed time from the reference time (t0) and before the elapse of each second elapsed time. It is determined as a determination time, and when the binary signal output from any of the comparison circuits is not inverted at the time of determination, it is determined that an input operation has been performed,
The input operation position detecting means compares each elapsed time from the reference time (t0) to the inversion of the binary signal based on the binary signal output from the comparison circuit for each detection electrode, Detects the input operation position where the input operation body approaches a specific detection electrode,
When the input operation position detection means does not detect that an input operation has been performed in a predetermined period sufficiently longer than the detection cycle in which the input operation position is detected during the normal mode, all the charge / discharge circuits and the comparison circuit The circuit and the input determination means shift to a sleep mode where the operation is intermittent,
When the input determining means determines that an input operation has been performed during the sleep mode, all of the charge / discharge circuit and the comparison circuit and the input operation position detecting means shift to a normal mode in which they continuously operate. Capacitive touch panel. Said first elapsed time each is, the to be substantially identical in each of the detection electrodes, thereby adjusting the circuit constants of the respective detection electrodes, to synchronize the reference time (t0) of all of the charging and discharging circuit,
2. The input determination unit according to claim 1, wherein the binary signal output from all the comparison circuits determines an inversion state of the binary signal at the time of determination determined at the same time. Capacitive touch panel. The input operation position detecting means includes
Wherein in a sufficiently short cycle than the second elapsed time, temporary logical value of the binary signals output from a plurality of said comparator circuit, as parallel data of plural bits to one of said binary signal is inverted A parallel input register to store;
Said monitoring the parallel data stored in the parallel input register, either register value monitoring means for detecting a change in at least one of the bit data of the parallel data by said binary signal is inverted,
A counter that counts the elapsed time from the synchronized reference time (t0);
Each for detecting a change in the parallel data is the register value monitoring unit are stored in the parallel input register, and the counter value at the time of detection, the detection time of the parallel input register stored parallel data and storing that stores in association with Further comprising means,
After the binary signal output from all of the comparison circuit is inverted, from the stored counter value and the parallel data in the storage means, for detecting the input operation position input operation member approaches the particular detection electrodes The capacitive touch panel according to claim 2 .

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