JP4843334B2 - Memory control device - Google Patents

Description

  The present invention relates to a memory control device for writing data to a semiconductor memory device.

  In recent years, with the improvement of the processing capability of a CPU (Central Processing Unit), there is an increasing need to increase the operation speed of a semiconductor memory device. One of the semiconductor memory devices that realize this high speed is DDR (Double-Data-Rate) -SDRAM (Synchronous Dynamic Random Access Memory). There is a DDR2-SDRAM that is a further improvement of the DDR-SDRAM.

  In SDRAM, data is transferred in synchronization with the rising edge of the clock signal. In DDR-SDRAM or DDR2-SDRAM, data is transferred in synchronization with both rising and falling edges of the clock signal. The transfer speed is doubled compared to the above.

  In such a DDR-SDRAM or DDR2-SDRAM semiconductor memory device, various inventions have been made for the purpose of enabling efficient data transfer.

  Patent Document 1 discloses a technique for performing delay control when fetching data from a DDR-SDRAM. As one method of data interface between devices, there is a method in which a device that transmits data outputs a strobe signal and data, and a device that receives the data uses the strobe signal and data received to capture the data. The invention disclosed in Patent Document 1 realizes a delay control device that simply and appropriately synchronizes the data and the strobe signal.

Patent Document 2 discloses a technique related to a write operation for a DDR type memory. A memory control device that controls a DDR type memory outputs (synchronously) the first data to the memory in response to the rising edge of the external (internal) clock, and the memory control apparatus ( Output the second data (synchronously). In the invention disclosed in Patent Document 2, the memory control device has a configuration in which the internal clock operation flip-flop based on the rising clock and the internal clock operation flip-flop based on the falling clock are combined by a multiplexer as described above. Data output is realized.
JP 2005-94597 A US Patent 6584037

  However, in the invention disclosed in Patent Document 1, there is a description about delay control at the time of reading data from DDR-SDRAM, that is, at the time of reading, but control at the time of writing data to DDR-SDRAM has been studied. Absent.

  Here, tDQSS, tDSS, tDSH shown in FIG. 1 are the standards that must be considered by the memory control device that performs the write operation as a standard for the write operation to the DDR-SDRAM or DDR2-SDRAM. There are standards. tDQSS represents a transition time (from a write command to the generation of the first strobe signal), tDSS represents a setup time (strobe signal), and tDSH represents a hold time (strobe signal). In the invention disclosed in Patent Document 2, a configuration in which two flip-flops are combined with a multiplexer and an attempt is made to satisfy the above-mentioned standard by performing a write operation based on the rising and falling edges of the clock. A time delay occurs between the two flip-flops that capture the falling edges. Control over this time delay (delay control) is difficult, and this problem has not been studied. Further, Patent Document 2 describes that the output of the first burst data is determined on the basis of only the clock rising edge. Here, considering the delay of the IO cells, there arises a problem that it is difficult to output at the same timing when the clock frequencies are different. Therefore, it becomes difficult to satisfy the standard shown in FIG. However, the delay of the IO cell has not been studied.

  The present invention has been devised in order to solve this problem in view of the above points, and can perform a write operation on a semiconductor memory device by realizing a delay control that flexibly supports even when the operation clock frequency is different. An object of the present invention is to provide a memory control device that effectively performs the above-described operation.

  In order to achieve the above object, a memory control device according to the present invention includes a clock generation circuit that generates a plurality of clock signals and a strobe signal that is supplied to the semiconductor storage device in a memory control device that writes data to the semiconductor storage device. A write strobe control circuit for controlling, and a write data buffer for temporarily writing data to be supplied to the semiconductor memory device, wherein the clock generation circuit multiplies the first clock synchronized with an external clock and the external clock Generating a second clock, a third clock whose phase is inverted with respect to the second clock, and a fourth clock synchronized with the second clock; 2 operates in synchronization with the second clock, and outputs the strobe signal in synchronization with the third clock. Tabaffa can the second operates in synchronization with a clock, configuring the data so as to output in synchronization with the fourth clock.

  As a result, it is possible to provide a memory control device that effectively performs a write operation on a semiconductor memory device by flexibly realizing delay control even when the operation clock frequency is different.

  In order to achieve the above object, a memory control device according to the present invention includes a clock generation circuit for generating a plurality of clock signals and one of the plurality of clock signals in a memory control device for writing data to a semiconductor memory device. Write control circuit clock generating circuit for generating a plurality of clock signals based on the write strobe control circuit for controlling a strobe signal applied to the semiconductor memory device, and a write data buffer for temporarily writing data applied to the semiconductor memory device The clock generation circuit generates a first clock synchronized with an external clock and a second clock obtained by multiplying the external clock, and the write control circuit clock generation circuit includes the second clock. A third clock whose phase is inverted, and a fourth clock synchronized with the second clock. The write strobe control circuit operates in synchronization with the second clock, outputs the strobe signal in synchronization with the third clock, and the write data buffer It can be configured to operate in synchronization with a clock and output the data in synchronization with the fourth clock.

  As a result, it is possible to provide a memory control device that effectively performs a write operation on a semiconductor memory device by flexibly realizing delay control even when the operation clock frequency is different.

  In order to achieve the above object, a memory control device according to the present invention includes a clock generation circuit for generating a plurality of clock signals and one of the plurality of clock signals in a memory control device for writing data to a semiconductor memory device. And a plurality of write data / write strobe control circuits for outputting data and strobe signals based on the plurality of write data / write strobe control circuits, each of the plurality of write data / write strobe control circuits based on one of the plurality of clock signals. A clock generation circuit for a write control circuit for generating a clock signal; a write strobe control circuit for controlling a strobe signal applied to the semiconductor storage device; and a write data buffer for temporarily writing data applied to the semiconductor storage device The clock generation circuit includes a first clock synchronized with an external clock and The second clock generated by multiplying the external clock is generated, and the clock generation circuit for the write control circuit is synchronized with the second clock and the third clock whose phase is inverted with respect to the second clock. The write strobe control circuit operates in synchronization with the second clock, outputs the strobe signal in synchronization with the third clock, and the write data buffer It can be configured to operate in synchronization with the second clock and to output the data in synchronization with the fourth clock.

  As a result, it is possible to provide a memory control device that effectively performs a write operation on a semiconductor memory device by flexibly realizing delay control even when the operation clock frequency is different.

  To achieve the above object, the first clock according to the present invention uses an address control circuit for generating a signal for controlling an address of the semiconductor memory device and a memory control for generating a signal for controlling the write strobe control circuit. The circuit can be configured to have an operation clock.

  This makes it easy to interface the write strobe control circuit with the address control circuit and the memory control circuit.

  In order to achieve the above object, the clock generation circuit for a write control circuit according to the present invention comprises a switching means for switching one of the second clock and the third or fourth clock to a synchronized state. It can comprise so that it may have. As the switching means here, for example, the switching circuit 30 of FIG. 8 can be used.

  As a result, flexible timing adjustment can be performed between the second clock and any one of the third or fourth clock, and as a result, the timing adjustment can be simplified even when the clock frequencies are different. It becomes possible to carry out with a circuit configuration.

  In order to achieve the above object, the data width of the data written to the write data buffer of the present invention is an integer multiple of the data width of the data output from the write data buffer, The data can be written in synchronization with a predetermined clock.

  As a result, data input to the memory control device can be performed in synchronization with the predetermined clock, and data output from the memory control device can be performed in synchronization with the strobe signal. It is possible to reduce idle cycles in the data transfer.

  In order to achieve the above object, the predetermined clock of the present invention can be configured to have the first clock.

  Thus, data input to the memory control device is performed in synchronization with the first clock, and data output from the memory control device is synchronized with the strobe signal (clock multiplied by N times the first clock). In other words, by multiplying the integer multiple of the data width by N, the data transfer from the external clock can be performed without any delay in the DDR burst transfer. It becomes possible.

  In order to achieve the above object, the predetermined clock according to the present invention can be configured to have a fifth clock having no synchronization relationship or multiplication relationship with the external clock.

  Thereby, the data input to the memory control device can be performed in synchronization with the fifth clock, and the data output from the memory control device can be performed in synchronization with the strobe signal. Input of data to the control device and output of data from the memory control device can be performed completely asynchronously. As a result, it is possible to reduce idle cycles in data transfer between memories.

  According to the present invention, it is possible to provide a memory control device that effectively performs a write operation on a semiconductor memory device by realizing delay control that flexibly supports even when the operation clock frequency is different.

  Embodiments of the present invention will be described below with reference to the drawings. In the embodiment described below, the multiplication is assumed to be two in order to describe a memory control device for writing data to a DDR type semiconductor memory device. However, the scope of the present invention is not limited to this case, and includes the case where the multiplication is N multiplication (N is a natural number).

  FIG. 2 is a block diagram showing the configuration of the memory control apparatus according to the first embodiment of the present invention.

  In FIG. 2, the memory control device 100 includes a clock generation circuit 11, a write strobe control circuit 12, a write data buffer 13, a timing control circuit 14, a memory control circuit 15, a data strobe signal IO buffer 16, and a data IO. A buffer 17 is provided. The write strobe control circuit 12 includes a strobe control circuit 12a and a write strobe output interface circuit 12b. The write data buffer 13 includes a data buffer 13a and a write data output interface circuit 13b.

  The clock generation circuit 11 is a PLL (Phase Locked Loop), and receives first to fourth clocks (hereinafter referred to as clkm, clkm × 2w, clkm × 2w01, and clkm × 2w02), respectively, with an externally input memory clock as an input. Clkm is output to the clock generation circuit 11, clkm × 2w is output to the strobe control circuit 12a, the data buffer 13a and the timing control circuit 14, and clkm × 2w01 is output to the write strobe output interface circuit 12b. X2w02 is output to the write data output interface circuit 13b.

  The strobe control circuit 12a receives the clkm × 2w output from the clock generation circuit 11 and the write signal output from the memory control circuit 15, generates a strobe signal based on the input write signal, and generates the generated strobe The signal is output to the write strobe output interface circuit 12b in synchronization with clkm × 2w.

  The write strobe output interface circuit 12b receives the clkm × 2w01 output from the clock generation circuit 11 and the strobe signal output from the strobe control circuit 12a, and operates the input strobe signal with the input clkm × 2w01. The data strobe signal is output to the IO buffer 16 via the flip-flop. Here, it is important that the output logic of the flip-flop is directly connected to the IO buffer cell.

  The data buffer 13a receives clkm × 2w output from the clock generation circuit 11, inputs data from the memory control circuit 15, and outputs the input data to the write data output interface circuit 13b in synchronization with clkm × 2w. To do.

  The write data output interface circuit 13b receives the clkm × 2w02 output from the clock generation circuit 11 and the data output from the data buffer 13a, and inputs the input data into a flip-flop that operates with the input clkm × 2w02. And output to the data IO buffer 17. Here, it is important that the output logic of the flip-flop is directly connected to the IO buffer cell.

  The timing control circuit 14 controls the output timing of the strobe control circuit 12a and the output of the data buffer 13a.

The memory control circuit 15 outputs a write signal to the strobe control circuit 12a and outputs data to the data buffer 13a.
The data strobe signal IO buffer 16 receives the strobe signal output from the write strobe output interface circuit 12 b and outputs the input strobe signal to the memory device 50.
The data IO buffer 17 receives the data output from the write data output interface circuit 13 b and outputs the input data to the memory device 50.

  The memory device 50 receives the strobe signal output from the data strobe signal IO buffer 16 and the data output from the data IO buffer 17.

  The memory control device 100 receives the memory clock and outputs a strobe signal and data to the memory device 50, that is, writes data to the memory device 50.

  Next, the operation of the memory control device 100 according to the first embodiment will be described in detail. FIG. 3 is a time chart for explaining the first embodiment of the present invention.

  First, the clock generation circuit 11 receives a memory clock, clkm synchronized with the memory clock, and clkm × 2w, clkm × 2w synchronized with the memory clock multiplied by two, clkm × 2w01, clkm × Outputs clkm × 2w02 synchronized with 2w. The memory control circuit 15 outputs a write signal to the strobe control circuit 12a and outputs data to the data buffer 13a. The strobe control circuit 12a to which the write signal is input operates in synchronization with clkm × 2w and outputs the strobe signal to the write strobe output interface circuit 12b. The write strobe output interface circuit 12b sets the strobe signal (strobe signal (FF)) as a preamble (starts driving) at the rising edge of clkm × 2w01 at t0 ′. The strobe signal (FF) is output to the data strobe signal IO buffer 16 in synchronization with clkm × 2w01 at the rising edge of clkm × 2w01 at t1 ′ after the lapse of one clock preamble period. The data strobe signal IO buffer 16 delays the input strobe signal (FF) by the IO buffer delay time and outputs it to the external memory device as a strobe signal output (strobe signal distinguished from the strobe signal (FF)). The waveform of the strobe signal output at this time is as shown in FIG. In addition, the data buffer 13a receives timing control from the timing control circuit 14 in response to generation of the strobe signal in the strobe control circuit 12a, and outputs data input by the memory control circuit 15. Thereafter, the data buffer 13a outputs the data to the write data output interface circuit 13b in synchronization with clkm × 2w. Here, the timing control circuit 14 adjusts the timing between the output of the strobe signal from the strobe control circuit 12a and the output of data from the data buffer 13a. Then, the write data output interface circuit 13b outputs the data input from the data buffer 13a to the data IO buffer 17 in synchronization with clkm × 2w02, and the data IO buffer 17 is delayed by an IO buffer delay time as a data output. Output to external memory device. The waveform of the data output at this time is as shown in FIG. As a result, the strobe signal output and the data output are executed in response to the rise and fall of the memory click, and the phase is inverted.

According to the first embodiment described above, the memory control device 100 can output the strobe signal and the data to the memory device in a state where the phase is inverted in accordance with the rise and fall of the memory clock. . This inverted phase relationship does not depend on the frequency of the memory clock. Therefore, the following effects are exhibited. The effect is that the AC timing can be easily adjusted to satisfy the setup time and hold time for the memory even when the frequency of the input memory clock is different. Further, even when the memory control device of the first embodiment is incorporated into a plurality of ASICs, since it can be reused, it can be easily built to satisfy the AC timing for the memory.
(Modification 1 of Example 1)
FIG. 4 is a block diagram illustrating a configuration of the memory control device according to the first modification of the first embodiment.

  4, the configuration of the memory control device according to the first modification of the first embodiment is different from that according to the first embodiment in that it has an ASIC internal clock 18.

  In the first modification of the first embodiment, the following operations are different from those in the first embodiment. The operation is that the data buffer 13a receives the ASIC internal clock 18 instead of clkm × 2w, and inputs data having a data width more than twice the data output by the data buffer 13a (see FIG. 4). ).

  According to the first modification of the first embodiment described above, the memory control device 100 performs data input and output (strictly speaking, data input / output to / from the data buffer 13a) in synchronization with different clocks. Also, the data width of input data is different from that of output data. That is, the memory control device 100 asynchronously inputs and outputs data having different data widths. Therefore, the following effects are exhibited. The effect is to reduce idle cycles in data transfer between memories. In addition, it is possible to obtain a configuration suitable for an ASIC on which various functional circuits are mounted. For example, when a memory is used as a data buffer for a DSP in an ASIC equipped with a high-speed DSP (Digital Signal Processor), the data transfer clock can be directly transferred from the DSP clock to clkm × 2w. desirable. Therefore, it is desired that data writing to the data buffer 13a be completely asynchronous (transferable without a synchronous clock or multiplication). Such a configuration can be realized by the first modification of the first embodiment.

  In the first modification of the first embodiment, the ASIC internal clock 18 is input to the data buffer 13a, but the present invention is not limited to this case, and the clock clkm synchronized with the memory clock is not limited to this case. Alternatively, a clock having no synchronization relationship or multiplication relationship with the memory clock may be input. In particular, when the clock clkm synchronized with the memory clock is input to the data buffer 13a, there is an effect that data can be transferred without a DDR burst transfer even if the data is transferred from the memory clock operation. In the first modification of the first embodiment, data having a data width more than twice the data output from the data buffer 13a is input to the data buffer 13a. However, the present invention is limited to this case. It is not a thing.

  FIG. 5 is a block diagram showing the configuration of the memory control apparatus according to the second embodiment of the present invention.

  In FIG. 5, the memory control device 200 includes a clock generation circuit 11, a write strobe control circuit 12, a write data buffer 13, a timing control circuit 14, a memory control circuit 15, a data strobe signal IO buffer 16, and a data An IO buffer 17 and an address / command control circuit 19 are provided. The write strobe control circuit 12 includes a strobe control circuit 12a and a write strobe output interface circuit 12b. The write data buffer 13 includes a data buffer 13a and a write data output interface circuit 13b.

  The operation of each circuit constituting the memory control device 200 of the second embodiment is the same as that of the first embodiment except for the clock generation circuit 11, the memory control circuit 15, and the address / command control circuit 19. Here, operations of the clock generation circuit 11, the memory control circuit 15, and the address / command control circuit 18 will be described, and description of other circuits will be omitted.

  The clock generation circuit 11 is a PLL and generates first to fourth clocks (hereinafter referred to as clkm, clkm × 2w, clkm × 2w01, and clkm × 2w02, respectively) by using a memory clock input from the outside as clkm. Is output to the clock generation circuit 11, the memory control circuit 15 and the address / command control circuit 19, clkm × 2w is output to the strobe control circuit 12a, the data buffer 13a and the timing control circuit 14, and clkm × 2w01 is output to the write strobe output interface. Output to the circuit 12b, and output clkm × 2w02 to the write data output interface circuit 13b.

  The memory control circuit 15 receives clkm output from the clock generation circuit 11, outputs a write signal to the strobe control circuit 12a in synchronization with clkm, and outputs data to the data buffer 13a in synchronization with clkm.

  The address / command control circuit 19 receives the clkm output from the clock generation circuit 11 and generates and generates a RAS (Row Active Strobe) signal, a CAS (Column Active Strobe) signal, a WE (Write Enable) signal, and the like. The above-described signals and the like are output to the memory device 50 in synchronization with clkm.

  According to the second embodiment described above, the memory control circuit 15 and the address / command control circuit 19 can operate in synchronization with the clkm output from the clock generation circuit 11. That is, the memory control circuit 15 and the address / command control circuit 19 can operate in synchronization with the memory clock (synchronized with clkm). Therefore, the following effects are exhibited. The effect is that the memory control circuit 15 and the address / command control circuit 19 can easily interface with the clkm × 2w double clock generated by the clock generation circuit 11, so that strobe generation from the memory control circuit to the strobe control circuit occurs. It is easy to synchronize the signal for transmitting the timing inside the ASIC. In addition, since clkm × 2w01 and clkm × 2w02 that operate flip-flops related to external AC timing are different clock systems, timing adjustment can be performed regardless of the timing of these flip-flops. For this reason, the layout of the ASIC is easy. In the second embodiment, the memory control device 200 includes the memory control circuit 15 and the address / command control circuit 19 as components, and both operate in synchronization with the clkm output from the clock generation circuit 11. However, the present invention is not limited to this case, and it is assumed that the same configuration and operation can be achieved in Examples 3 and 4 described later.

  FIG. 6 is a block diagram showing the configuration of the memory control apparatus according to the third embodiment of the present invention.

  In FIG. 6, the memory control device 300 includes a clock generation circuit 11, a write strobe control circuit 12, a write data buffer 13, a timing control circuit 14, a memory control circuit 15, a data strobe signal IO buffer 16, and a data An IO buffer 17 and a write control circuit clock generation circuit 20 are provided. The write strobe control circuit 12 includes a strobe control circuit 12a and a write strobe output interface circuit 12b. The write data buffer 13 includes a data buffer 13a and a write data output interface circuit 13b.

  The operation of each circuit constituting the memory control device 300 of the third embodiment is as follows. The clock generation circuit 11, the strobe control circuit 12a, the write strobe output interface circuit 12b, the data buffer 13a, the write data output interface circuit 13b, Except for the write control circuit clock generation circuit 20, the second embodiment is the same as the first embodiment.

  Here, operations of the clock generation circuit 11, the strobe control circuit 12a, the write strobe output interface circuit 12b, the data buffer 13a, the write data output interface circuit 13b, and the write control circuit clock generation circuit 20 will be described. Description of other circuits is omitted.

  The clock generation circuit 11 is a PLL, and generates clkm and clkm × 2w with an externally input memory clock as an input. clkm is output to the clock generation circuit 11, and clkm × 2w is output to the clock generation circuit 20 for the write control circuit.

  The strobe control circuit 12a receives clkm × 2w output from the write control circuit clock generation circuit 20 and the write signal output from the memory control circuit 15, and generates a strobe signal based on the input write signal. The generated strobe signal is output to the write strobe output interface circuit 12b in synchronization with clkm × 2w.

  The write strobe output interface circuit 12b receives clkm × 2w01 output from the write control circuit clock generation circuit 11 and the strobe signal output from the strobe control circuit 12a, and inputs the input strobe signal to the input clkm × The data strobe signal is output to the IO buffer 16 through a flip-flop operating at 2w01. Here, it is important that the output logic of the flip-flop is directly connected to the IO buffer cell.

  The data buffer 13a receives clkm × 2w output from the write control circuit clock generation circuit 20, inputs data from the memory control circuit 15, and writes the input data in synchronization with clkm × 2w as a write data output interface. Output to the circuit 13b.

  The write data output interface circuit 13b inputs clkm × 2w02 output from the write control circuit clock generation circuit 20 and the data output from the data buffer 13a, and operates the input data with the input clkm × 2w02. To the data IO buffer 17 via the flip-flop. Here, it is important that the output logic of the flip-flop is directly connected to the IO buffer cell.

  The clock generation circuit 20 for the write control circuit receives the clkm × 2w output from the clock generation circuit 11, outputs the clkm × 2w to the strobe control circuit 12a, the data buffer 13a, and the timing control circuit 14, and outputs clkm × 2w. Clkm × 2w01 whose phase is inverted is output to the write strobe output interface circuit 12b, and clkm × 2w02 synchronized with clkm × 2w is output to the write data output interface circuit 13b.

  The memory control device 300 receives the memory clock and outputs a strobe signal and data to the memory device 50. That is, data is written to the memory device 50.

According to the third embodiment described on more than, clkm × 2w02 is an operation clock of clkm × 2w01 and write data output interface circuit 13b is an operating clock of the write strobe output interface circuit 12b, which occurs in the clock generation circuit 11 Rather than the write strobe control circuit 12 and the write data buffer 13, the clock generation circuit 20 for the write control circuit in the vicinity of the control circuit generates an access request to the memory control unit, Even if the buffer circuit that holds the data to be originally written operates at a different clock frequency, it can cope with the problem. Therefore, the following effects are exhibited. The effect is that it can cope with the diversity of ASIC such as the internal clock and the memory clock being different. On the ASIC, there is data exchange between clkm and clkm × 2w, but there is no data exchange between clkm and clkm × 2w01 and clkm × 2w02. By making clkm independent of clkm × 2w01 and clkm × 2w02, timing adjustment inside the ASIC is facilitated. Further, the block layout can be implemented by closing the write strobe control circuit 12 and the write data buffer 13 which are closed in FIG.
(Modification of Example 3)
FIG. 7 is a block diagram illustrating a configuration of a memory control device according to a modification of the third embodiment.

  7, the memory control device 300 has a plurality of write data / write strobe control circuits (21a, 21b,...). Here, each write data / write strobe control circuit (21a, 21b,...) Has a write strobe control circuit 12, a write data buffer 13, a timing control circuit 14 and a write control circuit clock generation shown in the third embodiment. The circuit 20 is combined.

  The write data / write strobe control circuit 21a receives clkm × 2w output from the clock generation circuit 11 as an input, the write strobe control circuit 12, the write data buffer 13, and the timing control circuit constituting the write data / write strobe control circuit 21a. 14 and the write control circuit clock generation circuit 20 output a strobe signal to the data strobe signal IO buffer 16a and a corresponding data signal (0 to 7) to the data IO buffer 17a.

  The write data / write strobe control circuit 21b outputs a strobe signal to the data strobe signal IO buffer 16b by the same operation as the write data / write strobe control circuit 20a, and outputs the corresponding data signal (8-15) to the data IO buffer. To 17b.

  According to the modification of the third embodiment described above, the write data / write strobe control circuit 21 which is a combination of the write strobe control circuit 12, the write data buffer 13, and the write control circuit clock generation circuit 20 is provided in units of strobe signals. Stated to have more than one. Therefore, the following effects are exhibited. The effect is that it is not necessary to change the circuit configuration even when the memory bus width is increased, and the diversion and versatility when developing different ASICs are enhanced. Further, the write data / write strobe control circuit 21 can be used as one general-purpose cell. In this case, since the timing is fixed in cell units, the timing between clkm × 2w, clkm × 2w01, and clkm × 2w02 in the write data / write strobe control circuit 21 does not need to be adjusted when developing another ASIC. .

  FIG. 8 is a block diagram showing the configuration of the memory control apparatus according to the fourth embodiment of the present invention.

  8, the memory control device 400 includes a clock generation circuit 11, a write strobe control circuit 12, a write data buffer 13, a timing control circuit 14, a memory control circuit 15, and a write control circuit clock generation circuit 20. .

  The operation of each circuit constituting the memory control device 400 of the fourth embodiment is the same as that of the third embodiment except for the write control circuit clock generation circuit 20. Here, the operation of the clock generation circuit 20 for the write control circuit will be described, and description of other circuits will be omitted.

  The clock generation circuit 20 for the write control circuit receives the clkm × 2w output from the clock generation circuit 11, outputs the clkm × 2w to the strobe control circuit 12a, the data buffer 13a, and the timing control circuit 14, and outputs a clock switching signal. Clkm × 2w01 and clkm × 2w02 whose phase relationship is controlled are output to the write strobe output interface circuit 12b and the write data output interface circuit 13b, respectively. Details of the phase-related control by the click switching signal will be described later.

  Next, the operation of the memory control device 400 according to the fourth embodiment will be described in detail focusing on the phase-related control operation by the clock switching signal in the write control circuit clock generation circuit 20 described above. FIG. 9 is a time chart for explaining the fourth embodiment. 9A shows a case where the edge of the memory clock A and the falling edge of clkm × 2w01 are synchronized. FIG. 9B shows a case where the clock frequency is different, for example, at a clock frequency twice that of the memory clock A. When the edge of the memory clock B is synchronized with the falling edge of clkm × 2w01, FIG. 9C shows the case where the edge of the memory clock B is synchronized with the rising edge of clkm × 2w01. The waveforms of memory clock, clkm × 2w01, strobe signal output (FF output), IO buffer output enable, and strobe signal output are shown. The parameter A in FIGS. 9A, 9B, and 9C indicates the timing difference between the rising edge of the memory clock and the rising edge of the strobe signal output in each case. Here, the output delay of the IO buffer (a constant value regardless of the clock frequency) is also taken into consideration.

  First, the operation shown in FIG. 9A will be described. First, the strobe signal (FF output) is set to the preamble (drive start) at the rising edge of clkm × 2w01 at t0 ′. A strobe signal (FF output) is output in synchronization with clkm × 2w01 at the rising edge of clkm × 2w01 at t1 ′ after the lapse of one clock preamble period. At this time, the waveform of the strobe signal output to the memory device 50 is a waveform obtained by delaying the strobe signal (FF output) by the delay amount of the IO buffer output. At this time, the parameter A is indicated by 91 in FIG.

  Next, the operation shown in FIG. 9B will be described. First, the strobe signal (FF output) is set to the preamble (drive start) at the rising edge of clkm × 2w01 at t0 ′. The strobe signal (FF output) is output in synchronization with clkm × 2w01 at the rising edge of clkm × 2w01 at t1 ′ after the preamble period of one clock elapses. At this time, the waveform of the strobe signal output to the memory device 50 is a waveform obtained by delaying the strobe signal (FF output) by the delay amount of the IO buffer output. At this time, the parameter A is indicated by 92 in FIG.

  Finally, the operation shown in FIG. 9C will be described. First, at the rising edge of clkm × 2w01 at t1, the strobe signal (FF output) is set as a preamble (start of driving). A strobe signal (FF output) is output in synchronization with clkm × 2w01 at the rising edge of clkm × 2w01 at t2 after the lapse of one clock preamble period. At this time, the waveform of the strobe signal output to the memory device 50 is a waveform obtained by delaying the strobe signal (FF output) by the delay amount of the IO buffer output. At this time, the parameter A is indicated by 93 in FIG.

  Here, when FIG. 9A is compared with FIG. 9B, the timing difference of 92 is wider than 91. That is, as the clock frequency changes, the performance related to the signal timing of the memory clock and the strobe signal output is degraded. 9B is compared with FIG. 9C, the timing difference of 93 is narrower than that of 92. That is, the performance related to the timing of the memory clock and strobe signal output is improved.

  According to the fourth embodiment described above, when the case shown in FIG. 9A is considered as a reference, when the clock frequency is different (see FIG. 9B), the phase of clkm × 2w01 is controlled. (See FIG. 9 (c)), the performance related to the timing of the memory clock and strobe signal output can be improved (compare FIG. 9 (b) and FIG. 9 (c)). Therefore, the following effects are exhibited. The effect is that the delay control can be performed by the clock switching signal in the write control circuit clock generation circuit 20 even when the clock frequency is different. For this reason, even when the clock frequency is different, it is possible to cope with it, and it is possible to cope with a simple circuit configuration. In addition, there are more choices to meet the standards shown in FIG. In the fourth embodiment, the memory control device 400 uses a memory clock as an input. However, a clock generated by a general-purpose clock generator inside or outside the memory control device 400 may be used as an input. Here, the reference clock of the general-purpose clock generator may be output from the memory control device 400.

Time chart showing standards for write operation to DDR-SDRAM 1 is a block diagram showing a configuration of a memory control device according to a first embodiment of the present invention. Time chart for explaining Example 1 of the present invention The block diagram which shows the structure of the memory control apparatus of the modification of Example 1 of this invention. The block diagram which shows the structure of the memory control apparatus of Example 2 of this invention. The block diagram which shows the structure of the memory control apparatus of Example 3 of this invention. The block diagram which shows the structure of the memory control apparatus of the modification of Example 3 of this invention. FIG. 5 is a block diagram showing the configuration of a memory control device according to a fourth embodiment of the present invention. Time chart for explaining Example 4 of the present invention

Explanation of symbols

11 clock generation circuit 12 write strobe control circuit 12a strobe control circuit 12b write strobe output interface circuit 13 write data buffer 13a data buffer 13b write data output interface circuit 14 timing control circuit 15 memory control circuits 16, 16a, 16b data strobe signal IO buffer 17, 17a, 17b Data IO buffer 18 ASIC internal clock 19 Address / command control circuit 20 Write control circuit clock generation circuit 21a, 21b Write data / write strobe control circuit 30 Switching circuit 50 Memory device 100, 200, 300, 400 Memory Control device

Claims (8)

In a memory control device that writes data to a semiconductor memory device,
A clock generation circuit for generating a plurality of clock signals;
A write strobe control circuit for controlling a strobe signal applied to the semiconductor memory device;
A write data buffer for temporarily writing data to be given to the semiconductor memory device;
The clock generation circuit includes a first clock synchronized with an external clock, a second clock obtained by multiplying the external clock, a third clock whose phase is inverted with respect to the second clock, and the second clock And a fourth clock synchronized with the clock of
The write strobe control circuit operates in synchronization with the second clock, outputs the strobe signal in synchronization with the third clock,
The write data buffer operates in synchronization with the second clock, and outputs the data in synchronization with the fourth clock. In a memory control device that writes data to a semiconductor memory device,
A clock generation circuit for generating a plurality of clock signals;
A clock generation circuit for a write control circuit that generates a plurality of clock signals based on one of the plurality of clock signals;
A write strobe control circuit for controlling a strobe signal applied to the semiconductor memory device;
A write data buffer for temporarily writing data to be given to the semiconductor memory device;
The clock generation circuit generates a first clock synchronized with an external clock and a second clock obtained by multiplying the external clock;
The write control circuit clock generation circuit generates a third clock whose phase is inverted with respect to the second clock, and a fourth clock synchronized with the second clock,
The write strobe control circuit operates in synchronization with the second clock, outputs the strobe signal in synchronization with the third clock,
The write data buffer operates in synchronization with the second clock, and outputs the data in synchronization with the fourth clock. In a memory control device that writes data to a semiconductor memory device,
A clock generation circuit for generating a plurality of clock signals;
A plurality of write data / write strobe control circuits for outputting data and a strobe signal based on one of the plurality of clock signals;
Each of the plurality of write data / write strobe control circuits includes:
A clock generation circuit for a write control circuit that generates a plurality of clock signals based on one of the plurality of clock signals;
A write strobe control circuit for controlling a strobe signal applied to the semiconductor memory device;
A write data buffer for temporarily writing data to be given to the semiconductor memory device;
The clock generation circuit generates a first clock synchronized with an external clock and a second clock obtained by multiplying the external clock;
The write control circuit clock generation circuit generates a third clock whose phase is inverted with respect to the second clock, and a fourth clock synchronized with the second clock,
The write strobe control circuit operates in synchronization with the second clock, outputs the strobe signal in synchronization with the third clock,
The write data buffer operates in synchronization with the second clock, and outputs the data in synchronization with the fourth clock.   The first clock is an address control circuit that generates a signal for controlling an address of the semiconductor memory device, and a memory control circuit that generates a signal for controlling the write strobe control circuit and / or a signal for controlling the write data buffer. 4. The memory control device according to claim 1, wherein the memory control device is an operation clock of the memory control device.   5. The write control circuit clock generation circuit includes switching means for switching any one of the second clock and the third or fourth clock to a synchronous state. The memory control device according to 1.   The data width of the data written to the write data buffer is an integer multiple of the data width of the data output from the write data buffer, and the writing of the data to the write data buffer is synchronized with a predetermined clock. 6. The memory control device according to claim 1, wherein the memory control device is performed as described above.   The memory control device according to claim 6, wherein the predetermined clock is the first clock.   7. The memory control device according to claim 6, wherein the predetermined clock is a fifth clock having no synchronization relationship or multiplication relationship with the external clock.

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