JP4718863B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device capable of wireless communication.

  Semiconductor devices typified by ID chips capable of transmitting and receiving data such as identification information wirelessly are being put to practical use in various fields, and further expansion of the market is expected as a new type of communication information terminal. . An ID chip is also called a wireless tag, an RFID (Radio frequency identification) tag, or an IC tag, and a type having an antenna and an integrated circuit formed using a semiconductor substrate is now in practical use. is there.

  Unlike magnetic cards and barcodes, which can also read data wirelessly, ID chips are not likely to be able to read stored data by a physical method and are difficult to tamper with. Are better. Unlike magnetic cards, bar codes, etc., the production of ID chips requires a relatively large-scale production facility, and therefore has the advantage of being difficult to forge.

For example, the following Patent Document 1 proposes a method in which a fine IC chip is mounted on securities to prevent unauthorized use and can be reused if it is lost or stolen and can be returned to an authorized management source. Has been.
JP 2001-260580 A

  If it is possible to more reliably prevent forgery of the ID chip and unauthorized rewriting of data recorded in the ID chip, for example, forgery of an object to which the ID chip is attached can be prevented. It is possible to prevent impersonation of the product origin, producer, distribution channel, and the like. However, as ID chip counterfeiting and illegal data rewriting techniques become more sophisticated, it is not easy to prevent counterfeiting or forgery or to detect them simply by using an ID chip.

  In addition, by forming a non-volatile memory in which data cannot be rewritten in the integrated circuit of the ID chip, the ID chip can be more counterfeited than when a rewritable memory is used. It can be surely prevented. Among non-volatile memories that cannot be rewritten, for example, a mask ROM can be used for an ID chip relatively easily without complicating the process. However, since the data stored in the integrated circuit includes an identification number unique to the ID chip, the photomask for determining unique data among the photomasks used for forming the mask ROM is disposable. Therefore, the problem that cost cannot be suppressed arises.

  Further, in principle, the ID chip can be made smaller than a magnetic card, a bar code, or the like, and therefore, it is expected to further expand the range of applications. However, it is assumed that the ID chip is attached to a flexible material (flexible material) such as paper or plastic depending on the application, but the semiconductor substrate used as the base of the ID chip is a machine compared to the above-described material. Low strength. Therefore, if an ID chip is formed on a packaging material, tag, certificate, banknote, securities, or the like that uses a flexible material as a support, the ID chip may be damaged in the process of use, which is not practical.

  Note that the mechanical strength of the ID chip can be improved to some extent by reducing the area of the ID chip itself. However, in this case, it is difficult to ensure the circuit scale, and the use of the ID chip is limited. Therefore, if it is important to secure the circuit scale of the ID chip, the area of the ID chip cannot be reduced without limitation, and there is a limit in improving the mechanical strength.

  Further, in the case of an ID chip formed using a semiconductor substrate, the semiconductor substrate functions as a conductor and shields radio waves, so that there is a problem that radio wave signals are easily attenuated depending on directions.

  In view of the above problems, the present invention provides a semiconductor device that can prevent forgery or illegal data rewriting while suppressing cost and can increase mechanical strength without reducing the circuit scale of an integrated circuit. Is an issue.

  A semiconductor device typified by an ID chip of the present invention is a thin film semiconductor having two regions: a first region with high crystallinity and a second region with lower crystallinity than the first region. Use a membrane. Specifically, among the thin semiconductor films, a TFT (thin film transistor) of a circuit that requires high speed operation is formed using the first region, and the second region is used for an identification ROM. Forming a memory element.

  The formation of the first region and the second region can be realized, for example, by crystallization using a continuous wave laser. In the case of a continuous wave laser, unlike a pulsed laser, a semiconductor film is irradiated with laser light while scanning in one direction, and a crystal is continuously grown in the scanning direction. A first region having a long collection of crystal grains can be formed. By using a collection of crystal grains extending along the scanning direction for the active layer of the TFT, a TFT with relatively uniform characteristics with few crystal grain boundaries intersecting the carrier movement direction is formed. It is considered possible.

  In addition, when a continuous wave laser is used, the second region in which crystal grains are significantly smaller than the center of the beam spot and the crystallinity is inferior at both ends of the beam spot in the direction perpendicular to the scanning direction. It is formed. In the present invention, the memory element is formed by using the second region having poor crystallinity out of the semiconductor film crystallized by the laser, thereby varying the characteristics of each memory element. The variation in the characteristics of the memory element depends on the variation in crystallinity, and thus can be generated irregularly even if the circuit configuration and layout are made common and the same manufacturing process is used. Therefore, by using the variation in characteristics of each memory element as data, a nonvolatile memory in which unique data is stored can be formed. In this specification, a ROM that uses variation in characteristics of each memory element as data is hereinafter referred to as a random number ROM.

  The integrated circuit may be formed over a substrate, or after being formed over the substrate, may be attached to a separately prepared flexible (flexible) substrate. The ID chip of the present invention can take a form having an antenna in addition to an integrated circuit. The integrated circuit operates using an alternating voltage generated by the antenna and modulates the alternating voltage applied to the antenna, thereby transmitting a signal to the reader / writer. Note that the antenna may be formed together with the integrated circuit, or may be formed separately from the integrated circuit and electrically connected later. Such an ID chip on which an antenna is mounted is also called a wireless chip.

  An integrated circuit is bonded by a method in which a metal oxide film is provided between a substrate having high heat resistance and the integrated circuit, the metal oxide film is weakened by crystallization, and the integrated circuit is peeled off and bonded together. A substrate having high heat resistance, in which a separation layer is provided between the integrated circuit and the integrated circuit, and the separation layer is removed by laser light irradiation or etching to separate and bond the substrate and the integrated circuit; Various methods can be used such as a method in which the integrated circuit is separated from the substrate by being mechanically deleted or removed by etching with a solution or gas and bonded.

In addition, the integrated circuits may be stacked by attaching separately manufactured integrated circuits to increase the circuit scale and the memory capacity. Since the integrated circuit is remarkably thinner than an ID chip manufactured using a semiconductor substrate, the mechanical strength of the ID chip can be maintained to some extent even when a plurality of integrated circuits are stacked. For connecting the stacked integrated circuits, a known connection method such as a flip chip method, a TAB (Tape Automated Bonding) method, or a wire bonding method can be used.

  Since the circuit configuration and layout may be common in the present invention, it is not necessary to dispose a photomask for each ID chip unlike a mask ROM, and thus the cost spent for manufacturing the ID chip can be suppressed. Further, in the case of manufacturing a non-volatile memory such as a flash memory other than the mask ROM, it is difficult to reduce the cost because it is necessary to increase the manufacturing process. However, in the case where a TFT is used as the memory element of the random number ROM, the TFT used as the memory element can be manufactured by the same manufacturing process as the TFT used in other integrated circuits constituting the ID chip. Therefore, it is possible to prevent forgery of the ID chip or unauthorized data rewriting while suppressing an increase in cost associated with the production of the random number ROM.

  When a mask ROM is used, the identification number may be decoded by analyzing the circuit layout. However, since the random number ROM can be formed with the same circuit configuration, layout, and manufacturing process, it is possible to prevent data contents from being read by a method other than electrical data reading.

  In the ID chip of the present invention, an integrated circuit is formed using insulated TFTs, and thus a flexible substrate can be used. In this case, higher mechanical strength can be obtained without reducing the area of an ID chip using a semiconductor substrate. Therefore, it is possible to increase the mechanical strength of the ID chip and further expand the application range of the ID chip without reducing the circuit scale.

  In addition, in the ID chip of the present invention, an integrated circuit is formed using insulated TFTs, so that unlike a transistor formed on a semiconductor substrate, a parasitic diode is not easily formed between the substrate and the ID chip. Therefore, a large amount of current does not flow into the drain region due to the potential of the AC signal applied to the source region or the drain region, and deterioration or destruction is unlikely to occur. In addition, the ID chip of the present invention is advantageous in that radio waves are less likely to be shielded than an ID chip formed using a semiconductor substrate, and the signal can be prevented from being attenuated by shielding the radio waves.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  First, a structure of a semiconductor film crystallized using a continuous wave laser will be described with reference to FIG. In FIG. 1A, reference numeral 101 corresponds to a beam spot of laser light. It is assumed that the beam spot 101 is scanned in a direction perpendicular to the major axis direction of the beam spot 101 as indicated by a hollow arrow. The semiconductor film crystallized by the beam spot 101 can be classified into the first region 102 and the second region 103 depending on the difference in crystallinity.

  In the first region 102 that overlaps with the central region of the beam spot 101, the energy density of the irradiated laser light is high, so that the semiconductor film can be completely melted. The region where the semiconductor film is completely melted is continuously moved in the semiconductor film by scanning the beam spot 101. Therefore, large-sized crystal grains continuously grown in the scanning direction are formed. It is formed. Specifically, crystal grains having a width in the scanning direction of 10 to 30 μm and a width in the direction perpendicular to the scanning direction of about 1 to 5 μm can be formed.

  In the second region 103 overlapping with the vicinity of the edge of the beam spot 101, it is difficult to form a state in which the semiconductor film is completely melted because the energy density of the irradiated laser light is low. Therefore, unlike the first region 102, only relatively small crystal grains (microcrystals) having a random position and size and a grain size of about 0.2 μm to several μm are easily formed.

FIGS. 20A and 20B show a scanning electron microscope (SEM) of the first region obtained by crystallization using the second harmonic of a continuous wave Nd: YVO ₄ laser. ). 20A corresponds to an SEM image with a magnification of 10,000 times, and FIG. 20B corresponds to an SEM image with a magnification of 30,000 times. FIG. 21 shows an SEM image of the second region obtained by crystallization using the second harmonic of a continuous wave Nd: YVO ₄ laser. FIG. 21 corresponds to an SEM image with a magnification of 30,000. Note samples are used in both FIGS. 20 and 21, using an amorphous semiconductor film with a thickness of 200 nm, is obtained by irradiating a laser beam at a scanning rate 75 cm / sec, seco solution (HF: H ₂ O = 2: 1 (chemical solution prepared using K ₂ Cr ₂ O ₇ as an additive) is applied (seco-etching), and crystal grain boundaries are revealed.

  As can be seen from FIGS. 20A and 20B, the first region grows continuously in the scanning direction, has a width in the scanning direction of 10 to 30 μm, and is perpendicular to the scanning direction. It can be seen that there are crystal grains having a width in the direction of about 1 to 5 μm. Further, as can be seen from FIG. 21, it can be seen that crystal grains having a grain size of about 0.2 μm to several μm exist in the second region.

  In the present invention, a semiconductor element other than the random number ROM in the integrated circuit is formed using the semiconductor film in the first region 102. A memory element used for the random number ROM is formed using the semiconductor film in the second region 103.

  FIG. 1B shows a layout of the active layer 104 of the TFT formed in the first region 102. The active layer 104 is desirably laid out so that the carrier moving direction and the scanning direction of the laser light coincide. It is considered that by making the carrier moving direction coincide with the scanning direction of the laser beam, it is possible to form a TFT having relatively uniform characteristics by preventing the crystal grain boundary from crossing the carrier moving direction.

  FIG. 1C shows a layout of an active layer 105 of a TFT used as a memory element formed in the second region 103. The active layer 105 is preferably laid out so that the channel length L is from half the crystal grain size X to about two to three times the crystal grain size, that is, X / 2 ≦ L ≦ 3X. With the above structure, one or a plurality of crystal grain boundaries are formed in the active layer 105 across the direction in which carriers move. Note that it is desirable that the number of crystal grain boundaries crossing the direction of carrier movement varies between the active layers 105 to such an extent that the data between the memory elements can be different.

  Next, a specific configuration of the random number ROM will be described with reference to FIG. FIG. 2A shows an example of a random number ROM. The random number ROM includes a decoder 201, a memory cell array 202, and a reading circuit 203. In the memory cell array 202, a plurality of memory cells 204 are laid out in a matrix, and each memory cell 204 is connected to a word line 205 and a bit line 206.

  When the word line 205 is selected by the decoder 201 and the bit line 206 is selected by the reading circuit 203, the memory cell 204 at a specific address can be selected. Data can be read from the selected memory cell 204 by amplifying and reading the potential of the selected bit line 206 in the read circuit 203.

  An example of the memory cell 204 is shown in FIG. The memory cell 204 has a TFT 207 used as a memory element. The TFT 207 has one of a source region and a drain region connected to the bit line 206 and the other connected to the word line 205. The gate electrode of the TFT 207 is connected to the word line 205.

  In the memory cell 204, when a voltage Vword higher than the threshold voltage Vth of the TFT 207 is applied to the word line 205, the voltage Vbit of the bit line 206 becomes Vword−Vth. Note that since the threshold voltage Vth of the TFT 207 has variations due to crystal grain boundaries, the voltage Vbit of the bit line 206 also varies. FIG. 2C shows the distribution of the number of memory cells 204 with respect to the voltage Vbit of the bit line 206 when the variation of the threshold voltage Vth is σVth. As shown in FIG. 2C, the threshold voltage Vth of the TFT 207 of each memory cell 204 varies, so that the voltage Vbit of the bit line 206 has a unique value corresponding to each memory cell 204. .

  Next, an example of a functional configuration of the ID chip of the present invention will be described with reference to FIG.

  In FIG. 3, 900 is an antenna, and 901 is an integrated circuit. The antenna 900 includes an antenna coil 902 and a capacitor element 903 formed in the antenna coil 902. The integrated circuit 901 includes a demodulation circuit 909, a modulation circuit 904, a rectifier circuit 905, a microprocessor 906, a memory 907, a switch 908 for applying load modulation to the antenna 900, and a random number ROM 910. Note that the memory 907 is not limited to one, and a plurality of memories 907 may be used, such as SRAM, flash memory, ROM, or FRAM (registered trademark).

  A signal transmitted as a radio wave from the reader / writer is converted into an AC electrical signal by electromagnetic induction in the antenna coil 902. The demodulation circuit 909 demodulates the alternating electrical signal and transmits it to the subsequent microprocessor 906. The rectifier circuit 905 generates a power supply voltage using an alternating electrical signal and supplies the power supply voltage to the subsequent microprocessor 906.

  The microprocessor 906 performs various arithmetic processes according to the input signal. The memory 907 stores programs and data used in the microprocessor 906, and can also be used as a work area during arithmetic processing.

  The random number ROM 910 stores data unique to the ID chip. When a signal designating an address is transmitted from the microprocessor 906 to the random number ROM 910, the random number ROM 910 can read out data stored in the memory cell at the designated address and send it to the microprocessor 906.

  When data is sent from the microprocessor 906 to the modulation circuit 904, the modulation circuit 904 can control the switch 908 and apply load modulation to the antenna coil 902 according to the data. The reader / writer receives the load modulation applied to the antenna coil 902 as an electromagnetic wave, and as a result, can read data from the microprocessor 906.

  Note that the ID chip of the present invention does not necessarily have the antenna 900. In the case where the antenna 900 is not provided, a connection terminal for electrical connection with the antenna 900 is provided on the ID chip.

  Note that the ID chip shown in FIG. 3 only shows one embodiment of the present invention, and the present invention is not limited to the above structure. The ID chip of the present invention does not necessarily have the microprocessor 906 and the memory 907. The signal transmission method is not limited to the electromagnetic coupling method as shown in FIG. 3, and an electromagnetic induction method, a microwave method, or other transmission methods may be used.

  Next, the layout of the integrated circuit and the layout of the first region and the second region formed by laser light irradiation will be described with reference to FIGS.

  In FIG. 4, a first region 401 in which large-sized crystal grains continuously grown in the laser beam scanning direction indicated by the arrow are formed, and a second region 402 in which microcrystals are easily formed. An example of the layout is shown. The first region 401 and the second region 402 are alternately formed and both extend in the laser beam scanning direction indicated by the arrow.

  FIG. 4 shows a layout of the integrated circuit. Reference numeral 403 denotes a circuit group other than the random number ROM in the integrated circuit. Reference numeral 404 denotes a reading circuit included in the random number ROM, 405 corresponds to a decoder included in the random number ROM, and 406 corresponds to a memory cell array included in the random number ROM.

  At least the memory cell array 406 is laid out in the second region 402 where microcrystals are easily formed. The circuits 403 other than the random number ROM are laid out in the first region 401 in which continuously grown crystal grains having a large grain size are formed. Then, a wiring (for example, 407) for connecting circuits 403 other than the random number ROM, a wiring (for example, 408) for connecting the circuit 403 other than the random number ROM, the reading circuit 404, the decoder 405, or the memory cell array 406, etc. Can be laid out so as to cross the region 402.

  Note that it is not always necessary to lay out all the circuits 403 other than the random number ROM in the first area 401. For example, a circuit that requires high-speed driving or a circuit that requires reduction in variation in characteristics of semiconductor elements is laid out in the first region 401, and other circuits are laid out in the second region 402. Anyway.

  In FIG. 4, the reading circuit 404 and the decoder 405 used for the random number ROM are both laid out in the first area 401, but the present invention is not limited to this configuration. A reading circuit 404 or a decoder 405 may be laid out in the second region 402 together with the memory cell array 406.

  Next, a detailed manufacturing method of the ID chip of the present invention will be described. Note that in this embodiment, an isolated TFT is exemplified as a semiconductor element; however, a semiconductor element used for an integrated circuit is not limited to this, and any circuit element can be used. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, and the like are typically given.

  First, as illustrated in FIG. 5A, a separation layer 501 is formed over a heat-resistant substrate (first substrate) 500 by using a sputtering method. As the first substrate 500, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate including a SUS substrate or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. .

  As the separation layer 501, a layer containing silicon as its main component, such as amorphous silicon, polycrystalline silicon, single crystal silicon, or microcrystalline silicon (including semi-amorphous silicon) can be used. The separation layer 501 can be formed by a sputtering method, a low pressure CVD method, a plasma CVD method, or the like. In this embodiment mode, amorphous silicon with a thickness of about 50 nm is formed by a low pressure CVD method and used as the separation layer 501. Note that the separation layer 501 is not limited to silicon and may be formed using a material that can be selectively removed by etching. The thickness of the release layer 501 is desirably 50 to 60 nm. The semi-amorphous silicon release layer 501 may be 30 to 50 nm.

  Next, a base film 502 is formed over the peeling layer 501. The base film 502 is provided in order to prevent alkali metal such as Na or alkaline earth metal contained in the first substrate 500 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element such as TFT. The base film 502 also has a role of protecting the semiconductor element in a process of peeling the semiconductor element later. The base film 502 may be a single layer or a stack of a plurality of insulating films. Therefore, the insulating film is formed using an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film.

In this embodiment mode, the base film 502 is formed by sequentially laminating a 100 nm thick SiON film, a 50 nm thick SiNO film, and a 100 nm thick SiON film. However, the present invention is not limited to this. For example, instead of the lower SiON film, a siloxane-based resin having a film thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiNx, Si ₃ N ₄ or the like) may be used instead of the middle-layer SiNO film. Further, an SiO ₂ film may be used instead of the upper SiON film. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Alternatively, the lower layer of the base film 502 closest to the peeling layer 501 may be formed of a SiON film or a SiO ₂ film, the middle layer may be formed of a siloxane-based resin, and the upper layer may be formed of a SiO ₂ film.

Here, the silicon oxide film may be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD using a mixed gas such as SiH ₄ / O ₂ , TEOS (tetraethoxysilane) / O _2, or the like. it can. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ / NH ₃ . The silicon oxynitride film (SiOxNy: x> y) and the silicon nitride oxide film (SiNxOy: x> y) are typically formed by plasma CVD using a mixed gas of SiH ₄ / N ₂ O. Can do.

  Next, a semiconductor film 503 is formed over the base film 502. The semiconductor film 503 is preferably formed without being exposed to the air after the base film 502 is formed. The thickness of the semiconductor film is 20 to 200 nm (desirably 40 to 170 nm, preferably 50 to 150 nm). Note that the semiconductor film 503 may be an amorphous semiconductor, a semi-amorphous semiconductor, or a polycrystalline semiconductor. As the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

An amorphous semiconductor can be obtained by glow discharge decomposition of a silicide gas. Typical silicide gases include SiH ₄ and Si ₂ H ₆ . This silicide gas may be diluted with hydrogen, hydrogen and helium.

Note that a semi-amorphous semiconductor is a film including a semiconductor having an intermediate structure between an amorphous semiconductor and a semiconductor having a crystal structure (including single crystal and polycrystal). This semi-amorphous semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline one having a short-range order and having a lattice strain, and having a grain size of 0.5 to 20 nm. It can be dispersed in a single crystal semiconductor. The semi-amorphous semiconductor has its Raman spectrum shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of Si (111) and (220) crystal lattices are observed in X-ray diffraction. Further, hydrogen or halogen is contained at least 1 atomic% or more as a neutralizing agent for dangling bonds. Here, for convenience, such a semiconductor is referred to as a semi-amorphous semiconductor (SAS). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a good semi-amorphous semiconductor can be obtained.

SAS can be obtained by glow discharge decomposition of silicide gas. A typical silicide gas is SiH ₄ , and in addition, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4 and the} like can be used. In addition, it is easy to form a SAS by diluting and using this silicide gas with hydrogen or a gas obtained by adding one or more kinds of rare gas elements selected from helium, argon, krypton, and neon to hydrogen. It can be. It is preferable to dilute the silicide gas at a dilution rate in the range of 2 to 1000 times. Furthermore, a carbide gas such as CH ₄ or C ₂ H ₆ , a germanium gas such as GeH ₄ or GeF ₄ , F ₂ or the like is mixed in the silicide gas, so that the energy bandwidth is 1.5-2. You may adjust to 4 eV or 0.9-1.1 eV.

For example, when using a gas added with H ₂ to SiH _4, or the case of using the added gas F ₂ to SiH _4, when TFT is formed by using the formed semi-amorphous semiconductor, the subthreshold coefficient of the TFT (S Value) can be 0.35 V / sec or less, typically 0.25 to 0.09 V / sec, and the mobility can be 10 cm ² / Vsec. When a TFT using the semiamorphous semiconductor, for example, a 19-stage ring oscillator is formed, the oscillation frequency can be obtained from 1 MHz to 100 MHz or more at a power supply voltage of 3 to 5V. Further, at a power supply voltage of 3 to 5 V, the delay time per inverter stage can be 26 ns or less.

  Then, as shown in FIG. 5A, the semiconductor film 503 is crystallized using a laser. Alternatively, a crystallization method using a catalytic element and a laser crystallization method using a laser may be combined.

Before the laser crystallization, it is desirable to perform thermal annealing at 500 ° C. for 1 hour on the semiconductor film in order to increase the resistance of the semiconductor film to the laser. By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second harmonic to the fourth harmonic of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light with an output of 10 W. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. In this case, a power density of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

As the laser, a known continuous wave gas laser or solid-state laser can be used. Examples of gas lasers include Ar laser and Kr laser, and solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, etc. There is a laser using a single crystal. Furthermore, a ceramic laser using a polycrystal such as a Y ₂ O ₃ laser can also be cited as a solid-state laser.

Alternatively, laser crystallization may be performed using a frequency band that is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used, with an oscillation frequency of pulsed laser light of 10 MHz or higher. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming crystal grains in which crystal axes extending along the scanning direction are oriented in one direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in the channel length direction of the TFT.

  By irradiating the above-described semiconductor film with laser light, a semiconductor film with higher crystallinity is formed. The semiconductor film is divided into a first region 504 and a second region 505 having different crystallinity in the central region of the beam spot and in the vicinity of the edge. The first region 504 includes crystal grains having a width in the scanning direction of 10 to 30 μm and a width in the direction perpendicular to the scanning direction of about 1 to 5 μm. On the other hand, in the second region 505, the position and size are random, and only relatively small crystal grains having a grain size of about 0.2 μm to several μm are easily formed.

  Next, as illustrated in FIG. 5B, the first region 504 and the second region 505 of the crystallized semiconductor film are patterned, and the island-shaped semiconductor film 506 is formed from the first region 504. In step 507, an island-shaped semiconductor film 508 is formed from the second region 505. Then, a gate insulating film 509 is formed so as to cover the island-shaped semiconductor films 506 to 508. The gate insulating film 509 can be formed using a single layer or a stack of films containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride by a plasma CVD method, a sputtering method, or the like. In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

Note that after the gate insulating film 509 is formed, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the island-shaped semiconductor films 506 to 508. May be performed. By this hydrogenation step, dangling bonds can be terminated by thermally excited hydrogen. Further, as another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. Further, even if a defect is formed in the semiconductor film by bending the second substrate after the semiconductor element is bonded to the flexible second substrate in a later step, the semiconductor film is formed by hydrogenation. The hydrogen concentration in the semiconductor film is 1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm ^3, preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ , so that the hydrogen contained in the semiconductor film Defects can be terminated. In order to terminate the defect, the semiconductor film may contain halogen.

  Next, as shown in FIG. 5C, gate electrodes 510 to 512 are formed. In this embodiment, after forming Si and W to be stacked by a sputtering method, gate electrodes 510 to 512 are formed by performing etching using resist 513 as a mask. Needless to say, the material, structure, and manufacturing method of the gate electrodes 510 to 512 are not limited to these, and can be selected as appropriate. For example, a stacked structure of Si and NiSi (nickel silicide) doped with an n-type impurity or a stacked structure of TaN (tantalum nitride) and W (tungsten) may be used. Alternatively, a single layer may be formed using various conductive materials.

  In place of the resist mask, a mask such as SiOx may be used. In this case, a step of patterning to form a mask (referred to as a hard mask) of SiOx, SiON, or the like is added, but since the film thickness of the mask during etching is less than that of the resist, the gate electrodes 510 to 512 having a desired width. Can be formed. Alternatively, the gate electrodes 510 to 512 may be selectively formed using a droplet discharge method without using a mask.

  As the conductive material, various materials can be selected depending on the function of the conductive film. In the case where the gate electrode and the antenna are formed at the same time, materials may be selected in consideration of their functions.

Note that although a mixed gas of CF ₄ , Cl ₂ , and O ₂ or Cl ₂ gas is used as an etching gas for forming the gate electrode by etching, it is not limited to this.

Next, as shown in FIG. 5D, an island-shaped semiconductor film 507 to be a p-channel TFT is covered with a resist 515, and the island-shaped semiconductor films 506 and 508 are formed on the island-shaped semiconductor films 506 and 508 using the gate electrodes 510 and 512 as a mask. An impurity element imparting a mold (typically P (phosphorus) or As (arsenic)) is doped at a low concentration (first doping step). The conditions of the first doping step are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 kV, but are not limited thereto. In this first doping step, doping is performed through the gate insulating film 509, and a pair of low-concentration impurity regions 516 and 517 are formed in the island-shaped semiconductor films 506 and 508. Note that the first doping step may be performed without covering the island-shaped semiconductor film 507 to be a p-channel TFT with a resist.

Next, as shown in FIG. 5E, after removing the resist 515 by ashing or the like, a resist 518 is newly formed so as to cover the island-shaped semiconductor films 506 and 508 to be n-channel TFTs. Using the electrode 511 as a mask, the island-shaped semiconductor film 507 is doped with an impurity element imparting p-type (typically B (boron)) at a high concentration (second doping step). The conditions for the second doping step are a dose amount of 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage of 20 to 40 kV. In this second doping step, doping is performed through the gate insulating film 509, and a pair of p-type high concentration impurity regions 520 are formed in the island-shaped semiconductor film 507.

Next, as shown in FIG. 6A, after removing the resist 518 by ashing or the like, an insulating film 521 is formed so as to cover the gate insulating film 509 and the gate electrodes 510 to 512. In this embodiment, a 100 nm thick SiO ₂ film is formed by plasma CVD.
After that, the insulating film 521 and the gate insulating film 509 are partially etched by an etch back method, and the sidewalls 522 to 524 are formed so as to be in contact with the sidewalls of the gate electrodes 510 to 511 as shown in FIG. Self-aligned (self-aligned). As the etching gas, a mixed gas of CHF ₃ and He was used. Note that the step of forming the sidewall is not limited to these.

  If an insulating film is also formed on the back surface of the substrate when the insulating film 521 is formed, a resist is formed on the substrate surface after forming the sidewalls, and the insulating film formed on the back surface is etched. You may make it remove. Alternatively, when the sidewall is formed by the etch back method, the insulating film 521, part of the gate insulating film 509, and all of the insulating film formed on the back surface of the substrate may be removed at the same time.

  Note that the sidewalls 522 and 524 function as masks when a low concentration impurity region or a non-doped offset region is formed below the sidewalls 522 and 524 by doping with an impurity imparting a high concentration n-type later. is there. Therefore, in order to control the width of the low-concentration impurity region or the offset region, the size of the sidewall may be adjusted by appropriately changing the conditions of the etch-back method when forming the sidewall.

Next, as shown in FIG. 6C, a resist 526 is newly formed so as to cover the island-shaped semiconductor film 507 to be a p-channel TFT, and the gate electrodes 510 and 512 and the sidewalls 522 and 524 are masked. As described above, an impurity element imparting n-type conductivity (typically P or As) is doped at a high concentration (third doping step). The conditions for the third doping step are as follows: dose amount: 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² , acceleration voltage: 60 to 100 kV. In this third doping step, doping is performed, and a pair of n-type high concentration impurity regions 527 and 528 are formed in the island-shaped semiconductor films 506 and 508.

  Next, after removing the resist 526 by ashing or the like, the impurity regions may be thermally activated. For example, after a 50 nm SiON film is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours. Further, after forming a SiNx film containing hydrogen to a thickness of 100 nm, defects in the polycrystalline semiconductor film can be repaired by performing heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere. This terminates dangling bonds existing in the polycrystalline semiconductor film, for example, and is called a hydrogenation process.

  Through the series of steps described above, an n-channel TFT 530, a p-channel TFT 531 and an n-channel TFT 532 are formed. In the manufacturing process, a TFT having a channel length of 0.2 μm to 2 μm can be formed by appropriately changing the conditions of the etch back method and adjusting the size of the sidewall. Note that although the TFTs 530 to 532 have a top gate structure in this embodiment mode, a bottom gate structure (reverse stagger structure) may be used.

  Further, after that, a passivation film (not shown in the figure) for protecting the TFTs 530 to 532 may be formed. As the passivation film, it is desirable to use silicon nitride, silicon nitride oxide, aluminum nitride, aluminum oxide, silicon oxide, or the like that can prevent alkali metal or alkaline earth metal from entering the TFTs 530 to 532. Specifically, for example, a SiON film having a thickness of about 600 nm can be used as the passivation film. In this case, the hydrogenation process may be performed after the formation of the SiON film. As another example, three layers of insulating films of SiON, SiNx, and SiON may be sequentially formed from the substrate side, and the structure and material are not limited to these. By using the above structure, the TFTs 530 to 532 are covered with the base film 502 and the passivation film, so that an alkali metal such as Na or an alkaline earth metal diffuses into the semiconductor film used in the semiconductor element, and the semiconductor An adverse effect on the characteristics of the element can be further prevented.

  Next, as shown in FIG. 6D, a first interlayer insulating film 533 is formed so as to cover the TFTs 530 to 532. For the first interlayer insulating film 533, an organic resin having heat resistance such as polyimide, acrylic, or polyamide can be used. In addition to the organic resin, a low dielectric constant material (low-k material), a resin containing a Si—O—Si bond formed from a siloxane-based material (hereinafter referred to as a siloxane resin), or the like is used. Can do. Siloxane has a skeleton structure of silicon (Si) and oxygen (O). An organic group containing at least hydrogen as a substituent (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen as a substituent and a fluoro group may be used. The first interlayer insulating film 533 is formed by spin coating, dipping, spray coating, droplet discharge method (inkjet method) printing method (screen printing, offset printing, etc.), doctor knife, roll coater depending on the material. Curtain coaters, knife coaters, etc. can be employed. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the first interlayer insulating film 533 may be formed by stacking these insulating films.

  Further, in this embodiment, a second interlayer insulating film 534 is formed over the first interlayer insulating film 533. As the second interlayer insulating film 534, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma CVD method, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, a siloxane resin, or the like may be used.

  Note that the first interlayer insulating film 533 or the second interlayer insulating film 533 or the first interlayer insulating film 533 or the second interlayer insulating film 534 is subjected to stress caused by a difference in thermal expansion coefficient between a conductive material or the like that forms a wiring to be formed later. In order to prevent the second interlayer insulating film 534 from being peeled off or cracked, a filler may be mixed in the first interlayer insulating film 533 or the second interlayer insulating film 534.

Next, as shown in FIG. 6D, contact holes are formed in the first interlayer insulating film 533 and the second interlayer insulating film 534, and wirings 535 to 539 connected to the TFTs 530 to 532 are formed. The gas used for etching when opening the contact hole is a mixed gas of CHF ₃ and He, but is not limited to this. In this embodiment mode, the wirings 535 to 539 have a five-layer structure in which Ti, TiN, Al—Si, Ti, and TiN are sequentially stacked from the substrate side, are formed by a sputtering method, and are then patterned.

  In addition, by mixing Si in Al, generation of hillocks in resist baking at the time of wiring patterning can be prevented. Further, instead of Si, about 0.5% Cu may be mixed. Further, the hillock resistance is further improved by sandwiching the Al—Si layer with Ti or TiN. In the patterning, it is desirable to use the hard mask made of SiON or the like. Note that the wiring material and the formation method are not limited to these, and the material used for the gate electrode described above may be employed.

  Note that the wirings 535 and 536 are in the high-concentration impurity region 527 of the n-channel TFT 530, the wirings 536 and 537 are in the high-concentration impurity region 520 of the p-channel TFT 531, and the wirings 538 and 539 are high-concentration impurity regions in the n-channel TFT 532. 528, respectively. Further, the wiring 539 is also connected to the gate electrode 512 of the n-channel TFT 532. The n-channel TFT 532 can be used as a memory element of a random number ROM.

  Next, as illustrated in FIG. 6E, a third interlayer insulating film 541 is formed over the second interlayer insulating film 534 so as to cover the wirings 535 to 539. The third interlayer insulating film 541 is formed so as to have an opening at a position where the wiring 535 is partially exposed. Note that the third interlayer insulating film 541 can be formed using a material similar to that of the first interlayer insulating film 533.

  Next, the antenna 542 is formed over the third interlayer insulating film 541. The antenna 542 is formed using a conductive material including one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn, Sn, and Ni, and a metal compound. Can do. The antenna 542 is connected to the wiring 535. Note that in FIG. 6E, the antenna 542 is directly connected to the wiring 535; however, the ID chip of the present invention is not limited to this structure. For example, the antenna 542 and the wiring 535 may be electrically connected using a separately formed wiring.

  The antenna 542 can be formed by a printing method, a photolithography method, an evaporation method, a droplet discharge method, or the like. In this embodiment mode, the antenna 542 is formed using a single-layer conductive film; however, an antenna 542 in which a plurality of conductive films are stacked can be formed. For example, the antenna 542 may be formed by coating a wiring formed of Ni or the like with electroless plating.

  The droplet discharge method means a method of forming a predetermined pattern by discharging droplets containing a predetermined composition from the pores, and includes an ink jet method and the like in its category. The printing method includes a screen printing method and an offset printing method. By using a printing method or a droplet discharge method, the antenna 542 can be formed without using an exposure mask. In addition, unlike the photolithography method, there is no waste of material that is removed by etching in the droplet discharge method and the printing method. In addition, since it is not necessary to use an expensive exposure mask, the cost for manufacturing the ID chip can be suppressed.

  In the case of using a droplet discharge method or various printing methods, for example, conductive particles in which Cu is coated with Ag can be used. Note that in the case where the antenna 542 is formed by a droplet discharge method, it is preferable that treatment for increasing the adhesion of the antenna 542 be performed on the surface of the third interlayer insulating film 541.

  As a method for improving the adhesion, specifically, for example, a method of attaching a metal or a metal compound capable of enhancing the adhesion of the conductive film or the insulating film to the surface of the third interlayer insulating film 541 by a catalytic action. An organic insulating film having high adhesion to the formed conductive film or insulating film, a method of attaching a metal or a metal compound to the surface of the third interlayer insulating film 541, and a surface of the third interlayer insulating film 541 Examples include a method of improving the surface adhesion by performing plasma treatment under atmospheric pressure or reduced pressure. Examples of the metal having high adhesion to the conductive film or insulating film include titanium, titanium oxide, 3d transition elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Zn. Is mentioned. Examples of the metal compound include the above-described metal oxides, nitrides, and oxynitrides. Examples of the organic insulating film include polyimide and siloxane resin.

  When the metal or metal compound attached to the third interlayer insulating film 541 has conductivity, the sheet resistance is controlled so that the normal operation of the antenna is not hindered. Specifically, the average thickness of the conductive metal or metal compound may be 1 to 10 nm, for example, or the metal or metal compound may be partially or entirely insulated by oxidation. Alternatively, the deposited metal or metal compound may be selectively removed by etching except for the region where the adhesion is desired to be improved. Alternatively, the metal or the metal compound may be selectively attached only to a specific region by using a droplet discharge method, a printing method, a sol-gel method, or the like, instead of attaching the metal or the metal compound to the entire surface of the substrate in advance. Note that the metal or the metal compound does not need to be a completely continuous film on the surface of the third interlayer insulating film 541 and may be dispersed to some extent.

  Then, as shown in FIG. 7A, after the antenna 542 is formed, a protective layer 545 is formed over the third interlayer insulating film 541 so as to cover the antenna 542. The protective layer 545 is formed using a material that can protect the antenna 542 when the peeling layer 501 is removed later by etching. For example, the protective layer 545 can be formed by applying an epoxy resin, an acrylate resin, or a silicon resin soluble in water or alcohols to the entire surface.

In this embodiment, a water-soluble resin (manufactured by Toa Gosei: VL-WSHL10) is applied by spin coating so as to have a film thickness of 30 μm, and after exposure for 2 minutes to perform temporary curing, UV light is applied. Exposure is performed for 2.5 minutes from the back side and 10 minutes from the front side for a total of 12.5 minutes to perform main curing to form the protective layer 545. In addition, when laminating | stacking some organic resin, there exists a possibility that organic resins may melt | dissolve partially at the time of application | coating or baking with the solvent currently used, or adhesiveness may become high too much. Therefore, when both the third interlayer insulating film 541 and the protective layer 545 are made of an organic resin that is soluble in the same solvent, the third interlayer insulating film is removed so that the protective layer 545 can be removed smoothly in the subsequent process. An inorganic insulating film (SiN _x film, SiN _x O _y film, AlN _x film, or AlN _x O _y film) is preferably formed so as to cover 541.

  Next, as shown in FIG. 7B, a groove 546 is formed in order to separate the ID chips. The groove 546 may be of a size that exposes the release layer 501. The groove 546 can be formed by dicing, scribing, or the like. Note that the groove 546 is not necessarily formed when the ID chip formed over the first substrate 500 does not need to be separated.

Next, as illustrated in FIG. 7C, the peeling layer 501 is removed by etching. In this embodiment mode, halogen fluoride is used as an etching gas, and the gas is introduced from the groove 546. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used, and the temperature is 350 ° C., the flow rate is 300 sccm, the atmospheric pressure is 800 Pa, and the time is 3 hours. Alternatively, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogen fluoride such as ClF ₃ , the peeling layer 501 is selectively etched, and the first substrate 500 can be peeled from the TFTs 530 to 532. The halogen fluoride may be either a gas or a liquid.

  Next, as illustrated in FIG. 8A, the peeled TFTs 530 to 532 and the antenna 542 are attached to the second substrate 551 with an adhesive 550. As the adhesive 550, a material capable of bonding the second substrate 551 and the base film 502 is used. As the adhesive 550, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the second substrate 551, an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used as the second substrate 551. As the plastic substrate, ARTON (manufactured by JSR) made of polynorbornene with a polar group can be used. Polyester represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin and the like. The second substrate 551 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Next, as shown in FIG. 8B, after the protective layer 545 is removed, an adhesive 552 is applied over the third interlayer insulating film 541 so as to cover the antenna 542, and a cover material 553 is attached thereto. The cover material 553 can be formed using a flexible organic material such as paper or plastic, like the second substrate 551. The thickness of the adhesive 552 may be, for example, 10 to 200 μm.

  The adhesive 552 is formed using a material that can bond the cover material 553 to the third interlayer insulating film 541 and the antenna 542. As the adhesive 552, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

The ID chip is completed through the above-described steps. By the above manufacturing method, an extremely thin integrated circuit having a total film thickness of 0.3 μm to 3 μm, typically about 2 μm, can be formed between the second substrate 551 and the cover material 553. Note that the thickness of the integrated circuit includes not only the thickness of the semiconductor element itself but also the thicknesses of various insulating films and interlayer insulating films formed between the adhesive 550 and the adhesive 552. The area occupied by the integrated circuit included in the ID chip, 5 mm square (25 mm ²⁾ or less, and more preferably may be 0.3mm square (0.09 mm ²⁾ to 4 mm square (16 mm ²⁾ degree.

  Note that the mechanical strength of the ID chip can be increased by positioning the integrated circuit at a more central position between the second substrate 551 and the cover material 553. Specifically, when the distance between the second substrate 551 and the cover material 553 is d, the distance x between the second substrate 551 and the center in the thickness direction of the integrated circuit satisfies the following formula 1. As described above, it is desirable to control the thicknesses of the adhesive 550 and the adhesive 552.

  Preferably, the thicknesses of the adhesive 550 and the adhesive 552 are controlled so as to satisfy the following formula 2.

Further, as shown in FIG. 19, the distance (t _under ) from the lower surface of the island-shaped semiconductor film of the TFT to the lower surface of the lower base film in the integrated circuit, and the third interlayer between the lower surface of the island-shaped semiconductor film and the upper layer The base film 502, the first interlayer insulating film 533, the second interlayer insulating film 534, or the third interlayer insulating film 541 are arranged so that the distance (t _over ) to the upper surface of the insulating film 541 is equal or substantially equal. The thickness may be adjusted. In this manner, by placing the island-shaped semiconductor film in the center of the integrated circuit, the stress on the semiconductor layer can be relieved and the occurrence of cracks can be suppressed.

  Note that FIG. 8B illustrates an example in which the cover material 553 is used; however, the present invention is not limited to this structure. For example, the process may be ended up to the step shown in FIG.

  Note that although this embodiment mode describes a method in which a separation layer is provided between the first substrate 500 having high heat resistance and the integrated circuit and the first substrate and the integrated circuit are separated by etching, the ID of the present invention The method for manufacturing the chip is not limited to this configuration. For example, a metal oxide film may be provided between a substrate having high heat resistance and the integrated circuit, and the integrated circuit may be peeled by weakening the metal oxide film by crystallization. Alternatively, a separation layer using an amorphous semiconductor film containing hydrogen may be provided between the substrate with high heat resistance and the integrated circuit, and the separation layer may be removed by laser light irradiation. Alternatively, the integrated circuit may be separated from the substrate by mechanically removing the highly heat-resistant substrate on which the integrated circuit is formed or removing the substrate by etching with a solution or gas.

  In order to ensure the flexibility of the ID chip, in the case where an organic resin is used for the adhesive 550 in contact with the base film 502, a silicon nitride film or a silicon nitride oxide film is used as the base film 502 so that the organic resin can be replaced with Na or the like. The alkali metal or alkaline earth metal can be prevented from diffusing into the semiconductor film.

  In addition, the surface of the object to which the ID chip is attached has a curved surface, whereby the second substrate 551 of the ID chip attached to the curved surface has a curved surface drawn by movement of the generatrix such as a cone surface or a column surface. In the case of bending so as to have, it is desirable to align the direction of the bus and the direction in which the carriers of the TFTs 530 to 532 move. With the above structure, even when the second substrate 551 is bent, the characteristics of the TFTs 530 to 532 can be suppressed from changing. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, even when the second substrate 551 is bent, the characteristics of the TFTs 530 to 532 are further suppressed from changing. be able to.

  Note that although an example in which the antenna is formed over the same substrate as the integrated circuit is described in this embodiment mode, the present invention is not limited to this structure. An antenna formed over another substrate and the integrated circuit may be bonded later to be electrically connected.

  In general, the frequency of radio waves used in an ID chip is 13.56 MHz and 2.45 GHz, and it is very important to increase the versatility to form an ID chip so that radio waves of that frequency can be detected. Is important to.

In addition, the ID chip of this embodiment has an advantage that radio waves are less likely to be shielded than an ID chip formed using a semiconductor substrate, and the signal can be prevented from being attenuated by shielding the radio waves. Further, since it is not necessary to use a semiconductor substrate, the cost of the ID chip can be significantly reduced. For example, a case where a silicon substrate having a diameter of 12 inches is used is compared with a case where a glass substrate of 730 × 920 mm ² is used. The area of the former silicon substrate is about 73000 mm ² , while the area of the latter glass substrate is about 672000 mm ² , and the glass substrate corresponds to about 9.2 times the silicon substrate. When the area of the latter glass substrate is about 672000 mm ² , ignoring the area consumed by dividing the substrate, it is calculated that about 672,000 1 mm square ID chips can be formed, and the number is about 9.2 times that of the silicon substrate. It is equivalent to the number of Capital investment for mass production of ID chips requires fewer steps when a 730 × 920 mm ² glass substrate is used than when a 12-inch diameter silicon substrate is used. It can be done in a third. Further, in the present invention, the glass substrate can be used again after the integrated circuit is peeled off. Therefore, cost can be significantly reduced as compared with the case of using a silicon substrate, even in view of the cost of filling a damaged glass substrate or cleaning the surface of the glass substrate. Even if the glass substrate is discarded without being reused, the cost of a 730 × 920 mm ² glass substrate is about half that of a silicon substrate having a diameter of 12 inches, thus greatly reducing the cost of the ID chip. You can see that

Therefore, it can be seen that when a glass substrate of 730 × 920 mm ² is used, the price of the ID chip can be reduced to about 1/30 compared to the case of using a 12-inch diameter silicon substrate. Since the ID chip is expected to be used on the premise that it is disposable, the ID chip of the present invention, which can significantly reduce the cost, is very useful for the above application.

  Note that although an example in which the integrated circuit is separated and attached to a flexible substrate is described in this embodiment mode, the present invention is not limited to this structure. For example, an integrated circuit on a glass substrate may be used as the ID chip.

  In this embodiment, one mode of a reading circuit used in a random number ROM will be described. FIG. 9 illustrates one mode of a memory cell array 801 and a reading circuit 802 included in the random number ROM. Note that FIG. 9 illustrates one memory cell 803 included in the memory cell array 801 and a part of the reading circuit 802 corresponding to the memory cell 803.

  The read circuit 802 includes a reference memory cell 804, a differential amplifier circuit 805, and a latch circuit 806. When the word line 807 is selected, the memory cell 803 supplies the voltage Vbit to the differential amplifier circuit 805 via the bit line 808. On the other hand, the reference voltage Vref is output from the reference memory cell 804 and supplied to the differential amplifier circuit 805. The difference between the two voltages Vbit and Vref is amplified by the differential amplifier circuit 805 and stored in the latch circuit 806.

  Note that the reference voltage Vref is preferably close to the average value of the voltage Vbit of the bit line 808 supplied by a plurality of memory cells. By doing so, the data stored in the plurality of memory cells included in the memory cell array 801 can be assigned to 0 or 1 with a probability of almost ½. For example, the reference voltage Vref can be made closer to the average value of the voltage Vbit by making the channel width of the TFT 810 included in the reference memory cell 804 larger than the channel width of the TFT 811 included in the memory cell 803.

  As described above, 1-bit data is determined based on the difference between the threshold voltage of the TFT 810 included in the reference memory cell 804 and the threshold voltage of the TFT 811 included in the selected memory cell 803 and stored in the latch circuit 806. Is done. More precisely, it can be said that the data is determined including not only variations in threshold voltage of the TFT 811 included in the memory cell 803 but also variations in threshold voltage of the TFT 810 included in the differential amplifier circuit 805. In this way, even when formed using the same manufacturing process, a random number ROM that stores unique data for each ID chip can be formed.

  Note that the random number ROM described above can be manufactured by using a normal TFT manufacturing technique, and can be manufactured in the same process as that for manufacturing other integrated circuits. Therefore, an increase in cost associated with the production of the random number ROM can be suppressed, and the cost can be reduced as compared with the case of producing a flash memory.

Note that the probability that the data stored in the random number ROM matches in different ID chips is not necessarily zero. However, for example, even if a capacity of about 128 bits is considered, there are 2 ¹²⁸ random numbers that can exist, and the probability that the data match can be regarded as substantially zero.

  By using the random number ROM as described above, and using the data as data unique to the ID chip, it is possible to avoid the disposable use of the photomask when manufacturing the mask ROM, and to reduce the cost without increasing the cost. The ID chip can be manufactured.

    In the present embodiment, the configuration of a random number ROM different from that in FIG. 9 will be described with reference to FIG. Although FIG. 9 shows a random number ROM that determines data by comparing each memory cell with a reference memory cell, in this embodiment, a random number ROM that determines data by comparing voltages between adjacent memory cells. An example of

    FIG. 10 illustrates two memory cells 821 and 822 included in the memory cell array 820 and a part of the read circuit 823 corresponding to the memory cells 821 and 822. When the memory cells 821 and 822 in the memory cell array 820 are selected, voltages corresponding to the threshold voltages of the TFTs 824 and 825 included in the memory cells 821 and 822 are supplied to the corresponding bit lines 826 and 827, respectively. A differential amplifier circuit 828 included in the reading circuit 823 amplifies a voltage difference between both the bit lines 826 and 827 and stores the amplified voltage difference in a latch circuit 829 included in the reading circuit 823.

    Note that the TFT characteristics may vary depending on factors other than the position of the crystal grain boundary, such as the thickness distribution of the gate insulating film and the concentration distribution of the impurity element to be doped. If the TFT characteristics vary due to factors other than the position of the crystal grain boundary, the characteristics of TFTs laid out at close positions are relatively the same, but the characteristics of TFTs that are far from each other vary. Often happens. In this case, when viewed from the whole memory cell array, regularity occurs in the variation in TFT characteristics, which is not preferable. However, in the case of the random number ROM of this embodiment, unlike the random number ROM shown in FIG. 9, the memory cells to be compared are laid out at adjacent positions. Therefore, the TFT of each memory cell is not easily influenced by the macro characteristic variation depending on the position of the memory cell, and is easily affected by the characteristic variation depending on the position of the crystal grain boundary. As a result, it is possible to obtain a random number ROM in which data with a small distribution of characteristic distribution is stored.

  In order for the ID chip to hold unique data that can be identified, the ID chip only needs to have a random number ROM that can store a small amount of data. For example, if the capacity of the random number ROM is 128 bits, it is sufficient to store data for identifying the ID chip. In the case of a small-capacity random number ROM, a flip-flop circuit may be used.

  FIG. 11 shows an example of the random number ROM of this embodiment. As shown in FIG. 11, the read circuit 840 included in the random number ROM of this embodiment includes a shift register 841 and a switching element 842. The shift register 841 has a flip-flop circuit 843.

  When the switching element 842 is selected by the load signal in the memory cell array 844 included in the random number ROM, data from the memory cells 845 and 846 is input to the shift register 841. In the shift register 841, when data is input from the memory cells 845 and 846, the data is serially output in accordance with the clock signal (CLK).

  The operation of the shift register 841 will be described in more detail. First, when a load signal is asserted, the power supply potential of the shift register 841 is grounded, information stored in the flip-flop 843 is erased, and the memory cells 845 and 846 The voltage depending on the variation in threshold voltage is applied to the flip-flop 843 through the switching element 842. Thereafter, when the load signal is deasserted, the switching element 842 is turned off, and the flip-flop 843 and the memory cells 845 and 846 are disconnected. In parallel with this, the flip-flop 843 stores data with voltages supplied from the memory cells 845 and 846 as initial values. Thereafter, by inputting a clock signal, unique data stored in the flip-flop 843 is serially output.

  Note that although an example in which two flip-flop circuits 843 correspond to a pair of memory cells 845 and 846 corresponds to this embodiment, the present invention is not limited to this configuration. For example, two pairs of memory cells may correspond to a plurality of sets and one flip-flop circuit 843. In this case, a circuit for selecting any of a plurality of pairs of memory cells may be provided in the random number ROM.

  In this embodiment, a structure of an ID chip in which an antenna formed over another substrate and an integrated circuit are electrically connected is described.

  FIG. 12A shows a cross-sectional view of the ID chip of this embodiment. In FIG. 12A, an adhesive 1203 is applied over the third interlayer insulating film 1204 so as to cover the wiring 1202 electrically connected to the TFT 1201. Then, the cover material 1205 is bonded to the third interlayer insulating film 1204 with an adhesive 1203.

  An antenna 1206 is formed on the cover material 1205 in advance. In this embodiment, the anisotropic conductive resin is used for the adhesive 1203 so that the antenna 1206 and the wiring 1202 are electrically connected.

  An anisotropic conductive resin is a material in which a conductive material is dispersed in a resin. As the resin, for example, those having thermosetting properties such as epoxy-based, urethane-based, and acrylic-based materials, thermoplastic materials such as polyethylene-based and polypropylene-based materials, and siloxane-based resins can be used. As conductive materials, for example, plastic particles such as polystyrene and epoxy are plated with Ni, Au, metal particles such as Ni, Au, Ag, and solder, particulate or fibrous carbon, and fibrous Ni. A material plated with Au can be used. The size of the conductive material is preferably determined in accordance with the pitch between the antenna 1206 and the wiring 1202.

  Further, between the antenna 1206 and the wiring 1202, the anisotropic conductive resin may be pressed while applying ultrasonic waves, or may be pressed while being cured by irradiation with ultraviolet rays.

  Note that although an example in which the antenna 1206 and the wiring 1202 are electrically connected with an adhesive 1203 using an anisotropic conductive resin is described in this embodiment, the present invention is not limited to this structure. Instead of the adhesive 1203, the antenna 1206 and the wiring 1202 may be electrically connected by pressure bonding an anisotropic conductive film.

  In this embodiment, the ID chip formed by attaching the peeled integrated circuit to a separately prepared substrate is described as an example, but the present invention is not limited to this structure. For example, an integrated circuit on a glass substrate may be used as the ID chip. FIG. 12B is a cross-sectional view illustrating one mode of an ID chip formed using a glass substrate.

  In the ID chip illustrated in FIG. 12B, a glass substrate is used as the substrate 1210, and the base film 1214 is formed between the TFTs 1211 to 1213 and the substrate 1210 used for the integrated circuit without interposing an adhesive. It is formed in contact with the substrate and the TFT.

  A structure of an ID chip in the case where a wiring connected to a TFT and an antenna are formed together by patterning one conductive film is described with reference to FIG. FIG. 13A shows a cross-sectional view of the ID chip of this embodiment.

  In FIG. 13A, reference numeral 1401 corresponds to a TFT. The TFT 1401 includes an island-shaped semiconductor film 1402, a gate insulating film 1403 in contact with the island-shaped semiconductor film 1402, and a gate electrode 1404 overlapping the island-shaped semiconductor film 1402 with the gate insulating film 1403 interposed therebetween. have. The TFT 1401 is covered with a first interlayer insulating film 1405 and a second interlayer insulating film 1406. The wiring 1407 formed over the second interlayer insulating film 1406 is connected to the island-shaped semiconductor film 1402 through contact holes formed in the first interlayer insulating film 1405 and the second interlayer insulating film 1406. Has been.

  An antenna 1408 is formed over the second interlayer insulating film 1406. The wiring 1407 and the antenna 1408 can be formed by forming a conductive film over the second interlayer insulating film 1406 and patterning the conductive film. By forming the antenna 1408 together with the wiring 1407, the number of manufacturing steps of the ID chip can be reduced.

  Next, the structure of the ID chip in the case where the gate electrode of the TFT and the antenna are formed together by patterning the conductive film will be described with reference to FIG. FIG. 13B shows a cross-sectional view of the ID chip of this embodiment.

  In FIG. 13B, reference numeral 1411 corresponds to a TFT. The TFT 1411 includes an island-shaped semiconductor film 1412, a gate insulating film 1413 that overlaps with the island-shaped semiconductor film 1412, and a gate electrode 1414 that overlaps with the island-shaped semiconductor film 1412 with the gate insulating film 1413 interposed therebetween. have. An antenna 1418 is formed over the gate insulating film 1413. The gate electrode 1414 and the antenna 1418 can be formed by forming a conductive film over the gate insulating film 1413 and patterning the conductive film. By forming the antenna 1418 together with the gate electrode 1414, the number of manufacturing steps of the ID chip can be suppressed.

  Note that in this example, an example in which an integrated circuit is peeled off and attached to a separately prepared substrate is described; however, the present invention is not limited to this structure. For example, an integrated circuit on a glass substrate may be used as the ID chip.

  In this embodiment, a structure of a TFT used in the ID chip of the present invention will be described.

  FIG. 14A shows a cross-sectional view of the TFT of this example. Reference numeral 701 corresponds to an n-channel TFT, and 702 corresponds to a p-channel TFT. A more detailed configuration will be described by taking an n-channel TFT 701 as an example.

  The n-channel TFT 701 includes an island-shaped semiconductor film 705 used as an active layer. The island-shaped semiconductor film 705 includes two impurity regions 703 used as a source region or a drain region and the two impurity regions 703. A channel forming region 704 sandwiched between the two impurity regions 703 and two LDD (Light Doped Drain) regions 710 sandwiched between the channel forming region 704. The n-channel TFT 701 includes a gate insulating film 706 covering the island-shaped semiconductor film 705, a gate electrode 707, and two sidewalls 708 and 709 formed of the insulating film.

  In this embodiment, the gate electrode 707 includes two conductive films 707a and 707b. However, the present invention is not limited to this structure. The gate electrode 707 may be formed of a single conductive film or may be formed of two or more conductive films. The gate electrode 707 overlaps with a channel formation region 704 included in the island-shaped semiconductor film 705 with the gate insulating film 706 interposed therebetween. Further, the sidewalls 708 and 709 overlap with two LDD regions 710 included in the island-shaped semiconductor film 705 with the gate insulating film 706 interposed therebetween.

  The sidewall 708 can be formed by etching a silicon oxide film having a thickness of 100 nm, for example, and the sidewall 709 can be formed by etching an LTO film (low temperature oxide) having a thickness of 200 nm, for example. . In this embodiment, a silicon oxide film used for the sidewall 708 is formed by a plasma CVD method, and an LTO film used for the sidewall 709, here, a silicon oxide film is formed by a low pressure CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  In the impurity region 703 and the LDD region 710, after doping the island-shaped semiconductor film 705 with n-type impurities using the gate electrode 707 as a mask, sidewalls 708 and 709 are formed, and the sidewalls 708 and 709 are used as masks. The island-shaped semiconductor film 705 can be formed separately by doping an n-type impurity.

  Note that the p-channel TFT 702 has almost the same configuration as the n-channel TFT 701, but differs only in the configuration of the island-shaped semiconductor film 711 included in the p-channel TFT 702. The island-shaped semiconductor film 711 does not have an LDD region, and has two impurity regions 712 and a channel formation region 713 sandwiched between the two impurity regions 712. The impurity region 712 is doped with p-type impurities. Note that FIG. 14A illustrates an example in which the p-channel TFT 702 does not have an LDD region; however, the present invention is not limited to this structure. The p-channel TFT 702 may have an LDD region.

  FIG. 14B illustrates the case where the TFT illustrated in FIG. 14A has one sidewall. Each of the n-channel TFT 721 and the p-channel TFT 722 illustrated in FIG. 14B has one sidewall 728 and 729, respectively. The sidewalls 728 and 729 can be formed by etching a silicon oxide film having a thickness of 100 nm, for example. In this embodiment, a silicon oxide film used for the sidewalls 728 and 729 is formed by a plasma CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  Next, FIG. 14C illustrates a structure of a bottom-gate TFT. 741 corresponds to an n-channel TFT, and 742 corresponds to a p-channel TFT. A more detailed configuration will be described by taking an n-channel TFT 741 as an example.

In FIG. 14C, an n-channel TFT 741 includes an island-shaped semiconductor film 745. The island-shaped semiconductor film 745 includes two impurity regions 743 used as a source region or a drain region, and the two A channel formation region 744 sandwiched between the impurity regions 743 and two LDD (Light Doped Drain) regions 750 sandwiched between the two impurity regions 743 and the channel formation region 744 are provided. The n-channel TFT 741 is
A gate insulating film 746, a gate electrode 747, and a protective film 748 formed of an insulating film are included.

  The gate electrode 747 overlaps with a channel formation region 744 included in the island-shaped semiconductor film 745 with the gate insulating film 746 interposed therebetween. The gate insulating film 746 is formed after the gate electrode 747 is formed, and the island-shaped semiconductor film 745 is formed after the gate insulating film 746 is formed. The protective film 748 overlaps with the gate insulating film 746 with the channel formation region 744 interposed therebetween.

  The protective film 748 can be formed by etching a silicon oxide film having a thickness of 100 nm, for example. In this embodiment, a silicon oxide film used for the protective film 748 is formed by a plasma CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  In the impurity region 743 and the LDD region 750, a protective film 748 is formed over the island-shaped semiconductor film 745, and an n-type impurity is added to the island-shaped semiconductor film 745 using a mask formed of a resist so as to cover the protective film. After the doping, the resist is removed, and the island-shaped semiconductor film 745 is doped with n-type impurities using the protective film 748 as a mask.

  Note that the p-channel TFT 742 has almost the same configuration as the n-channel TFT 741, but differs only in the configuration of the island-shaped semiconductor film 751 included in the p-channel TFT 742. The island-shaped semiconductor film 751 does not have an LDD region, and has two impurity regions 752 and a channel formation region 753 sandwiched between the two impurity regions 752. The impurity region 752 is doped with p-type impurities. Note that FIG. 14A illustrates an example in which the p-channel TFT 742 does not have an LDD region; however, the present invention is not limited to this structure. The p-channel TFT 742 may have an LDD region.

  This embodiment can be implemented in combination with the configurations of the first to fifth embodiments.

  In this embodiment, a method for peeling a chip and attaching it to another substrate will be described.

  First, the integrated circuit 301 and the antenna 302 are formed over a substrate having heat resistance, and then peeled off, and then attached to a separately prepared substrate 303 with an adhesive 304 as shown in FIG. Note that FIG. 15A illustrates a state where the integrated circuit 301 and the antenna 302 are bonded to the substrate 303 one by one, but the present invention is not limited to this structure. The set of the integrated circuit 301 and the antenna 302 may be peeled off in a state where they are connected to each other and attached to the substrate 303 at a time.

  Next, as illustrated in FIG. 15B, a cover material 305 is attached to the substrate 303 so that the integrated circuit 301 and the antenna 302 are interposed therebetween. At this time, an adhesive 306 is applied on the substrate 303 so as to cover the integrated circuit 301 and the antenna 302. By attaching the cover material 305 to the substrate 303, the state shown in FIG. Note that in FIG. 15C, the integrated circuit 301 and the antenna 302 are shown through the cover member 305 so that the positions of the integrated circuit 301 and the antenna 302 are clear.

  Next, as shown in FIG. 15D, the integrated circuit 301 and the antenna 302 are separated from each other by dicing or scribing, whereby the ID chip 307 is completed.

  Note that although an example in which the antenna 302 is peeled off together with the integrated circuit 301 is shown in this embodiment, this embodiment is not limited to this configuration. An antenna may be formed over the substrate 303 in advance, and the integrated circuit 301 and the antenna may be electrically connected when the integrated circuit 301 is bonded. Alternatively, after the integrated circuit 301 is attached to the substrate 303, an antenna may be attached so as to be electrically connected to the integrated circuit 301. Alternatively, an antenna may be formed over the cover material 305 in advance, and the integrated circuit 301 and the antenna may be electrically connected when the cover material 305 is attached to the substrate 303.

  Note that in the case where the substrate 303 and the cover member 305 are flexible, the ID chip 307 can be used in a state where stress is applied. In the present invention, the stress applied to the ID chip 307 can be relaxed to some extent by the stress relaxation film. Further, by providing a plurality of barrier films, the stress per barrier film can be suppressed, so that the characteristics of the semiconductor element can be improved by the stress or by diffusion of alkali metal, alkaline earth metal or moisture into the semiconductor film. It can prevent adverse effects.

  An ID chip using a glass substrate can be called an IDG chip (Identification Glass Chip), and an ID chip using a flexible substrate can be called an IDF chip (Identification Flexible Chip).

  This embodiment can be implemented in combination with the first to sixth embodiments.

  In this embodiment, a shape of a groove formed when a plurality of integrated circuits formed over one substrate is peeled will be described. FIG. 16A shows a top view of a substrate 603 over which a groove 601 is formed. FIG. 16B is a cross-sectional view taken along line AA ′ of FIG.

  The integrated circuit 602 is formed over the peeling layer 604, and the peeling layer 604 is formed over the substrate 603. The groove 601 is formed between the integrated circuits 602 and has a depth enough to expose the release layer 604. In this embodiment, the plurality of integrated circuits 602 are not completely separated but partially separated by the grooves 601.

  Next, the state after the etching gas is poured into the groove 601 shown in FIGS. 16A and 16B and the peeling layer 604 is removed by etching is shown in FIGS. 16C and 16D. . FIG. 16C corresponds to a top view of the substrate 603, and FIG. 16D corresponds to a cross-sectional view taken along line AA ′ in FIG. It is assumed that the etching of the peeling layer 604 has progressed from the groove 601 to the region indicated by the broken line 605 by etching. As shown in FIGS. 16C and 16D, the plurality of integrated circuits 602 are separated by the groove 601 in a state of being partially connected to each other, not completely, so that the peeling layer 604 is etched. It is possible to prevent the integrated circuits 602 from moving without support later.

  When the state shown in FIGS. 16C and 16D is formed, the tape to which the adhesive is attached is attached to the integrated circuit 602, and the integrated circuit 602 is peeled from the substrate 603 by peeling it off. The plurality of separated integrated circuits 602 are attached to a separately prepared substrate before or after being separated from each other.

  Note that this embodiment shows an example of a method for manufacturing an ID chip, and the method for manufacturing an ID chip of the present invention is not limited to the structure shown in this embodiment.

  This embodiment can be implemented in combination with the first to seventh embodiments.

  In this embodiment, the use of the ID chip of the present invention will be described.

  In the case of using a flexible substrate, the ID chip of the present invention is suitable for bonding to a flexible object or a curved object. Further, forgery of the object to which the ID chip is attached can be prevented by the random number ROM included in the ID chip of the present invention. Further, for example, using the ID chip of the present invention for food products whose merchandise value is greatly influenced by the production area, producer, etc. is useful for preventing impersonation of the production area, producer, etc. at a low cost.

  Specifically, the ID chip of the present invention can be used by being attached to a tag having object information such as a tag, a price tag, and a name tag. Alternatively, the ID chip itself of the present invention may be used as a tag. Also, for example, a certificate equivalent to a document that proves the fact, such as a family register copy, resident card, passport, license, identification card, membership card, certificate, credit card, cash card, prepaid card, examination ticket, commuter pass, etc. May be. Also, for example, it may be attached to securities corresponding to securities displaying private property rights, such as bills, checks, cargo exchange certificates, shipping securities, warehouse securities, stock certificates, bonds, gift certificates, mortgage securities.

  FIG. 17A shows an example of a check 1301 to which the ID chip 1302 of the present invention is attached. In FIG. 17A, the ID chip 1302 is attached to the inside of the check 1301, but may be exposed to the front.

  FIG. 17B shows an example of a passport 1304 to which the ID chip 1303 of the present invention is attached. In FIG. 17B, the ID chip 1303 is attached to the cover of the passport 1304, but may be attached to another page of the passport 1304.

  FIG. 17C shows an example of a gift certificate 1306 to which the ID chip 1305 of the present invention is attached. The ID chip 1305 may be formed inside the gift certificate 1306 or may be formed so as to be exposed on the surface of the gift certificate 1306.

  An ID chip using an integrated circuit having TFTs is inexpensive and thin. For this reason, the ID chip of the present invention is suitable for applications that are ultimately disposable by consumers. In particular, when used for a product whose price difference in units of several yen or several tens of yen greatly affects sales, the packaging material having an inexpensive and thin ID chip of the present invention is very useful. The packaging material corresponds to a support that can be molded or molded to wrap an object such as a wrap, a plastic bottle, a tray, or a capsule.

  FIG. 18A shows a state where a boxed lunch 1309 for sale is packaged with a packaging material 1308 to which an ID chip 1307 of the present invention is attached. By recording the price of the product in the ID chip 1307, the price of the bento 1309 can be settled with a register having a function as a reader / writer.

  In addition, for example, the ID chip of the present invention is attached to the label of the product, and the usage method of managing the distribution of the product using the ID chip is also possible.

  As shown in FIG. 18B, the ID chip 1311 of the present invention is attached to a support such as a label 1310 of a product whose back surface is adhesive. Then, the label 1310 to which the ID chip 1311 is attached is attached to the product 1312. Identification information regarding the product 1312 can be read wirelessly from the ID chip 1311 attached to the label 1310. Therefore, the ID chip 1311 facilitates the management of merchandise during the distribution process.

  For example, when a writable nonvolatile memory is used as the memory included in the integrated circuit in the ID chip 1311, the distribution process of the product 1312 can be recorded. Also, by recording the process at the product production stage, it becomes easy for wholesalers, retailers, and consumers to understand the production area, producer, date of manufacture, processing method, and the like.

  This embodiment can be implemented in combination with the configurations of the first to eighth embodiments.

The top view of the laser beam spot and the crystallized semiconductor film. The block diagram which shows the structure of random number ROM, the circuit diagram of each memory cell, and the figure which shows distribution of a memory cell. The block diagram which shows one form of a functional structure of the ID chip of this invention. FIG. 6 is a diagram showing a layout of an integrated circuit and a layout of a first region and a second region formed by laser light irradiation. 4A and 4B illustrate a method for manufacturing an ID chip of the present invention. 4A and 4B illustrate a method for manufacturing an ID chip of the present invention. 4A and 4B illustrate a method for manufacturing an ID chip of the present invention. 4A and 4B illustrate a method for manufacturing an ID chip of the present invention. The figure which shows the structure of the memory cell array which random number ROM has, and a reading circuit. The figure which shows the structure of the memory cell array which random number ROM has, and a reading circuit. The figure which shows the structure of the memory cell array which random number ROM has, and a reading circuit. Sectional drawing of ID chip | tip of this invention. Sectional drawing of ID chip | tip of this invention. Sectional drawing of TFT used for the ID chip | tip of this invention. FIG. 5 shows a method for manufacturing a plurality of ID chips of the present invention using a large substrate. The figure which shows the shape of the groove | channel formed when peeling the some integrated circuit formed on one board | substrate. The figure shown about the utilization method of ID chip of this invention. The figure shown about the utilization method of ID chip of this invention. Sectional drawing of ID chip | tip of this invention. SEM image of the first region. SEM image of the second region.

Explanation of symbols

101 Beam spot
102 area
103 area
104 Active layer
105 active layer

Claims (14)

Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of semiconductor elements comprising a plurality of first thin film transistors;
A plurality of second thin film transistors, and a plurality of memory elements used as identification ROMs,
Either the source region or the drain region of the second thin film transistor is electrically connected to the gate electrode of the second thin film transistor ,
The active layer of the second thin film transistor, of the semi-conductor film, the position and size are used a second region having a random fine crystal,
The active layer of the first thin film transistor uses a first region of the semiconductor film having crystal grains having a grain size larger than that of the microcrystal and having higher crystallinity than the second region. A semiconductor device. Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of memory elements used as a ROM for identification ;
A microprocessor;
A connection terminal;
A first circuit that generates a power supply voltage from an AC signal input to the connection terminal by the antenna;
A second circuit for demodulating the alternating signal to form a signal;
By controlling the switch in accordance with data read from said plurality of memory elements by said signal, anda third circuit for modulating a load applied to the antenna,
Active layer of the plurality of second thin film transistor used in the plurality of memory devices, among the semi-conductor film, and by using the second region of which position and size have a random fine crystal,
The active layers of the plurality of first thin film transistors used in the microprocessor and the first to third circuits have crystal grains having a grain size larger than that of the microcrystals in the semiconductor film. And using the first region having higher crystallinity than the second region,
Wherein one of a source region and a drain region having the second thin film transistor, a semiconductor device, wherein the second thin film transistor is a gate electrode electrically connected with. Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of semiconductor elements comprising a plurality of first thin film transistors;
A plurality of second thin film transistors, and a plurality of memory elements used as identification ROMs,
Either the source region or the drain region of the second thin film transistor is electrically connected to the gate electrode of the second thin film transistor,
Active layer before Symbol first thin film transistor, of the semiconductor film, and by using the first region,
Active layer before Symbol second thin film transistor, of the semiconductor film, and using said second region different from the first region,
The first region includes crystal grains continuously grown in one direction,
The semiconductor device, wherein the second region includes crystal grains having a grain size in a range of ½ or more of a channel length of the second thin film transistor and three times or less of the channel length. Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of memory elements used as a ROM for identification ;
A microprocessor ;
A connection terminal;
A first circuit that generates a power supply voltage from an AC signal input to the connection terminal by the antenna;
A second circuit for demodulating the alternating signal to form a signal;
By controlling the switch in accordance with data read from said plurality of memory elements by said signal, anda third circuit for modulating a load applied to the antenna,
The active layer of the plurality of first thin film transistor used in the microprocessor and the first circuit to the third circuit of the semiconductor film, and by using the first region,
The active layers of the plurality of second thin film transistors used in the plurality of memory elements use a second region different from the first region in the semiconductor film,
Either the source region or the drain region of the second thin film transistor is electrically connected to the gate electrode of the second thin film transistor,
The first region includes crystal grains continuously grown in one direction,
The semiconductor device, wherein the second region includes crystal grains having a grain size in a range of ½ or more of a channel length of the second thin film transistor and three times or less of the channel length. In claim 3 or claim 4,
The active layer having the previous SL first thin film transistor, wherein a laid out such that the the direction of movement of the carrier in one direction coincide. Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of semiconductor elements comprising a plurality of first thin film transistors;
A plurality of second thin film transistors, and a plurality of memory elements used as identification ROMs,
Either the source region or the drain region of the second thin film transistor is electrically connected to the gate electrode of the second thin film transistor,
Active layer of the second thin film transistor, out of the semi-conductor film crystallized by a continuous wave laser is used the second region of which position and size have a random fine crystal,
The active layer of the first thin film transistor uses a first region of the semiconductor film having crystal grains having a grain size larger than that of the microcrystal and having higher crystallinity than the second region. A semiconductor device. Has a Integrated Circuit, a and electrically connected to the antenna to the integrated circuit,
The integrated circuit comprises:
A plurality of memory elements used as a ROM for identification ;
A microprocessor;
A connection terminal;
A first circuit that generates a power supply voltage from an AC signal input to the connection terminal by the antenna;
A second circuit for demodulating the alternating signal to form a signal;
By controlling the switch in accordance with data read from said plurality of memory elements by said signal, anda third circuit for modulating a load applied to the antenna,
Active layer of the plurality of second thin film transistor used in the prior SL plurality of memory elements, of the crystallized semiconductor film by a continuous wave laser, the position and size of a second with random microcrystalline Using the area,
The active layers of the plurality of first thin film transistors used in the microprocessor and the first to third circuits have crystal grains having a grain size larger than that of the microcrystals in the semiconductor film. And using the first region having higher crystallinity than the second region,
Wherein one of a source region and a drain region having the second thin film transistor, a semiconductor device, wherein the second thin film transistor is a gate electrode electrically connected with. In claim 6 or claim 7,
The first region is a semiconductor device characterized by comprising said crystal grains that have grown continuously in the scanning direction of the laser beam. In claim 8,
Before SL active layer having the first thin film transistor, and wherein a laid out such that the scanning direction and the moving direction of the carrier coincide. In any one of Claims 6 thru | or 9,
The second region includes the microcrystal having a grain size in a range of ½ or more of the channel length of the second thin film transistor and three times or less of the channel length. . In any one of Claims 2, 4 or 7,
The first circuit to the third circuit and the microprocessor are provided in the first region of the first region and the second region which are alternately formed, and the second circuit A semiconductor device, wherein the semiconductor device is electrically connected by a wiring extending over a region. In any one of claims 2, 4, 7 or 11,
A semiconductor device wherein data is determined by comparing voltages between adjacent memory cells among the plurality of memory elements. Forming a semiconductor film on the substrate;
The semiconductor film is irradiated with laser light in one direction to form a first region and a second region having lower crystallinity than the first region in the semiconductor film,
Forming an active layer of a first thin film transistor using the first region, forming an integrated circuit having the first thin film transistor;
An active layer of a second thin film transistor is formed using the second region, and a memory element used as an identification ROM having the second thin film transistor is formed ;
A method for manufacturing a semiconductor device, wherein an antenna electrically connected to the integrated circuit is formed . Forming a semiconductor film on the substrate;
The semiconductor film is irradiated with laser light in one direction to form a first region and a second region having lower crystallinity than the first region in the semiconductor film,
Forming an active layer of a first thin film transistor using the first region, forming an integrated circuit having the first thin film transistor;
An active layer of a second thin film transistor is formed using the second region, and a memory element used as an identification ROM having the second thin film transistor is formed;
A method for manufacturing a semiconductor device, wherein a wiring electrically connected to the first thin film transistor and the second thin film transistor and an antenna are formed in the same step.