JP4716911B2 - Ultrasound diagnostic processor - Google Patents

Description

  The present invention relates to a processor for an ultrasonic diagnostic apparatus, and more particularly to a processor for an ultrasonic diagnostic apparatus that performs parallel processing on data obtained by transmitting and receiving ultrasonic waves.

  In an ultrasonic diagnostic apparatus for medical use, an ultrasonic probe is brought into contact with or inserted into a body surface of a subject and an ultrasonic wave is transmitted, and an internal state of the body is determined based on a reflected wave signal of the ultrasonic wave. A diagnostic image or the like is obtained. In general, in an ultrasonic diagnostic apparatus, a signal inside the apparatus is converted into digital data and then processed. That is, an analog signal as a received signal is converted into a digital signal, and a variety of calculations are performed on the signal, resulting in the formation of a diagnostic image or the like. For this reason, the amount of digital data to be processed inside the ultrasonic diagnostic apparatus is enormous. In order to improve the image responsiveness and real-time display performance of the ultrasonic diagnostic apparatus, it is indispensable to process a large amount of digital data at high speed and image it at high speed. Therefore, in the ultrasonic diagnostic apparatus, a plurality of processors are used in each stage of each process, and each processor is required to have a high processing speed in order to process a huge amount of data. Yes.

  Here, a processor represented by a central processing unit (CPU) and a digital signal processor (DSP) is a key component for speeding up data processing. A DSP is a semiconductor device specialized for signal processing, and various functions can be realized by executing a signal processing program in the same manner as a CPU. These processors are equipped with various speed-up means for improving data processing capability as technology advances. One of the speed-up means is SIMD (Single Instruction Multiple Data). The SIMD system means a data processing system that processes a plurality of data simultaneously and in parallel with a single instruction. In a processor adopting the SIMD system, a data format and an instruction set to be handled can perform a batch operation on a plurality of data input in parallel. That is, instead of occupying the maximum data bus width of the processor with only one piece of data, the data bus width is functionally divided so that a plurality of data can be handled simultaneously in parallel. When a SIMD processor is used, parallel processing of data becomes possible, so that the processing speed can be increased.

  In the following, Patent Document 1 describes a technique related to an arithmetic unit using the SIMD method and an arithmetic processing device using the arithmetic unit. Patent Document 2 describes a technique related to an ultrasonic diagnostic system using a SIMD processor.

JP 2000-47998 A JP 2000-189422 A

  As shown in the background art, performing a data operation using a CPU or DSP equipped with a SIMD function is an effective means for increasing the processing speed. However, even if the SIMD function is used, a high processing speed may not be maintained. This is a case where conditional branch processing represented by an if statement is executed. In the case of executing a SIMD operation, a process that determines the value of the operation result in the middle of the operation and performs conditional branching is not suitable for SIMD. In other words, conditional branching processing that determines whether or not a certain predetermined condition is met and selects a jump destination in the program in an alternative is not compatible with SIMD processing. This is because when it is determined whether or not a certain condition is met for a plurality of data, there are rare cases where all the data matches the condition, or conversely, all the data does not match the condition. This is because there are many cases where data that matches the condition and data that does not match are usually mixed. In this way, when matching and mismatching with respect to the determination condition coexist, it is necessary to perform individual processing for each data according to the determination result, and the level of translation processing is disturbed. As described above, when a conditional branch process is executed as it is in a processor equipped with a SIMD arithmetic function, the translation process of the data string is disturbed, and there is a problem that the processing speed of the program is remarkably reduced.

  Note that none of the SIMD methods described in Patent Document 1 and Patent Document 2 described above proposes a special method for solving such a problem. In particular, the concept of using an operation table for simultaneous parallel processing is not presented.

  An object of the present invention is to provide a processor for an ultrasonic diagnostic apparatus that can execute high-speed data computation while maintaining parallel processing.

  (1) In the ultrasonic diagnostic apparatus processor for parallel processing each input data constituting the input data string obtained by transmitting and receiving ultrasonic waves, the present invention compares the input data string and the comparison data string, First arithmetic means for generating a comparison result data string; representative bit string extraction means for extracting a representative bit from each comparison result data constituting the comparison result data string and generating a representative bit string from the representative bits; and An operation table storing a plurality of operation data strings corresponding to bit patterns that can be represented by the representative bit string, and a specific operation data string selected according to the representative bit string from the plurality of operation data strings, And second calculation means for executing data calculation on the input data string and generating an output data string.

  According to the above configuration, in the first calculation means, the input data string and the comparison data string are compared by parallel processing to generate a comparison result data string. Then, representative bits are extracted from each comparison result data constituting the comparison result data string, and a representative bit string in which these representative bits are arranged is generated. Here, a plurality of operation data strings are prepared in advance in correspondence with bit patterns that can be represented by representative bit strings, and specifically, these operation data strings are stored in an operation table. Then, a specific operation data string is selected according to a certain bit pattern formed by the representative bit string. The selected specific operation data string is used by the second calculation means to execute data calculation on the input data string. Therefore, in such a configuration, it is possible to perform a batch data calculation while maintaining the parallelism of the calculations performed by the first calculation unit and the second calculation unit. That is, since the parallelism of operations is not disturbed, high-speed arithmetic processing can be performed as compared with conventional arithmetic processing. Further, for example, even when conditional branch processing is performed, no branch occurs, so that high processing speed can be realized while maintaining parallel processing of operations. Incidentally, the first calculation unit and the second calculation unit may be configured by a common calculation unit. Further, the operation table may be configured in an internal memory provided in the processor or may be configured on a storage unit of a peripheral device existing outside the processor.

  Preferably, the data operation includes a logical operation corresponding to a conditional branch process. According to this configuration, it is possible to perform conditional branch processing by batch processing by logical operation while ensuring parallelism of data to be calculated. That is, when performing conditional branch processing, a logical operation is used in addition to the use of the table as described above, instead of the conditional branch instruction.

  Preferably, the data operation further includes an arithmetic operation. According to this configuration, a desired output data string can be obtained by combining the logical operation and the arithmetic operation in the second arithmetic means.

  Preferably, in the data calculation, the operation data constituting the specific operation data sequence is applied to the input data constituting the input data sequence, and the storage processing or change processing of the input data is performed. It includes a calculation that is selectively executed. According to this configuration, each operation data selected as a specific operation data string from among the operation data strings stored in the operation table exhibits an action for alternative processing for each input data, and is calculated. It is possible to perform high-speed computation while maintaining simultaneous parallelism.

  Preferably, the data calculation is performed by causing the derived operation data generated according to each operation data constituting the specific operation data sequence to act on each input data constituting the input data sequence, It includes an operation for selectively executing a storage process or a change process of input data. For example, when a plurality of different operation tables are used, a derived operation data string can be generated by causing the operation data strings specified from each operation table to interact with each other. Derived operation data strings are composed of multiple derived operation data. By using the derived operation data, it is possible to perform high-speed operations while maintaining the parallelism of operations with the action for alternative processing for each input data. Can be performed.

  Preferably, each representative bit constituting the representative bit string is a sign bit representing positive or negative. According to this configuration, for example, when the calculation operation in the first calculation means is a difference calculation, it is determined based on the sign bit string whether the comparison result for size determination is positive or negative. can do.

  Preferably, each comparison data constituting the comparison data string is a plurality of threshold data for size discrimination. According to this configuration, the arithmetic operation in the first arithmetic means can be used as an arithmetic means for judging the magnitude relationship of numerical values as a means for conditional branch processing.

  (2) The present invention provides an ultrasonic diagnostic apparatus processor for parallel processing of N pieces of input data (where N is an integer equal to or greater than 2) obtained by transmission / reception of ultrasonic waves. First arithmetic means for comparing N pieces of comparison data to generate N pieces of comparison result data, N representative bits are extracted from the N pieces of comparison result data, and a representative bit string is determined by the representative bits. Representative bit string extraction means to be generated, an operation table storing a plurality of operation data strings corresponding to bit patterns that can be represented by the representative bit string, and specific operation data according to the representative bit string from among the plurality of operation data strings A column is selected, and N operation data constituting this specific operation data sequence is used to perform data operation on the N input data to generate N output data. And having a second calculating means. The possible value of N is preferably a value represented by a power of 2, such as 2, 4, 8 or 16, but may be any other numerical value. Incidentally, it is desirable to select a value of N that is as large as the specifications of the processor allow, which increases the parallel processing capability.

  (3) The present invention relates to a processor for an ultrasonic diagnostic apparatus that processes in parallel each input data that constitutes an input data sequence obtained by transmission and reception of ultrasonic waves. The processor for an ultrasonic diagnostic apparatus includes a calculation unit and a storage unit. And the arithmetic unit generates a comparison result data string by an arithmetic operation of the input data string and the comparison data string, and extracts representative bits from each comparison result data constituting the comparison result data string, A representative bit string is generated from these representative bits, and a data operation on the input data string is performed using a specific operation data string selected according to the representative bit string from the plurality of operation data strings prepared in advance. And generating an output data string, and the storage unit stores the plurality of operation data strings, and the plurality of operation data strings may be represented by the representative bit string Characterized in that it corresponds to the Ttopatan. According to the above configuration, a function for generating a comparison result data string by an arithmetic operation of an input data string and a comparison data string, a function for extracting a representative bit from each comparison result data, and generating a representative bit string are prepared in advance. The function of executing the data operation on the input data string and generating the output data string using the specific operation data string selected from the plurality of operation data strings is achieved by the common calculation unit.

  As described above, according to the present invention, high-speed data computation can be executed while maintaining the translation processing of computation. Therefore, for example, even in the process corresponding to the conditional branch process, no branch occurs, so that high-speed arithmetic processing can be performed without disturbing the process flow for the input data string.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an overall configuration of an ultrasonic diagnostic apparatus in which a processor according to the present invention is mounted. The system control unit 30 in FIG. 1 has a role of comprehensively controlling the ultrasonic diagnostic apparatus, and the system control unit 30 includes a CPU 31 that performs overall control. Further, the system control unit 30 outputs a signal or the like as a basis of control timing to each unit shown in FIG.

  The transmission beam former 18 has a plurality of transmission delay circuits, and an output signal of each transmission delay circuit is supplied to each vibration element in the probe 10. The plurality of transmission delay circuits are driven based on the basic signal of the control timing output from the system control unit 30, and the delay time is controlled for the plurality of vibration elements arranged in the probe 10. The transmitted signal is output.

  The probe 10 has an array transducer configured by arranging a large number of transducer elements. Each vibration element transmits an ultrasonic wave by a transmission signal whose timing is controlled toward a living body. The ultrasonic wave transmitted toward the living body is received as a reflected wave from the living body. In FIG. 1, this ultrasonic transmission / reception state is conceptually shown as a single ultrasonic beam B. By scanning the ultrasonic beam B electronically, a sector-shaped scanning surface 14 is formed. The scanning plane 14 is a data capturing plane, and the data capturing position is grasped using r indicating the distance from the transducer and the scanning angle θ. In the present embodiment, the sector scanning method is illustrated, but linear scanning, convex scanning, radial scanning, and other scanning methods can also be employed.

  The reception beam former 16 includes a plurality of A / D conversion circuits, a plurality of reception wave phase matching circuits, and an addition circuit. Each A / D conversion circuit (not shown) has a function of converting an echo signal received by each vibration element into digital data. Each received wave phase matching circuit has a function of controlling the delay amount of each echo signal to align the phases, and an adding circuit has a function of adding a plurality of phase-matched echo signals. The plurality of echo signals obtained by the probe 10 are phased and added by the reception beam former 16 to form one echo data, which is sent to the beam processing unit 20.

  In the beam processing unit 20, the following signal processing is sequentially performed on the echo data transmitted from the reception beam former 16. That is, processing such as detection processing for detecting an envelope of a received high-frequency signal and dynamic range compression processing for correcting the luminance of the signal. In order to perform such signal processing, a plurality of DSPs 34 are mounted on the beam processing unit. Each DSP 34 performs signal processing by executing a predetermined program. The echo data for which signal processing has been completed is sent to the image processing unit 22 at the next stage.

  In the image processing unit 22, conversion processing such as threshold processing and binarization processing is performed on the echo data. In the image processing unit 22, various processes may be performed depending on the operation mode of the ultrasonic diagnostic apparatus. For example, when displaying a blood flow image on a B-mode image by the color Doppler method, the image processing unit 22 performs spatial filter processing and the like. The image processing unit 22 also uses a plurality of image data processing DSPs 36. The echo data output from the image processing unit 22 is sent to a digital scan converter (DSC) 24 at the next stage.

  In the DSC 24, image data is created. An image memory is provided inside the DSC 24 and has a coordinate conversion function and an interpolation processing function. By performing the coordinate conversion process, the echo data managed in the transmission / reception coordinate system is converted into image data managed in the display coordinate system. The DSP 38 is also used for such image data production processing.

  The video output unit 26 converts the image data output from the DSC 24 into a monitor signal for displaying an image on the display unit 28. A CRT or LCD is generally used as the display unit 28. For example, a tomographic image corresponding to the sector-shaped scanning plane 14 is displayed on the display unit 28 in B mode display.

  The operation panel 32 has data input devices such as a keyboard and a trackball. The operation panel is electrically connected to the system control unit 30, and data input from the operation panel 32 can be stored in the system control unit 30. Examples of data stored in the system control unit 30 include a threshold value for threshold processing and a phase angle for aliasing correction processing.

  As described above, in the present embodiment, a CPU 31 for system control and a plurality of processors such as a plurality of DSPs 34, 36, and 38 for echo data processing are used in this embodiment. ing.

  FIG. 2 shows a schematic block diagram of the ultrasonic diagnostic apparatus processor according to the embodiment of the present invention. The processor 40 includes a computing unit 42 and an internal memory 44, and the computing unit 42 transmits and receives data to and from the data bus 46 via the internal memory 44. By using the data bus 46, the CPU 31 and the DSPs 34, 36, and 38 of the system control unit can exchange data with each other via an external memory (not shown). Details of the operation will be described with reference to FIGS. 5 to 21 described later.

  Prior to describing a specific example of the embodiment of the present invention, a conventional echo data processing method will be described with reference to FIG. The content described with reference to FIG. 3 is a content for supplementary explanation of the above-described problems of the prior art.

  A C language program 50 shown in FIG. 3 is a program for threshold processing. This is a process for comparing the echo data, which is data to be calculated, with a threshold value, storing the echo data without processing for values above the threshold value, and setting the echo data to 0 for values below the threshold value. Is described. The threshold value TH to be compared is a constant value. The echo data used in the program 50 is stored in the array data [i] 54 as shown in FIG. The first line of the program 50 in FIG. 3 indicates that the repetition process is executed N times using the variable i as a number counter. The second line shows conditional branch processing of the if statement. The magnitude relationship between the calculation target value data [i] and the threshold value TH is examined, and a branch destination is determined according to the result. If the value of certain echo data data [i] is larger than the threshold value TH, the processing moves to the branch destination of the third line of the program 50, and the value of data [i] is directly changed to the array output [i]. Stored in If the value of data [i] is less than or equal to the threshold value TH, the process moves to the branch destination on the fifth line of the program 50, and 0 is stored in output [i].

  When the threshold processing as shown in the program 50 in FIG. 3 is performed by SIMD parallel computation, the conditional branch destination as described above cannot be specified, or the conditional branch destination can be specified. There arises a problem that subsequent processing is greatly disturbed. For example, when four echo data are to be processed in parallel, as one case, one data is larger than the threshold value TH and the remaining data is sufficiently lower than the threshold value TH. As described above, when data that satisfies the determination condition and data that does not satisfy the condition are mixed, it is difficult to perform a process of selecting a branch destination in one of two alternatives. When a situation occurs where the judgment conditions are mixed, the parallelism of the four data read in a batch is disturbed, and the data can only be decomposed and processed individually. The magnitude relationship with the threshold value is determined for each data, and the data is sequentially processed. Even when trying to execute conditional branch processing while maintaining parallel processing using a processor equipped with a SIMD operation function in this way, high-speed data processing cannot be desired because parallelism cannot be maintained. . Therefore, this embodiment will be described below.

  FIG. 5 shows a conceptual diagram of a preferred first embodiment of the present invention. Specifically, the contents regarding threshold processing for determining the size of echo data are shown. This threshold processing is data processing executed using the DSP 36 in the image processing unit 22 shown in FIG. Hereinafter, in FIG. 5, the description of the threshold processing will be described in detail along the flow of data processing. The input data string 70 to be calculated is composed of four input data. More specifically, the input data string 70 shown in FIG. 5 is composed of four 16-bit input data (data [0], data [1], data [2], data [3]). The input data string 70 is input to the first calculator 72 and the second calculator 84. Here, the comparison data string 74 input to the first calculator 72 is also composed of four comparison data. In the first computing unit 72, the following parallel computation is performed using the input data string 70 and the comparison data string 74.

FIG. 6 shows details of the calculation performed by the first calculator 72. The input data string 70 input to the first calculator 72 is subtracted for comparison with the comparison data string 74 to obtain a comparison result data string 88. That is, four comparison data (TH [0], TH [1]) are converted from four input data (data [0], data [1], data [2], data [3]) by the subtraction operation of the SIMD method. , TH [2], TH [3]) are subtracted collectively to obtain four comparison result data (tmp [0], tmp [1], tmp [2], tmp [3]). Although subtraction is used here, arithmetic operations other than subtraction, logical operations, and other operations may be used to obtain comparison result data. The four comparison result data serve as means for judging the magnitude relationship between the input data and the comparison data. As is well known, the most significant bit of a numerical value in binary notation can be used as a sign bit representing the sign of the numerical value. Therefore, also in this comparison result data string 88, the 16th bit which is the most significant bit of each comparison result data can be used as each sign bit 68. That is, the four code bits (S ₀ , S ₁ , S ₂ , S ₃ ) represented by the symbol S in FIG. 6 are either “1” or “0” depending on the magnitude relationship between the echo data and the threshold value. (In this specification, a numerical value in binary notation is enclosed by “”). Here, as a specific example, it is assumed that the values of four sign bits are determined, and S ₀ = “0”, S ₁ = “1”, S ₂ = “0”, and S ₃ = “0”. When these four code bits are extracted and arranged in order, a 4-bit code bit string 76 is created. In the example illustrated in FIG. 6, the code bit string 76 represented by the symbol SIGN is “0010”. Originally, the sign bit takes either a value of “0” or “1”, so that there are 2 ⁴ = 16 combinations that can be identified by a 4-bit bit pattern.

  Next, the code bit string 76 and the operation table A80 shown in FIG. 5 will be described in detail with reference to FIG. In FIG. 7, the code bit string 76 is exemplified as the bit pattern of “0010” described above. On the other hand, the operation table A80 includes 16 sets (16 columns) of operation data strings 92, and each operation data string 92 includes four operation data 90a, 90b, 90c, and 90d. When a bit pattern of a certain code bit string 76 is determined, an arrow 94 shown in the figure indicates that a specific operation data string 82 is determined accordingly.

The value of each code bit constituting the code bit string 76 is obtained by extracting information on the magnitude relationship between the input data and the threshold comparison data. In order to execute threshold processing, if the sign bit is “0”, the input data may be processed without conversion. Conversely, if the sign bit is “1”, the input data is converted to 0. And then process it. In order to select whether conversion is necessary or not, either 0xFFFF or Ox0000 is selected as the operation data corresponding to the value of the sign bit. The selection method in the threshold processing of 0xFFFF and 0x0000 is performed by the following two methods. (I) When the sign bit is “0”, 0xFFFF is selected as operation data. (Ii) When the sign bit is “1”, 0x0000 is selected as operation data. Incidentally, both 0xFFFF and 0x0000 are numbers in hexadecimal notation. Here, since the illustrated code bit string 76 is “0010”, it corresponds to four code bits S ₀ = "0", S ₁ = "1", S ₂ = "0", and S ₃ = "0". When the four pieces of operation data selected are listed, they become 0xFFFF, 0x0000, 0xFFFF, and 0xFFFF. These four pieces of operation data are TABLE_A [8] = 0xFFFF, TABLE_A [9] = 0x0000, TABLE_A [10] = 0xFFFF, TABLE_A [11] as the operation data sequence at position # 2 indicated by the arrow 94 shown in FIG. = 0xFFFF. As can be seen from this example, when all four code bits are determined, a combination of specific operation data strings 82 corresponding thereto can be automatically determined. Here, since the bit patterns that can be taken by the code bit string 76 are 16 patterns from “0000” to “1111”, the specific operation data string 82 includes 16 sets of operations from # 0 to # 15 shown in FIG. Corresponds to one of the data columns. The operation table A80 is configured by collecting these 16 sets of operation data strings. Further, the four pieces of operation data constituting the operation data string 92 are determined to be either 0xFFFF or 0x0000 in accordance with the two rules (i) and (ii) described above. Whatever value the sign bit string 76 can take, a specific operation data string 82 corresponding to the value is stored in advance in the operation table A80. The substantial configuration of the operation table A80 is a set of data strings configured on the internal memory 44 in the processor 40 shown in FIG. When a certain operation data string 92 is specified according to the bit pattern of the sign bit string 76, a relative memory address management number managed in the program may be used or assigned to the memory. The hardware address number may be used directly. The symbol TABLE_A [i] shown in FIG. 7 indicates a memory address management number. Incidentally, the operation table A80 may be configured in a storage unit of a peripheral device outside the processor 40. It is also possible to configure an operation table A80 that cannot be erased by writing to a non-volatile memory.

  Next, the relationship among the specific operation data string 82, the input data string 70, and the second calculator 84 shown in FIG. 5 will be described in detail with reference to FIG. FIG. 8 shows the contents of the calculation performed by the second calculator 84. The input data string 70 input to the second calculator 84 is converted into an output data string 86 by performing a logical AND operation with a specific operation data string 82. That is, four input operation data (data [0], data [1], data [2], data [3]) are converted into four specific operation data (0xFFFF, 0x0000, 0xFFFF, 0xFFFF) by SIMD logical operation. ) To obtain a logical product in a lump, thereby obtaining four output data (out [0], out [1], out [2], out [3]). As is well known, in a logical product operation, the output value in bit units becomes “1” only when the input values in both bit units are “1”. In addition, when even one input value in bit units has “0”, the output value in bit units is “0”. In the present embodiment, the four specific operation data constituting the specific operation data string 82 for performing threshold processing are either 0xFFFF or 0x0000, and 0xFFFF is applied in the logical product operation. Means an operation that does not perform any conversion processing on the input data to be calculated. That is, the input data is stored and output as it is. On the other hand, applying 0x0000 is a change process for replacing the input data to be calculated with 0. That is, applying 0x0000 is a replacement process to zero. In the specific example shown in FIG. 8, only data [1] is operated with 0x0000 in the logical product operation, so only out [1] becomes 0. The other three data out [0], out [2], and out [3] are the values of the input data data [0], data [2], and data [3] as they are. As a result, an appropriate threshold value process is performed by a logical product operation in the second operation unit 84, whereby an output data string 86 is obtained in a lump.

  As described above, as shown in the conceptual diagram of FIG. 5, the output data string 86 is output by the second calculator 84 from the stage when the input data string 70 as echo data is input to the first calculator 72 and the second calculator 84. The four data are all processed in translation until the stage of outputting is output, so that the order of operations is not disturbed. Thus, maintaining the parallelism of data processing is extremely effective in maintaining a high execution speed.

Incidentally, in this embodiment, according to the two rules (i) and (ii) described above, 0xFFFF is associated when the sign bit is “0”, and 0x0000 when the sign bit is “1”. It corresponds. However, as another application example, another operation table A ₂ that corresponds to 0x0000 when the sign bit is “0” and applies 0xFFFF when the sign bit is “1” is used for threshold processing. It is also possible to use it. When threshold processing is performed using another operation table A ₂ , immediately after the bit pattern of the sign bit string 76 is determined and before the specific operation data string 82 is determined, the bit pattern is subjected to a negative logic operation. It is necessary to invert by (NOT calculation). That is, it is possible to by adding negative logical operation of the code bit string 76 to obtain a correct result of the threshold processing be another operation table A _2. However, when the other operation table A ₂ is used, the calculation time for executing the negative logic operation is accumulated, resulting in a disadvantage in terms of processing speed. That, considering the speed of computation purposes, rather than using the operation table A ₂ which are not shown, it is desirable to use an operating table A80 shown in FIG.

  Next, for reference, a specific program for causing the processor to execute the threshold processing shown in the conceptual diagram of FIG. 5 will be described with reference to FIG. The program 96 shown in FIG. 9 consists of four lines in total. Since there is no operator that expresses SIMD operations in the C language, the symbol “[]” is provisionally used as an operator that handles data in parallel.

  An expression tmp [] = data [] − TH [] written in the first line of the program 96 is an expression indicating parallel subtraction processing by the SIMD method, and corresponds to an operation performed by the first calculator 72. That is, four comparisons constituting the comparison data string TH [] are made from the four input data (data [0], data [1], data [2], data [3]) constituting the input data string data []. By subtracting the data (TH [0], TH [1], TH [2], TH [3]) all at once, the four comparison result data (tmp [0]) constituting the comparison result data string tmp [] , Tmp [1], tmp [2], tmp [3]).

  The expression described in the second line of the program 96 is an expression showing a process in which the sign bit S is extracted from the comparison result data string tmp [] and the sign bit string SIGN is generated. The processor capable of SIMD processing according to the present embodiment has a function of detecting a bit corresponding to a sign bit. Therefore, data corresponding to the SIGN bit pattern can be directly derived without performing a shift instruction, a logical product operation, or the like as shown in the expression on the second row. Accordingly, the parallel operation is not disturbed in the sign bit extraction process and the sign bit string SIGN generation process. Incidentally, the expression described in the second row illustrates the calculation method for the sign bit extraction process and the sign bit string SIGN generation process. First, for the part (tmp [3] >> 12), the comparison result data tmp [3] as data in binary notation is shifted to the right by 12 digits. Then, the numerical value of the sign bit located at the 16th most significant bit of tmp [3] is moved to the 4th bit counted from the least significant bit. By performing a logical product with 0x8 on the binary notation data after the right shift by 12 digits, bit determination is made as to whether only the fourth digit is “1” or “0”. Similar processing is performed for the other three input data tmp [2], tmp [1], and tmp [0]. In other words, the sign bit of tmp [2] is shifted to the right by 13 digits and moved to the third digit, and bit judgment of only the third digit is performed by performing a logical product with 0x4. The sign bit of tmp [1] is shifted to the right by 14 digits, moved to the second digit, and is subjected to a logical AND with 0x2, whereby only the second digit is determined. The sign bit of tmp [0] is shifted to the right by 15 digits, moved to the first digit, and is subjected to a logical product with 0x1 to determine the bit of only the first digit. The data of the four bit determinations for which the bit determination is performed for each of the fourth digit, the third digit, the second digit, and the first digit are collected into one data by taking four logical sums. By consolidating four code bits into one data, a bit pattern of a 4-bit code bit string SIGN is formed. (In fact, only the extraction process corresponding to the shift instruction and logical product is executed in the processor, and the parallelism for each data is not disturbed.) The sign bit is used because it is optimal, but the extracted bit may be any number of bits. For example, it is also possible to extract a specific bit other than the most significant bit as a representative bit after the arithmetic operation is performed by the first arithmetic unit 72 and accumulate the representative bit string from these representative bits.

  The expression shown in the third line of the program 96 is an expression indicating a process for specifying one operation data string from the operation table A80 in which the operation data string is stored. The specific operation data string is determined by the bit pattern of the sign bit string SIGN. That is, one operation data string is specified from the array TABLE_A [] that is the operation table A80 according to the bit pattern of the sign bit string SIGN. The identified operation data string is substituted into MASK as a variable written on the left side of the expression.

  The expression out [] = data [] & MASK [] written in the fourth line of the program 96 is an expression showing parallel logical product operation by the SIMD method. MASK [] indicates a specific operation data string 82, which is equivalent to the variable MASK determined by the expression in the third row. Four input data (data [0], data [1], data [2], data [3]) that constitute data [] as the input data string 70 and specific operation data are obtained by the expression in the fourth row. By taking a logical product with MASK [] as the column 82, (out [0], out [1], out [2], out [3]) as the output data sequence 86 can be obtained.

  By performing threshold processing according to the above procedure, four input data can be processed in a batch. After the threshold processing of the first input data string (data [0], data [1], data [2], data [3]) is completed, the subsequent input data strings (data [4], data [ It goes without saying that threshold processing of 5], data [6], data [7]) is executed sequentially. Since sequential determination processing using a conditional branch instruction is not performed, processing corresponding to the determination condition can be performed at high speed, and a processing speed several times higher than that of sequential processing can be expected.

  Next, as a second embodiment of the present invention, a correction process for the aliasing phenomenon when a blood flow image is formed by the color Doppler method will be described in detail. The color Doppler method is a method for displaying a blood flow state using an ultrasonic Doppler effect generated in the blood flow. The color Doppler method is an effective method for visualizing and displaying blood flow. However, when the blood flow velocity is larger than the upper limit determined by the sampling period, the direction of blood flow approaches the probe. Or the direction of moving away from each other. This is known as a folding phenomenon that occurs when the deviation frequency exceeds the so-called Nyquist frequency, and is a phenomenon that hinders calculation of an appropriate blood flow velocity. Therefore, in order to obtain an appropriate average value of blood flow velocity in the vicinity of the folding speed, folding correction processing is performed on the speed data.

  In general, in the color Doppler method, ultrasonic waves are transmitted / received to / from a living body a plurality of times in the same direction, and an average value of blood flow velocity is obtained based on respective echo data. In this case, since there is an upper and lower limit of blood flow velocity detection, the blood flow velocity value includes folded data. When the averaging process or the like is performed on the blood flow velocity, it is necessary to selectively perform the aliasing correction process for each piece of data between the aliasing speeds. Hereinafter, the aliasing correction process will be described in detail with reference to FIGS. 10 to 18.

  A complex plane graph 114 shown in FIG. 10 is a schematic diagram for illustrating the blood flow velocity and the blood flow direction obtained based on the ultrasonic Doppler effect. The velocity information can be described as a vector having a phase angle θ on the complex plane. On the complex plane graph 114 shown in FIG. 10, θ1 (reference numeral 116) and θ2 (reference numeral 118) are shown as phases of two pieces of velocity information. Both θ1 and θ2 are measured values obtained by observing blood flow in the same direction approaching the probe. Then, it is appropriate that both θ1 and θ2 are measured as positive values (for example, θ1 = 130 °, θ2 = 200 °). However, as a measurement value measured by the Doppler method, θ2 is measured as a negative value (for example, θ2 = −160 °). This is called a folding phenomenon. If the measured value is used as it is and (θ1 + θ2) / 2, which is a simple average value, is calculated, θ2 is apparently a negative value, so the angle indicated by the θa vector 120 shown in the graph 114 of FIG. Is required. However, since θ2 is actually a positive value, the position of the vector 120 of θa is inappropriate. The correct average value (θ1 + θ2) / 2 is properly represented as the vector 122 of θb shown in the graph 114.

  Therefore, in order to obtain a correct average value, a two-stage process is performed according to the procedure described below. First, as a first stage process, an absolute value of an angle difference between two values to be calculated is obtained, and it is checked whether or not the angle difference Δθ is larger than a predetermined angle 180 °. The angle difference Δθ is expressed by the equation Δθ = | θ1-θ2 |. If the angle difference Δθ is greater than 180 °, it is determined that the arrow representing the vector needs to be reversed. Conversely, if it is 180 ° or less, no reversal is performed, so no processing is performed. If it is determined that it is necessary to invert, the next second stage processing is performed. In the second stage of processing, in order to invert the arrow representing the vector, processing for determining whether to invert 180 ° in the clockwise rotation direction or 180 ° in the counterclockwise direction is performed. Specifically, in the second stage process, the calculation result of the simple average value θavg is used for the determination. The simple average value θavg is expressed by the equation θavg = (θ1 + θ2) / 2. If the value of θavg is 0 or more, 180 ° is subtracted from the simple average value. That is, the reversal process is performed by rotating 180 ° in the clockwise direction. On the other hand, if the value of θavg is smaller than 0, 180 ° is added to the simple average value. That is, the reversal process is performed by rotating 180 ° counterclockwise. As described above, the aliasing correction process can be performed by obtaining the simple average value θavg and the angle difference Δθ and performing the first and second stage processes together. Although the two-stage merge process itself can be said to be a known technique, in the present embodiment, this is realized by the SIMD method.

  FIG. 11 shows a conceptual diagram of the aliasing correction processing of the color Doppler method. This processing is data processing executed using the DSP 36 in the image processing unit 22 shown in FIG. Hereinafter, the aliasing correction processing will be described in detail along the flow of data processing with reference to FIG. The calculation target input data string 124 includes four input data ave_TH [0], ave_TH [1], ave_TH [2], and ave_TH [3]. Here, ave_TH [P] is a value of a simple average value {θ (2P + 1) + θ (2P + 2)} / 2 (where P is an integer of 0 or more), for example, ave_TH [0] = (θ1 + θ2) ) / 2, and ave_TH [1] = (θ3 + θ4) / 2. Further, the value of ave_TH [2] is obtained using θ5 and θ6, and the value of ave_TH [3] is obtained using θ7 and θ8. Here, the values that each θ can take are merely examples, and the same values may be included or different values. These simple average values ave_TH [P] are obtained in advance by calculation at a stage before being assigned to the input data string 124. The input data string 124 is input to the first calculator 126 and the second calculator 148.

The contents of the calculation performed by the first calculator 126 will be described with reference to FIG. In the first computing unit 126, the comparison result data string 152 is obtained by subtracting the comparison data string 140 from the input data string 124. In the embodiment of the aliasing correction process, since all the values of the comparison data string 140 are 0, each of the four code bits (S ₀ , S ₁ , S ₂ , S ₃ ) extracted from the comparison result data string 152 is displayed. The value indicates the sign of each simple average value ave_TH [].

Next, the relationship between the code bit string 128 and the operation table B130 shown in FIG. 11 will be described with reference to FIG. In FIG. 13, the code bit string 128 indicates “0101” as an example bit pattern. If the value of each code bit constituting the code bit string 128 is “0”, the vector 120 indicating the simple average value is located in a region above the real number axis (horizontal axis) of the graph 114 shown in FIG. Indicates that Therefore, the sign bit being “0” indicates that the clockwise direction is appropriate when the vector 120 is inverted. Conversely, if the value of the sign bit is “1”, it means that the vector 120 indicating the simple average value is located in a region below the real number axis (horizontal axis) of the graph 114 shown in FIG. Show. Therefore, the sign bit being “1” indicates that the counterclockwise direction is appropriate when the vector 120 is inverted. In summary, if the sign bit is “0”, operation data rotated by −180 ° may be applied, and if the sign bit is “1”, operation data rotated by + 180 ° may be applied. Since 180 in decimal notation is 0x00B4 in hexadecimal notation, in the operation table B130 shown in FIG. 13, when the code bit is “0”, 0xFF4C is selected, and (vi) the code bit is “ In the case of “1”, 0x00B4 is selected. The value of the operation data stored in the operation table B130 is determined according to two rules (iii) and (vi). As shown in FIG. 13, the specific operation data string 132 corresponding to the exemplary bit pattern “0101” is the operation data string 132 at the position # 5 indicated by the arrow 154, and TABLE_B [20] = 0xFF4C, TABLE_B [21] = 0x00B4, TABLE_B [22] = 0xFF4C, TABLE_B [23] = 0x00B4. The specific operation data string 132 is assigned to an array named OFFSET [] at the stage of performing a logical operation in the second arithmetic unit 148 described later. Whatever value the bit pattern of the sign bit string 128 takes, a specific operation data string corresponding to the bit pattern is prepared in advance in the operation table B130. Since the illustrated code bit string 128 is 4 bits, the operation table B130 is composed of 16 sets of operation data strings. If the parallelism of SIMD operations is high and the code bit string 128 is 8 bits, the operation table B130 prepared in advance corresponding to the code bit string 128 is composed of 256 sets of operation data strings. . In general, when the representative bit string has N digits, the operation table prepared in advance includes 2 ^N sets of operation data strings. Here, ± 180 ° is expressed as an integer value so that angle correction can be easily understood. However, in order to ensure accuracy, ± 180 ° is normalized to ± 1.0 and processed with a 16-bit fixed point. Better to do.

  Returning to FIG. 11 and confirming the calculation so far, a specific operation data sequence 132 is determined based on the input data sequence 124, the first calculator 126, the sign bit sequence 128, and the operation table B130. An operation for determining the direction in which the vector 120 indicating the speed is reversed has been performed. By the way, in addition to the determination of the vector rotation direction, another determination condition is required for the determination of whether reversal is necessary or unnecessary. Therefore, it is necessary to perform an operation for deriving the determination condition. In the following, the necessity / unnecessity determination processing determined by using the reference data string 156, the third arithmetic unit 134, the sign bit string 136 and the operation table C138 shown in FIG. 11 will be described.

  The reference data string 156 to be calculated is composed of four input data delt_TH [0], delt_TH [1], delt_TH [2], and delt_TH [3]. Here, delt_TH [P] indicates the absolute value of the phase difference {θ (2P + 1) −θ (2P + 2)} (where P is an integer equal to or greater than 0). For example, delt_TH [0 ] = | Θ1-θ2 |, and delt_TH [1] = | θ3-θ4 |. These angle differences delt_TH [P] are calculated in advance before being assigned to the reference data string 156. The reference data string 156 is input to the third calculator 134.

The contents of the calculation performed by the third calculator 134 shown in FIG. 11 will be described with reference to FIG. The third computing unit 134 subtracts the comparison data string 158 from the reference data string 156 to obtain a comparison result data string 160. Since the determination as to whether the inversion is necessary is determined based on the magnitude relationship with 180 °, all the values assigned to the comparison data string 158 are 180. That is, PI [0] = 0x00B4, PI [1] = 0x00B4, PI [2] = 0x00B4, PI [3] = 0x00B4. Each value of the four sign bits (S ₀ , S ₁ , S ₂ , S ₃ ) extracted from the comparison result data string 160 has determination information that does not need to be inverted.

  Next, the relationship between the code bit string 136 and the operation table C138 will be described with reference to FIG. In FIG. 15, the code bit string 136 indicates “0110” as an example bit pattern. If the value of each sign bit constituting the sign bit string 136 is “0”, it indicates that the value obtained by subtracting 180 ° from the absolute value of the angle difference is positive or 0, and inversion processing is required. Means that. The operation data string 162 specified from the operation table C138 is premised on acting with the specific operation data string 132 for determining the rotation direction described above. Therefore, when inversion is necessary, an operator of 0xFFFF may be selected. On the contrary, if the value of the sign bit is “1”, it indicates that the value obtained by subtracting 180 ° from the absolute value of the angle difference is negative, which means that the inversion process is unnecessary. Therefore, if inversion is not necessary, an operator of 0x0000 may be selected. In the operation table C138 shown in FIG. 15, (v) 0xFFFF is selected when the sign bit is “0”, and (vi) 0x0000 is selected when the sign bit is “1”. The values of all the operation data stored in the operation table C138 are determined according to two rules (v) and (vi). As shown in FIG. 15, the specific operation data string 162 corresponding to the exemplary bit pattern “0110” is the operation data string at position # 6 indicated by the arrow 164, and TABLE_B [24] = 0xFFFF, TABLE_B [25 ] = 0x0000, TABLE_B [26] = 0x0000, TABLE_B [27] = 0xFFFF. The specific operation data string 162 is assigned to an array named MASK [] at the stage of performing a logical operation in the second arithmetic unit 148 described later. Incidentally, the operation table C138, which is the purpose of determining whether reversal is necessary, and the operation table A80, which is the purpose of performing threshold processing, are substantially the same operation table.

  Next, the calculation performed by the second calculator 148 in FIG. 11 will be described. The second computing unit 148 includes two computing units, a logical computing unit 164 and an arithmetic computing unit 166. FIG. 16 shows the contents of the data calculation performed by the logical calculator 164 that is a part of the second calculator 148. A specific operation data string 132 derived from the operation table B130 and a specific operation data string 162 derived from the operation table C138 are input to the logical operator 164. The logical operator 164 performs a logical product operation to obtain a derived operation data string 168. That is, in the logical operator 164, operation data (OFFSET [0], OFFSET [1], OFFSET [2], OFFSET [3]) derived from the four operation tables B130 and four specific operation data (MASK [ 0], MASK [1], MASK [2], MASK [3]), and the four data obtained again (OFFSET [0], OFFSET [1], OFFSET [2], OFFSET [ 3]) is overwritten and stored. The specific operation data string 132 stores either a value of +180 or −180 that specifies the reverse rotation direction, and a value of 0xFFFF or 0x0000 stored in the specific operation data string 162 As a result, a logical product operation is performed, and a derivative operation data string 168 is obtained. By performing the logical product operation, one process is selected from the following three processes. That is, one is a process that does not require reversal, the other is a process that requires reversal and rotates 180 ° counterclockwise, and the other one requires reversal and rotates 180 degrees clockwise. This is a rotation process. In this way, various operations can be executed by causing two operation data strings derived from two different operation tables to interact with each other. In the present embodiment, the processing that does not need to be inverted does not need to be further subdivided into two, so that the processing consisting of three operations can be performed in parallel. By the way, in general, if two operation tables are used, four different processes can be performed simultaneously and in parallel. The obtained calculation result is stored again in OFFSET [] and used in the arithmetic operation unit 166 in the next stage.

  FIG. 17 shows the contents of the data calculation performed by the arithmetic calculator 166 that is a part of the second calculator 148. The arithmetic operation unit 166 receives the OFFSET [] derived operation data sequence 168 output from the logical operation unit 164 and the input data sequence 124 of ave_TH []. The arithmetic operator 166 adds the input data string 124 and the derived operation data string 168, which is the operation result of the logical operator 164, to obtain an output data string 170. The operation performed by the arithmetic operation unit 166 is performed by appropriately performing the aliasing correction processing on individual input data ave_TH [0], ave_TH [1], ave_TH [2], and ave_TH [3] that have not yet been aliasing corrected. It can be regarded as an operation for correcting the generated data. In order to correct to the appropriate data, any one of the three operations described above is selectively performed, and each data (out [0], out [1], out [2] ], Out [3]).

  As described above, by performing the calculation as shown in the conceptual diagram of FIG. 11, the input data string 124, which is a simple average value of the flow velocity, is input to the first calculator 126 to generate the sign bit string 128, A specific operation data string 132 is selected from the above. Further, the reference data string 156 is input to the third computing unit 134 to generate a sign bit string 136, and a specific operation data string 162 is selected from the operation table C138. Then, the second arithmetic unit 148 performs a logical operation on the operation data string 132 and the operation data string 162. The input data string 124 is added to the derived operation data string 168 obtained by the logical operation, and an output data string 170 is obtained. In this way, all four data are translated and processed at all stages of the calculation, and the steps of the calculation are not disturbed. By using the two operation tables of the operation table B130 and the operation table C138, it is possible to perform processing for selectively specifying one operation from the three operations.

  For reference, next, the aliasing correction process shown in the conceptual diagram of FIG. 11 is described as a specific program for causing the processor to execute. A program 174 shown in FIG. 18 is a program for the aliasing correction process, and is composed of seven lines in total. In the program 174, a simple average value data string ave_TH [P] and an angle difference delt_TH [P] are used as calculation targets. However, it is assumed that the data string ave_TH [P] of the simple average value and the angle difference delt_TH [P] have already been obtained before the execution of the program 174. That is, the value of the simple average value {θ (2P + 1) + θ (2P + 2)} / 2 (where P is an integer greater than or equal to 0) is already stored in the array ave_TH [], and the absolute value of the angle difference For the value of | θ (2P + 1) −θ (2P + 2) | (where P is an integer equal to or greater than 0), it is assumed that the value is already stored in the array delt_TH [], and calculation using those data is started. I will explain from the part to be.

  An expression tmp [] = delt_TH []-PI [] written in the first line of the program 174 shown in FIG. 18 is an expression showing parallel subtraction processing by the SIMD method. This corresponds to the comparison calculation performed by the third calculator 134 shown in FIG. That is, four comparisons constituting the comparison data string PI [] from the four input data (delt_TH [0], delt_TH [1], delt_TH [2], delt_TH [3]) constituting the input data string delt_TH []. By subtracting the data (PI [0], PI [1], PI [2], PI [3]) at once, the four comparison result data (tmp [0]) constituting the comparison result data string tmp [] , Tmp [1], tmp [2], tmp [3]).

  The expression described in the second line of the program 174 is an expression indicating a process in which the sign bit S is extracted from the comparison result data string tmp [] and the sign bit string SIGN is generated. This corresponds to the generation process of the code bit string 136 shown in FIG. The processing on the right side of the expression on the second line will be described. First, for the part (tmp [3] >> 12), the data in binary notation of the comparison result data tmp [3] is shifted to the right by 12 digits. Then, the numerical value of the sign bit located at the 16th most significant bit of tmp [3] is moved to the 4th bit counted from the least significant bit. Next, perform logical AND with 0x8 on the numeric value after shifting right by 12 digits [(tmp [3] >> 12) & 0x8], so that only the fourth digit is “1” or “0” Bit determination is performed. Similar processing is performed for the other three input data tmp [2], tmp [1], and tmp [0]. That is, the sign bit of tmp [2] is moved to the third digit by shifting it to the right by 13 digits, and is logically ANDed with 0x4 so that only the third digit is “1” or “0”. Bit determination is performed. The sign bit of tmp [1] is shifted to the right by 14 digits, moved to the second digit, and logical AND with 0x2 is performed to determine whether only the second digit is “1” or “0” Is done. The sign bit of tmp [0] is shifted to the right by 15 digits to move to the first digit, and by performing a logical AND with 0x1, only the first digit is determined to be “1” or “0”. Is done. A total of four bit determination data in the fourth digit, the third digit, the second digit, and the first digit are collected into one data by taking four logical sums. The & symbol in the expression shown in the second line represents a logical product, and the | symbol represents a logical sum operation. The bit pattern of the sign bit string SIGN is formed by aggregating the four sign bits into one data.

  The expression shown in the third line of the program 174 is an expression indicating a process for specifying one operation data string from the operation table C138 in which the operation data string is stored. This corresponds to processing for specifying a specific operation table 162 as shown in FIG. One operation data string is specified from the array TABLE_C [] of the operation table C138 according to the bit pattern of the code bit string SIGN of the operation table C138 of the code bit string 136, and determined as the specified operation data string called MASK. . As shown in FIG. 15, when the sign bit string 136 is SIGN = “0110”, TABLE_C [24] = 0xFFFF, TABLE_C [25] = 0x0000, TABLE_C [26] = 0x0000, TABLE_C [27] = 0xFFFF Are used as specific operation data. In the program of FIG. 18, a specific operation data string is designated by the name MASK.

  The expression described in the fourth line of the program 174 is an expression indicating a process in which the sign bit string SIGN2 is generated by extracting the sign bit S from the input data string ave_TH []. The processing on the right side of the expression on the fourth line will be described. First, the part of (ave_TH [3] >> 12) is shifted to the right by 12 digits as binary notation data of the input data ave_TH [3]. Then, the numerical value of the sign bit located at the 16th most significant bit of ave_TH [3] is moved to the 4th bit counted from the least significant bit. Next, perform logical AND with 0x8 on the numeric value after shifting right by 12 digits {(ave_TH [3] >> 12) & 0x8} so that only the 4th digit is “1” or “0” A determination is made. Similar processing is performed for the other three input data ave_TH [2], ave_TH [1], and ave_TH [0]. In other words, the sign bit of ave_TH [2] is shifted to the third digit by shifting it to the right by 13 digits, and by performing an AND operation with 0x4, only the third digit is a bit that is “1” or “0”. A determination is made. The sign bit of ave_TH [1] moves to the second digit by shifting it 14 digits to the right, and by performing a logical product with 0x2, only the second digit is judged to be “1” or “0”. Done. The sign bit of ave_TH [0] is shifted to the right by 15 digits and moved to the first digit. By performing logical AND with 0x1, only the first digit is judged as “1” or “0”. Done. A total of four bit determination data in the fourth digit, the third digit, the second digit, and the first digit are collected into one data by taking four logical sums. The bit pattern of the sign bit string SIGN2 is formed by aggregating the four sign bits into one data.

  The expression shown in the fifth row is an expression indicating a process for specifying one operation data string from the operation table B130 in which the operation data string is stored. According to the bit pattern of the sign bit string SIGN2, one operation data string is specified from the array TABLE_B [] of the operation table B130, and is determined as a specific operation data string named OFFSET. When a specific numerical value is used, for example, when the code bit string SIGN2 is “0101”, TABLE_B [20] = 0xFF4C, TABLE_B [21] = 0x00B4, TABLE_B [22] = 0xFF4C, TABLE_B [23] = Four pieces of data of 0x00B4 are used as specific operation data. In the program of FIG. 18, a specific operation data string 132 is designated by the name OFFSET.

  The expression OFFSET [] = OFFSET [] & MASK [] described in the sixth line is an expression indicating parallel AND operation by the SIMD method. MASK [] indicates a specific operation data string 162, which is equivalent to the variable MASK determined by the expression in the third row. The four input data (OFFSET [0], OFFSET [1], OFFSET [2], OFFSET [3]) constituting the operation data string 132 and the MASK as a specific operation data string 162 are obtained by the expression in the fourth row. By taking a logical product with [], (OFFSET [0], OFFSET [1], OFFSET [2], OFFSET [3]) as a derived operation data string can be obtained.

  The expression out [] = ave_TH [] + OFFSET [] written in the seventh line is an expression indicating a parallel addition operation by the SIMD method. By adding the derived operation data string OFFSET [] to the input data string ave_TH [] that has not yet undergone aliasing correction processing, appropriate aliasing correction processing is selectively performed on each data, and the result Is stored in out [].

  Next, echo data binarization processing will be described in detail as a modification. The binarization process described in this specification indicates a process for setting the luminance value of the pixels constituting the image to 1 if the luminance value is larger than the determination reference value, and to 0 if the luminance value is smaller. As a specific application example, the present invention can be applied to the case where the boundary between the myocardium, which is a biological tissue part, and the heart chamber is detected when echo data relating to the tomographic plane of the heart is processed. This binarization processing is data processing performed by the DSP 36 in the image processing unit 22 shown in FIG.

Hereinafter, detailed description will be given along the flow of the binarization processing using FIG. The input data string 178 to be calculated is composed of four input data and is input to the first calculator 180. A comparison data string 182 composed of four comparison data is also input to the first calculator 180. The value stored in the comparison data string 182 is, for example, a determination reference value for determining the brightness of the pixel luminance value. In the first computing unit 180, subtraction is performed by subtracting the comparison data string 182 from the input data string 178 to generate a comparison result data string. Therefore, each value of the four code bits (S ₀ , S ₁ , S ₂ , S ₃ ) extracted from the comparison result data string has information on a determination result having a magnitude relationship with the determination reference value. The code bit string 184 is a set of four code bits.

  Next, the code bit string 184 and the operation table D186 shown in FIG. 19 will be described in detail with reference to FIG. The code bit string 184 shown in FIG. 20 is exemplified as a bit pattern “0010”. On the other hand, the operation table D186 shown in FIG. 20 includes 16 sets (16 columns) of operation data strings, and each operation data string includes four operation data. When the bit pattern of the sign bit string 184 is determined, it is indicated by an arrow 190 shown in FIG. 20 that a specific operation data string 188 is determined from among the 16 sets.

The value of each code bit constituting the code bit string 184 is obtained by extracting information on the magnitude relationship between the input data and the threshold comparison data. Therefore, in order to execute the binarization process, if the sign bit is “0”, the input data may be replaced with 1. Conversely, if the sign bit is “1”, the input data may be replaced with 0. In order to select whether or not the replacement processing is necessary, either 0x0001 or Ox0000 is selected as operation data corresponding to the value of the sign bit. The selection method in the binarization processing of 0x0001 and 0x0000 is performed by the following two methods. (Vii) When the sign bit is “0”, 0x0001 is selected. (Viii) When the sign bit is “1”, 0x0000 is selected. Here, since the exemplified code bit string 184 is “0010”, it corresponds to four code bits S ₀ = "0", S ₁ = "1", S ₂ = "0", and S ₃ = "0". The four pieces of operation data selected in this way are listed as 0x0001, 0x0000, 0x0001, and 0x0001. These four pieces of operation data are TABLE_D [8] = 0x0001, TABLE_D [9] = 0x0000, TABLE_D [10] = 0x0001, TABLE_D [11] as the operation data string at position # 2 indicated by the arrow 190 shown in FIG. = 0x0001. As can be seen from this example, when all four code bits are determined, a combination of specific operation data strings 188 corresponding thereto can be automatically determined. The operation table D186 is configured by collecting these 16 sets of operation data strings. Further, the four operation data constituting the operation data string is determined as either 0x0001 or 0x0000 according to the two rules (vii) and (viii) described above. Whatever value the sign bit string 184 can take, a specific operation data string 188 corresponding to the value is stored in the operation table D186 in advance.

  As shown in FIG. 19, the specified operation data string 188 can be used as the output data string 192 as it is. Since two types of values can be stored in the operation table D186 in advance, the second arithmetic unit is not particularly required in the case of binarization processing.

  A program 194 shown in FIG. 21 exemplifies a program for binarization processing. The processing performed in the first and second lines of the program 194 is substantially the same as the processing performed in the first and second lines of the threshold processing program 96 shown in FIG. That is, parallel subtraction processing by the SIMD method is performed by the processing described in the first line of the program 194. Then, a 4-bit code bit string 184 represented by SIGN is created by the processing described in the second line of the program 194. The expression shown in the third line of the program 194 is an expression indicating a process for specifying one operation data string from the operation table D186 in which a plurality of operation data strings are stored. That is, one operation data string is specified from the array TABLE_D [] of the operation table D186 shown in FIG. 20 according to the SIGN bit pattern shown in the second row of the program 194. Then, the value of the specific operation data string 188 is directly assigned to the array out [].

  As described above, even when the binarization process is performed, it is possible to process the four input data at once by using the operation table D186 for the binarization process. However, when the binarization processing shown in the conceptual diagram of FIG. 19 is performed, unlike the embodiments shown in FIGS. 5 and 11 and the like, those corresponding to the second arithmetic unit are not included.

  In the description of the threshold processing, the aliasing correction processing using the color Doppler method, and the binarization processing described in detail so far, an arithmetic unit having a maximum data bus width of 64 bits is used. An example of a SIMD type arithmetic unit capable of parallel calculation of 16 bits × 4 data with one data length of 16 bits is shown. However, operations that can be performed by a SIMD processor are not limited to 16 bits × 4 data. Depending on the specifications of the processor, it may have a data bus width of 32 bits, 128 bits, or 256 bits, and the data bus width is divided into two division values, four divisions, eight divisions, 16 divisions, etc. It is also possible to select one of them and execute parallel processing. When performing parallel processing, the number of data that can be processed simultaneously is N (where N is an integer of 2 or more). In that case, the input data string, the comparison data string, the comparison result data string, the specific operation data string, and the output data string are all composed of N pieces of data. The number of digits in the representative bit string is N digits. The coincidence of the numbers N with respect to the number of data strings or the number of digits indicates that parallel processing is consistently performed during the operation. When a plurality of SIMD type arithmetic units are provided, the performance improvement degree of the high-speed processing is further increased.

1 is a block diagram showing an overall configuration of an ultrasonic diagnostic apparatus in which a processor according to the present invention is mounted. 1 is a schematic block diagram of a processor for an ultrasonic diagnostic apparatus according to an embodiment of the present invention. It is a figure which shows the example of a program which shows the processing method of the echo data by a prior art. FIG. 5 is a schematic diagram of an array data [i] that stores data to be calculated. It is the figure which showed the conceptual diagram of suitable embodiment of this invention. It is outline | summary explanatory drawing of the calculation performed with a 1st calculator. 4 is a diagram illustrating a correspondence relationship between a code bit string and an operation table A. FIG. It is outline | summary explanatory drawing of the calculation performed with a 2nd calculator. It is a figure which shows the example of a program for making a processor perform the threshold value process shown in the conceptual diagram of FIG. It is a figure which shows the graph of the complex plane which illustrates the speed and direction of the blood information obtained based on an ultrasonic Doppler effect. It is the figure which showed the conceptual diagram of the calculation of the folding correction process of a color Doppler method. It is outline | summary explanatory drawing of the calculation performed with a 1st calculator. 4 is a diagram illustrating a correspondence relationship between a code bit string and an operation table B. FIG. It is a schematic explanatory drawing of the calculation performed with a 3rd calculator. 4 is a diagram illustrating a correspondence relationship between a code bit string and an operation table C. FIG. It is a conceptual explanatory drawing of the data calculation performed with the logic calculator which is a part of 2nd calculator. It is a schematic explanatory drawing of the data calculation performed with the arithmetic calculator which is a part of 2nd calculator. It is a figure which shows the example of a program for making a processor perform the folding correction | amendment process shown to the conceptual diagram of FIG. It is the figure which showed the conceptual diagram of the calculation of a binarization process. 4 is a diagram illustrating a correspondence relationship between a code bit string and an operation table D. FIG. It is a figure which shows the example of a program for making a processor perform the binarization process shown to the conceptual diagram of FIG.

Explanation of symbols

  70 input data string, 72 first operator, 74 comparison data string, 76 sign bit string, 80 operation table A, 82 specific operation data string, 84 second operator, 86 output data string.

Claims (9)

In the processor for an ultrasonic diagnostic apparatus that processes in parallel each input data constituting an input data string obtained by transmission / reception of ultrasonic waves,
A first computing means for comparing the input data string and the comparison data string to generate a comparison result data string;
Representative bit string extracting means for extracting representative bits from each comparison result data constituting the comparison result data string, and generating a representative bit string by those representative bits;
An operation table storing a plurality of operation data strings corresponding to bit patterns that can be represented by the representative bit string;
Using a specific operation data string selected according to the representative bit string from among the plurality of operation data strings, a second calculation means for executing a data operation on the input data string and generating an output data string;
A processor for an ultrasonic diagnostic apparatus, comprising: The processor for an ultrasonic diagnostic apparatus according to claim 1,
The processor for an ultrasonic diagnostic apparatus, wherein the data operation includes a logical operation corresponding to a conditional branch process. The processor for an ultrasonic diagnostic apparatus according to claim 2,
The processor for an ultrasonic diagnostic apparatus, wherein the data calculation further includes an arithmetic calculation. The processor for an ultrasonic diagnostic apparatus according to claim 1,
In the data calculation, each input data constituting the input data string is caused to act on each operation data constituting the specific operation data string, so that the storage process or change process of each input data is selectively performed. A processor for an ultrasonic diagnostic apparatus, comprising an operation to be executed. The processor for an ultrasonic diagnostic apparatus according to claim 1,
The data calculation is performed by causing derived operation data generated according to each operation data constituting the specific operation data sequence to act on each input data constituting the input data sequence, and A processor for an ultrasonic diagnostic apparatus, comprising an operation for selectively executing a storage process or a change process. The processor for an ultrasonic diagnostic apparatus according to claim 1,
The processor for an ultrasonic diagnostic apparatus, wherein each representative bit constituting the representative bit string is a sign bit representing positive or negative. The processor for an ultrasonic diagnostic apparatus according to claim 1,
Each of the comparison data constituting the comparison data string is a plurality of threshold data for size discrimination, the ultrasonic diagnostic apparatus processor. In a processor for an ultrasonic diagnostic apparatus that processes N pieces of input data (where N is an integer of 2 or more) obtained by transmission / reception of ultrasonic waves in parallel,
First arithmetic means for comparing the N input data and the N comparison data to generate N comparison result data;
Representative bit string extracting means for extracting N representative bits from the N comparison result data and generating a representative bit string by using the representative bits;
An operation table storing a plurality of operation data strings corresponding to bit patterns that can be represented by the representative bit string;
A specific operation data string is selected from the plurality of operation data strings according to the representative bit string, and N pieces of operation data constituting the specific operation data string are used for the N pieces of input data. Second calculation means for executing data calculation and generating N pieces of output data;
A processor for an ultrasonic diagnostic apparatus, comprising: In the processor for an ultrasonic diagnostic apparatus that processes in parallel each input data constituting an input data string obtained by transmission / reception of ultrasonic waves,
The ultrasonic diagnostic apparatus processor includes a calculation unit and a storage unit,
The computing unit is
A comparison result data string is generated by an arithmetic operation of the input data string and the comparison data string,
A representative bit is extracted from each comparison result data constituting the comparison result data string, and a representative bit string is generated by the representative bits,
Using a specific operation data string selected according to the representative bit string from the plurality of operation data strings prepared in advance, generating an output data string by performing a data operation on the input data string,
The storage unit stores the plurality of operation data strings,
The processor for an ultrasonic diagnostic apparatus, wherein the plurality of operation data strings correspond to bit patterns that can be represented by the representative bit string.

Images