JP4713901B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit used in a microprocessor, and more particularly to an information processing apparatus equipped with a semiconductor integrated circuit excellent in low power consumption operation characteristics.

  With the miniaturization of the chip manufacturing process, an increase in leakage current has become a problem. Examples of the leakage current include a subthreshold leakage current due to a reduction in threshold voltage, a gate leakage current due to thinning of a gate insulating film due to miniaturization, and a GID (Gate induced drain leakage) current. In order to reduce the leakage current, there is a method of shutting down the circuit power supply during standby.

  As shown in Non-Patent Document 1, the power supply is shut down in units of areas in which a plurality of IPs or functional circuits are grouped, but it is conceivable that fine power supply cutouts in units of IPs will be performed in the future. There are Patent Literature 1 and Patent Literature 2 as literatures that consider power shutdown in IP units.

  In Patent Document 1, power is shut down in units of system circuits including a processor, and when the system circuit does not require operation, a process of writing an instruction to the power shut-off control register is performed. In Patent Document 2, a power cutoff register having a bit indicating power supply for each functional block is provided, and power supply is stopped for each functional block when the functional block is not used.

T.A. Yamada, et. al, “A 133 MHz 170 mW 10 μA standby application processor for 3G cellular phones”, “ISCC, Dig. Tech. Papers”, Feb. 2002, p. 370-371 Japanese Patent Laid-Open No. 2003-114742 Japanese Patent Application Laid-Open No. 7-141074 JP 2003-218682 A

When fine-tuned power control is performed on an IP basis, it is important to know how to shut down IP power and determine the timing of supply. In Patent Document 2, as a method of grasping the power-off timing, the reception of predetermined data by UART and the combination of an external interrupt signal and a timer are cited, but the method is limited to a method using specific IP. It is desirable for each IP to have a common method for grasping the power shutoff and supply timing. Accordingly, the first object of the present invention is to obtain a semiconductor integrated circuit capable of dynamically controlling power supply interruption and supply using a method capable of grasping the power supply interruption and supply timing at any IP by hardware. And The first object is dynamic power control by hardware, but a second object is to obtain a semiconductor integrated circuit capable of controlling power supply and interruption statically in IP units by software.
By the way, to reduce the current during operation, it is effective to finely control the clock to the IP. By using a method similar to the method of controlling power supply dynamically and statically, clock control can be performed statically and dynamically on IP. Therefore, a third object is to obtain a semiconductor integrated circuit capable of performing clock control to IP by the same method as power supply control.
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The present invention includes at least one functional block and a power control register that holds information indicating a power supply state of the functional block, and controls power supply to the functional block according to the information held in the power control register It has a power control circuit and an interrupt control circuit that receives an interrupt signal indicating the end of processing notified from the functional block, and is held in the power control register by a signal notified from the interrupt control circuit based on the interrupt signal. This can be achieved by rewriting the current power supply state.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when the IP operation is unnecessary, it is possible to dynamically determine when it is necessary by hardware, and to perform power supply control of power supply / cutoff in units of IP. Further, since the power control register for setting the power control is a memory mapped register, it can be changed by software. As a result, fine power control in IP units can be performed, and leakage current can be reduced.
Further, even when the number of IPs is very large, the number of wirings can be reduced by using the IP ID as a bus for the interrupt signal and the power supply control signal.

  Furthermore, these power control methods can also be applied to clock supply / stop control.

  Hereinafter, embodiments will be described in detail.

FIG. 1 shows a main part of a system on chip (SOC) according to an example of the present invention. The system-on-chip (SOC) 1 shown in FIG. 1 is not particularly limited, but a single semiconductor such as single crystal silicon is formed by a semiconductor integrated circuit technology for forming a known CMOS (complementary MOS transistor) or bipolar transistor. Formed on a semiconductor substrate.
The system-on-chip (SOC) 1 includes a central processing unit (CPU) 2 as a main processor, an interrupt controller (INTC) 3, a power supply controller (PWRC) 4, a cache (CCH) 5, and three function modules IP1 as an example. 6, IP2 7, IP3 8, and system bus 9. The IP1 is connected to the interrupt controller (INTC) 3 via the interrupt request signal int1_r and the interrupt acknowledge signal int1_a, and the power supply controller is connected to the power supply control request signal pwr1_r and the power supply control acknowledge signal pwr1_a. Also connected.
As an example, if the three functional modules IP1, IP2, and IP3 are collectively referred to as area 1, a power control area request is made between area 1 and power control controller (PWRC) 4 as a signal for performing power control in area units. A signal pwral_r and a power control area acknowledge signal pwral_a are provided.

The present invention is characterized by grasping the end of IP processing and performing power control using an internal interrupt signal indicating the end of general IP processing.
The interrupt controller (INTC) 3 includes an interrupt priority determination circuit (PRI-JDG) 10 that determines interrupt priority, and a comparator (COMP) 11 that compares an interrupt signal with an interrupt mask.
The power control controller (PWRC) includes a power control register (PCTR) 4A. The power supply control register is a memory-mapped register and has an I / O space address. Read / write can be performed using load / store instructions. The registers are provided in units of areas, and each bit is a power control bit for IP belonging to the area. When there are a plurality of areas, a plurality of power control registers are prepared. Each bit represents a state of 0 (power cutoff) and 1 (power supply) in IP units. The power state of the area is represented by OR of each bit. That is, when any IP bit in a certain area is 1 (power supply), the power supply state is established, and when all IP bits are 0 (power interruption), the area is in a power supply interruption state. Here, it is not particularly limited that there are a plurality of power control registers in one area and that the bits are inverted. The value of the power supply control register (PCTR) 4A can be rewritten by two methods.

[1] Method of dynamically changing using interrupt controller (INTC) When an interrupt request signal int1_r from IP1 is received by the CPU, the interrupt controller (INTC) asserts an interrupt acknowledge signal int1_a to IP and simultaneously supplies power The power supply control signal pctl1 is asserted to the control controller (PWRC). The power control signal is composed of two bits, a power trigger signal and a power status signal. As for the power status signal, 0 is power shutdown and 1 is power supply.

  First, the power shutdown will be described. Since the bits of the power control register indicate the power state of IP, when the corresponding bit of IP1 is 1, the power of IP1 is supplied, and when the corresponding bit of IP1 is 0, the power of IP1 is cut off. When the power cutoff signal from the interrupt controller is asserted, the power of the IP1 is still supplied, so the corresponding bit of the power control register is 1. In order to set the corresponding bit of the IP to 0, it is necessary to confirm that the power of the IP is shut down, so the following procedure is performed. First, the interrupt controller asserts the power supply control signal pctl1. Specifically, the power supply trigger signal is asserted and the power supply state signal is set to zero. When the power trigger signal is asserted, the power control controller (PWRC) compares the power status signal 0 and the current value 1 of the corresponding bit of the power control register by exclusive OR, and if they are different, the power control The request signal pwr1_r is asserted to instruct IP1 to turn off the power. Since IP1 knows its power state, it receives the power control request signal, shuts off the power of IP1, and asserts the power control acknowledge signal pwr1_a when the power shut-off process ends. The power supply controller (PWRC) receives the power supply control acknowledge signal from IP1, and writes the value 0 of the power supply state signal to the power supply control register for the first time. By this procedure, consistency between the power state of IP1 and the value of the power control register is maintained.

Supply power in the same procedure. In the case of power supply, the corresponding bit of the IP of the power control register is changed from 0 to 1. A procedure for setting the corresponding bit of IP to 1 will be described. First, the interrupt controller asserts the power supply control signal pctl1. Specifically, the power supply trigger signal is asserted and the power supply state signal is set to 1. When the power trigger signal is asserted, the power control controller (PWRC) compares the power status signal 1 and the current value 0 of the corresponding bit of the power control register by exclusive OR, and if they are different, the power control The request signal pwr1_r is asserted to instruct IP1 to supply power. Since IP1 knows its power state, it receives the power control request signal, supplies power to IP1, and asserts the power control acknowledge signal pwr1_a when the power supply processing is completed. The power supply controller (PWRC) receives the power supply control acknowledge signal from IP1, and writes the value 1 of the power supply state signal to the power supply control register for the first time.
As a means for the IP to grasp its own power state, the IP has a glue logic unit to which power is always supplied, and the glue logic unit grasps the power state of the block unit of the main body, Power can be supplied and shut off.

[2] Method of changing statically using software Since the power control register is mapped in the I / O space of the address, it can be read and written using a software load / store instruction via the system bus . When the data on the system bus is written to the power control register, the power control controller (PWRC) internally generates a control signal similar to the power control signal from the interrupt controller (INTC). To do. That is, when data on the system bus is written to the power control register, the power control controller (PWRC) generates a 2-bit system bus power control signal in units of power control registers. The two bits are a power supply trigger signal and a power supply state signal, and the power supply state signal is 0 for power shutdown and 1 for power supply. The difference from the power control signal from the interrupt controller is that the interrupt controller controls the power of one IP, whereas in the case of software, since it is a register unit, the power of the entire IP existing in the register is controlled. This outputs the power control request signal to all the IPs present in the register, and the writing is completed after receiving all the power control acknowledge signals. Each bit can be written upon receipt of a power control acknowledge signal.

  Let's start with the power shutdown. For simplicity, it is assumed that 0 is written to all bits of the power control register while power is supplied to all IPs. At this time, the power supply trigger signal is asserted and the power supply state signal is set to zero. When the power trigger signal is asserted, the power control controller (PWRC) compares the power status signal 0 with the current value 1 of the corresponding bit of the power control register by exclusive OR. For example, when different in IP1, the power control request signal pwr1_r is asserted to instruct IP1 to shut off the power. Since IP1 knows its power state, it receives the power control request signal, shuts off the power of IP1, and asserts the power control acknowledge signal pwr1_a when the power shut-off process ends. The power supply controller (PWRC) receives the power supply control acknowledge signal from IP1, and writes the value 1 of the power supply state signal to the power supply control register for the first time. Similarly, the power supply of each IP is cut off, the power supply control acknowledge signal is asserted, and the value 1 of the power supply state signal is written to the bit of IP1 of the power supply control register. When the power control controller receives power control acknowledge signals for all IPs belonging to the power control register, the writing to the power control register is completed.

  Next, power supply will be described. For simplicity, it is assumed that 1 is written to all bits of the power control register in a state where the power is shut off to all IPs. At this time, the power supply trigger signal is asserted and the power supply state signal is set to 1. When the power trigger signal is asserted, the power control controller (PWRC) compares the power status signal 1 and the current value 0 of the corresponding bit of the power control register by exclusive OR. For example, when different in IP1, the power control request signal pwr1_r is asserted to instruct IP1 to supply power. Since IP1 knows its power state, it receives the power control request signal, supplies power to IP1, and asserts the power control acknowledge signal pwr1_a when the power supply processing is completed. The power control controller (PWRC) receives the power control acknowledge signal from IP1, and writes the value 1 of the power status signal to the bit of IP1 of the power control register for the first time. Similarly, the power supply of each IP is cut off, the power supply control acknowledge signal is asserted, and the value 1 of the power supply state signal is written to the power supply control register. When the power control controller receives power control acknowledge signals for all IPs belonging to the power control register, the writing to the power control register is completed.

  In the method of dynamically changing using the interrupt controller, when performing power control in units of areas, the power control of the entire IP existing in the register may be performed just like the method of changing by software. This outputs a power control request signal to all the IPs present in the register, and after receiving all the power control acknowledge signals, the writing to the power control register is completed. Each bit can be written upon receipt of a power control acknowledge signal. The procedure for shutting off the power supply is the same as the method for changing the register unit by software, and is therefore omitted.

  The power shutoff and supply operation of the IP 1 according to the first embodiment will be described with reference to FIG. (1) IP1, IP2, and IP3 are supplied with power, IP1 processing is completed, (2) IP1 power is shut off, (3) IP1 power is supplied again Indicates.

  In (1), since the processing of IP1 is completed, the internal interrupt signal int1_r indicating the processing end is asserted to the interrupt controller. Here, interrupt masking is not performed, and the interrupt controller (INTC) determines the priority level 1 of the interrupt from IP1 by the priority determination unit (PRI-JDG) when the interrupt mask (intmsk) is set to the lowest level 0. Since there is no other interrupt signal, an interrupt from IP1 is selected. Then, the comparator (COMP) compares the interrupt level 1 of IP1 with the interrupt mask 0. Since the interrupt level of IP1 is high, the interrupt of IP1 is accepted and an interrupt request (intreq) is notified to the CPU. The power control register (PCTR) indicates the power state of each IP, and is all set to 1 because power is supplied to each IP.

  In (2), when the CPU interrupt acceptance (intack) is notified, the interrupt controller (INTC) asserts for the interrupt acceptance (int1_a) notification to IP1 and the power supply controller (PWRC). On the other hand, the power control signal pctl1 is asserted so that the corresponding bit of IP1 of the power control register (PCTR) becomes 0 in the power shutdown state. Since the power control signal is composed of a power trigger signal and a power status signal, the power trigger signal is asserted and the power status signal is set to zero. When the power trigger signal is asserted, the power control controller (PWRC) compares the power status signal 0 with the current value 1 of the corresponding bit of the power control register by exclusive OR, and asserts the power control request signal pwr1_r. And instructs IP1 to shut off the power. IP1 asserts the power control acknowledge signal pwr1_a after completing the power shutdown process. As will be described later, the IP has a block unit in the power cutoff possible region and a glue logic unit in the power supply region, and only the block unit is powered off. The power supply controller (PWRC) receives the power supply control acknowledge signal pwr1_a from IP1, and writes the value 0 of the power state signal to the bit of IP1 of the power supply control register for the first time.

  (3) Start up IP1 in the power-off state from the CPU. The operation setting of IP1 can be realized by setting a configuration register in the IP mapped in the I / O space of the address. Usually, there are a plurality of configuration registers, and there are uses of IP1 enable, IP1 mode setting, and IP1 activation. The power supply of IP1 is also realized using an interrupt request signal (int1_r) from IP1. The configuration register writes to the configuration register of IP1 using a software load store instruction via the system bus. A store command (IP1en) by a store instruction for setting IP1 enable is output from the CPU to the bus, and IP1 receives the command. When IP1 is in the power-off state, the glue logic unit of IP1 recognizes that the start command has been received in the power-off state, and notifies the interrupt controller (int1_r) to the interrupt controller. Then, the same processing as (1) is performed, and an interrupt request (intreq) to the CPU is asserted. When the CPU interrupt acceptance is notified, the interrupt controller (INTC) notifies the IP1 of the interrupt acceptance and the power control controller (PWRC), as in (2). The power control signal pctl1 is asserted so that the corresponding bit of IP1 becomes 1 in the power supply state. Then, handshaking is performed between the IP1 and the power supply controller (PWRC) using the power supply control request signal and the power supply control acknowledge signal, and the corresponding bit of the IP1 of the power supply control register (PCTR) becomes 1 after the power supply of the IP1. Then, the CPU continues to write to a plurality of configuration registers to IP1 in order to set an operation mode for IP and a setting for starting IP. Then, IP1 is activated after the writing to the configuration register for activation is completed.

  FIG. 3 shows a detailed view of the IP of the first embodiment of the present invention. IP is a representative diagram of IP1, IP2, and IP3 in FIG. 1, and includes a block unit 31 and a glue logic unit 32 for connection to a bus and power management, a power switch 36 for power cutoff, a power switch controller 35, and a different power source. It consists of a micro IO 37 for inter-circuit interface. The present invention is characterized in that the block unit which is the main body of the IP does not have a circuit for power management, and the control logic for power management is collected in a glue logic unit for performing bus connection. When the IP is incorporated in the SOC, the glue logic unit 32 is generally redesigned according to the specifications of the system bus. When redesigning for bus connection, control logic for power shutdown and supply may be added. The glue logic unit can be made common between IPs due to bus-connected I / F logic, but can also be made common even if power management control logic is included. The glue logic unit 32 includes a control unit 38 and a gate 39 for fixing a signal at the time of internal reset. The control unit performs bus connection I / F and power management control. The glue logic unit is always supplied with power unless the upper area unit is powered off. In addition to the glue logic unit that controls power management, a micro IO 37 is placed between circuits between different power sources. The micro IO 37 is an I / F circuit for preventing a through current disclosed in Patent Document 3. Since the output node of the circuit where the power is shut off is in a floating state, a circuit receiving a signal from the output node causes a through current to flow. For this reason, in order to prevent a through current, the micro IO 37 includes an OR gate 40 for fixing a signal outside the IP when the signal of the block portion becomes floating. Using the power switch 36 and the power switch controller 35 disclosed in Patent Document 3, the block unit is powered off. Since the power switch 36 is composed of a thick film NMOS, the power controller 35 includes a level shifter for voltage conversion, power switch control, and micro IO control. Here, an NMOS transistor is provided as a power switch between the block portion and the ground line (VSS). On the other hand, a PMOS transistor may be provided as a power switch between the circuit block and the power line (VDD). The micro IO 37 and the power switch controller 35 are always supplied with power as long as power is not shut off in units of upper areas.

  The control unit of the glue logic circuit has a power supply mode holding flip-flop 42, which is used to grasp its own power supply state. When the content of the flip-flop is 1, the power is supplied, and when the content is 0, the power is cut off. With this information, when the power control request pwr_r signal is asserted, it is possible to determine whether it is a power shutdown request or a power supply request.

  The block unit BLK31, which is the main body of the IP, includes a functional unit FUNC33 and a configuration register unit CFG_REG34. The configuration register 34 normally has a plurality of configuration registers and has configuration information that defines an IP operation mode and the like. Specifically, as described above, there are uses of IP enable, IP mode setting, and IP activation. The configuration register is a register mapped to the address I / O space. The functional unit is composed of a flip-flop that holds temporary information and a combinational circuit, and realizes a function necessary for IP.

  The data held in the block unit when the IP is powered off will be described. Since the flip-flop (FF) of the functional unit holds only temporary data, the contents may be lost when the power is turned off. Depending on the IP, configuration information may or may not be lost when the power is turned off. The case where the information can be lost when the power is shut off is a method of setting the configuration every time the IP is activated, and may be handled in the same manner as the flip-flop of the functional unit. FIG. 3 corresponds to this case, and information is lost when the power is turned off. If the information cannot be lost, the configuration register unit or the FF of the configuration register unit is moved to the glue logic unit 32 to which power is supplied.

  When the IP power is turned on, a reset signal (Rst) is generated internally, and the flip-flops of the function unit (FUNC) 33 and the configuration register unit (CFG_REG) 34 are initialized. Until the initialization is completed, in order to prevent an output signal sig_out such as a bus request from being an incorrect value, the output signal is fixed by the OR gate 39. Then, after the initialization of the internal flip-flop by the reset is completed, the power supply control acknowledge signal (pwr_a) is asserted.

In FIG. 3, when the configuration information is not lost when the IP is powered off, the configuration register unit or the FF of the configuration register unit is moved to the glue logic unit 32 to which power is supplied. .
As another method, the configuration register unit in the block unit can be used as it is by saving and restoring the contents of the configuration register in the memory. The method will be described with reference to FIG.
FIG. 4 is a processing flow of the software interrupt routine. In order to use this method as a premise, the power supply mode holding flip-flop of FIG. 3 is changed.

  The power mode holding flip-flop 42 in FIG. 3 is given an address as a new control register, here CFG_REG_G. Then, the IP state when the interrupt request signal (int_r) is asserted is stored in the 1 bit Pwr. This means that this bit can be changed by an instruction designating an address.

  Let's move on to the processing flow. First, by examining the interrupt event in the interrupt routine, it can be determined which IP caused the interrupt (1). Here, it is assumed that an interrupt has occurred in IP_N. Load configuration register CFG_REG_G [Pwr] in IP_N. By examining the corresponding bit, it is possible to know the power state of IP_N when IP_N asserts the interrupt request signal (2).

  First, if the power supply state CFG_REG_G [Pwr] = 1, it can be seen that this interrupt is due to the end of processing. Therefore, the contents of the configuration register CFG_REG at that time are saved in the memory (3). Then, after the last data is saved in the memory, the IP_N power-off permission is performed. Therefore, the power supply state CFG_REG_G [Pwr] is set to 0 by the store instruction (4). In hardware, after CFG_REG_G [Pwr] becomes 0, the permission signal pwrn_a for power-off is asserted. Processing of the power supply interrupt routine ends.

Next, if the power cutoff state CFG_REG_G [Pwr] = 0, it can be seen that this interrupt is for power supply. Therefore, it waits in a software loop until the IP_N power is supplied (5). Specifically, when the corresponding bit IP_N of the power control register PCTR becomes 1, the power supply state of IP_N is in effect, so the power control register is read until it becomes 1. When the corresponding bit becomes 1, the load instruction is executed, and the contents on the memory are restored to the IP control register (6). Then, the permission signal pwrn_a for power supply is asserted. The interrupt routine processing in the power-off state ends.
As described above, by performing the processing in the interrupt routine of FIG. 4, it is possible to save and restore the control register in the memory by software.

  In FIG. 3, it is necessary to move the configuration register unit or the flip-flop (FF) of the configuration register unit to the glue logic unit 32 to which power is supplied in order not to lose the data of the configuration register when the power is shut off. Further, in FIG. 4, in order not to lose the data in the configuration register when the power is turned off, a save / restore process to the memory by software is necessary. These are because FF information is lost when the power is turned off. FIG. 5 shows an example in which FF information is not lost even when the power is turned off.

FIG. 5 is a block diagram when the flip-flop (FF) in the IP according to the first embodiment of the present invention is constituted by a nonvolatile FF. As an example, the non-volatile FF has a structure in which two power sources, a breakable power source and a non-breakable power source, are provided inside the FF, and an inverter loop for holding values is provided on the non-cutoff power source side. The structure of the nonvolatile FF is not particularly limited even if it is another means. The IP is connected to a block unit 31 similar to the structure of FIG. 3, a glue logic unit 32 for connection to a bus and power management, a power switch 36 for power cutoff, a power switch controller 35, and a micro IO 37 for inter-power supply circuit interface. In addition,
A nonvolatile FF controller 50 is provided for controlling the nonvolatile FF.

  When the nonvolatile FF is used, the contents of the FF are not lost even if the power of the block unit is shut off. Therefore, the control register unit or the FF of the control register unit does not need to be arranged in the glue unit as shown in FIG. Further, it is not necessary to save and restore the configuration register in the memory as shown in FIG. This has the advantage that the processing time at the time of power-off and supply is short. In addition, since the FF information of the function unit is held, internal reset processing is unnecessary, and it is not necessary to fix the output signal.

  In order to facilitate power supply design, the power switch controller (PSWC) can be concentrated in one place for the sake of layout. FIG. 6 shows an example in which the power switch controller (PSWC) in the IP of FIG. 3 is concentrated in one place. If the power switch controllers for IP1, IP2, and IP3 are PSWC1 61, PSWC2 62, and PSWC3 63, respectively, a power switch controller unit 60 is provided. However, the operation is the same as FIG.

FIG. 7 shows a configuration diagram when the number of IPs in the SOC is very large (n power of 2) as a second embodiment of the present invention. As in the first embodiment, when each IP is connected to the interrupt controller (INTC) and the power supply controller (PWRC) in a one-to-one relationship, the wiring area increases, which is not realistic. Therefore, an n-bit ID is added to each IP, and an interrupt signal and a power control signal are made into a bus composed of an n-bit ID and additional information. In each IP, when the ID matches its own number, the interrupt signal and the power control signal become active for the corresponding IP. Specifically, an interrupt request signal (int_r), an interrupt acknowledge signal (int_a), an interrupt bus (Int-bus) composed of ID, a power control request signal (pwr_r), a power control acknowledge signal (pwr_a), and ID This is a power control bus (Pwr-bus) configured. An IP codec (ID-CODEC) that decodes and encodes an ID number is provided in the IP. The interrupt controller and the power supply controller also have an ID codec. As for the signal from the interrupt controller (INTC) to the power supply controller (PWRC), not only the power supply control signal (pctl) but also the ID is output.
The method of grasping the IP processing state by using the internal interrupt signal of the IP of the second embodiment can be applied in addition to the power shutdown.

FIG. 8 shows a configuration diagram of clock control when the number of IPs in the SOC is very large (n power of 2) as a third embodiment of the present invention. Instead of the power control register (PCTR) of the power control controller of FIG. 7, a clock stop register (CSTPR) for controlling clock stop / supply of each IP is used for a clock pulse generator unit (CPG) that performs clock control. An n-bit ID is added to each IP, and an interrupt signal and a clock control signal are a bus composed of an n-bit ID and additional information. Specifically, an interrupt request signal (int_r), an interrupt acknowledge signal (int_a), an interrupt bus (Int-bus) composed of ID, and a clock bus (Clk-bus) composed of a clock stop signal (cstp) and ID ). As a signal from the interrupt controller (INTC) to the power supply control controller (PWRC), a clock control signal (cctl) and ID are output instead of the power supply control signal.
With respect to clock control, since it is not necessary to receive an acknowledge signal from the IP, only the clock request signal (cstp) is used, and the ID is only encoded (ID-ENC) in the clock pulse generator unit.

FIG. 9 shows an example of a portable information system as a preferred application example of the system-on-chip. A cellular phone system is roughly divided into a communication part and an application part. The communication part includes a radio frequency unit (RF) 90 that transmits and receives radio waves with an antenna, a baseband modem and baseband processor (BBP) 89 that performs codec, and a memory (MRYa) 88. The application part includes a central processing unit (CPU) 4, a cache (CCH) 5, MPEG IP 92, 3D graphics IP 93, 2D graphics IP 94, interrupt controller (INTC) 3, and power supply controller 4 as IP groups. 1 is the center. The system-on-chip 1 is connected to a baseband processor 89 via a bus BUS via an interface (I / F) 81, and a camera (CMR) 83, a memory card (CARD) 84, and a sound source unit via a peripheral interface (PPH) 82. A (SOD) 85 and a keyboard (KEY) 86 are connected, and a liquid crystal display (LCD) 87 and a memory (MRYb) 91 are connected via an external bus. This system configuration example is for a mobile phone, but various system configuration examples such as a portable information terminal and a digital camera can be considered.
With this system, power consumption is reduced because the power supply is appropriately shut down when the IP operation is unnecessary, and the added value of the portable information system can be increased.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

1 is a block diagram of a system on chip (SOC) according to a first embodiment of the present invention. FIG. 3 is an operation diagram of power supply cutoff and supply of IP1 according to the first embodiment of the present invention. It is a block diagram of IP which concerns on the 1st Example of this invention. It is a figure which shows the processing flow of a software interruption routine. It is a block diagram in the case of implement | achieving IP using the non-volatile FF which concerns on 1st Example of this invention. It is a block diagram in the case of concentrating the power switch controller which concerns on 1st Example of this invention in one place. It is a block diagram in the case of performing power supply control using very many IP concerning the 2nd Example of this invention. It is a block diagram in the case of performing clock control using very many IP concerning the 3rd Example of this invention. 1 is a system configuration diagram for a mobile phone according to an embodiment of the present invention.

Explanation of symbols

1 ... System on chip (SOC),
2 Central processing unit (CPU),
3. Interrupt controller (INTC),
4 ... Power supply controller (PWRC),
4A: Power control register (PCTR),
5 ... Cache (CCH),
6, 7, 8 ... functional modules IP1 to IP3,
9 ... System bus,
10: Interrupt priority determination circuit (PRI-JDG),
11 ... Comparator (COMP) of interrupt signal and interrupt mask,
31 ... Block part,
32 ... glue logic part,
35 ... Source switch controller 36 ... Power switch for power shutdown,
38. Control unit,
39 ... Gate,
40 ... Micro IO,
42. Flip-flop for holding power mode,
50: Non-volatile FF controller,
81 ... Connection interface (I / F) with the baseband processor,
82 ... Peripheral interface (PPH),
83 ... Camera (CMR),
84 ... Memory card (CARD),
85 ... Sound source part (SOD),
86 ... Keyboard (KEY),
87 ... Liquid crystal display (LCD),
88, 91 ... Memory (MRYa), Memory (MRYb),
89 ... Baseband processor (BBP),
90 ... high frequency part (RF),
92 ... MPEG IP,
93 ... 3D graphics IP,
94 ... 2D graphics IP,
int1_r: interrupt IP1 request signal,
int1_a: interrupt IP1 acknowledge signal,
pwr1_r: power control IP1 request signal,
pwr1_a: power control IP1 acknowledge signal,
pwra1_r: power control area request signal,
pwra1_a: power control area acknowledge signal,
intmsk ... interrupt mask,
intreq-interrupt request to CPU,
cstp ... clock request signal,
Int-bus ... interrupt bus,
Pwr-bus: Power control bus.

Claims (10)

At least one functional block;
A power control register that holds information indicating a power supply state of the functional block; a power control circuit that controls power supply to or shuts off the functional block according to the information held in the power control register;
An interrupt control circuit for receiving an interrupt signal indicating the end of processing notified from the functional block;
A CPU for receiving an interrupt signal indicating the end of processing notified from the functional block via the interrupt control circuit ,
Based on the signal notified from the interrupt control circuit based on the interrupt signal, the power supply state held in the power control register is rewritten ,
The power control register has an address;
A semiconductor integrated circuit device in which the information value held in the power supply control register is rewritten from the CPU using an instruction designating the address .   2. The semiconductor integrated circuit device according to claim 1, wherein power is supplied to and cut off from the functional block according to an interrupt signal notified from the functional block. The functional block is
A block unit having a desired processing function, and a glue logic unit that performs connection between the functional block and the bus and power management of the functional block,
The semiconductor integrated circuit device according to claim 1 , wherein the glue logic unit includes a power control unit configured to shut off the power of the block unit. 4. The semiconductor integrated circuit device according to claim 3 , further comprising an interface circuit that prevents a through current flowing in a circuit connected to a circuit that is powered off when the power of the functional block is shut off . Before Symbol function block,
A block unit having a desired processing function, and a glue logic unit that performs connection between the functional block and the bus and power management of the functional block,
The glue logic unit, a semiconductor integrated circuit device according to claim 1, further comprising a flip-flop which holds information defining an operation mode of the functional blocks. The functional block is
A block unit having a desired processing function, and a glue logic unit that performs connection between the functional block and the bus and power management of the functional block,
The semiconductor integrated circuit device according to claim 1, wherein the block unit includes a configuration register that holds information defining an operation mode of the functional block. 7. The semiconductor integrated circuit device according to claim 5, further comprising a memory unit that stores information held in the configuration register when the function block is powered off . It said block portion, a semiconductor integrated circuit device according to claim 5 or claim 6 wherein has a flip-flop circuit. Before notated flip-flop circuit, the semiconductor integrated circuit device according to claim 8, wherein that consists in a nonvolatile flip-flop. Multiple functional blocks;
An interrupt bus for transmitting an identifier for each of the plurality of functional blocks and an interrupt signal indicating processing termination notified from the functional blocks;
An interrupt controller for performing priority determination of the interrupt signal;
A power supply control register indicating a supply state of power supplied to each functional block;
An identifier of the functional block and a power control bus for transmitting power control information;
Based on said interrupt signal, a semi-conductor integrated circuit device to rewrite the power control register.

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