JP4703131B2 - Active matrix display device - Google Patents

Description

  The present invention relates to an active matrix display device, for example, a display device using organic electroluminescence (hereinafter referred to as EL).

  In recent years, organic EL display devices have attracted attention. In organic EL display devices, organic light-emitting elements, which are self-luminous elements, are used in the pixel portion, and they are composed of a laminated structure of solid thin films, and light sources such as backlights and front lights are used like liquid crystal display devices. do not need. Therefore, the organic EL display device can be made thinner and lighter than the liquid crystal display device, and a display device with good impact resistance can be realized.

  The organic light emitting element is driven by a driving transistor of a pixel circuit, and a gate voltage corresponding to a video signal is applied to the gate electrode of the driving transistor. Accordingly, a stable current corresponding to the video signal is supplied from the driving transistor to the corresponding light emitting element, and the light emitting element emits light with a luminance corresponding to the video signal.

The gate voltage for the driving transistor is given by a voltage signal system or a current signal system. U.S. Pat. No. 6,229,506 B1 (Document 1) showing a voltage signal (or voltage writing) system, U.S. Pat. No. 6 showing a current signal (or current writing) system as a technology related to a pixel circuit of a light emitting element 373,454 B1 (Reference 2).
US Pat. No. 6,229,506 B1 US Pat. No. 6,373,454 B1 specification

  In the pixel circuit, a plurality of switch transistors are provided to apply a gate voltage to the gate electrode of the drive transistor. By turning on and off these switch transistors, the gate voltage is set for each frame, for example. The problem here is that the gate voltage, that is, the desired voltage corresponding to the video signal, is not always set accurately for the on / off operation of the switch transistor. One factor that has such an effect is the “penetration voltage” of the switch transistor that constitutes the pixel circuit. This punch-through voltage is affected by the response characteristics of the transistor. When the value of the gate voltage fluctuates, there is a problem that the output current amount of the driving transistor fluctuates, and the display element cannot be operated at a luminance corresponding to the video signal.

  By the way, the inventor has also paid attention to the following points as causes of luminance unevenness (display unevenness). That is, when a scanning signal is given from the driving circuit to the switch transistors in the pixel portion for one row, the scanning signal has different signal waveforms on the driving circuit output side, wiring center side, and wiring terminal side. This is due to an equivalent time constant circuit generated in the pixel portion. If the waveform of the scanning signal differs depending on the location on the screen, the value of the “penetration voltage” described above will differ on the screen, resulting in uneven brightness (display unevenness) on the entire screen. That is, the value of the “penetration voltage” is different on each of the drive circuit output side, the wiring center side, and the wiring end side, resulting in luminance unevenness (display unevenness).

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an active matrix type display device that suppresses the difference in the waveform of the scanning signal in each part of the scanning line and can obtain uniform luminance over the entire screen.

In order to achieve the above object, the present invention provides a display element that operates in accordance with a supply current amount, a drive transistor that supplies a drive current corresponding to an input signal supplied from a video input terminal to the display element, A capacitor having a terminal connected to the gate of the driving transistor and the other terminal connected to the source of the driving transistor, and capable of maintaining a potential difference between the source and the gate of the driving transistor corresponding to the input signal; A switch connected in series between the gate and drain of the transistor, a plurality of display pixels arranged in a matrix, and provided for each row of the display pixels, to the control terminal of the switch A plurality of scanning lines connected to each other, and an on-potential and an on-off so as to turn on and off the switch through the scanning lines A scanning line driving circuit for outputting a control signal having a potential, and a buffer circuit is provided between each scanning signal output portion of the scanning line driving circuit and a scanning line corresponding to the output portion. ,
The buffer circuit includes a p-channel and an n-channel transistor connected in series, a first constant current source connected to a source of the p-channel transistor, and a second constant current connected to a drain of the n-channel transistor. Each of the gates of the p-channel and n-channel transistors is connected to the output part of each scanning signal of the scanning line driving circuit, and the drain of the p-channel transistor and the n-channel transistor. The scanning line corresponding to the output unit is connected to the source of the signal, the transition time from the initial potential to the off potential when the signal waveform output from the buffer circuit shifts from on to off, and the end of the scanning line The waveform is shaped so that the transition time of the signal waveform on the side becomes substantially the same.

  According to the present invention, it is possible to output a scanning signal having a uniform waveform at each part of the scanning line, thereby realizing a good display.

  Hereinafter, an organic EL display device will be described as an embodiment of the present invention with reference to the drawings.

  FIG. 1 is a schematic view of an organic EL display device according to the present invention.

  The organic EL display device includes a pixel array region serving as a display portion, a scanning line driving circuit and a signal line driving circuit for driving the display portion, and a controller for driving these driving circuits.

  The pixel array region 110 is formed on a support substrate (not shown) made of a light transmissive insulating substrate such as glass. In the pixel array area 110, pixel portions Px (1,1), Px (2,1)..., Px (1,2),..., Px (n, m) are arranged in a matrix.

  A scanning line driving circuit 111 and a signal line driving circuit 112 are configured in the outer region of the pixel array region 110 on the support substrate. The scanning line driving circuit 111 includes a shift register and a buffer circuit, sequentially transfers a horizontal scanning start pulse supplied from the outside to the next stage, and outputs the output of each stage as a scanning signal to the corresponding scanning line via the buffer circuit. To do. Thereby, the pixel portions Px (1,1), Px (2,1)..., Px (1,2),..., Px (n, m) arranged in a matrix are scanned for each row. .., Px (1,2),..., Px (n, m) are set in a data receiving state and a data holding state. The signal line driver circuit 112 outputs a write signal to the signal lines Data1, Data2,.

  The controller 113 is formed on the drive circuit board separately from the support board, and includes data signals for obtaining operations of the signal line drive circuit 112 and the scanning line drive circuit 11, various timing signals (signal capture, signal output, etc.), And a clock signal is output.

  FIG. 2 shows the connection state of one scanning line Ysc. Here, when the scanning signal of the scanning line Ysc changes from the low level to the high level, the switch transistor (not shown) of the pixel portion shifts from on to off, and the pixel portion shifts from the data receiving state to the data holding state. It shall be.

  A buffer circuit 130 is provided at the final output stage of the scanning line driving circuit 111, and a scanning signal is output to the corresponding scanning line via the buffer circuit 130. The pixel array area 110 is a display area, and the scanning lines Ysc in this area are shown to be electrically equivalent. The scanning line Ysc can be regarded as a state in which a time constant circuit of a resistor and a capacitor is connected in series in the pixel array region 110. In the buffer circuit 130, for example, TFTs having different conductivity types, a p-channel TFT (thin film transistor) 131, and an n-channel TFT 132 are connected in series between a power supply Vdd and a reference potential (ground potential) as shown in FIG.

  As the output of the buffer circuit, when a signal having a rising waveform faster than the time constant of the wiring is supplied from the input unit 140 to the display unit, the waveforms on the drive circuit side, the wiring center side, and the wiring end side are as shown in FIG. (3A, 3B, 3C). In other words, the side close to the output of the drive circuit is a rectangular wave itself, but the center side of the wiring is affected by the time constant and rises and falls. Further, the rising and falling of the waveform are further greatly deformed at the end of the wiring farthest from the output of the drive circuit. When the switch transistors of the respective pixel portions arranged in the row direction with such a waveform are turned off, the values of the punch-through voltages in the respective pixel portions are different. This means that luminance unevenness occurs in the row direction.

  Therefore, the channel length and / or channel width of the buffer circuit of the present invention is adjusted so that the output waveform does not deform in each scanning line.

  FIG. 3 (3D, 3E, 3F) shows waveforms on the side closer to the output of the drive circuit, the center of the wiring, and the end of the wiring far from the output of the drive circuit when the output waveform is adjusted. Yes. As can be seen from this figure, in the present invention, the waveforms of the scanning signals on the drive circuit side, the wiring center side, and the wiring end side are set to be the same waveform. In other words, the output waveform of the buffer circuit 130 is designed to output a waveform whose rise time and fall time are larger than the time constant of the scanning line. Here, the rise time refers to the time until the scan waveform shifts from the lowest potential to the highest potential, and the fall time refers to the time until the scan waveform shifts from the highest potential to the lowest potential. As a result, the waveforms on the drive circuit side, the wiring center side, and the wiring end side are substantially the same. In particular, here, the rise times tu1 to tu3 when changing from the low level to the high level are made equal for each part of the scanning line (tu1 = tu2 = tu3), so that the amount of penetration voltage generated in each pixel part can be determined for each scanning. The pixel portions connected to the line can be made equal, and no large variation occurs. This means that luminance unevenness (display unevenness) due to the punch-through voltage does not occur. Here, the waveform of the scanning signal has the same waveform. Here, the waveform shaping of the scanning signal has been described using the highest potential and the lowest potential, but the signal waveform output from the buffer circuit 130 shifts from on to off. It is important that the transition time from the initial potential to the off potential at that time and the transition time of the signal waveform at the end of the scanning line are substantially the same, and the signal waveform shape when transitioning from the on state to the off state is It means that it becomes the same within the same scanning line. In the transition from OFF to ON, it is further desirable that the transition time from the initial potential to the ON potential is substantially the same between the buffer circuit output and the scanning line end side.

  The buffer circuit 130 is not limited to the above embodiment. In the above configuration, p-channel and n-channel transistors 131 and 132 are connected in series. In addition, as long as the switch transistor of the driver circuit in the pixel portion is turned off at the rising edge of the scanning signal, the drain of the p-channel transistor 131 may be directly connected to the reference potential. That is, the n-channel transistor 132 may be omitted.

  FIG. 4 shows still another embodiment of the buffer circuit 130. In the circuit according to this embodiment, the waveform of the previous scanning signal Ysc can be formed more accurately. The source of the p-channel transistor 131 is connected to the constant current line 141 via the constant current source 133. The drain of the n-channel transistor 132 is connected to the constant current line 142 via the constant current source 134. The constant current source 133 includes a p-channel transistor 135 whose source is connected to the power supply line Vdd. A capacitor 136 is connected between the gate and source of the transistor 135. The gate of the transistor 135 is connected to the constant current line 141 via the switch SW1, the switch SW2 is connected between the gate and the drain, and the drain is connected to the source of the transistor 131 via the switch SW3. The constant current source 134 includes an n-channel transistor 137 whose source is connected to a reference potential. A capacitor 138 is connected between the gate and source of the transistor 137. The gate of the transistor 137 is connected to the constant current line 142 via the switch SW4, the switch SW5 is connected between the gate and the source, and the source is connected to the drain of the transistor 132 via the switch SW6.

  In the invention described in this specification, various types of transistors can be employed. Therefore, the source / drain may be referred to as a first terminal / second terminal, and the gate may be referred to as a control terminal.

  FIG. 5 is a timing chart showing the operation of the buffer circuit 130 described above. 5A shows the input (1), and FIG. 5B shows the output (scanning signal Ysc). (C)-(E) in FIG. 5 show the state of each switch. FIG. 5F shows a signal waveform output from the buffer circuit 130. This waveform is the same on the drive circuit side, the wiring center side, and the wiring end side in the scanning line.

  The period T1 is a period (writing period or reset period) in which a predetermined voltage is accumulated in the capacitors 136 and 138 of the constant current sources 133 and 134 in order to operate the constant current sources 133 and 134 stably. In this period, first, the switches SW1, SW2, SW4, and SW5 are turned on, SW3 and SW6 are turned off, and then all the switches SW1 to SW6 are turned off. Subsequently, SW3 and SW6 are turned on to enter a standby state. Here, when the input (1) falls, the transistor 131 is turned on and the transistor 132 is turned off. From this time, a constant current from the constant current source 133 flows in the transistor 131, and a waveform is obtained in which the output rises at a constant slope from the low level to the high level.

  According to the buffer circuit 130, since the current flows with high accuracy by the constant current source, the variation in the column direction due to the transistor characteristics is reduced. That is, there is no variation in the output of the buffer circuit of each scanning line. Visually, streaky luminance unevenness due to gate lines (scanning lines) is reduced.

  In the present invention, the constant current lines 141 and 142 are connected to the constant current sources 143 and 144, respectively. The constant current lines 141 and 142 are commonly used in output buffer circuits for a plurality of corresponding scanning lines. For this reason, since the common constant current sources 143 and 144 are used for resetting the output buffer circuits of the plurality of scanning lines, there is no variation in reset conditions for the output buffer circuits of the respective scanning lines.

  FIG. 6 further shows another form of the buffer circuit 130 according to the present invention. The same parts as those of the circuit shown in FIG. In the circuit of FIG. 6, the drain connection point of the p-channel transistor 131 and the source connection point of the n-channel 132 are connected in series to the drain connection point of the p-channel transistor 151 and the source connection point of the n-channel transistor 152. The source of the p-channel transistor 151 is connected to the constant power supply line Vdd, and the drain of the n-channel transistor 152 is connected to the reference potential. The control inputs (2) and (3) are supplied to the gate electrodes of the transistors 151 and 152.

  FIG. 7 is a timing chart showing the operation of the buffer circuit 130 described above. 7A shows the input (1), and FIG. 7B shows the output (scanning signal Ysc). FIGS. 7C and 7D show the input (2) and the input (3). (E)-(G) in FIG. 7 show the state of each switch.

  The period T1 is a period (writing period or reset period) in which a predetermined voltage is accumulated in the capacitors 136 and 138 of the constant current sources 133 and 134 in order to operate the constant current sources 133 and 134 stably. In this period, first, the switches SW1, SW2, SW4, and SW5 are turned on, SW3 and SW6 are turned off, and then all the switches SW1 to SW6 are turned off. Subsequently, SW3 and SW6 are turned on to enter a standby state. Here, when the input (1) falls, the transistor 131 is turned on and the transistor 132 is turned off. At this time, the input (3) falls and the transistor 152 is turned off. From this time, a constant current from the constant current source 133 flows through the transistor 131, and the output (1) has a waveform that rises at a constant slope from the low level to the high level. When a desired time elapses, the input (2) falls and the transistor 151 is turned on. Then, the output is stably maintained at the voltage Vdd. In this way, the connection switch (p-channel transistor) is disconnected from the constant voltage source (Vdd, reference power supply) in the writing period (constant slope period) from the constant current sources 133 and 134 and connected to the constant voltage source after the constant slope period ends. 151 and the n-channel transistor 152) can prevent the output from being in a floating state.

  The buffer circuit 130 is not limited to the above embodiment. The above configuration is configured by combining p-channel and n-channel transistors. This circuit operated so that the rising and falling of the output changed with a constant slope. However, the circuit configuration on the p-channel transistor side is sufficient as long as the switch transistor of the pixel portion drive circuit is turned off at the rising edge of the scanning signal.

  In the above description, the relationship between the scanning line driving circuit and one scanning line to which an output (scanning signal) of the scanning line driving circuit is supplied via the buffer circuit has been described. However, in practice, since a large number of scanning lines are provided, a scanning signal for each scanning line is given through the buffer circuit described above.

  In FIG. 8, the pixel portion Px (1,1) in the pixel array region 110 shown in FIG. Each pixel unit includes a display element that operates according to the amount of supply current, a drive transistor 202 that supplies a drive current corresponding to an input signal supplied from a video input terminal to the display element, and one terminal of the drive transistor 202. A capacitor 204 connected to the gate electrode and capable of maintaining a potential difference between the source and gate electrode of the driving transistor 202 corresponding to the input signal, and a switch connected in series between the gate electrode and the drain electrode of the driving transistor 202 And a transistor 205. A power supply line 201 is supplied with a power supply voltage Vdd. A source electrode of the driving transistor 202 is connected to the power supply line 201. A capacitor 204 is connected between the source and gate electrodes of the driving transistor 202. A series circuit including first and second switch transistors 205 and 206 is connected between the gate and drain electrodes of the driving transistor 202. Further, a pixel switch 207 is connected between the drain electrode of the driving transistor 202 and the signal line (Data 1). The drain electrode of the driving transistor 202 is connected to a self-light emitting element, for example, an anode electrode of an organic light emitting element (OLED1) via a switch transistor (output transistor) 203, and the cathode of the organic light emitting element (OLED1) is a low power supply line. (Or earth line).

  The capacitor 204 between the gate and drain electrodes of the driving transistor 202 can hold a driving voltage. The pixel switch 207 is used for signal supply. The signal line (Data 1) is driven by the previous signal line driver circuit 112.

  Next, the first scanning line Ysc1 is connected to the gate electrode of the previous pixel switch 207, and the second and third scanning lines Ysc2 and Ysc3 are connected to the gate electrodes of the switch transistors 205 and 206, respectively. Yes. The fourth scanning line Ysc4 is connected to the gate electrode of the switch transistor 203. Corresponding scanning signals are given to the first to fourth scanning lines Ysc1 to Ysc4 from the previous scanning line driving circuit 111, respectively. In particular, as described with reference to FIGS. 2 to 7, in the apparatus of the present invention, the scanning signal Ysc2 is output via the buffer circuit 103-2.

  Although the pixel portion Px (1, 1) has been described as a representative, the configuration of the other pixel portions is the same. However, corresponding signal lines are connected according to the column in which the pixel portion is located. Further, the corresponding power supply line 201 and the first to fourth scanning lines Ysc1 to Ysc4 are connected according to the row where the pixel portion is located.

  FIG. 9 is a timing chart for explaining the operation of the pixel portion Px (1,1). The pixel portion Px (1, 1) having this configuration is a current signal method. Assume that the scanning signals of the scanning lines Ysc1, Ysc2, and Ysc3 are at the low level and the scanning signal of the scanning line Ysc4 is at the high level at the time t1 in FIG. At this time, the pixel switch 207 and the switch transistors 205 and 206 are on, and the output transistor 203 is off. At this time, the driving transistor 202 is in a diode connection state. During this period, that is, the period from the time point t1 to the time point t2, the potential of the gate electrode of the driving transistor 202 is displaced to a value corresponding to the video signal, and the capacitor 204 is responded to the video signal via the signal line (Data1). In this period, the gate-source potential of the driving transistor is written. During this period, charge corresponding to the video signal is accumulated in the capacitor 204 regardless of the characteristics of the driving transistor 202. That is, a signal for obtaining the luminance of the video signal (pixel portion Px (1, 1)) is supplied.

  Next, during the period from time t3 to time t4, the charge written in the capacitor 204 is stably held. After time t4, the pixel switch 207 is turned off and the switch transistor 203 is turned on. At this time, the driving transistor 202 and the capacitor 204 function as a stable current source, and a current is supplied to the organic light emitting element (OLED 1) to emit light. The amount of current (luminance) at this time depends on the electric charge charged in the capacitor 204 that sets the gate-source bias of the driving transistor 202.

  This circuit is characterized by the switch transistors 205 and 206 and their control methods. That is, as shown in FIG. 9, the switch transistor 205 is turned off from time t2 to time t3, and then the switch transistor 206 is turned off after time t3. For this purpose, the switch transistor 205 and 206 connected in series between the gate and drain of the drive transistor 202 is turned off earlier than the other switch transistors 206 by turning off the switch transistor 205 closest to the gate of the drive transistor. The amount of voltage generated can be reduced. As a result, it is possible to reduce undesired potential fluctuations of the driving transistor.

  In addition, since the gate control of the switch transistor 205 closest to the gate of the drive transistor is controlled using a scanning signal controlled so as to have a uniform waveform in the scanning line, the amount of punch-through voltage generated is made uniform in the screen. This makes it possible to obtain a uniform display image in which display unevenness is suppressed.

  Further, the area of the transistor 205 can be further reduced to further reduce the amount of penetration voltage generated. Furthermore, the switch transistor 205 may have a smaller channel area or a shorter channel length than the switch transistor 206. With such a configuration, the amount of potential fluctuation of the gate electrode of the driving transistor 202 can be further reduced, and luminance unevenness (display unevenness) as a display device can be reduced.

  In the above-described embodiment, the case where the pixel switch 207 and the switch transistor 206 are controlled using different scanning lines has been described. However, these scanning lines may be shared.

  The pixel portion has a current signal circuit configuration. However, the present invention is not limited to this circuit configuration, and may be a voltage signal type circuit configuration.

  FIG. 10 shows a circuit configuration of a voltage signal system. A source electrode of the driving transistor 212 is connected to the power supply line 201. A capacitor 214 is connected between the gate and source electrodes of the driving transistor 212. A series circuit of switch transistors 215 and 216 is connected between the gate and drain electrodes of the drive transistor 212. Further, the gate electrode of the driving transistor 212 is connected to the source electrode of the pixel switch 217 via the capacitor 218, and the drain electrode of the pixel switch 217 is connected to the signal line (Data1). The drain electrode of the drive transistor 212 is connected to the anode electrode of the organic light emitting device (OLED1) via the switch transistor (output transistor) 213, and the cathode electrode of the organic light emitting device (OLED1) is connected to the low power line (or ground). Line).

  The gate electrode of the pixel switch 217, the gate electrodes of the first and second switch transistors 215 and 216, and the gate electrode of the output transistor 213 are connected to the scanning lines Ysc1, Ysc2, Ysc3, and Ysc4, respectively.

  FIG. 11 is a timing chart showing the circuit operation of the pixel portion. In this circuit, the pixel switch 217 is an n-channel TFT (Thin Film Transistor).

  In the organic EL display device using the circuit of FIG. 10 (voltage signal method threshold cancellation type), when any pixel is brought into the display state, first, in the reset period, the output transistor is changed from the on state to the off state, and the subsequent Vth. In the cancel period, the output transistors 213 are turned off using the fourth scanning line Ysc4, the switch transistors 215, 216 are turned on using the second and third scanning lines Ysc2, 3, and the driving transistor 212 is turned on. Charge is supplied to the capacitors 214 and 218 until no current flows between the source and the drain of the capacitor. In this state, since the drain and gate of the drive transistor 212 are connected, the gate potential of the drive transistor 212 becomes the threshold value Vth of the drive transistor 212. During this period, the scanning signal is supplied from the scanning line driver circuit to the first scanning line Ysc1, the pixel switch 217 is turned on, and the reset signal Vrst is supplied from the signal line driver circuit to the signal line.

  After the above operation is completed, the switch transistors 215 and 216 are turned off in the writing period, and the video signal Vsig is supplied from the signal line driver circuit to the signal line. As a result, the gate potential of the drive transistor 212 varies from the threshold value Vth by an amount equal to the variable amount from Vrst to Vsig. In the light emission period subsequent to the writing period, the pixel switch is turned off and the output transistor is turned on. As a result, a drive current corresponding to the fluctuation amount is supplied from the power supply wiring 201 to the organic EL element OLED via the drive transistor 212 and the output transistor 213.

  As shown in FIGS. 10 to 11, a plurality of switch transistors are connected in series between the drain and gate of the drive transistor in the Vth cancellation period, and the switch transistor closest to the gate of the drive transistor is turned off first. It is possible to reduce the gate potential fluctuation of the driving transistor due to the punch-through voltage generated when the transistor is off. Further, by shaping the drive waveform for driving the switch transistor closest to the gate of the drive transistor to have the same waveform shape in each part in the same scanning line, the same effect as in the above-described embodiment can be obtained. Can do.

  As described above, the present invention can be applied to any type of current signal system and voltage signal system. Of course, the semiconductor element may be either a semiconductor element made of amorphous silicon or a semiconductor element made of polysilicon.

  The above-described circuit also employs the buffer circuit described above, and the wave of the scanning signal is the same on the drive circuit side, the wiring center side, and the wiring end side. In addition, a more stable operation can be obtained in combination with the operations of the transistors 205, 206, 215, and 216, and display unevenness can be reduced.

  The present invention is not limited to the above embodiment, and may be configured as shown in FIGS. The circuits in FIGS. 12 and 13 are circuits in which the switch transistors 206 and 216 and the scanning line Ysc3 are omitted compared to the circuits in FIGS. 8 and 10, respectively, and the other parts are the same as those in FIGS. It is the same as 10 circuits. Even in this circuit, the buffer circuit described above is employed, and the waveform of the scanning signal is the same on the drive circuit side, the wiring center side, and the wiring end side.

  In the above-described embodiment, the case where the scanning line driving circuit is arranged on one end side of each scanning line has been described. However, the scanning line driving circuit is arranged on both sides of each scanning line, and scanning signals are output from both sides. It may be a thing. In this case, the “driving circuit side” means the side close to the output of each scanning line driving circuit, and the “wiring end side” means a point equidistant from each scanning line driving circuit, that is, at the center of the scanning wiring. Correspondingly, the “wiring center side” corresponds to between the scanning line driving circuit and the central portion.

  As described above in detail, according to the present invention, it is possible to output a scanning signal having a uniform waveform at each part of the scanning line, and to realize a good display.

Explanatory drawing which shows schematic structure of the element array board | substrate of the active matrix type display apparatus which concerns on this invention. FIG. 2 is an explanatory diagram showing a relationship between a buffer circuit in the scanning line driving circuit of FIG. 1 and an equivalent circuit of a pixel array region. The timing chart shown in order to demonstrate operation | movement of the circuit of FIG. FIG. 3 is a circuit diagram showing another example of the buffer circuit of FIG. 2. 6 is a timing chart shown for explaining the operation of the circuit of FIG. FIG. 4 is a circuit diagram showing still another example of the buffer circuit of FIG. 2. 7 is a timing chart shown for explaining the operation of the circuit of FIG. 6. The figure which shows the specific circuit example of the pixel part by which the circuit which concerns on this invention was employ | adopted. 9 is a timing chart shown for explaining the operation of the circuit of FIG. 8. The figure which shows the other example of the specific circuit of the pixel part by which the circuit based on this invention was employ | adopted. 11 is a timing chart shown for explaining the operation of the circuit of FIG. The figure which shows the further another example of the specific circuit of the pixel part by which the circuit which concerns on this invention was employ | adopted. The figure which shows the further another example of the specific circuit of the pixel part by which the circuit based on this invention was employ | adopted.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 110 ... Pixel arrangement area, 111 ... Scan line drive circuit, 112 ... Signal line drive circuit, 130 ... Buffer circuit, 201 ... Power supply line, 202 ... Drive transistor, 203, 205, 206 ... Switch transistor, 204 ... Capacitor, 207 ... Pixel switch, OLED1... Organic light emitting element.

Claims (4)

A display element that operates in accordance with the amount of supply current; a drive transistor that supplies a drive current corresponding to an input signal supplied from a video input terminal to the display element; and one terminal connected to the gate of the drive transistor, the other A capacitor connected to the source of the driving transistor and capable of maintaining a potential difference between the source and the gate of the driving transistor corresponding to the input signal, and a series connection between the gate and the drain of the driving transistor. A plurality of display pixels arranged in a matrix, each comprising a switch connected to
A plurality of scanning lines provided for each row of the display pixels and connected to a control terminal of the switch;
A scanning line driving circuit that outputs a control signal having an on-potential and an off-potential so as to control on and off of the switch through the scanning line;
A buffer circuit is provided between each scanning signal output unit of the scanning line driving circuit and a scanning line corresponding to the output unit,
The buffer circuit includes a p-channel and an n-channel transistor connected in series, a first constant current source connected to a source of the p-channel transistor, and a second constant current connected to a drain of the n-channel transistor. Each of the gates of the p-channel and n-channel transistors is connected to the output part of each scanning signal of the scanning line driving circuit, and the drain of the p-channel transistor and the n-channel transistor. A scanning line corresponding to the output unit is connected to the source of
The waveform so that the transition time from the initial potential to the off potential when the signal waveform output from the buffer circuit shifts from on to off is substantially the same as the transition time of the signal waveform at the end of the scanning line. An active matrix display device characterized by shaping. A pixel array region formed by intersecting a plurality of scanning lines and a plurality of signal lines;
Pixel portions formed respectively in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines;
A scanning line driving circuit that is connected to the plurality of scanning lines in a region outside the pixel array region and is configured to sequentially apply a scanning signal in a row direction to the plurality of pixel portions;
A signal line drive circuit connected to the plurality of signal lines and formed to supply a signal to each column of the plurality of pixel portions in a region outside the pixel array region;
A buffer circuit is provided between each scanning signal output unit of the scanning line driving circuit and a scanning line corresponding to the output unit,
The buffer circuit includes a p-channel and an n-channel transistor connected in series, a first constant current source connected to a source of the p-channel transistor, and a second constant current connected to a drain of the n-channel transistor. Each of the gates of the p-channel and n-channel transistors is connected to the output part of each scanning signal of the scanning line driving circuit, and the drain of the p-channel transistor and the n-channel transistor. A scanning line corresponding to the output unit is connected to the source of
The rise or fall time of the scanning signal waveform output from at least one of the buffer circuits is a signal affected by the time constant that appears on the end side of the scanning line when a rectangular wave signal is applied to the corresponding scanning line. An active matrix display device, wherein the buffer circuit is designed to have a time substantially equal to or longer than a waveform rise or fall time. A pixel array region formed by intersecting a plurality of scanning lines and a plurality of signal lines;
A pixel portion formed in the vicinity of an intersection of the plurality of scanning lines and the plurality of signal lines, each having a driving transistor having a source electrode connected to a power supply line and one electrode connected to a gate of the driving transistor The first switch transistor connected in series between the storage capacitor having the other electrode connected to the source and the gate / drain electrode of the drive transistor and being close to the gate electrode of the drive transistor by a different gate signal is the second switch transistor. The first and second switch transistors configured to be turned off earlier than the switch transistor of the first and second transistors are connected between the drain electrode of the drive transistor and the signal line, and the signal line is connected to the gate electrode of the drive transistor. A pixel switch for supplying a signal from the pixel and a drain electrode of the driving transistor are connected to a third switch. A pixel portion having a connected light emitting element through the pitch transistors,
A scanning line driving circuit that is connected to the plurality of scanning lines in a region outside the pixel array region and is configured to sequentially apply a scanning signal in a row direction to the plurality of pixel portions;
A signal line driver circuit connected to the plurality of signal lines and configured to supply a signal to each column of the plurality of pixel portions in a region outside the pixel array region;
A buffer circuit provided between each scanning signal output unit of the scanning line driving circuit and a scanning line corresponding to the output unit;
The buffer circuit includes a p-channel and an n-channel transistor connected in series, a first constant current source connected to a source of the p-channel transistor, and a second constant current connected to a drain of the n-channel transistor. Each of the gates of the p-channel and n-channel transistors is connected to the output part of each scanning signal of the scanning line driving circuit, and the drain of the p-channel transistor and the n-channel transistor. A scanning line corresponding to the output unit is connected to the source of
In the buffer circuit, the rise or fall time of the scanning signal waveform output from the buffer circuit is affected by the time constant appearing on the end side of the scanning line when a rectangular wave signal is applied to the corresponding scanning line. An active matrix display device configured to have a time substantially equal to or longer than the rise or fall time of the signal waveform . A pixel array region formed by intersecting a plurality of scanning lines and a plurality of signal lines;
A pixel portion formed in the vicinity of an intersection of the plurality of scanning lines and the plurality of signal lines, the driving transistor having a source connected to a power supply line and connected between a gate and a source electrode of the driving transistor; The first switch transistor close to the gate electrode of the drive transistor is turned off earlier than the second switch transistor by a different gate signal connected in series between the storage capacitor and the gate / drain electrode of the drive transistor. The at least first and second switch transistors, the pixel switch connected between the drain electrode of the drive transistor and the signal line, and the drain electrode of the drive transistor are connected via the third switch transistor. Light emitting element, the pixel switch, the first, second and third switches First, second, third and fourth scanning lines for independently turning on and off the transistors;
A scanning line driving circuit that is connected to the plurality of scanning lines in a region outside the pixel array region and is configured to sequentially apply a scanning signal in a row direction to the plurality of pixel portions;
A signal line driver circuit connected to the plurality of signal lines and configured to supply a signal to each column of the plurality of pixel portions in a region outside the pixel array region;
A buffer circuit provided between each scanning signal output unit of the scanning line driving circuit and a scanning line corresponding to the output unit;
The buffer circuit includes a p-channel and an n-channel transistor connected in series, a first constant current source connected to a source of the p-channel transistor, and a second constant current connected to a drain of the n-channel transistor. Each of the gates of the p-channel and n-channel transistors is connected to the output part of each scanning signal of the scanning line driving circuit, and the drain of the p-channel transistor and the n-channel transistor. A scanning line corresponding to the output unit is connected to the source of
In the buffer circuit, the rise or fall time of the scanning signal waveform output from the buffer circuit is affected by the time constant appearing on the end side of the scanning line when a rectangular wave signal is applied to the corresponding scanning line. An active matrix display device configured to have a time substantially equal to or longer than the rise or fall time of the signal waveform .

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