JP4799965B2 - Heterostructure field effect transistor using nitride semiconductor - Google Patents

Description

  The present invention relates to a heterostructure field effect transistor using a nitride semiconductor.

  Heterostructure field effect transistors (HFETs) using nitride semiconductors are very promising as next-generation high-frequency, high-output, and high-voltage ultrahigh-frequency transistors, and are being put to practical use. Currently, research is actively conducted.

  As a feature of the element structure that is usually employed in GaN-based HFETs using GaN, which is a nitride semiconductor, an insulating film is deposited on the element surface as a surface passivation film (surface protective film). Can be mentioned. The purpose of GaN-based HFETs is to apply an undesirable phenomenon called current collapse (such as an increase in drain voltage or a negative increase in gate voltage) when the device is operated with the device surface exposed to the atmosphere. This is because a phenomenon in which the drain current decreases due to the history occurs), and this phenomenon is reduced or suppressed by the surface passivation film.

Currently, a SiN insulating film (Si ₃ N ₄ is a typical example) capable of forming a high-quality interface with a GaN-based material is usually used as a surface passivation film. A surface passivation film is formed by depositing Si ₃ N _{4 of} about 200 nm on the element surface (see Non-Patent Document 1 below).

Bruce M. Green, et al., IEEE Electron Device Lett., Vol. 21, pp.267-270, June 2000.

  By the way, in order to further improve the device characteristics of the HFET, the channel resistance under the source-gate electrode region and the gate-drain electrode region (hereinafter simply referred to as “interelectrode region”) may be reduced. It is valid. This is particularly important in an HFET designed for high output and high withstand voltage or designed for switching and having a large distance between the source and gate electrodes and a large distance between the gate and drain electrodes. Further, in the future, even when the film thickness of the barrier layer of the HFET (AlGaN layer in the AlGaN / GaN HFET) is reduced for the purpose of obtaining a higher gain, the channel resistance under the inter-electrode region generally increases and the gain increases. Since this is an obstacle, it is very important to reduce the resistance.

  Thus, obtaining a low channel resistance under the inter-electrode region is very important for improving the device characteristics of the GaN-based HFET in the future. Here, since the above-described surface passivation film is usually deposited in the inter-electrode region, it is eventually possible to use an insulating film that can obtain a lower channel resistance as a result of the deposition as the surface passivation film, thereby improving the device characteristics. It is important to make it.

  However, at present, as a surface passivation film, a SiN-based insulating film having a good current collapse suppressing effect is usually used because a high-quality interface can be formed with a GaN-based material. No surface passivation film has been developed from the viewpoint of further reducing the resistance, and there is no guideline for that purpose.

  In such a state of the art, the development of a passivation film that further reduces the channel resistance under the deposition region is an extremely innovative attempt, and is extremely important for further improvement of device characteristics in the future.

  The present invention has been made in connection with the above attempt, and the problem to be solved by the present invention is to provide a heterostructure field effect transistor using a nitride semiconductor having a surface passivation film that greatly reduces channel resistance. Is to provide.

In order to solve the above problems, in the present invention, as described in claim 1,
In a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on a barrier layer, a region between the source electrode and the gate electrode, the gate electrode, and the source electrode An Si ₃ N ₄ film and an Al ₂ O ₃ film are deposited in this order on the barrier layer in the region between and the thickness of the Si ₃ N ₄ film is 0.28 nm or more and 4 nm or less. The film thickness of the Al ₂ O ₃ film is 4 nm or more and 200 nm or less, and the total film thickness of the Si ₃ N ₄ film and the Al ₂ O ₃ film is 8 nm or more and 200 nm or less. A heterostructure field effect transistor using a nitride semiconductor is formed.

In the present invention, as described in claim 2,
In a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on a barrier layer, a region between the source electrode and the gate electrode, the gate electrode, and the source electrode _{the Si} 3 _{N 4} film on the barrier layer in a region between, AlN film is deposited in this order, wherein _{the Si} 3 _{N 4} film of thickness 0.28nm or more and 4nm or less, the AlN A heterostructure using a nitride semiconductor, wherein a film thickness is 4 nm or more and 200 nm or less, and a total film thickness of the Si ₃ N ₄ film and the AlN film is 8 nm or more and 200 nm or less A field effect transistor is formed.

In the present invention, as described in claim 3,
In a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on a barrier layer, a region between the source electrode and the gate electrode, the gate electrode, and the source electrode _{the Si} 3 _{N 4} film on the barrier layer in a region between, SiO ₂ film is deposited in this order, wherein _{the Si} 3 _{N 4} film of thickness 2nm or more and 4nm or less, the SiO ₂ The thickness of the film is 4 nm or more and 200 nm or less, and the total film thickness of the Si ₃ N ₄ film and the AlO ₂ film is 8 nm or more and 200 nm or less. A structure field effect transistor is constructed.

In a GaN-based HFET, a thin Si ₃ N ₄ film is deposited in the source-gate region and the gate-drain region, and an Al ₂ O ₃ film, AlN film, or SiO ₂ film is further deposited thereon. By using the insulating film structure thus formed as a surface passivation film, it is possible to provide a heterostructure field effect transistor using a nitride semiconductor having a surface passivation film that greatly reduces channel resistance.

  Hereinafter, the best mode for carrying out the present invention will be described for a GaN-based HFET as an example of a heterostructure field effect transistor using a nitride semiconductor.

A feature of the present invention is that, for example, in a GaN-based HFET, a thin Si ₃ N ₄ film is deposited in the source-gate region and the gate-drain region on the surface of the HFET, and the Si ₃ N ₄ film is formed thereon. _Use of an insulating film structure in which an Al ₂ O ₃ film, an AlN film, or an SiO ₂ film, which is an insulating film having a larger band gap than a ₃ N ₄ film, is deposited as a surface passivation film It is.

  The effect | action by this invention is demonstrated using figures.

FIG. 5 schematically shows an element structure of a standard GaN-based HFET (AlGaN / GaN HFET) on which a conventional surface passivation film is deposited. A two-dimensional electron gas exists in the GaN layer 2 near the AlGaN / GaN heterointerface 1 to form a channel. On the AlGaN barrier layer 3, a source electrode 4, a gate electrode 5, and a drain electrode 6 are formed. Has been. Further, in the source-gate region 7 and the gate-drain region 8 (both are collectively referred to as inter-electrode regions 7, 8), Si ₃ N is used as a conventional surface passivation film on the AlGaN barrier layer 3. _Four films are deposited. Since a good interface can be formed between Si ₃ N ₄ and AlGaN, current collapse is reduced / suppressed by surface passivation with the Si ₃ N ₄ film.

  In FIG. 5, the intrinsic region of the transistor is the region under the gate electrode 5, and the intrinsic characteristics of the HFET are determined by the characteristics of this region. However, in order to improve the actual device characteristics, the interelectrode regions 7, 8 ( In particular, it is effective to reduce the channel resistance under the source-gate electrode region 7).

  FIG. 6 shows an AlGaN / GaN HFET under the interelectrode regions 7 and 8 when the surface passivation film is not deposited in the interelectrode regions 7 and 8 (that is, when the AlGaN surface is exposed to the atmosphere). The potential shape is schematically shown along with the state of accumulation of two-dimensional electrons at the AlGaN / GaN heterointerface 1.

FIG. 7 shows an AlGaN / GaN HFET under the inter-electrode regions 7 and 8 when a Si ₃ N ₄ film is deposited as a surface passivation film in the inter-electrode regions 7 and 8 (in the case of FIG. 5). The potential shape is schematically shown along with the state of accumulation of two-dimensional electrons at the AlGaN / GaN heterointerface 1.

  The difference in the two-dimensional electron concentration in FIGS. 6 and 7 will be described below.

In FIG. 7, the position of the potential at the bottom of the conduction band between AlGaN and Si ₃ N ₄ is generally different (ie, there is a potential step), and the most commonly used Al _X Ga _1-X N / GaN (X = In the 0.2 to 0.4) HFET, as shown in FIG. 7, the potential position of Si ₃ N ₄ is higher than that of AlGaN. This is because in Al _X Ga _1-X N / GaN (X = 0.2 to 0.4) HFET, Si ₃ N ₄ has a larger band gap than AlGaN. The relative position of the lower end of the conduction band of the GaN layer 2 at the AlGaN / GaN heterointerface 1 of 7 with respect to the Fermi level is generally lower than that in FIG. As a result, in FIG. 7, a two-dimensional electron gas with a higher concentration accumulates than in the case of FIG. That is, the two-dimensional electron concentration in FIG. 7 is higher than in the case of FIG. As the two-dimensional electron concentration increases, the two-dimensional electron mobility generally decreases, but the effect of increasing the electron concentration is generally larger than the effect of decreasing the electron mobility (the ratio of the effects is not necessarily universal). As the two-dimensional electron concentration increases, the channel resistance (inversely proportional to the product of electron concentration and mobility) decreases. As a result, the channel resistance is lower in the case of FIG. 7 than in the case of FIG. That is, since the Si ₃ N ₄ film is deposited as the surface passivation film in the inter-electrode regions 7 and 8, the channel resistance under the inter-electrode regions 7 and 8 is reduced.

FIG. 1 schematically shows a device structure of a GaN-based HFET (AlGaN / GaN HFET) on which a surface passivation film is deposited as an example of a device structure of a heterostructure field effect transistor using a nitride semiconductor according to the present invention. It is shown. In FIG. 1, a source electrode 4, a gate electrode 5, and a drain electrode 6 are formed on an AlGaN barrier layer 3, a source / drain region 7 that is a region between the source electrode 4 and the gate electrode 5, and a gate electrode 5 a thin _{the Si} 3 _{N 4} film on the AlGaN barrier layer 3 is deposited on the gate-drain region 8 Prefecture is a region between the drain electrode 6, thereon, _Si 3 _{N 4} larger band than the membrane An Al ₂ O ₃ film, an AlN film, or a SiO ₂ film, which is an insulating film having a gap, is deposited. The surface passivation film having such a feature is the surface passivation film structure of the HFET according to the present invention.

In FIG. 1, by depositing a thin Si ₃ N ₄ film, a good semiconductor / insulating film heterointerface having a low interface state density can be formed between the Si ₃ N ₄ film and the AlGaN barrier layer 3. As a result, even if the insulating film occupying the main film thickness is an Al ₂ O ₃ film, an AlN film, or a SiO ₂ film, a good semiconductor / insulating film heterointerface can be formed as the entire surface passivation film structure. In other words, the current passivation is reduced and suppressed by the surface passivation film of the HFET according to the present invention, as in the case of the surface passivation film by the conventional Si ₃ N ₄ film.

FIG. 2 shows the surface passivation film of the HFET according to the present invention in the inter-electrode regions 7 and 8 (referred to as the source-gate region 7 and the gate-drain region 8 together) in the AlGaN / GaN HFET. Schematically shows the potential shape under the inter-electrode regions 7 and 8 together with the state of the accumulation of two-dimensional electrons at the AlGaN / GaN heterointerface 1 (channel) in the case where is deposited (in the case of FIG. 1). It is. Comparing FIG. 2 to FIG. 7 in which a conventional surface passivation film is used, in FIG. 2, the relative position of the lower end of the conduction band of the GaN layer 2 at the AlGaN / GaN heterointerface 1 with respect to the Fermi level is Compared to the case of FIG. 7, the position is lower, and as a result, the two-dimensional electron concentration is higher in FIG. This is because an Al ₂ O ₃ film, which is an insulating film occupying the main film thickness in the surface passivation film of the HFET according to the present invention, and an AlN film, as compared with the Si ₃ N ₄ film (FIG. 7) which is a conventional surface passivation film. This is because the film or the SiO ₂ film has a larger band gap. Therefore, in FIG. 2, the effect of lowering the relative position of the conduction band lower end of the GaN layer 2 at the AlGaN / GaN heterointerface 1 with respect to the Fermi level is deposited on the Si ₃ N ₄ film. The larger the band gap of the insulating film is, the larger the two-dimensional electron concentration and the lower the channel resistance. The values of band gaps (band gap energy) of insulating films or semiconductor films related to the HFET according to the present invention, that is, SiO ₂ film, Al ₂ O ₃ film, AlN film, Si ₃ N ₄ film, and GaN film are shown in FIG. 3 shows.

As described above, in the GaN-based HFET, in the source-gate region 7 and the gate-drain region 8 on the surface of the HFET,
(I) Since a thin Si ₃ N ₄ film is deposited, it is possible to form a favorable semiconductor (AlGaN) / insulator (Si ₃ N ₄ ) interface. As a result, current collapse is reduced and suppressed, and On the thin Si ₃ N ₄ film,
(Ii) As a result of increasing the two-dimensional electron concentration by depositing the Al ₂ O ₃ film, the AlN film, or the SiO ₂ film, which is an insulating film having a larger band gap than the Si ₃ N ₄ film, Channel resistance is reduced. Thus, the surface passivation film in the GaN-based HFET according to the present invention schematically shown in FIG. 1 provides a surface passivation film that can further reduce the channel resistance under the deposition region by the deposition. . As described above, all the effects of the present invention are shown.

[Embodiment 1]
In FIG. 1, a Si ₃ N ₄ film and an Al ₂ O ₃ film are deposited in this order in the source-gate region 7 and the gate-drain region 8 on the surface of the HFET. A surface passivation film structure was formed. Here, the thickness of the Si ₃ N ₄ film is 0.28 nm (0.5 atomic layer) or more and 4 nm or less, the thickness of the Al ₂ O ₃ film is 4 nm or more and 200 nm or less, the Si ₃ N ₄ film and the Al ₂ The total film thickness of the O ₃ film was 8 nm or more and 200 nm or less. Such a surface passivation film can be deposited by plasma sputtering or other methods.

  In general, in a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on the barrier layer, and the surface passivation film having the above characteristics including the film thickness value Is formed on the barrier layer, the effect of the present invention appears.

FIG. 4 schematically shows the dependency of the channel resistance change due to the deposition of the surface passivation film on the insulating film thickness. The Si ₃ N ₄ / Al ₂ O ₃ film of the HFET according to the present invention is a conventional type. This is shown together with the case of the Si ₃ N ₄ film of HFET. The vertical axis in the figure shows the channel resistance ratio, that is, the value obtained by dividing the channel resistance in the presence of the surface passivation film by the channel resistance in the absence of the surface passivation film, and the horizontal axis represents the insulation film thickness, that is, the surface passivation. The thickness of the entire film is shown. The insulating film thickness dependency when the surface passivation film is a Si ₃ N ₄ film is represented by a dotted line, and the insulating film thickness dependency when the surface passivation film is a laminated film of Si ₃ N ₄ and Al ₂ O ₃ Is represented by a solid line.

In any of the passivation films, the channel resistance decreases as the film thickness increases and is almost saturated at a film thickness of about 8 to 10 nm, but the Si ₃ N ₄ / Al ₂ O ₃ film is more Si ₃ N ₄ film. It is shown that the channel resistance is further reduced than in the case of. (Quantitatively, the channel resistance reduction rate depends on details such as the layer structure of the HFET and the deposition method of the passivation film.)
In FIG. 4, the total film thickness of the Si ₃ N ₄ film and the Al ₂ O ₃ film is 8 nm or more, which is a film thickness (channel resistance saturation minimum film thickness) that approaches 80% or more of the saturation value at which the channel resistance is reduced. Although necessary, a film thickness exceeding 200 nm is not necessary from the viewpoint of protecting the element against the air and moisture. In addition, a good semiconductor / insulator (Si ₃ N ₄ ) is formed between the Si ₃ N ₄ / Al ₂ O ₃ film (laminated film of Si ₃ N ₄ and Al ₂ O ₃ ) and the semiconductor layer immediately below the Si ₃ N ₄ / Al ₂ O ₃ film. In order to enable the formation of the interface, the film thickness of the Si ₃ N ₄ film needs to be 0.28 nm (0.5 atomic layer) or more. On the other _{hand, Si} 3 _{N 4} film in _{Si 3 N 4 / Al 2 O} 3 film is, half of 8nm which is the channel resistance saturated minimum thickness, i.e. greater than 4 nm, _Al 2 _{O 3} film deposited effect (channel Therefore, the thickness of the Si ₃ N ₄ film needs to be 4 nm or less. Conversely, in order to effectively obtain the effect of depositing the Al ₂ O ₃ film (the effect of reducing the channel resistance) in the Si ₃ N ₄ / Al ₂ O ₃ film, the Al ₂ O ₃ film has a minimum channel resistance saturation. It is necessary that the thickness is 1/2 of 8 nm, that is, 4 nm or more. Thus, as a request for the Si ₃ N ₄ / Al ₂ O ₃ surface passivation film, the thickness of the Si ₃ N ₄ film is 0.28 nm (0.5 atomic layer) to 4 nm, and the Al ₂ O ₃ film The film thickness is required to be 4 nm or more and 200 nm or less, and the total film thickness of the Si ₃ N ₄ film and the Al ₂ O ₃ film is required to be 8 nm or more and 200 nm or less.

As an example of this embodiment, a 1 nm Si ₃ N ₄ film and a 20 nm Al ₂ O ₃ film are deposited in this order on an Al _0.3 Ga _0.7 N / GaN HFET designed for high output high frequency. When the insulating film structure used was used as a surface passivation film, the channel resistance under the surface passivation film was reduced by 25% compared to the case of using a surface passivation film having a conventional structure (100 nm Si ₃ N ₄ film), As a result, the source resistance was reduced by 20%.

Further, as a secondary effect according to the present embodiment, as a result of the Al ₂ O ₃ film having a higher withstand voltage than the Si ₃ N ₄ film having the conventional structure, the drain withstand voltage is 30 as compared with the conventional structure. % Increase.

[Embodiment 2]
In FIG. 1, a surface passivation is characterized in that a Si ₃ N ₄ film and an AlN film are deposited in this order in the source-gate region 7 and the gate-drain region 8 on the surface of the HFET. A film structure was formed. Here, the film thickness of the Si ₃ N ₄ film is 0.28 nm (0.5 atomic layer) or more and 4 nm or less, the film thickness of the AlN film is 4 nm or more and 200 nm or less, and the total film of the Si ₃ N ₄ film and the AlN film The thickness was 8 nm or more and 200 nm or less. Such a surface passivation film can be deposited by plasma sputtering or other methods. The basis for the request for the insulating film thickness in the present embodiment is exactly the same as in the first embodiment.

  In general, in a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on the barrier layer, and the surface passivation film having the above characteristics including the film thickness value Is formed on the barrier layer, the effect of the present invention appears.

Compared to the first embodiment, the band gap of the AlN film, which is the main insulating film, is smaller than that of the Al ₂ O ₃ film (see FIG. 3). This embodiment has the disadvantage that it is smaller than the first embodiment. However, according to the present embodiment, the control of the deposition conditions necessary for the deposition of a good quality AlN film is generally easier than the control of the deposition conditions necessary for the deposition of a good quality Al ₂ O ₃ film. Has advantages in film deposition.

As an example of this embodiment, an insulating film in which a 1 nm Si ₃ N ₄ film and a 20 nm AlN film are deposited in this order on an Al _0.3 Ga _0.7 N / GaN HFET designed for high output high frequency. When the structure is used as a surface passivation film, the channel resistance under the surface passivation film is reduced by 20% compared to the case where a surface passivation film having a conventional structure (100 nm Si ₃ N ₄ film) is used. The source resistance was reduced by 15%. Further, as a secondary effect of the present embodiment, the AlN film has a higher withstand voltage than the Si ₃ N ₄ film having the conventional structure, and as a result, the drain withstand voltage is increased by 30% compared to the conventional structure. .

[Embodiment 3]
In FIG. 1, a surface passivation film characterized in that a Si ₃ N ₄ film and a SiO ₂ film are deposited in this order in the source-gate region and the gate-drain region on the surface of the HFET. A structure was formed. Here, the film thickness of the Si ₃ N ₄ film is 2 nm to 4 nm, the film thickness of the SiO ₂ film is 4 nm to 200 nm, and the total film thickness of the Si ₃ N ₄ film and the SiO ₂ film is 8 nm to 200 nm. It was. Such a surface passivation film can be deposited by plasma sputtering or other methods.

  In general, in a heterostructure field effect transistor using a nitride semiconductor, a source electrode, a gate electrode, and a drain electrode are formed on the barrier layer, and the surface passivation film having the above characteristics including the film thickness value Is formed on the barrier layer, the effect of the present invention appears.

The only difference from Embodiment 1 and Embodiment 2 in the request for the insulating film thickness in this embodiment is that the film thickness of the Si ₃ N ₄ film is 2 nm or more. This is because when the film thickness of the Si ₃ N ₄ film is less than 2 nm, oxygen (O) atoms from the SiO ₂ film pass through the Si ₃ N ₄ film and diffuse into the semiconductor layer in the device fabrication process. As a result, the channel resistance increases due to a decrease in electron mobility, which is a condition for preventing this. Thus, by setting the film thickness of the Si ₃ N ₄ film to 2 nm or more, the diffusion / mixing of the oxygen atoms into the semiconductor layer is reduced / suppressed, and the first embodiment and the second embodiment are described. As in the case of the present embodiment, the effect of reducing the channel resistance is obtained.

Compared with the first embodiment and the second embodiment, the effect of reducing the channel resistance is approximately the same as that of the second embodiment (thus slightly smaller than the first embodiment). This is because the SiO ₂ film that is the main insulating film has an advantage that the band gap of the Al ₂ O ₃ film and the AlN film is larger (see FIG. 3) (thus, a higher electron concentration can be obtained). This is a result of offsetting the disadvantage that the electron mobility decreases due to the expansion and mixing of oxygen (O) atoms. In the present embodiment, the SiO ₂ film, which is the most common insulating film in the semiconductor industry, is used as the main insulating film. Therefore, the deposition conditions of the insulating film can be further controlled as compared with the second embodiment. It has the advantage of insulating film deposition that it becomes easy.

As an example of this embodiment, a 2 nm Si ₃ N ₄ film and a 20 nm SiO ₂ film are deposited in this order on an Al _0.3 Ga _0.7 N / GaN HFET designed for high output high frequency. When the film structure is used as a surface passivation film, the channel resistance under the surface passivation film is reduced by 20% compared to the case where a surface passivation film having a conventional structure (100 nm Si ₃ N ₄ film) is used. The source resistance was reduced by 15%. Further, as a secondary effect of the present embodiment, as a result of the SiO ₂ film having a higher withstand voltage than the Si ₃ N ₄ film having the conventional structure, the drain withstand voltage is increased by 30% compared to the conventional structure. did.

As described above, the surface resistance film of the HFET according to the present invention can further reduce the channel resistance under the deposition region by the deposition. Further, as a secondary effect of the present invention, the Al ₂ O ₃ film, the AlN film, or the SiO ₂ film has a higher withstand voltage than the conventional Si ₃ N ₄ film. Increased compared to

It is the figure which showed typically the element structure of GaN-type HFET (AlGaN / GaN HFET) with which the surface passivation film based on this invention is deposited. In the AlGaN / GaN HFET, when the surface passivation film of the HFET according to the present invention is deposited in the inter-electrode region (in the case of FIG. 1), the potential shape under the inter-electrode region is expressed in two dimensions at the AlGaN / GaN heterointerface. It is the figure typically shown with the mode of accumulation | storage of an electron. It is a figure which shows the value of the band gap of the insulating film or semiconductor film relevant to HFET which concerns on this invention. It is the figure which showed typically the insulation film thickness dependence of the change of the channel resistance by deposition of a surface passivation film. It is the figure which showed typically the element structure of standard GaN-type HFET (AlGaN / GaN HFET) with which the conventional surface passivation film was deposited. In the AlGaN / GaN HFET, the potential shape under the interelectrode region when no surface passivation film is deposited in the interelectrode region is schematically shown along with the state of accumulation of two-dimensional electrons at the AlGaN / GaN heterointerface. FIG. In the AlGaN / GaN HFET, the potential shape under the interelectrode region when a Si ₃ N ₄ film is deposited as a surface passivation film in the interelectrode region (in the case of FIG. 5) is expressed as a two-dimensional shape at the AlGaN / GaN heterointerface. It is the figure typically shown with the mode of accumulation | storage of an electron.

Explanation of symbols

  1: AlGaN / GaN heterointerface, 2: GaN layer, 3: AlGaN barrier layer, 4: source electrode, 5: gate electrode, 6: drain electrode, 7: source-gate region, 8: gate-drain region.

Claims (3)

In a heterostructure field effect transistor using a nitride semiconductor,
A source electrode, a gate electrode and a drain electrode are formed on the barrier layer;
A Si ₃ N ₄ film and an Al ₂ O ₃ film are deposited in this order on the barrier layer in the region between the source electrode and the gate electrode and in the region between the gate electrode and the source electrode. And
The film thickness of the Si ₃ N ₄ film is 0.28 nm or more and 4 nm or less,
The film thickness of the Al ₂ O ₃ film is 4 nm or more and 200 nm or less,
A heterostructure field effect transistor using a nitride semiconductor, wherein a total film thickness of the Si ₃ N ₄ film and the Al ₂ O ₃ film is 8 nm or more and 200 nm or less. In a heterostructure field effect transistor using a nitride semiconductor,
A source electrode, a gate electrode and a drain electrode are formed on the barrier layer;
A Si ₃ N ₄ film and an AlN film are deposited in this order on the barrier layer in the region between the source electrode and the gate electrode and in the region between the gate electrode and the source electrode,
The film thickness of the Si ₃ N ₄ film is 0.28 nm or more and 4 nm or less,
The thickness of the AlN film is 4 nm or more and 200 nm or less,
A heterostructure field effect transistor using a nitride semiconductor, wherein a total film thickness of the Si ₃ N ₄ film and the AlN film is 8 nm or more and 200 nm or less. In a heterostructure field effect transistor using a nitride semiconductor,
A source electrode, a gate electrode and a drain electrode are formed on the barrier layer;
A Si ₃ N ₄ film and a SiO ₂ film are deposited in this order on the barrier layer in the region between the source electrode and the gate electrode and in the region between the gate electrode and the source electrode,
The film thickness of the Si ₃ N ₄ film is 2 nm or more and 4 nm or less,
The thickness of the SiO ₂ film is 4 nm or more and 200 nm or less,
A heterostructure field effect transistor using a nitride semiconductor, wherein a total film thickness of the Si ₃ N ₄ film and the AlO ₂ film is 8 nm or more and 200 nm or less.

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