JP4797821B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a buried wiring.

  With miniaturization and speeding up of element structures in semiconductor devices, it is desired to lower wiring resistance and lower dielectric constant of interlayer insulating films. In response to this, it has become common for state-of-the-art devices to use lower resistance copper (Cu) wiring instead of conventional aluminum (Al) alloy wiring. In the formation of Cu wiring, since it is difficult to pattern the Cu film by dry etching, it is common to form the Cu wiring as a buried wiring.

  In the case of forming a buried wiring, a dual damascene structure in which a wiring groove and a connection hole are dug from the bottom is formed in an interlayer insulating film, and the inside is simultaneously filled with a conductive material (Cu or the like), and then the interlayer insulating film A method of polishing and removing the conductive material remaining thereon by CMP (Chemical Mechanical Polishing) has been performed.

  Various methods for forming the dual damascene structure have been proposed. First, a connection hole (via) pattern is formed by lithography, and using this as a mask, all or part of the interlayer insulating film is etched. A so-called first via method is generally used in which after forming the connection hole, a wiring groove pattern is formed by lithography, and the upper part of the interlayer insulating film is etched using this as a mask to etch the wiring groove.

  In this case, first, as shown in FIG. 11 (1), the diffusion prevention film 3 made of SiC (N, H) and the porous film made of SiCOH are formed on the substrate 1 on which the buried lower layer wiring 1a is formed. An interlayer insulating film 5 and a hard mask layer 7 made of SiN are sequentially formed, and a resist pattern 9 having a connection hole pattern formed thereon is formed by lithography. Next, as shown in FIG. 11 (2), connection holes 5 a are formed in the hard mask layer 7 and the interlayer insulating film 5 by etching using the resist pattern 9 as a mask. Thereafter, the resist pattern 9 is removed. Next, as shown in FIG. 11 (3), a resist pattern 11 having a wiring groove pattern 9 is newly formed on the hard mask layer 7 by lithography, and wiring is performed on the hard mask layer 7 by etching using the resist pattern 11 as a mask. The groove pattern 7-1 is opened. Thereafter, the resist pattern 9 is removed.

  Next, as shown in FIG. 11 (4), a wiring groove 5 b is formed in the interlayer insulating film 5 by etching from above the hard mask layer 7. Next, as shown in FIG. 12A, the hard mask layer 7 and the diffusion prevention film 3 are removed by etching to expose the lower layer wiring 1a at the bottom of the connection hole 5a. Thus, a dual damascene structure is formed by the so-called first via method, in which the connection hole (via) pattern is formed first.

  After that, as shown in FIG. 12 (2), the barrier metal layer 13 is formed in a state of covering the wiring groove 5b and the inner wall of the connection hole 5a provided at the bottom, and further a Cu seed layer is formed. Then, the Cu film 15 is plated in a state in which the inside of the wiring groove 5b and the connection hole 5a is embedded. Thereafter, the Cu film 15 and the barrier metal layer 13 on the interlayer insulating film 5 are removed by CMP, and the embedded wiring 15a in which the Cu film 15 is embedded via the barrier metal layer 13 only in the wiring groove 5b and the connection hole 5a. (See Patent Document 1 below).

See JP-A-2006-41519

  However, in the formation of the dual damascene structure by the above-described via method, as shown in FIG. 12A, when the diffusion barrier film 3 is removed and the lower layer wiring 1a is exposed, the bottom of the wiring trench 5b is formed. When exposed to plasma for a long time, the upper part of the connection hole 5a is likely to fall down and become tapered.

  Therefore, in the next step shown in FIG. 12 (2), when the sputter film formation is performed in the formation of the barrier metal layer 13 and the Cu seed layer when the wiring groove 5a and the connection hole 5b are embedded, Sputtering material is reattached to the upper part A of the tapered connection hole 5b to form an overhang (reference: A. Kajita et al., “Highly Reliable Cu / Low-k Dual-Damascene Interconnect Technology with Hybrid ( PAE / SiOC) Dielectrics for 65nm-Node High Performance eDRAM ”Proceedings of the IEEE 2003 International Interconnect Technology Conference, p.9). As a result, a void B is generated inside the connection hole 5b, and the connection resistance between the upper-layer buried wiring 15a and the lower-layer wiring 1a via the connection hole 5b is remarkably increased, which causes the reliability of the semiconductor device to deteriorate. .

  Further, such a shoulder drop at the upper portion A of the connection hole 5b is likely to occur when a low dielectric film (relative dielectric constant k <3.2) is used as the interlayer insulating film 5, and a porous material is used. This is particularly noticeable in low dielectric films.

  Therefore, the present invention can form a dual damascene structure with good shape accuracy in which the upper shoulder of the connection hole is prevented and can provide a highly reliable semiconductor device in which generation of voids is prevented. The object is to provide a possible manufacturing method.

The method of manufacturing a semiconductor device of the present invention for achieving such an object is characterized by performing the following steps. That is, a step of forming an interlayer insulating film on the substrate, a step of forming a first mask having a connection hole pattern on the interlayer insulating film, and a connection hole in the interlayer insulating film by etching from the first mask. forming, a method for manufacturing a semiconductor device which performs in this order, further, after this step, the second mask having a wiring groove pattern in connection holes formed the interlayer insulating film Forming a protective film in a state of covering the inner wall of the connection hole, etching the upper layer of the protective film and the interlayer insulating film by etching from above the second mask , and forming the inner wall by the protective film A step of forming a wiring groove above the protected connection hole, a step of exposing the substrate to the bottom of the connection hole by etching from above the protective film, and a state in which the wiring groove and the connection hole are embedded. A step of forming a material film, performing a step of forming a buried wiring by the conductive material film to remain only in the wiring groove and the connection hole is polished away, in this order.

  In the manufacturing method described above, in the dual damascene process of the first via method in which the connection hole pattern is formed before the wiring groove pattern is formed, the etching of the interlayer insulating film for the wiring groove pattern formation is performed on the inner wall of the connection hole. Is carried out in a state of being covered with a protective film. This prevents the etching for forming the wiring trench from affecting the opening shape of the connection hole, maintains the opening shape of the connection hole formed by etching from above the first mask, and maintains the upper portion of the opening of the connection hole. The fall of the shoulder is prevented. Therefore, when forming the embedded wiring in the sixth step, it is possible to prevent the conductive material film formed in a state of filling the wiring groove and the connection hole from being overhanging at the upper part of the opening of the connection hole, A buried wiring free from voids is formed.

  As described above, according to the present invention, it is possible to form a dual damascene structure with good shape accuracy in which shoulder drop at the upper portion of the connection hole is prevented, and high reliability in which generation of voids is prevented. A semiconductor device can be obtained.

  Embodiments in which the present invention is applied to the formation of Cu embedded wiring will be described in detail below.

<First Embodiment>
The manufacturing method of 1st Embodiment is demonstrated along the cross-sectional process drawing of FIGS. 1-3. In addition, the same code | symbol shall be attached | subjected and demonstrated to the component same as the conventional manufacturing method demonstrated using FIG.

First, as shown in FIG. 1A, a substrate 1 having a lower layer wiring 1a made of Cu-embedded wiring formed on the front surface side is prepared. Then, a Cu diffusion prevention film 3 made of silicon carbide (SiC) is formed on the substrate 1. The Cu diffusion preventing film 3 made of silicon carbide (SiC) may be configured as SiC (N, H) containing nitrogen (N) or hydrogen (H) by a gas used in the film forming process. Next, an interlayer insulating film 5 made of porous SiCOH is formed, and a hard mask layer 7 made of silicon oxide (SiO ₂ ) is formed thereon.

  Thereafter, a resist pattern 9 having a connection hole pattern 9a is formed as a first mask on the hard mask layer 7 by lithography.

Next, as shown in FIG. 1B, connection holes 5 a are formed in the hard mask layer (SiO ₂ ) 7 and the interlayer insulating film (porous SiCOH) 5 by etching from above the resist pattern 9. Thereafter, the resist pattern 9 is removed by an ashing process.

Next, as shown in FIG. 1 (3), a thin-film protective film 21 is formed so as to cover the inner wall of the connection hole 5a. This process is a characteristic process of the first embodiment. The protective film 21 is made of a material having etching resistance against the etching of the interlayer insulating film 5, and is, for example, a SiCOH thin film, a SiO ₂ thin film, a SiN thin film, a SiON thin film, a SiC thin film, or even CHO, CH, CF. , CN and other material thin films containing carbon (C) are used. Here, as an example, the protective film 21 made of a SiOCH thin film is formed.

Next, as shown in FIG. 2A, an organic embedding material film 23 is embedded and formed in a state of embedding the connection hole 5a. Next, a silicon oxide (SiO ₂ ) film 25 is formed on the organic embedding material film 23. Thereafter, a resist pattern 11 having a wiring groove pattern 11a is formed as a second mask on the silicon oxide film 25 by lithography.

  After that, as shown in FIG. 2B, the silicon oxide film 25 and the organic embedding material film 23 are etched by etching from above the resist pattern (second mask) 11, and further, the protective film 21, the hard mask layer 7, Then, the upper layer of the interlayer insulating film 5 is etched. Thereby, the wiring groove 5b is formed in the upper part of the connection hole 5a whose inner wall is protected by the protective layer 21. In this etching, the resist pattern 11 and the silicon oxide film 25 are removed by etching until the wiring groove 5 b is formed in the surface layer of the interlayer insulating film 5.

Next, as shown in FIG. 3A, the organic embedding material film 23 is removed by an ashing process. This ashing treatment is performed using a gas containing at least oxygen (O ₂ ), a gas containing nitrogen and hydrogen (N ₂ / H ₂ ), or a gas containing ammonia (NH ₃ ).

Thereafter, as shown in FIG. 3B, the lower layer wiring 1a of the substrate 1 is exposed at the bottom of the connection hole 5a by etching from above the protective film 21. At this time, the protective film 21 made of SiCOH and the diffusion prevention film 3 made of SiC (N, H) are etched. An example of the etching conditions is as follows.
Equipment: Parallel plate etching equipment Source power: 1000W
RF bias power: 300W
Gas and flow rate: CH ₂ F ₂ / Ar / O ₂ = 60/600/60 sccm
Pressure: 50 mTorr
Substrate temperature: 20 ° C
Gap interval: 40mm

  Thereafter, as shown in FIG. 3 (3), the embedded wiring 15 a is formed in the connection hole 5 a and the wiring groove 5 b through the barrier metal layer 13. Here, the barrier metal layer 13 is formed in a state of covering the wiring groove 5b and the inner wall of the connection hole 5a provided at the bottom, and further a Cu seed layer is formed to embed the inside of the wiring groove 5b and the connection hole 5a. In this state, the Cu film 15 is plated. Thereafter, the Cu film and the barrier metal layer 13 on the interlayer insulating film 5 are polished and removed by CMP, and the embedded wiring is formed by embedding the Cu film only in the wiring trench 5b and the connection hole 5a via the barrier metal layer 13. 15a is formed.

  According to the first embodiment described above, as described with reference to FIGS. 2 (2) to 3 (2), the hard mask layer 7, the interlayer insulating film 5 and the diffusion for forming the pattern of the wiring trench Etching of the prevention layer 3 is performed in a state where the inner wall of the connection hole 5 a is covered with the protective film 21. As a result, the etching for forming the wiring groove 5b is prevented from affecting the opening shape of the connection hole 5a, and a shoulder drop at the upper part of the connection hole 5a is prevented.

  For this reason, in the formation of the embedded wiring 15a described with reference to FIG. 3 (3), the barrier metal layer 13 and the Cu seed layer are prevented from being formed in an overhang state above the opening of the connection hole 5a. Therefore, it becomes possible to form the embedded wiring 15a by forming a Cu film inside the connection hole 5a without generating a void. As a result, it is possible to obtain a highly reliable semiconductor device in which the lower layer wiring 1a and the embedded wiring 15a are reliably connected.

In the first embodiment below, the protective film 21 is an insulating material film such as a SiCOH thin film, a SiO ₂ thin film, a SiN thin film, or a material thin film containing carbon (C) such as CHO, CH, CF, CN, etc. The configuration using the above has been described. However, in the step of exposing the lower layer wiring 1a to the bottom of the connection hole 5a described with reference to FIG. 3B, the protective film 21 is also completely removed from the hard mask layer 7. Alternatively, the material is not limited to the insulating material film as long as it can be removed by the CMP process described with reference to FIG. Even in this case, the protective film 21 is similarly configured using a material having etching resistance to the etching of the interlayer insulating film 5, and includes, for example, tantalum (Ta) or titanium (Ti). A metal material film is applied. When such a conductive material film is used as the protective film 21, the protective film 21 remaining on the inner wall of the connection hole 5a does not increase the dielectric constant between the wirings.

Second Embodiment
Next, the manufacturing method of 2nd Embodiment is demonstrated along the cross-sectional process drawing of FIGS. In addition, the same code | symbol is attached | subjected and demonstrated to the component similar to 1st Embodiment.

First, as shown in FIG. 4 (1), a substrate 1 having a lower layer wiring 1a made of Cu embedded wiring formed on the surface side is prepared, a Cu diffusion prevention film 3 made of SiC (N, H), An interlayer insulating film 5 made of SiCOH, a first hard mask layer 7-1 made of silicon nitride (SiN), and a second hard mask layer 7-2 made of silicon oxide (SiO ₂ ) are formed.

  Thereafter, a resist pattern 9 having a connection hole pattern 9a is formed as a first mask on the second hard mask layer 7-2 by lithography.

Next, as shown in FIG. 4B, the second hard mask layer (SiO ₂ ) 7-2 and the first hard mask layer (SiN) 7-1 are etched by etching from above the resist pattern 9. Further, the interlayer insulating film (porous SiCOH) 5 is etched halfway to form connection holes 5a. Thereafter, the resist pattern 9 is removed by an ashing process.

Thereafter, as shown in FIG. 5A, an organic embedding material film 23 is embedded and a silicon oxide (SiO ₂ ) film 25 is further formed in a state of embedding the connection hole 5a. Thereafter, a resist pattern 11 having a wiring groove pattern 11a is formed on the silicon oxide film 25 by lithography.

  Next, as shown in FIG. 5B, the silicon oxide film 25 and the organic embedding material film 23 are etched by etching from above the resist pattern (second mask) 11, and then the second hard mask layer 7-2. Etch. Thereby, the wiring groove pattern 11a is formed in the second hard mask 7-2, and this becomes the second mask. In this etching, the resist pattern 11 and the silicon oxide film 25 are removed by etching.

Next, as shown in FIG. 5C, the organic embedding material film 23 is removed by an ashing process. This ashing treatment is performed using a gas containing at least oxygen (O ₂ ), a gas containing nitrogen and hydrogen (N ₂ / H ₂ ), or a gas containing ammonia (NH ₃ ).

  Next, as shown in FIG. 6A, a thin protective film 21 is formed so as to cover the inner wall of the connection hole 5a. This process is a characteristic process of the second embodiment. The protective film 21 is made of the same material film as in the first embodiment, and is made of, for example, a SiCOH thin film.

Next, as shown in FIG. 6 (2), the upper layer of the protective film 21 and the interlayer insulating film 5 is etched by etching from above the protective film 21, and the opening edge of the connection hole 5 a is formed on the surface layer of the interlayer insulating film 5. A wiring groove 5 b whose portion is covered with a protective film 21 is formed, and the connection hole 5 a is dug down to expose the lower layer wiring 1 a of the substrate 1. At this time, the protective film 21 made of SiCOH, the first hard mask layer 7-1 made of SiN, the interlayer insulating film 5 made of porous SiCOH, and the diffusion prevention film 3 made of SiC (N, H) are etched. An example of the etching conditions is as follows.
Equipment: Parallel plate etching equipment Source power: 1000W
RF bias power: 300W
Gas and flow rate: CH2F2 / Ar / O2 = 60/600 / 60sccm
Pressure: 50 mTorr
Substrate temperature: 20 ° C
Gap interval: 40 mm

  Thereafter, as shown in FIG. 6 (3), the embedded wiring 15 a is formed in the connection hole 5 a and the wiring groove 5 b through the barrier metal layer 13. The formation of the embedded wiring 15a is performed in the same manner as described in the first embodiment with reference to FIG. That is, after the barrier metal layer 13 and the Cu seed layer are formed, and the Cu film is plated in a state of filling the wiring grooves 5b and the connection holes 5a, the Cu film and the barrier metal on the interlayer insulating film 5 are formed by CMP. The layer 13 is polished and removed by CMP, and a Cu film is embedded through the barrier metal layer 13 only in the wiring groove 5b and the connection hole 5a.

  According to the second embodiment described above, as described with reference to FIGS. 6A and 6B, the first hard mask layer 7-1 and the interlayer for pattern formation of the wiring groove 5b are provided. Etching of the insulating film 5 and the diffusion preventing layer 3 is performed in a state where the inner wall of the connection hole 5 a is covered with the protective film 21. Thus, as in the first embodiment, the etching for forming the wiring groove 5b affects the opening shape of the connection hole 5a, so that there is no shoulder drop at the top of the connection hole 5a. The embedded wiring 15a can be formed by film formation in which generation of voids is suppressed. As a result, it is possible to obtain a highly reliable semiconductor device in which the lower layer wiring 1a and the embedded wiring 15a are reliably connected.

<Third Embodiment>
Next, the manufacturing method of 3rd Embodiment is demonstrated along the cross-sectional process drawing of FIG.

  First, by performing the same procedure as described with reference to FIGS. 4A to 4C in the second embodiment, the interlayer insulating film 5 on the diffusion prevention film 3 is etched halfway to form connection holes. 5a is formed. Further, the wiring groove pattern 11a is transferred to the second hard mask layer 7-2 formed on the interlayer insulating film 5 via the first hard mask layer 7-1 to form a second mask.

  After the above, as shown in FIG. 7A, a layer obtained by hardening the inner wall surface layer of the connection hole 5a is formed as the protective film 31 by plasma treatment. In this plasma treatment, it is preferable to use an inert gas such as helium (He), neon (Ne), argon (Ar), xenon (Xe), etc., and thus hardened like non-porous SiCOH. The protective film 31 can be formed.

For example, an example of plasma processing conditions using He plasma is as follows.
Equipment: Parallel plate etching equipment Source power: 2200W
RF bias power: 400W
Gas and flow rate: He = 600 sccm
Pressure: 50 mTorr
Substrate temperature: 20 ° C
Gap interval: 40 mm

  Next, as shown in FIG. 7B, the wiring groove 5b is formed above the connection hole 5a whose inner wall is protected by the protective film 31 by etching from above the second hard mask layer (second mask) 7-2. And the lower layer wiring 1a of the substrate 1 is exposed at the bottom of the connection hole 5b. At this time, the hardened protective film 31, the first hard mask layer 7-1 made of SiN, the interlayer insulating film 5 made of porous SiCOH, and the diffusion prevention film 3 made of SiC (N, H) are etched. . This etching is performed in the same manner as the etching for forming the wiring trench described with reference to FIG. 6B in the second embodiment.

  Next, as shown in FIG. 7 (3), a buried wiring 15 a is formed in the connection hole 5 a and the wiring groove 5 b through the barrier metal layer 13. The formation of the embedded wiring 15a is performed in the same manner as described in the first embodiment with reference to FIG. That is, after the barrier metal layer 13 and the Cu seed layer are formed, and the Cu film is plated in a state of filling the wiring grooves 5b and the connection holes 5a, the Cu film and the barrier metal on the interlayer insulating film 5 are formed by CMP. The layer 13 is polished and removed by CMP, and a Cu film is embedded through the barrier metal layer 13 only in the wiring groove 5b and the connection hole 5a.

  According to the third embodiment described above, as described with reference to FIGS. 7A and 7B, the first hard mask layer 7-1 and the interlayer for pattern formation of the wiring groove 5b are provided. Etching of the insulating film 5 and the diffusion preventing layer 3 is performed in a state where the inner wall of the connection hole 5 a is covered with the protective film 31. Thus, as in the first embodiment, the etching for forming the wiring groove 5b affects the opening shape of the connection hole 5a, and there is no shoulder drop at the upper part of the connection hole 5a. The embedded wiring 15a can be formed by film formation in which generation of voids is suppressed. As a result, it is possible to obtain a highly reliable semiconductor device in which the lower layer wiring 1a and the embedded wiring 15a are reliably connected.

  In the third embodiment described above, a hardened layer may be formed on the inner wall of the connection hole 5a, and an electron beam irradiation process or an ultraviolet irradiation process may be performed instead of the plasma process.

  In the third embodiment, the protective film 31 in which the inner wall surface layer of the connection hole 5a is hardened is formed in a state where the connection hole 5a reaching the diffusion prevention film 3 is formed, and then the wiring groove 5b is formed. The procedure of performing the etching to form may be sufficient and the effect which forms the wiring groove | channel 5b in the state which provided the protective film 31 can be acquired similarly.

<Fourth embodiment>
Next, the manufacturing method of 4th Embodiment is demonstrated along the cross-sectional process drawing of FIGS. In the fourth embodiment, the present invention is applied to a case where a dual damascene structure is formed by a first via method on an interlayer insulating film having a hybrid structure in which an organic insulating film and an inorganic insulating film are stacked as an interlayer insulating film. A form is demonstrated.

  First, as shown in FIG. 8A, a substrate 1 having a lower layer wiring 1a made of a Cu-embedded wiring on the surface side is prepared. Then, a Cu diffusion prevention film 3 made of SiC (N, H) is formed on the substrate 1. Next, an inorganic interlayer insulating film 5-1 made of porous SiCOH is formed. Next, an organic interlayer insulating film 5-2 made of an organic low dielectric material is formed on the upper portion.

Next, on the organic interlayer insulating film 5-2, the first hard mask layer 7-1 made of silicon nitride (SiO ₂ ), the second hard mask layer 7-2 made of silicon oxide (SiN), and further silicon nitride. A third hard mask layer 7-3 made of (SiO ₂ ) is formed.

  Thereafter, as shown in FIG. 8B, a resist pattern 41 having a wiring groove pattern 41a is formed on the third hard mask layer 7-3 by lithography. Then, by etching the third hard mask layer 7-3 using the resist pattern 41 as a mask, the wiring groove pattern is transferred to the third hard mask layer 7-3. After the etching is completed, the resist pattern 41 is removed.

  Next, as shown in FIG. 8C, a resist pattern 43 including a connection hole pattern 43a is formed as a first mask on the second hard mask layer 7-2 by lithography. Here, the connection hole pattern 43a is formed in the opening (wiring groove pattern) of the third hard mask layer 7-3.

  Then, the second hard mask layer 7-2 and the first hard mask layer 7-1 are etched from above the resist pattern (first mask) 43 so that the second hard mask layer 7-2 and the first hard mask layer 7-1 are etched. The connection hole pattern is transferred to the mask layer 7-1. After the etching is completed, the resist pattern 43 is removed.

  Next, as shown in FIG. 9A, the organic interlayer insulating film 5-2 is etched using the third hard mask layer 7-3 and the second hard mask layer 7-2 as a mask to form a connection hole 5a. .

  Subsequently, as shown in FIG. 9B, the wiring groove pattern is transferred to the second hard mask layer 7-2 by etching from the third hard mask layer 7-3, and the inorganic interlayer insulating film 5-1 is also transferred. The connection hole 5a is dug.

  Further, as shown in FIG. 9 (3), etching from above the third hard mask layer 7-3 is advanced to transfer the wiring groove pattern to the first hard mask layer 7-1. Thereby, a second mask having a two-layer structure of the first hard mask layer 7-2 and the first hard mask layer 7-1 is formed. At the same time, the etching of the inorganic interlayer insulating film 5-1 is advanced to expose the diffusion prevention film 3 at the bottom of the connection hole 5a. By this etching, the third hard mask layer 7-3 is removed by etching, and the second hard mask layer 7-2 is exposed.

  Thereafter, as shown in FIG. 10A, a thin protective film 45 is formed so as to cover the inner wall of the connection hole 5a. This process is a characteristic process of the fourth embodiment. The protective film 45 is made of the same material film as that of the first embodiment, and is made of, for example, a SiCOH thin film.

  Next, as shown in FIG. 10B, etching is performed from above the protective film 45 using the first hard mask layer 7-2 and the first hard mask layer 7-1 as a second mask to form an organic interlayer insulating film. The wiring groove 5b is formed in 5-2, and the protective film 45 and the diffusion prevention layer 3 covering the bottom of the connection hole 5a are removed to expose the lower layer wiring 1a of the substrate 1.

  Thereafter, as shown in FIG. 10 (3), the embedded wiring 15 a is formed in the connection hole 5 a and the wiring groove 5 b through the barrier metal layer 13. The formation of the embedded wiring 15a is performed in the same manner as described in the first embodiment with reference to FIG. That is, after the barrier metal layer 13 and the Cu seed layer are formed, and the Cu film is plated in a state of filling the wiring grooves 5b and the connection holes 5a, the Cu film and the barrier metal on the interlayer insulating film 5 are formed by CMP. The layer 13 is polished and removed by CMP, and a Cu film is embedded through the barrier metal layer 13 only in the wiring groove 5b and the connection hole 5a.

  According to the fourth embodiment described above, as described with reference to FIGS. 10A and 10B, the etching of the organic interlayer insulating film 5-2 for forming the pattern of the wiring trench 5b is performed. This is performed with the inner wall of the connection hole 5 a covered with the protective film 21. Thus, as in the first embodiment, the etching for forming the wiring groove 5b affects the opening shape of the connection hole 5a, so that there is no shoulder drop at the top of the connection hole 5a. The embedded wiring 15a can be formed by film formation in which generation of voids is suppressed. As a result, it is possible to obtain a highly reliable semiconductor device in which the lower layer wiring 1a and the embedded wiring 15a are reliably connected.

  In the fourth embodiment, in the process described with reference to FIG. 10A, instead of forming the protective film 45 made of the SiOCH thin film, the protective film in which the inner wall surface layer of the connection hole 5a is hardened. The same effect can be obtained.

  Further, the material of the interlayer insulating film and the material of the hard mask layer, and the number of hard mask layers used in the first to fourth embodiments described above are merely examples, and do not depart from the gist of the present invention. In the range, it can change suitably. Furthermore, the etching conditions (etching apparatus) given as an example in each embodiment are merely examples, and can be appropriately changed without departing from the gist of the present invention.

FIG. 3 is a sectional process diagram (part 1) illustrating the manufacturing method according to the first embodiment. FIG. 6 is a sectional process diagram (part 2) illustrating the manufacturing method according to the first embodiment. FIG. 6 is a sectional process diagram (part 3) illustrating the manufacturing method according to the first embodiment; It is sectional process drawing (the 1) which shows the manufacturing method of 2nd Embodiment. It is sectional process drawing (the 2) which shows the manufacturing method of 2nd Embodiment. It is sectional process drawing (the 3) which shows the manufacturing method of 2nd Embodiment. It is sectional process drawing which shows the manufacturing method of 3rd Embodiment. It is sectional process drawing (the 1) which shows the manufacturing method of 4th Embodiment. It is sectional process drawing (the 2) which shows the manufacturing method of 4th Embodiment. It is sectional process drawing (the 3) which shows the manufacturing method of 4th Embodiment. It is sectional process drawing (the 1) which shows an example of the conventional manufacturing method. It is sectional process drawing (2) which shows an example of the conventional manufacturing method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 5 ... Interlayer insulation film, 5-1 ... Inorganic interlayer insulation film, 5-2 ... Organic interlayer insulation film, 5a ... Connection hole, 5b ... Wiring groove, 7-1 ... 1st hard mask layer (2nd Mask), 7-2 ... second hard mask layer (second mask), 9, 42 ... resist pattern (first mask), 11 ... resist pattern (second mask), 21, 31, 45 ... protective film, 15a ... Embedded wiring

Claims (1)

Forming an interlayer insulating film on the substrate;
Forming a first mask having a connection hole pattern on the interlayer insulating film;
Forming a connection hole in the interlayer insulating film by etching from above the first mask;
A method for manufacturing a semiconductor device that performs the steps in this order,
Furthermore, after performing this process,
Forming a second mask having a wiring groove pattern on the interlayer insulating film in which the connection hole is formed;
Forming a protective film in a state of covering the inner wall of the connection hole;
Etching the upper layer of the protective film and the interlayer insulating film by etching from above the second mask to form a wiring groove above the connection hole whose inner wall is protected by the protective film;
Exposing the substrate to the bottom of the connection hole by etching from above the protective film;
Forming a conductive material film in a state of filling the wiring groove and the connection hole;
Forming a buried wiring by polishing and removing the conductive material film so as to remain only in the wiring groove and the connection hole;
A method for manufacturing a semiconductor device, wherein the steps are performed in this order.

Images