JP4794159B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a display device having a shift register circuit.

  Conventionally, a resistance load type inverter circuit is known (for example, see Non-Patent Document 1). Conventionally, a shift register circuit including the above-described resistance load type inverter circuit is known. The shift register circuit is used, for example, in a circuit that drives a gate line or a drain line of a liquid crystal display device or an organic EL display device.

  FIG. 18 is a circuit diagram of a shift register circuit including a conventional resistance load type inverter circuit. Referring to FIG. 18, a conventional shift register circuit 1000a includes a first circuit unit 1001a and a second circuit unit 1002a. The second-stage shift register circuit 1000b includes a first circuit portion 1001b and a second circuit portion 1002b.

  The first circuit portion 1001a that constitutes the first-stage shift register circuit 1000a includes n-channel transistors NT201 and NT202, a capacitor C201, and a resistor R201. Hereinafter, in the description of the prior art, n-channel transistors NT201 and NT202 are referred to as transistors NT201 and NT202, respectively. The source of the transistor NT201 is connected to the node ND201, and the start signal ST is input to the drain. A clock signal CLK1 is supplied to the gate of the transistor NT201. The source of the transistor NT202 is connected to the negative potential VSS, and the drain is connected to the node ND202. One electrode of the capacitor C201 is connected to the node ND201, and the other electrode is connected to the negative potential VSS. One terminal of the resistor R201 is connected to the positive potential VDD, and the other terminal is connected to the node ND202. The transistor NT202 and the resistor R201 constitute an inverter circuit.

  The second circuit portion 1002a constituting the first stage shift register circuit 1000a includes an n-channel transistor NT203 and a resistor R202. Hereinafter, in the description of the prior art, n-channel transistor NT203 is referred to as transistor NT203. The source of the transistor NT203 is connected to the negative potential VSS, and the drain is connected to the node ND203. One terminal of the resistor R202 is connected to the positive potential VDD, and the other terminal is connected to the node ND203. The transistor NT203 and the resistor R202 constitute an inverter circuit.

  The second and subsequent stage shift register circuits also have a circuit configuration similar to that of the first stage shift register circuit 1000a. Note that the first circuit portion of the rear-stage shift register circuit is configured to be connected to the output node of the front-stage shift register circuit. Further, as described above, the clock signal CLK1 is supplied to the gate of the transistor NT201 in the first circuit section arranged in the odd-numbered stage, and the gate of the transistor NT201 in the first circuit section arranged in the even-numbered stage. The clock signal CLK2 is supplied.

  FIG. 19 is a waveform diagram for explaining the operation of the conventional shift register circuit shown in FIG. Next, the operation of the conventional shift register circuit will be described with reference to FIGS.

  First, the start signal ST becomes H level. Thereafter, the clock signal CLK1 becomes H level. At this time, in the first-stage shift register circuit 1000a, the transistor NT201 is turned on and the potential of the node ND201 is increased to the H level, so that the transistor NT202 is turned on. As a result, the potential of the node ND202 drops to the L level, whereby the transistor NT203 is turned off, so that the potential of the node ND203 rises to the H level and the H-level output signal SR1 from the first-stage shift register circuit 1000a. Is output. Note that an H-level potential is accumulated in the capacitor C201 during a period when the clock signal CLK1 is at an H level.

  Next, the clock signal CLK1 becomes L level. At this time, the transistor NT201 of the first-stage shift register circuit 1000a is turned off. Thereafter, the start signal ST becomes L level. Here, in the first-stage shift register circuit 1000a, even when the transistor NT201 is turned off, the potential of the node ND201 is held at the H level by the H level potential accumulated in the capacitor C201. NT202 is held in the on state. Therefore, since the potential of the node ND202 does not rise to the H level, the transistor NT203 is held in the off state. As a result, the H-level output signal SR1 is continuously output from the first-stage shift register circuit 1000a.

  Next, the clock signal CLK2 becomes H level. Thus, since the H-level output signal SR1 of the first-stage shift register circuit 1000a is input to the second-stage shift register 1000b, the same operation as the above-described first-stage shift register circuit 1000a is performed. Is called. As a result, the H-level output signal SR2 is output from the second-stage shift register circuit 1000b.

  Thereafter, the clock signal CLK1 becomes H level again. At this time, in the first-stage shift register circuit 1000a, the transistor NT201 is turned on, and the potential of the node ND201 drops to the L level. Therefore, the transistor NT202 is turned off and the potential of the node ND202 is increased to the H level, so that the transistor NT203 is turned on. As a result, the potential of the node ND203 drops from the H level to the L level, so that the L level output signal SR1 is output from the first-stage shift register circuit 1000a. Through the operation as described above, the H level output signals (SR1, SR2, SR3...) Whose timing is shifted are sequentially output from the shift register circuits of the respective stages.

Shogo Kishino, “Basics of Semiconductor Devices”, published by Ohmsha, April 25, 1985, pp. 184-187

  In the conventional shift register circuit shown in FIG. 18, as shown in FIG. 19, the H level period of the output signal of the previous stage output from the shift register circuits 1000a and 1000b of each stage and the H level of the output signal of the next stage. When the output signal is output to the gate line of the display device and the gate lines of each stage are sequentially driven, the previous stage gate line and the next stage gate line overlap. The inconvenience of being driven occurs. In order to eliminate such an inconvenience, it is conceivable that the output signal of every other shift register circuit in which the H level periods do not overlap is input to the gate line of each stage. However, in this case, in order to sequentially drive the gate lines of each stage, there is a disadvantage that a shift register circuit having the number of stages twice the number of gate lines is required. Accordingly, there is a problem that it is difficult to simplify the circuit configuration of the display device including the shift register circuit.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display device capable of simplifying the circuit configuration.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a display device according to one aspect of the present invention includes a first shift register circuit portion configured to include a first conductivity type transistor that outputs a first shift signal, and a first conductivity type transistor. And outputs a second shift signal, and logically synthesizes the second shift register circuit unit arranged at the next stage of the first shift register circuit unit, the first shift signal, and the second shift signal. A shift register circuit including a logic synthesis circuit unit that outputs a shift output signal.

  In the display device according to this aspect, as described above, the first shift register circuit unit that outputs the first shift signal and the second shift signal are output, and are arranged in the next stage of the first shift register circuit unit. By configuring the shift register circuit to include a second shift register circuit unit, a logic synthesis circuit unit that logically synthesizes the first shift signal and the second shift signal and outputs a shift output signal, Using the first shift signal of the first shift register circuit unit and the second shift signal of the second shift register circuit unit of the next stage, a predetermined shift output signal is output from the logic synthesis circuit unit of the shift register circuit And shift using the second shift signal of the second shift register circuit section and the shift signal of the next shift register circuit section of the second shift register circuit section. It can be from the logic composition circuit portion of the register circuit to output a next stage of the shift output signal not overlapping timings with respect to the predetermined shift output signal. Thus, two stages of shift register circuit units used for outputting a predetermined shift output signal and two stages of shift register used for outputting the next stage shift output signal whose timing does not overlap with the predetermined output signal. One shift register circuit portion can be shared with the other shift register circuit portion. Therefore, the number of stages of the shift register circuit portion included in the shift register circuit can be reduced, so that the circuit configuration of the display device including the shift register circuit can be simplified. Further, both the first shift register circuit portion and the second shift register circuit portion are configured by transistors of the first conductivity type, so that the first shift register circuit portion and the second shift register circuit portion are the first conductivity type and Compared to the case where two types of transistors of two conductivity types are used, the number of ion implantation steps and the number of ion implantation masks can be reduced when forming the first shift register circuit portion and the second shift register circuit portion. it can. Thereby, while being able to suppress that a manufacturing process becomes complicated, it can suppress that manufacturing cost increases.

  In the display device according to the above aspect, the logic synthesis circuit unit is preferably connected to a first signal line that supplies a first signal in which one of the source / drain is switched between the first potential and the second potential, The first conductivity type first transistor to which the first shift signal is input to the gate, one of the source / drain is connected to the other of the source / drain of the first transistor, and the second shift signal is input to the gate. And when the first shift signal and the second shift signal are at the first potential, the first transistor and the second transistor are turned on, and the first signal line is connected to the second transistor from the first signal line. When the first signal having the first potential is supplied to one of the source / drain of one transistor, the first potential is passed through the first transistor and the second transistor. When the shift output signal is output and the first shift signal changes from the first potential to the second potential, the first signal having the second potential is supplied from the first signal line to one of the source / drain of the first transistor. As a result, a shift output signal having the second potential is output through the first transistor and the second transistor. With this configuration, when the first shift signal and the second shift signal are at the first potential, the first shift signal having the first potential and the second shift signal are transmitted via the first transistor and the second transistor of the logic synthesis circuit unit. A shift output signal of the first potential obtained by logically synthesizing the second shift signal of one potential can be output, and when the first shift signal changes from the first potential to the second potential, Through the first transistor and the second transistor, a shift output signal having a second potential obtained by logically synthesizing the first shift signal having the second potential and the second shift signal having the first potential can be output. Thereby, a shift output signal obtained by logically synthesizing the first shift signal and the second shift signal can be easily output from the logic synthesis circuit unit.

  In this case, preferably, the shift output signal is forcibly held at the second potential while the first signal is at the second potential. According to this configuration, a plurality of logic synthesis circuit units are provided, and the potential of the shift output signal output from the plurality of logic synthesis circuit units is sequentially changed from the second potential (for example, L level) to the first potential ( For example, when the first signal is changed to H level, the shift output signal output from the preceding logic synthesis circuit unit and the output from the next logic synthesis circuit unit during the period in which the first signal is the second potential (L level). Both of the shifted output signals can be forced to the second potential (L level). Thus, when the shift output signal output from the preceding logic synthesis circuit unit is the first potential (H level) and the shift output signal output from the next stage logic synthesis circuit unit is the second potential (L level). In addition, by setting the first signal to the second potential (L level), it is possible to set both the shift output signals respectively output from the preceding and subsequent logic synthesis circuit units to the second potential (L level). Further, if only the shift output signal output from the logic synthesis circuit unit of the next stage is changed to the first potential (H level) after the period of the first signal being the second potential (L level), the logic of the previous stage is changed. The timing at which the shift output signal output from the synthesis circuit unit changes from the first potential (H level) to the second potential (L level), and the shift output signal output from the logic synthesis circuit unit at the next stage is the second potential. It is possible to suppress overlapping with the timing of changing from (L level) to the first potential (H level). As a result, the timing at which the shift output signal output from the preceding logic synthesis circuit unit changes from the first potential (H level) to the second potential (L level), and the shift output from the next logic synthesis circuit unit. It is possible to suppress the occurrence of noise due to the overlap of the timing at which the output signal changes from the second potential (L level) to the first potential (H level).

  In the configuration in which the shift output signal of the second potential is output when the first shift signal changes from the first potential to the second potential, the logic synthesis circuit unit preferably has the first shift signal as the first potential. And a potential fixing circuit unit for fixing the shift output signal to the second potential after changing from the first potential to the second potential. With this configuration, the shift output signal can be fixed to the second potential after the first shift signal has changed from the first potential to the second potential by the potential fixing circuit unit. The shift output signal can be fixed at the second potential when the second shift signal is the first potential at the second potential. Thereafter, the shift output signal is fixed to the second potential even when the first shift signal and the second shift signal both become the first potential due to the second shift signal changing to the second potential. Can do.

  In the configuration including the potential fixing circuit unit, preferably, the potential fixing circuit unit is connected between the second potential side and the second transistor, and when the first shift signal is the second potential, A third transistor of the first conductivity type that is turned on when a predetermined signal is input to the gate is included. With this configuration, after the first shift signal changes from the first potential to the second potential, a signal having the second potential can be supplied from the second potential side via the third transistor that is on. Therefore, if this second potential signal is output as a shift output signal, the shift output signal can be easily fixed at the second potential after the first shift signal has changed from the first potential to the second potential. .

  In the configuration in which the potential fixing circuit unit includes the third transistor, the shift register circuit preferably includes a third shift register circuit unit subsequent to the second shift register circuit unit, and the first shift signal is output from the first potential. When changing to the second potential, the output signal of the first potential is input from the third shift register circuit portion to the gate of the third transistor. With this configuration, the third transistor can be easily turned on when the first shift signal changes from the first potential to the second potential by the third shift signal of the first potential.

  In the configuration in which the potential fixing circuit portion includes the third transistor, preferably, the second signal is supplied from the second signal line that supplies the second signal that switches between the first potential and the second potential to the gate of the third transistor. When the first shift signal is supplied and has the second potential, the second signal having the first potential is input from the second signal line to the gate of the third transistor. With this configuration, the third transistor can be easily turned on when the first shift signal changes from the first potential to the second potential by the second signal having the first potential.

  In the configuration in which the potential fixing circuit section includes the third transistor, a first capacitor is preferably connected between the gate and the source of the third transistor. With this configuration, when a predetermined signal having the first potential is input to the gate of the third transistor, the first capacitor is charged, and thereafter the gate potential of the third transistor is set to the first potential. Can be held. As a result, when the first shift signal is at the second potential, the third transistor is turned on after the predetermined signal of the first potential is input to the gate of the third transistor to turn on the third transistor. Can be kept in a state. For this reason, the shift output signal output via the third transistor can be held in a state of being fixed at the second potential.

  In the configuration in which the potential fixing circuit unit includes the third transistor, preferably, the potential fixing circuit unit includes a fourth transistor of the first conductivity type that is connected to the gate of the third transistor and is diode-connected, and has a predetermined signal. Is input to the gate of the third transistor via the fourth transistor. With this configuration, even when the predetermined signal is switched between the first potential and the second potential, when the predetermined signal is the first potential, the predetermined signal of the first potential is the diode-connected first On the other hand, when the predetermined signal is at the second potential, the predetermined signal at the second potential is input to the third transistor via the diode-connected fourth transistor. It can be prevented from being input to the gate. Accordingly, even when the predetermined signal is switched between the first potential and the second potential, only the predetermined signal having the first potential can be input to the gate of the third transistor.

  In the configuration in which the potential fixing circuit portion includes the third transistor, the third transistor is preferably turned off when the first shift signal and the second shift signal are at the first potential. If comprised in this way, when the 1st shift signal and the 2nd shift signal are the 1st electric potential, when the 1st transistor and the 2nd transistor are in an ON state, the 3rd transistor can be made into an OFF state. Therefore, it is possible to suppress a through current from flowing between the first signal line and the second potential side via the first transistor, the second transistor, and the third transistor. Accordingly, an increase in current consumption of the display device including the shift register circuit can be suppressed.

  In this case, preferably, the potential fixing circuit unit is connected between the second potential side and the gate of the third transistor, and the first shift signal and the second shift signal are the first potential when the first shift signal and the second shift signal are at the first potential. It includes a fifth transistor of the first conductivity type that is turned on when an output signal of the first potential is input to the gate through the transistor and the second transistor. With this configuration, when the first shift signal and the second shift signal are at the first potential, the second potential is supplied from the second potential side to the gate of the third transistor through the fifth transistor that is on. be able to. Thus, the third transistor can be easily turned off by the fifth transistor when the first shift signal and the second shift signal are at the first potential.

  In the configuration in which the logic synthesis circuit unit includes a first transistor in which a first shift signal is input to a gate and a second transistor in which a second shift signal is input to a gate, preferably the first shift register circuit unit is A sixth transistor having a first potential supplied to the drain and a gate connected to a node from which the first shift signal is output; a second capacitor connected between the gate and the source of the sixth transistor; The second shift register circuit unit includes a seventh transistor having a first potential supplied to the drain and a gate connected to a node from which the second shift signal is output, a gate and a source of the seventh transistor, And the gate potential of the sixth transistor is the gate-source voltage of the sixth transistor to which the second capacitor is connected. The gate potential of the seventh transistor is maintained at the gate-source voltage of the seventh transistor to which the third capacitor is connected, as the source potential of the sixth transistor is increased or decreased. Thus, it rises or falls as the source potential of the seventh transistor rises or falls.

  With this configuration, for example, when the positive potential VDD is supplied to the drains of the sixth and seventh transistors, and the first and second transistors are n-channel transistors, the gates of the sixth and seventh transistors Since the potential can be raised to a potential higher than the VDD by a predetermined voltage (Vα) that is equal to or higher than the threshold voltage (Vt), the potentials higher than VDD + Vt (VDD + Vα) are applied to the gates of the first transistor and the second transistor, respectively. ) Can be provided with a first shift signal and a second shift signal. As a result, the potential of the shift output signal output via the first transistor and the second transistor is prevented from being lowered from VDD by the threshold voltage (Vt) of the first transistor and the second transistor. it can. When the negative potential VBB is supplied to the drains of the sixth and seventh transistors, and the first transistor and the second transistor are p-channel transistors, the gate potentials of the sixth and seventh transistors are set to a threshold value higher than VBB. Since the voltage can be lowered to a potential lower by a predetermined voltage (Vα) equal to or higher than the voltage (Vt), the gates of the first transistor and the second transistor each have a potential (VDD-Vα) lower than VBB-Vt. A first shift signal and a second shift signal can be provided. As a result, the potential of the shift output signal output via the first transistor and the second transistor is prevented from rising from VBB by the threshold voltage (Vt) of the first transistor and the second transistor. it can.

  In the configuration in which the second capacitor is connected between the gate and the source of the sixth transistor and the third capacitor is connected between the gate and the source of the seventh transistor, preferably the sixth transistor The third signal line for supplying a third signal that switches between the first potential and the second potential is connected to the drain of the first transistor, the first clock signal is supplied to the gate, and the drain of the seventh transistor is connected to the drain of the seventh transistor. The third signal line for supplying the third signal is connected, the gate is supplied with the second clock signal, and the third signal is supplied after the first clock signal is changed from the second potential to the first potential. And after the second clock signal changes from the second potential to the first potential, the second potential is switched to the first potential, respectively.

  According to this structure, the sixth transistor (the second clock signal) is changed by changing the gate potential of the sixth transistor (the seventh transistor) from the second potential to the first potential by the first clock signal (second clock signal). After the seventh transistor is turned on, the source potential of the sixth transistor (seventh transistor) can be changed from the second potential to the first potential by the third signal. As a result, the gate potential of the sixth transistor (seventh transistor) can also be raised or lowered by a change in the source potential of the sixth transistor (seventh transistor) at that time. That is, when the first potential which is a fixed potential is supplied to the drain of the sixth transistor (seventh transistor), the second capacitor (second capacitor) between the gate and the source of the sixth transistor (seventh transistor). In addition to the rise or fall of the gate potential of the sixth transistor (seventh transistor) due to (3 capacitance), the change amount when the source potential is changed from the second potential to the first potential is also the same as that of the sixth transistor (seventh transistor). The gate potential can be higher or lower. As a result, compared to the case where the first potential, which is a fixed potential, is supplied to the drains of the sixth transistor and the seventh transistor, the potentials of the first shift signal and the second shift signal are made higher than the first potential. Alternatively, the potential of the first and second shift signals can be more easily set to a potential higher than the threshold voltage (Vt) than VDD or a potential lower than the threshold voltage (Vt) than VBB. be able to. Therefore, the first shift signal and the second shift signal having a potential of VDD + Vt or higher or VBB−Vt or lower can be supplied to the gate of the first transistor and the gate of the second transistor more easily. It is possible to further suppress the potential of the shift output signal output via the first transistor and the second transistor from decreasing or increasing by the threshold voltage (Vt).

  In the configuration in which the second capacitor is connected between the gate and the source of the sixth transistor and the third capacitor is connected between the gate and the source of the seventh transistor, preferably the sixth transistor The third signal line for supplying a third signal that switches between the first potential and the second potential is connected to the drain of the first transistor, the first clock signal is supplied to the gate, and the drain of the seventh transistor is connected to the drain of the seventh transistor. The fourth signal line for supplying the fourth signal that switches between the first potential and the second potential is connected, the second clock signal is supplied to the gate, the first signal is the first clock signal After the second potential is changed to the first potential, the second potential is switched to the first potential. The fourth signal is changed from the second potential to the first potential after the second clock signal is changed from the second potential to the first potential. Switch to

  With this configuration, the sixth transistor of the first shift register circuit unit and the seventh transistor of the second shift register circuit unit are turned on in response to the first clock signal and the second clock signal, respectively. The source potentials of the sixth and seventh transistors can be changed from the second potential to the first potential in accordance with the timing. The sixth and sixth transistors of the first shift register circuit portion and the seventh transistor of the second shift register circuit portion are turned off in response to the first clock signal and the second clock signal, respectively. The source potential of the seventh transistor can be held at the first potential. As a result, the source potential of the sixth and seventh transistors becomes the second potential until the sixth and seventh transistors are turned off in response to the first and second clock signals. It is possible to suppress the inconvenience that the gate potentials of the sixth and seventh transistors fluctuate. In this case, the first shift signal output from the node to which the gate of the sixth transistor of the first shift register circuit unit is connected and the node from which the gate of the seventh transistor of the second shift register circuit unit is connected are output. The second shift signal can be prevented from fluctuating, so that the operation of the first transistor of the logic synthesis circuit portion in which the first shift signal is input to the gate and the second shift signal is input to the gate. It can be suppressed that the operation of the second transistor of the logic synthesis circuit portion becomes unstable.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram inside the V driver of the liquid crystal display device according to the first embodiment shown in FIG.

  First, referring to FIG. 1, in the first embodiment, a display unit 2 is provided on a substrate 1. In the display unit 2, the pixels 20 are arranged in a matrix. In FIG. 1, only one pixel 20 is shown for the sake of simplification of the drawing. Each pixel 20 includes an n-channel transistor 21 (hereinafter referred to as transistor 21), a pixel electrode 22, a counter electrode 23 common to each pixel 20 arranged to face the pixel electrode 22, and between the pixel electrode 22 and the counter electrode 23. The liquid crystal 24 is sandwiched between the liquid crystal 24 and the auxiliary capacitor 25. The source of the transistor 21 is connected to the pixel electrode 22 and the auxiliary capacitor 25, and the drain is connected to the drain line. The gate of the transistor 21 is connected to the gate line.

  A horizontal switch (HSW) 3 and an H driver 4 for driving (scanning) the drain line of the display unit 2 are provided on the substrate 1 along one side of the display unit 2. A V driver 5 for driving (scanning) the gate line of the display unit 2 is provided on the substrate 1 along the other side of the display unit 2. Although only two switches are shown in the horizontal switch 3 in FIG. 1, in actuality, the number of switches corresponding to the number of pixels is arranged. Further, each of the H driver 4 and the V driver 5 in FIG. 1 shows only two shift register circuit portions, but actually, the number of shift register circuit portions corresponding to the number of pixels is arranged.

  A driving IC 10 is installed outside the substrate 1. The drive IC 10 includes a signal generation circuit 11 and a power supply circuit 12. The video signal Video, start signal STV, scan direction switching signal CSV, clock signal CKV, enable signal ENB, positive potential VDD and negative potential VBB are supplied from the driver IC 10 to the H driver 4. Further, the start signal STV, the enable signal ENB, the scan direction switching signal CSV, the clock signal CKV, the positive potential VDD and the negative potential VBB are supplied from the driving IC 10 to the V driver 5.

  Referring to FIG. 2, in the first embodiment, the V driver 5 includes a plurality of stages of shift register circuit units 51 to 55, a scan direction switching circuit unit 60, an input signal switching circuit unit 70, A plurality of logic synthesis circuit units 81 to 83 are provided. In FIG. 2, for simplification of the drawing, only five stages of shift register circuit units 51 to 55 and three stages of logic synthesis circuit units 81 to 83 are illustrated. A number of shift register circuit sections and logic synthesis circuit sections are provided.

  The first-stage shift register circuit unit 51 includes a first circuit unit 51a and a second circuit unit 51b. First circuit portion 51a includes n-channel transistors NT1 and NT2, a diode-connected n-channel transistor NT3, and a capacitor C1. Second circuit portion 51b includes n-channel transistors NT4, NT5, NT6 and NT7, a diode-connected n-channel transistor NT8, and a capacitor C2. Hereinafter, n-channel transistors NT1 to NT8 are referred to as transistors NT1 to NT8, respectively.

  The transistors NT1 to NT8 provided in the first-stage shift register circuit unit 51 are all constituted by TFTs (thin film transistors) made of n-type MOS transistors (field effect transistors). Transistors NT1, NT2, NT6, NT7, and NT8 have two gate electrodes that are electrically connected to each other. In the first circuit unit 51a, the source of the transistor NT1 is connected to the negative potential VBB, and the drain is connected to the node ND1. One electrode of the capacitor C1 is connected to the negative potential VBB, and the other electrode is connected to the node ND1. The source of the transistor NT2 is connected to the node ND1 through the transistor NT3, and the drain is connected to the clock signal line (CKV1).

  In the second circuit unit 51b, the source of the transistor NT4 is connected to the node ND3, and the drain is connected to the positive potential VDD. The gate of the transistor NT4 is connected to the node ND2. The source of the transistor NT5 is connected to the negative potential VBB, and the drain is connected to the node ND3. The gate of the transistor NT5 is connected to the node ND1 of the first circuit unit 51a. The source of the transistor NT6 is connected to the negative potential VBB, and the drain is connected to the node ND2. The gate of the transistor NT6 is connected to the node ND1 of the first circuit unit 51a. The transistor NT6 is provided to turn off the transistor NT4 when the transistor NT5 is on. The source of the transistor NT7 is connected to the node ND2 via the transistor NT8, and the drain is connected to the clock signal line (CKV1). The capacitor C2 is connected between the gate and source of the transistor NT4.

  The shift register circuit units 52 to 55 in the second and subsequent stages have the same circuit configuration as the shift register circuit unit 51 in the first stage. Specifically, the second-stage and subsequent shift register circuit sections 52 to 55 have first circuit sections 52 a to 55 a each having the same circuit configuration as the first circuit section 51 a of the first-stage shift register circuit section 51. And second circuit portions 52b to 55b having the same circuit configuration as the second circuit portion 51b.

  Second-stage shift register circuit portion 52 includes n-channel transistors NT11 to NT18 corresponding to transistors NT1 to NT8 of first-stage shift register circuit portion 51, and capacitors C11 and C12 corresponding to capacitors C1 and C2. . The n-channel transistor NT14 is an example of the “sixth transistor” in the present invention, and the capacitor C12 is an example of the “second capacitor” in the present invention. Hereinafter, n-channel transistors NT11 to NT18 are referred to as transistors NT11 to NT18, respectively. The third-stage shift register circuit unit 53 includes n-channel transistors NT21 to NT28 corresponding to the transistors NT1 to NT8 of the first-stage shift register circuit unit 51, and capacitors C21 and C22 corresponding to the capacitors C1 and C2. including. The n-channel transistor NT24 is an example of the “sixth transistor” or the “seventh transistor” in the present invention, and the capacitor C22 is an example of the “second capacitor” in the present invention. Hereinafter, n-channel transistors NT21 to NT28 are referred to as transistors NT21 to NT28, respectively.

  The fourth-stage shift register circuit unit 54 includes n-channel transistors NT31 to NT38 corresponding to the transistors NT1 to NT8 of the first-stage shift register circuit unit 51, and capacitors C31 and C32 corresponding to the capacitors C1 and C2. including. The n-channel transistor NT34 is an example of the “sixth transistor” or “seventh transistor” in the present invention, and the capacitor C32 is an example of the “second capacitor” in the present invention. Hereinafter, n-channel transistors NT31 to NT38 are referred to as transistors NT31 to NT38, respectively. The fifth-stage shift register circuit unit 55 includes n-channel transistors NT41 to NT48 corresponding to the transistors NT1 to NT8 of the first-stage shift register circuit unit 51, and capacitors C41 and C42 corresponding to the capacitors C1 and C2. including. The n-channel transistor NT44 is an example of the “sixth transistor” or the “seventh transistor” in the present invention, and the capacitor C42 is an example of the “second capacitor” in the present invention. Hereinafter, n-channel transistors NT41 to NT48 are referred to as transistors NT41 to NT48, respectively.

  The transistors NT12 and NT17 of the second-stage shift register circuit section 52 and the transistors NT32 and NT37 of the fourth-stage shift register circuit section 54 are connected to the clock signal line (CKV2). The transistors NT22 and NT27 of the third-stage shift register circuit unit 53 and the transistors NT42 and NT47 of the fifth-stage shift register circuit unit 55 are connected to the clock signal line (CKV1). That is, the clock signal line (CKV1) and the clock signal line (CKV2) are alternately connected for each stage.

  Scan direction switching circuit unit 60 includes n-channel transistors NT51 to NT60. Hereinafter, n-channel transistors NT51 to NT60 are referred to as transistors NT51 to NT60, respectively. The transistors NT51 to NT60 are all composed of TFTs made of n-type MOS transistors.

  In the transistors NT51 to NT55, one of the source / drain and the other of the source / drain are connected to each other in this order. The gates of the transistors NT51, NT53 and NT55 are connected to a scan direction switching signal line (CSV), and the gates of the transistors NT52 and NT54 are connected to an inverted scan direction switching signal line (XCSV). Yes. That is, the scan direction switching signal line (CSV) and the inverted scan direction switching signal line (XCSV) are alternately connected to the gates of the transistors NT51 to NT55, respectively.

  In the transistors NT56 to NT60, one of the source / drain and the other of the source / drain are connected to each other in this order. An inverted scan direction switching signal line (XCSV) is connected to the gates of the transistors NT56, NT58 and NT60, and a scan direction switching signal line (CSV) is connected to the gates of the transistors NT57 and NT59. That is, the inverted scan direction switching signal line (XCSV) and the scan direction switching signal line (CSV) are alternately connected to the gates of the transistors NT56 to NT60, respectively.

  When the scan direction is the forward direction, the scan direction switching signal CSV is controlled to be H level (VDD) and the inverted scan direction switching signal XCSV is controlled to be L level (VBB). Therefore, when the scan direction is the forward direction, transistors NT51, NT53, NT55, NT57 and NT59 are turned on, and transistors NT52, NT54, NT56, NT58 and NT60 are turned off. Be controlled. Further, when the scanning direction is the reverse direction, the scanning direction switching signal CSV is controlled to be L level (VBB), and the inverted scanning direction switching signal XCSV is controlled to be H level (VDD). Therefore, when the scan direction is the reverse direction, transistors NT51, NT53, NT55, NT57 and NT59 are turned off, and transistors NT52, NT54, NT56, NT58 and NT60 are turned on. Be controlled.

  The gate of the transistor NT1 of the first-stage shift register circuit unit 51 is connected to the other of the source / drain of the transistor NT51 of the scan direction switching circuit unit 60 (one of the source / drain of the transistor NT52), The node ND3 of the first-stage shift register circuit unit 51 is connected to the other of the source / drain of the transistor NT56 (one of the source / drain of the transistor NT57) of the scan direction switching circuit unit 60.

  In addition, the gate of the transistor NT11 of the second-stage shift register circuit unit 52 is connected to the other of the source / drain of the transistor NT57 of the scan direction switching circuit unit 60 (one of the source / drain of the transistor NT58), The node ND3 of the second-stage shift register circuit unit 52 is connected to the other of the source / drain of the transistor NT52 (one of the source / drain of the transistor NT53) of the scan direction switching circuit unit 60.

  The gate of the transistor NT21 of the third-stage shift register circuit unit 53 is connected to the other of the source / drain of the transistor NT53 of the scan direction switching circuit unit 60 (one of the source / drain of the transistor NT54), The node ND3 of the third-stage shift register circuit unit 53 is connected to the other of the source / drain of the transistor NT58 (one of the source / drain of the transistor NT59) of the scan direction switching circuit unit 60.

  In addition, the gate of the transistor NT31 of the fourth-stage shift register circuit unit 54 is connected to the other of the source / drain of the transistor NT59 of the scan direction switching circuit unit 60 (one of the source / drain of the transistor NT60), The node ND3 of the fourth-stage shift register circuit unit 54 is connected to the other of the source / drain of the transistor NT54 (one of the source / drain of the transistor NT55) of the scan direction switching circuit unit 60.

  Further, the gate of the transistor NT41 of the fifth-stage shift register circuit unit 55 is connected to the other of the source / drain of the transistor NT55 of the scan direction switching circuit unit 60 and the fifth-stage shift register circuit unit 55 The node ND3 is connected to the other of the source / drain of the transistor NT60 of the scan direction switching circuit unit 60.

  By connecting the shift register circuit units 51 to 55 and the scan direction switching circuit unit 60 at each stage as described above, the first circuit unit of the shift register circuit unit at a predetermined stage is connected in the scan direction according to the scan direction. On the other hand, control is performed so that the previous shift output signals (SR11 to SR15) are input. However, the start signal STV is input to the first circuit unit 51 a of the first-stage shift register circuit unit 51.

  The input signal switching circuit unit 70 includes n-channel transistors NT61 to NT70 whose gates are connected to the scan direction switching signal line (CSV) and n-channel transistors whose gates are connected to the inverted scan direction switching signal line (XCSV). Including NT71 to NT80. Hereinafter, n-channel transistors NT61 to NT80 are referred to as transistors NT61 to NT80, respectively. The transistors NT61 to NT80 constituting the input signal switching circuit unit 70 are all constituted by TFTs made of n-type MOS transistors.

  The n-channel transistors connected to the scan direction switching signal line (CSV) and the n-channel transistors whose gates are connected to the inverted scan direction switching signal line (XCSV) are shift register circuit units 51 to 55 at each stage. In contrast, two are arranged respectively. Specifically, corresponding to the first-stage shift register circuit unit 51, the transistors NT61 and NT62 whose gates are connected to the scan direction switching signal line (CSV), and the gates which are the inverted scan direction switching signal lines (XCSV). Transistors NT71 and NT72 connected to are arranged. One of the sources / drains of the transistors NT61 and NT71 is connected to the gate of the transistor NT2 of the first-stage shift register circuit unit 51. The other of the source / drain of the transistor NT61 is connected to the node ND2 of the second-stage shift register circuit unit 52, and the other of the source / drain of the transistor NT71 is connected to the positive potential VDD. One of the sources / drains of the transistors NT62 and NT72 is connected to the gate of the transistor NT7 of the first-stage shift register circuit unit 51. The other of the source / drain of the transistor NT62 is connected to the other of the source / drain of the transistor NT51 (one of the source / drain of the transistor NT52) and the gate of the transistor NT1 of the scan direction switching circuit unit 60 to which the start signal STV is supplied. The other of the source / drain of the transistor NT72 is connected to the node ND2 of the second-stage shift register circuit unit 52.

  Corresponding to the shift register circuit section 52 in the second stage, the transistors NT63 and NT64 whose gates are connected to the scan direction switching signal line (CSV) and the gates are connected to the inverted scan direction switching signal line (XCSV). Transistors NT73 and NT74 are arranged. One of the sources / drains of the transistors NT63 and NT73 is connected to the gate of the transistor NT12 of the second-stage shift register circuit section 52. The other of the source / drain of the transistor NT63 is connected to the node ND2 of the third-stage shift register circuit unit 53, and the other of the source / drain of the transistor NT73 is the node of the first-stage shift register circuit unit 51. Connected to ND2. One of the sources / drains of the transistors NT64 and NT74 is connected to the gate of the transistor NT17 in the second-stage shift register circuit section 52. The other of the source / drain of the transistor NT64 is connected to the node ND2 of the first-stage shift register circuit unit 51, and the other of the source / drain of the transistor NT74 is the node of the third-stage shift register circuit unit 53. Connected to ND2.

  Corresponding to the third-stage shift register circuit unit 53, the transistors NT65 and NT66 whose gates are connected to the scan direction switching signal line (CSV) and the gates are connected to the inverted scan direction switching signal line (XCSV). Transistors NT75 and NT76 are arranged. One of the sources / drains of the transistors NT65 and NT75 is connected to the gate of the transistor NT22 of the third-stage shift register circuit portion 53. The other of the source / drain of the transistor NT65 is connected to the node ND2 of the fourth-stage shift register circuit unit 54, and the other of the source / drain of the transistor NT75 is a node of the second-stage shift register circuit unit 52. Connected to ND2. One of the sources / drains of the transistors NT66 and NT76 is connected to the gate of the transistor NT27 in the third-stage shift register circuit portion 53. The other of the source / drain of the transistor NT66 is connected to the node ND2 of the second-stage shift register circuit unit 52, and the other of the source / drain of the transistor NT76 is the node of the fourth-stage shift register circuit unit 54. Connected to ND2.

  Corresponding to the fourth-stage shift register circuit section 54, the transistors NT67 and NT68 whose gates are connected to the scan direction switching signal line (CSV) and the gates are connected to the inverted scan direction switching signal line (XCSV). Transistors NT77 and NT78 are arranged. One of the sources / drains of the transistors NT67 and NT77 is connected to the gate of the transistor NT32 of the fourth-stage shift register circuit portion 54. The other of the source / drain of the transistor NT67 is connected to the node ND2 of the fifth-stage shift register circuit unit 55, and the other of the source / drain of the transistor NT77 is the node of the third-stage shift register circuit unit 53. Connected to ND2. One of the sources / drains of the transistors NT68 and NT78 is connected to the gate of the transistor NT37 of the fourth-stage shift register circuit portion 54. The other of the source / drain of the transistor NT68 is connected to the node ND2 of the third-stage shift register circuit unit 53, and the other of the source / drain of the transistor NT78 is the node of the fifth-stage shift register circuit unit 55. Connected to ND2.

  Corresponding to the fifth-stage shift register circuit portion 55, the transistors NT69 and NT70 whose gates are connected to the scan direction switching signal line (CSV) and the gates are connected to the inverted scan direction switching signal line (XCSV). Transistors NT79 and NT80 are arranged. One of the sources / drains of the transistors NT69 and NT79 is connected to the gate of the transistor NT42 in the fifth-stage shift register circuit portion 55. The other of the source / drain of the transistor NT69 is connected to the node ND2 of the sixth-stage shift register circuit unit (not shown), and the other of the source / drain of the transistor NT79 is connected to the node of the fourth-stage shift register circuit unit 54. It is connected to the node ND2. One of the sources / drains of the transistors NT70 and NT80 is connected to the gate of the transistor NT47 of the fifth-stage shift register circuit portion 55. The other of the source / drain of the transistor NT70 is connected to the node ND2 of the fourth-stage shift register circuit section 54, and the other of the source / drain of the transistor NT80 is connected to the sixth-stage shift register circuit section (not shown). It is connected to the node ND2.

  By configuring the transistors NT61 to NT80 constituting the input signal switching circuit unit 70 as described above, when the scan direction is the forward direction, the transistors NT61 to NT70 are turned on, and the transistors NT71 to NT71 It is controlled so that NT80 is turned off. Further, by connecting the shift register circuit units 51 to 55 of each stage and the input signal switching circuit unit 70 as described above, the first circuit unit of the shift register circuit unit of the predetermined stage is scanned according to the scan direction. The next-stage shift signal (SR1 to SR5) is input to the direction, and the second-stage circuit of the predetermined-stage shift register circuit unit is shifted to the second stage in the scan direction (SR1 to SR5). Is controlled to be input. However, the start signal STV is input to the first circuit unit 51 a of the first-stage shift register circuit unit 51.

  The logic synthesis circuit units 81 to 83 are connected to a dummy gate line (Dummy), a first-stage gate line (Gate1), and a second-stage gate line (Gate2), respectively. Each of the logic synthesis circuit units 81 to 83 performs logic synthesis of the shift signal output from the corresponding shift register circuit unit of the predetermined stage and the shift signal output from the shift register circuit unit of the next stage of the predetermined stage. Thus, the shift output signal is output to the gate line of each stage. The logic composition circuit unit 81 connected to the dummy gate line (Dummy) includes n-channel transistors NT81 to NT84, diode-connected n-channel transistors NT85 and NT86, and a capacitor C81. The n-channel transistor NT81 is an example of the “first transistor” in the present invention, and the n-channel transistor NT82 is an example of the “second transistor” in the present invention. The n-channel transistor NT83 is an example of the “third transistor” of the present invention, the n-channel transistor NT84 is an example of the “fifth transistor” of the present invention, and the n-channel transistors NT85 and NT86 are the present invention. This is an example of the “fourth transistor”. The capacitor C81 is an example of the “first capacitor” in the present invention. Hereinafter, n-channel transistors NT81 to NT86 are referred to as transistors NT81 to NT86, respectively.

  Further, the potential fixing circuit portion 81a is configured by the transistors NT83 to NT86 and the capacitor C81. The potential fixing circuit unit 81a is provided to fix the L level potential of the shift output signal when the L level shift output signal is output from the logic synthesis circuit unit 81 to the dummy gate line (Dummy). Yes. The transistors NT81 to NT86 constituting the logic synthesis circuit unit 81 are all constituted by TFTs made of n-type MOS transistors. The drain of the transistor NT81 is connected to the enable signal line (ENB), and the source is connected to the drain of the transistor NT82. The enable signal line (ENB) is an example of the “first signal line” in the present invention. The source of the transistor NT82 is connected to the node ND4 (dummy gate line). The gate of the transistor NT81 is connected to the node ND2 from which the shift signal SR2 of the second-stage shift register circuit unit 52 is output, and the gate of the transistor NT82 is the shift signal of the third-stage shift register circuit unit 53. It is connected to the node ND2 from which SR3 is output.

  The source of the transistor NT83 is connected to the negative potential VBB and the drain is connected to the node ND4 (dummy gate line). The gate of this transistor NT83 is connected to the node ND5. The source of the transistor NT84 is connected to the negative potential VBB, and the drain is connected to the node ND5. The gate of the transistor NT84 is connected to the node ND4 (dummy gate line). One electrode of the capacitor C81 is connected to the negative potential VBB, and the other electrode is connected to the node ND5. The node ND5 is connected to the node ND3 from which the shift output signal SR11 of the first-stage shift register circuit unit 51 is output via the transistor NT85, and is shifted to the fourth stage via the transistor NT86. The shift signal SR14 of the register circuit unit 54 is connected to a node ND3 from which the shift signal SR14 is output.

  The logic synthesis circuit unit 82 connected to the first-stage gate line (Gate1) has the same circuit configuration as the logic synthesis circuit unit 81 connected to the dummy gate line (Dummy). Specifically, the logic synthesis circuit unit 82 connected to the first-stage gate line (Gate1) includes transistors NT81 to NT86 of the logic synthesis circuit unit 81 connected to the dummy gate line (Dummy), and a capacitor C81. And n-channel transistors NT91 to NT96 and a capacitor C91. The n-channel transistor NT91 is an example of the “first transistor” in the present invention, and the n-channel transistor NT92 is an example of the “second transistor” in the present invention. The n-channel transistor NT93 is an example of the “third transistor” of the present invention, the n-channel transistor NT94 is an example of the “fifth transistor” of the present invention, and the n-channel transistors NT95 and NT96 are the present invention. This is an example of the “fourth transistor”. The capacitor C91 is an example of the “first capacitor” in the present invention. Hereinafter, n-channel transistors NT91 to NT96 are referred to as transistors NT91 to NT96, respectively. Further, a potential fixing circuit portion 82a corresponding to the potential fixing circuit portion 81a of the logic synthesis circuit portion 81 connected to the dummy gate line (Dummy) is configured by transistors NT93 to NT96 and a capacitor C91.

  In the logic synthesis circuit unit 82 connected to the first-stage gate line (Gate1), the gate of the transistor NT91 is connected to the node ND2 from which the shift signal SR3 of the third-stage shift register circuit unit 53 is output. In addition, the gate of the transistor NT92 is connected to the node ND2 to which the shift signal SR4 of the fourth-stage shift register circuit unit 54 is output. The node ND5 is connected to the node ND3 from which the shift signal SR12 of the second-stage shift register circuit unit 52 is output via the transistor NT95, and is connected to the fifth-stage shift register via the transistor NT96. The shift signal SR15 of the circuit unit 55 is connected to a node ND3 from which the shift signal SR15 is output.

  The logic synthesis circuit unit 83 connected to the second-stage gate line (Gate2) has the same circuit configuration as the logic synthesis circuit unit 81 connected to the dummy gate line (Dummy). Specifically, the logic synthesis circuit unit 83 connected to the second-stage gate line (Gate2) includes transistors NT81 to NT86 of the logic synthesis circuit unit 81 connected to the dummy gate line (Dummy), and a capacitor C81. And n-channel transistors NT101 to NT106 and a capacitor C101. The n-channel transistor NT101 is an example of the “first transistor” in the present invention, and the n-channel transistor NT102 is an example of the “second transistor” in the present invention. The n-channel transistor NT103 is an example of the “third transistor” in the present invention, the n-channel transistor NT104 is an example of the “fifth transistor” in the present invention, and the n-channel transistors NT105 and NT106 are in the present invention. This is an example of the “fourth transistor”. The capacitor C101 is an example of the “first capacitor” in the present invention. Hereinafter, n-channel transistors NT101 to NT106 are referred to as transistors NT101 to NT106, respectively. Further, a potential fixing circuit portion 83a corresponding to the potential fixing circuit portion 81a of the logic synthesis circuit portion 81 connected to the dummy gate line (Dummy) is constituted by transistors NT103 to NT106 and a capacitor C101.

  In the logic synthesis circuit unit 83 connected to the second-stage gate line (Gate2), the gate of the transistor NT101 is connected to the node ND2 from which the shift signal SR4 of the fourth-stage shift register circuit unit 54 is output. In addition, the gate of the transistor NT102 is connected to the node ND2 from which the shift signal SR5 of the fifth-stage shift register circuit unit 55 is output. The node ND5 is connected to the node ND3 from which the shift signal SR13 of the third-stage shift register circuit unit 53 is output via the transistor NT105, and is connected to the sixth-stage (not shown) via the transistor NT106. The shift register circuit portion is connected to a node ND3 to which a shift signal is output.

  FIG. 3 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the first embodiment of the present invention. Next, the operation of the V driver of the liquid crystal display device according to the first embodiment will be described with reference to FIGS.

  First, a description will be given of a case where a shift output signal whose timing is shifted is sequentially output to the gate line of each stage along the forward direction in FIG. 2 (forward scan). In this forward scan, the scan direction switching signal CSV is held at the H level, and the inverted scan direction switching signal XCSV is held at the L level. Thereby, at the time of forward scanning, the transistors NT51, NT53, NT55, NT57, NT59 and NT61 to 70 to which the scanning direction switching signal CSV is inputted to the gate are held in the ON state. Further, the transistors NT52, NT54, NT56, NT58, NT60 and NT71-80, to which the inverted scan direction switching signal XCSV is input, are held in the OFF state. In the initial state, the shift signals SR1 to SR5 and the output signals SR11 to SR15 output from the shift register circuit units 51 to 55 in each stage are at the L level. Further, the shift output signals Dummy, Gate1, and Gate2 output from the logic synthesis circuit units 81 to 83 to the gate lines of the respective stages are all at the L level. In this state, as shown in FIG. 3, the start signal STV is raised to the H level. As a result, the H-level start signal STV is input to the gate of the transistor NT1 of the first-stage shift register circuit section 51 through the transistor NT51 in the on state. For this reason, the transistor NT1 is turned on. Thereafter, the clock signal CKV1 input to the drain of the transistor NT2 rises to the H level.

  At this time, the L-level shift signal SR2 output from the second-stage shift register circuit unit 52 is input to the gate of the transistor NT2 of the first-stage shift register circuit unit 51 via the on-state transistor NT6. Yes. As a result, the transistor NT2 is turned off. Therefore, even if the transistor NT1 is in the on state, no through current flows between the clock signal line (CKV1) and the negative potential VBB via the transistors NT1 and NT2.

  In addition, since the transistor NT1 of the first-stage shift register circuit unit 51 is on and the transistor NT2 is off, an L level potential is supplied from the negative potential VBB through the transistor NT1, thereby causing the node ND1 to The potential drops to the L level. Thereby, the transistors NT5 and NT6 whose gates are connected to the node ND1 of the first-stage shift register circuit unit 51 are turned off. The H level start signal STV is also input to the gate of the transistor NT7 in the first-stage shift register circuit section 51 via the transistors NT51 and NT62 in the on state. As a result, the transistor NT7 is turned on. Then, the potential of the clock signal CKV1 input to the drain of the transistor NT7 rises to the H level.

  At this time, even if the transistor NT7 is in the on state, the transistor NT6 is in the off state, so that a through current is generated between the clock signal line (CKV1) and the negative potential VBB via the transistors NT7, NT8, and NT6. There is no flow. Further, when the H level clock signal CKV1 is input via the transistor NT7 and the diode-connected transistor NT8, the potential of the node ND2 of the first-stage shift register circuit unit 51 rises to the H level. Thereby, the transistor NT4 is turned on. Then, an H level (VDD) potential is supplied from the positive potential VDD to the node ND3 through the transistor NT4.

  At this time, even if the transistor NT4 is in the on state, since the transistor NT5 is in the off state, no through current flows between the positive potential VDD and the negative potential VBB via the transistors NT4 and NT5. . Then, an H level (VDD) potential is supplied from the positive potential VDD to the node ND3 via the transistor NT4, whereby the potential of the node ND3 of the first-stage shift register circuit portion rises to the VDD side. At this time, the potential of the node ND2 of the first-stage shift register circuit portion is booted as the potential of the node ND3 is increased so that the gate-source voltage of the transistor NT4 is maintained by the capacitor C2. To rise. As a result, the potential of the node ND2 rises to a potential that is higher than the VDD by a predetermined voltage (Vα) that is equal to or higher than the threshold voltage (Vt). As a result, an H-level shift signal SR1 having a potential (VDD + Vα) of VDD + Vt or higher is output from the node ND2 of the first-stage shift register circuit unit 51. At the same time, an H level (VDD) output signal SR11 is output from the node ND3 of the first-stage shift register circuit portion.

  Then, the H level (VDD) output signal SR11 of the first-stage shift register circuit unit 51 is input to the gate of the transistor NT83 via the diode-connected transistor NT85 of the logic synthesis circuit unit 81 connected to the dummy gate line. Is done. Thereby, the transistor NT83 is turned on. At this time, the L-level shift signal SR2 is input from the second-stage shift register circuit section 52 to the gate of the transistor NT81 of the logic synthesis circuit section 81, and the third-stage shift signal SR2 is input to the gate of the transistor NT82. An L level shift signal SR3 is inputted from the shift register circuit portion 53. Thereby, both transistors NT81 and NT82 are in the off state. For this reason, the L-level potential is supplied from the negative potential VBB via the transistor NT83, so that the L-level shift output signal Dummy is output from the node ND4 of the logic synthesis circuit unit 81 to the dummy gate line. .

  Further, the H level (VDD) output signal SR11 of the first-stage shift register circuit section 51 is also input to the gate of the transistor NT11 of the second-stage shift register circuit section 52 via the transistor NT57 in the on state. . Thereby, the transistor NT11 is turned on. Then, the H level shift signal SR1 of the first-stage shift register circuit unit 51 is input to the gate of the transistor NT17 of the second-stage shift register circuit unit 52 via the transistor NT64 in the on state. Thereby, the transistor NT17 is turned on. The L-level shift signal SR3 output from the node ND2 of the third-stage shift register circuit unit 53 is input to the gate of the transistor NT12 of the second-stage shift register circuit unit 52. Thereby, the transistor NT12 is in an off state. Thereafter, the potential of the clock signal CKV2 input to the drains of the transistors NT12 and NT17 of the second-stage shift register circuit unit 52 rises to the H level.

  At this time, the shift signal SR1 is at a potential (VDD + Vα) that is higher than VDD by a predetermined voltage Vα that is equal to or higher than the threshold voltage (Vt). When this shift signal SR1 is input to the gate of the transistor NT17 in the second-stage shift register circuit unit 52, the gate voltage of the transistor NT64 is equal to the potential (VDD) of the scan direction switching signal CSV, so the gate voltage of the transistor NT17 is It is charged to (VDD-Vt). Thereafter, since the clock signal CKV2 rises from the L level (VBB) to the H level (VDD), the gate potential of the transistor NT17 is changed from VDD-Vt to VDD while the gate-source voltage is held by the MOS capacitance of the transistor NT17. And the potential difference between VBB increases. For this reason, the potential of the node ND2 of the second-stage shift register circuit portion 52 rises to the H level (VDD) potential without decreasing by the threshold voltage (Vt) of the transistor NT17. Thereafter, in the same manner as the operation of the first-stage shift register circuit unit 51, an H-level shift signal SR2 having a potential (VDD + Vα) of VDD + Vt or higher is output from the node ND2 of the second-stage shift register circuit unit 52. Is output. At the same time, an H level (VDD) output signal SR12 is output from the node ND3 of the second-stage shift register circuit section 52.

  Then, the H level (VDD + Vα> VDD + Vt) shift signal SR2 of the second-stage shift register circuit unit 52 is input to the gate of the transistor NT81 of the logic composition circuit unit 81 connected to the dummy gate line. The shift signal SR2 of H level (VDD + Vα> VDD + Vt) is input to the drains of the transistors NT61 and NT66 which are turned on when the VDD scan direction switching signal CSV is input to the gate. As a result, the source potentials of the transistors NT61 and NT66 become (VDD−Vt), so that the gate of the transistor NT2 of the first-stage shift register circuit unit 51 and the transistor NT27 of the third-stage shift register circuit unit 53 Is supplied with a potential of (VDD−Vt). The H level (VDD) output signal SR12 is input to the gate of the transistor NT21 of the third-stage shift register circuit unit 53 via the transistor NT53 in the on state, and is connected to the first-stage gate line. The signal is input to the gate of the transistor NT93 via the diode-connected transistor NT95 of the synthesis circuit unit 82. Then, the transistor NT81 of the logic composition circuit portion 81 connected to the dummy gate line is turned on when the shift signal SR2 of H level (VDD + Vα) is input to the gate. At this time, the transistor NT82 is held in the off state, and the transistor NT83 is held in the on state. Therefore, the potential of the node ND4 of the logic composition circuit unit 81 connected to the dummy gate line is held at the L level by the L level potential supplied from the negative potential VBB via the transistor NT83. As a result, the L level shift output signal Dummy is continuously output from the node ND4 of the logic synthesis circuit unit 81 to the dummy gate line.

  Further, the transistor NT2 of the first-stage shift register circuit unit 51 is turned on when the potential of (VDD−Vt) is input from the transistor NT61 to the gate. At the same time that the potential of the shift signal SR2 rises to the H level (VDD + Vα), the potential of the clock signal CKV1 input to the drains of the transistors NT2 and NT7 falls to the L level. At this time, the potential of the node ND1 of the first-stage shift register circuit unit 51 is held at the L level. Thereby, the transistors NT5 and NT6 of the first-stage shift register circuit unit 51 are held in the off state. Further, when the clock signal CKV1 falls to the L level, the gate voltage of the transistor NT7 becomes the L level, so that the transistor NT7 is turned off. As a result, the potential of the node ND2 of the first-stage shift register circuit unit 51 is held at the H level (VDD + Vα), so that the H-level (VDD + Vα) shift signal SR1 is output from the first-stage shift register circuit unit 51. It is output continuously. Further, since the potential of the node ND2 of the first-stage shift register circuit unit 51 is held at the H level (VDD + Vα), the transistor NT4 is held in an on state. Output signal SR11 of H level (VDD) is continuously output from node ND3.

  In addition, the transistor NT27 of the third-stage shift register circuit unit 53 is turned on when a potential of (VDD−Vt) is input to the gate, and the transistor NT21 outputs an H level (VDD) to the gate. The signal SR12 is turned on when the signal SR12 is input. At this time, the L-level shift signal SR4 of the fourth-stage shift register circuit section 54 is input to the gate of the transistor NT22 of the third-stage shift register circuit section 53. Thereby, the transistor NT22 is in an off state. Thereafter, the potential of the start signal STV is lowered to the L level. As a result, the transistor NT1 of the first-stage shift register circuit unit 51 is turned off. Therefore, the potential of the node ND1 of the first-stage shift register circuit unit 51 is held at the L level, so that the transistors NT5 and NT6 are held in the off state. Further, when the potential of the start signal STV is lowered to the L level, the transistor NT7 to which the start signal STV is input to the gate is also turned off. Thus, the potential of the node ND2 of the first-stage shift register circuit unit 51 is held at the H level (VDD + Vα), and the potential of the node ND3 is held at the H level (VDD). For this reason, the shift signal SR1 of H level (VDD + Vα) and the output signal SR11 of H level (VDD) are continuously output from the first-stage shift register circuit unit 51.

  Thereafter, the clock signal CKV1 input to the drains of the transistors NT22 and NT27 of the third-stage shift register circuit unit 53 rises to the H level. As a result, in the same manner as the operation of the first-stage shift register circuit unit 51, an H-level shift signal SR3 having a potential (VDD + Vα) of VDD + Vt or higher is output from the node ND2 of the third-stage shift register circuit unit 53. At the same time, an output signal SR13 of H level (VDD) is output from the node ND3 of the third-stage shift register circuit unit 53. Then, the shift signal SR3 at the H level (VDD + Vα> VDD + Vt) is supplied from the gate of the transistor NT82 of the logic synthesis circuit unit 81 connected to the dummy gate line and the gate of the transistor NT91 of the logic synthesis circuit unit 82 connected to the first-stage gate line. And input. The shift signal SR3 at H level (VDD + Vα> VDD + Vt) is input to the drain of the on-state transistor NT63 and to the drain of the on-state transistor NT68. Further, the H level (VDD) output signal SR13 is input to the gate of the transistor NT31 of the fourth-stage shift register circuit section 54 through the transistor NT59 in the on state and is connected to the second-stage gate line. The signal is input to the gate of the transistor NT103 via the diode-connected transistor NT105 of the synthesis circuit unit 83.

  In the first embodiment, in the logic synthesis circuit unit 81 connected to the dummy gate line, the shift signal SR2 and the shift signal SR3 respectively input to the gates of the transistors NT81 and NT82 are both at the H level (VDD + Vα). Transistor NT81 and transistor NT82 are both turned on. Thereby, the enable signal ENB is supplied from the enable signal line via the transistors NT81 and NT82. The enable signal ENB is at the L level when both the shift signals SR1 and SR2 are at the H level, and the potential is switched from the L level to the H level after a short period thereafter. As a result, the potential of the node ND4 of the logic synthesis circuit unit 81 connected to the dummy gate line rises to the H level, so that the H level shift output signal Dummy is output from the logic synthesis circuit unit 81 to the dummy gate line. That is, while the enable signal ENB is at the L level, the potential of the shift output signal Dummy is forcibly held at the L level, and as the potential of the enable signal ENB rises from the L level to the H level, Raised to H level.

  At this time, in the first embodiment, as the potential of the node ND4 (the potential of the shift output signal Dummy) of the logic composition circuit unit 81 connected to the dummy gate line rises to the H level, the gate is connected to the node ND4. The connected transistor NT84 is turned on. As a result, the L level potential is supplied from the negative potential VBB to the gate of the transistor NT83 via the transistor NT84, so that the transistor NT83 is turned off. Therefore, even when both of the transistors NT81 and NT82 are turned on, the transistor NT83 is turned off, so that the enable signal line (ENB) and the negative potential VBB are connected via the transistors NT81, NT82 and NT83. Through current is suppressed from flowing between.

  In the first embodiment, the high-level shift signals SR2 and SR3 having a potential (VDD + Vα) higher than the VDD by a predetermined voltage (Vα) higher than the threshold voltage (Vt) are applied to the gates of the transistors NT81 and NT82, respectively. Entered. As a result, when the H level enable signal ENB having the potential of VDD is supplied to the drain of the transistor NT81, the potential appearing at the node ND4 of the logic composition circuit portion 81 connected to the dummy gate line is changed from VDD to the transistors NT81 and NT82. Is reduced by the threshold voltage (Vt). For this reason, the potential of the shift output signal Dummy output from the logic synthesis circuit unit 81 to the dummy gate line is suppressed from decreasing from the H level.

  In the logic synthesis circuit unit 82 connected to the first-stage gate line, the shift signal SR3 at the H level (VDD + Vα) of the third-stage shift register circuit unit 53 is input to the gate of the transistor NT91, and the transistor NT92 The L level shift signal SR4 of the fourth-stage shift register circuit section 54 is input to the gate. Further, the H level (VDD) output signal SR12 of the second-stage shift register circuit section 52 is input to the gate of the transistor NT93. Thereby, in the logic synthesis circuit unit 82 connected to the first-stage gate line, the transistors NT91 and NT93 are turned on and the transistor NT92 is turned off. For this reason, the potential of the node ND4 of the logic composition circuit portion 82 connected to the first-stage gate line is held at the L level by the L level potential supplied from the negative potential VBB via the transistor NT93. As a result, the L-level shift output signal Gate1 is continuously output from the node ND4 of the logic synthesis circuit unit 82 to the first-stage gate line.

  In addition, the shift signal SR3 of H level (VDD + Vα> VDD + Vt) is input to the drain of the transistor NT63 which is turned on when the VDD scan direction switching signal CSV is input to the gate, whereby the source potential of the transistor NT63 Becomes (VDD-Vt). As a result, the potential of (VDD−Vt) is input to the gate of the transistor NT12 of the second-stage shift register circuit unit 52. For this reason, the transistor NT12 is turned on. At this time, the potential of the clock signal CKV1 is H level, and the potential of the clock signal CKV2 is L level. As a result, the potential of the node ND1 of the second-stage shift register circuit unit 52 is held at the L level, so that the transistors NT15 and NT16 are held in the off state. At this time, since the gate voltage of the transistor NT18 becomes L level by the clock signal CKV2, the transistor NT18 is turned off. Therefore, the potential of the node ND2 is held at the H level (VDD + Vα). As a result, the H-level (VDD + Vα) shift signal SR2 is continuously output from the second-stage shift register circuit section 52. Further, since the transistor NT15 is held in the off state, the potential of the node ND3 of the second-stage shift register circuit unit 52 is held at the H level (VDD). As a result, the H-level (VDD) output signal SR12 is continuously output from the second-stage shift register circuit section 52.

  Further, in the first-stage shift register circuit unit 51, the (VDD−Vt) potential is input to the gate continuously from the transistor NT61 to which the H level (VDD + Vα) shift signal SR2 is input to the drain, whereby the transistor NT2 is kept on. In this state, the clock signal CKV1 rises from the L level (VBB) to the H level (VDD). Therefore, in the transistor NT2, the gate potential is (VDD−Vt) while the gate-source voltage is held by the MOS capacitance of the transistor NT2. ), The potential difference between VDD and VBB increases. As a result, the potential of the node ND1 of the first-stage shift register circuit unit 51 rises to the H level (VDD) potential without decreasing by the threshold voltage (Vt) of the transistor NT2.

  Then, when the potential of the node ND1 of the first-stage shift register circuit unit 51 rises to the H level, the transistors NT5 and NT6 are turned on. At this time, since the transistor NT7 is in an off state, an L level potential is supplied from the negative potential VBB via the transistor NT6, whereby the potential of the node ND2 of the first-stage shift register circuit unit 51 is at the L level. To drop. As a result, the potential of the shift signal SR1 output from the first-stage shift register circuit unit 51 is lowered to the L level. Further, when the potential of the node ND2 is lowered to the L level, the transistor NT4 is turned off. As a result, an L level potential is supplied from the negative potential VBB via the transistor NT5, whereby the potential of the node ND3 of the first-stage shift register circuit unit 51 is lowered to the L level. Therefore, the potential of the output signal SR11 output from the first-stage shift register circuit unit 51 is lowered to the L level. Further, when the potential of the node ND1 of the first-stage shift register circuit unit 51 rises to H level, the capacitor C1 is charged. As a result, the transistor NT1 is turned on next time, and the potential of the node ND1 is held at the H level until the L level potential is supplied from the negative potential VBB via the transistor NT1. Therefore, transistors NT5 and NT6 are held in the on state until the next time transistor NT1 is turned on, so that the potentials of shift signal SR1 and output signal SR11 are held at the L level.

  Further, as shown in FIG. 3, before the potential of the shift signal SR1 is lowered to the L level, the potential of the enable signal ENB is lowered from the H level to the L level. Thereby, in the logic composition circuit unit 81 connected to the dummy gate line, the potential of the node ND4 is lowered to the L level by supplying the L level potential via the transistors NT81 and NT82. For this reason, the potential of the shift output signal Dummy output from the logic synthesis circuit unit 81 to the dummy gate line falls to the L level.

  In the fourth-stage shift register circuit portion 54, the potential of (VDD−Vt) is input to the gate of the transistor NT37 from the transistor NT68 to which the H level (VDD + Vα) shift signal SR3 is input to the drain. Further, the output signal SR13 of H level (VDD) is input to the gate of the transistor NT31. The L-level shift signal SR5 is input from the fifth-stage shift register circuit unit 55 to the gate of the transistor NT32. In this state, the potential of clock signal CKV2 input to the drains of transistors NT32 and NT37 rises to the H level. Thus, in the same manner as the operation of the first-stage shift register circuit unit 51, the H-level shift signal SR4 having a potential (VDD + Vα) of VDD + Vt or higher from the fourth-stage shift register circuit unit 54, and the H level. The output signal SR14 of (VDD) is output.

  In the first embodiment, the output signal SR14 at the H level (VDD) is input via the transistor NT86 that is diode-connected to the gate of the transistor NT83 of the logic composition circuit unit 81 connected to the dummy gate line. As a result, the transistor NT83 is turned on. For this reason, when the L level potential is supplied from the negative potential VBB via the transistor NT83, the potential of the node ND4 of the logic composition circuit portion 81 connected to the dummy gate line is fixed to the L level. As a result, the potential of the shift output signal Dummy output from the logic synthesis circuit unit 81 to the dummy gate line is fixed at the L level. In the first embodiment, when the output signal SR14 of H level (VDD) is input to the gate of the transistor NT83, the capacitor C81 is charged. As a result, the potential of the node ND5 (the gate potential of the transistor NT83) remains at the H level until the transistor NT84 is turned on and the L level potential is supplied from the negative potential VBB via the transistor NT84. Retained. Therefore, the transistor NT83 is kept on until the transistor NT84 is turned on next time, so that the potential of the shift output signal Dummy output from the logic synthesis circuit unit 81 to the dummy gate line is fixed at the L level. It is held in the state.

  In the logic composition circuit unit 82 connected to the first-stage gate line, the H level (VDD + Vα) shift signal SR3 is input to the gate of the transistor NT91, and the H level (VDD + Vα) shift is applied to the gate of the transistor NT92. Signal SR4 is input. As a result, both the transistor NT81 and the transistor NT82 are turned on, so that the enable signal ENB is supplied from the enable signal line via the transistors NT81 and NT82. The enable signal ENB is at the L level when both of the transistors NT81 and NT82 are turned on by the shift signals SR1 and SR2 both being at the H level, and after a short period of time, the L level to the H level. The potential switches to. As a result, the potential of the node ND4 of the logic synthesis circuit unit 82 connected to the first-stage gate line rises to the H level, so that the H-level shift output signal Gate1 is output from the logic synthesis circuit unit 82 to the first-stage gate line. Is output. That is, the potential of the shift output signal Gate1 is forcibly held at the L level while the enable signal ENB is at the L level, and as the potential of the enable signal ENB rises from the L level to the H level, Raised from L level to H level. Therefore, when the enable signal ENB is at the L level, the shift output signal Dummy output from the logic synthesis circuit unit 81 to the dummy gate line is also forcibly held at the L level, so that the shift output signal Dummy is changed from the H level to the L level. It is suppressed that the timing when the level falls and the timing when the shift output signal Gate1 rises from the L level to the H level are overlapped. As a result, the occurrence of noise due to the overlap of the timing at which the shift output signal Dummy falls from the H level to the L level and the timing at which the shift output signal Gate1 rises from the L level to the H level is suppressed. .

  Thereafter, operations similar to those of the above-described first to third stage shift register circuit units 51 to 53 are sequentially performed in the fourth and subsequent stage shift register circuit units 54 and 55. The same operation as that of the logic synthesis circuit unit 81 connected to the dummy gate line described above is performed in the logic synthesis circuit units 82 and 83 connected to the first and subsequent dummy gate lines. Then, the timing at which the H level shift signal and the H level output signal are output from the shift register circuit portion of each stage is shifted. Along with this, the timing at which both the preceding stage shift signal and the next stage shift signal become H level also shifts as the stage proceeds. As a result, the enable signal ENB rises to the H level in a period in which the H level shift signal at the previous stage and the H level shift signal at the next stage overlap, whereby the corresponding gate line from the logic synthesis circuit unit at each stage. Also, the timing at which the H level shift output signal is output shifts as it proceeds to the subsequent stage. Then, the gate lines of each stage are sequentially driven by the H level shift output signal shifted in timing.

  As described above, the gate lines of each stage of the liquid crystal display device according to the first embodiment are sequentially driven (scanned). Then, the above operation is repeated until the last gate line scan is completed. Thereafter, the above operation is repeated from the first-stage shift register circuit unit 51 again.

  Next, when a shift output signal whose timing is shifted is sequentially output to the gate lines of each stage along the reverse direction in FIG. 2 (in the case of reverse scan), the scan direction switching signal CSV is L level. And the inverted scan direction switching signal XCSV is held at the H level. Thereby, at the time of reverse scanning, the transistors NT51, NT53, NT55, NT57, NT59 and NT61-70 to which the scanning direction switching signal CSV is input to the gate are held off, and the inverted scanning direction switching signal XCSV is gated. Transistors NT52, NT54, NT56, NT58, NT60, and NT71-80 that are input to are kept on. Then, during the backward scan, the same operation as in the forward scan described above is performed in the shift register circuit unit at each stage and the logic synthesis circuit unit connected to the gate line at each stage along the reverse direction in FIG. Done. At this time, when the shift signal and the output signal are input from the previous shift register circuit unit to the next shift register circuit unit, or the shift signal and the output signal are input from the next shift register circuit unit to the previous shift register circuit unit. Is input via the transistors NT52, NT54, NT56, NT58, NT60 and NT71-80 which are turned on by the H-level inverted scan direction switching signal XSCV.

  In the first embodiment, as described above, the previous shift register circuit units 52 to 55 that output the shift signals SR2 to SR5, the next shift register circuit units 53 to 55 that output the shift signals SR3 to SR5, The shift register circuit of the V driver 5 is configured to include logic synthesis circuit units 81 to 83 that logically synthesize the previous stage shift signal and the next stage shift signal and output the shift output signals Dummy, Gate1, and Gate2. Thus, for example, the shift signal SR2 of the second-stage shift register circuit unit 52 and the shift signal SR3 of the third-stage shift register circuit unit 53 are logically synthesized and the shift output signal is output from the logic synthesis circuit unit 81. Dummy can be output, and the shift signal SR3 of the third stage shift register circuit unit 53 and the fourth stage The shift signal SR4 of the register circuit unit 54 is logically synthesized, and the next-stage shift output signal Gate1 that does not overlap with the shift output signal Dummy is output from the logic synthesis circuit unit 82. it can. As a result, two stages of shift register circuit units used to output the shift output signal Dummy and two stages of shift register circuit units used to output the next stage shift output signal Gate1 are equivalent to one stage. The shift register circuit portion 53 can be shared. For this reason, since the number of stages of the shift register circuit portion constituting the shift register circuit of the V driver 5 can be reduced, the circuit configuration of the liquid crystal display device including the V driver can be simplified.

  In addition, by configuring the V driver 5 with only n-channel transistors, the number of ion implantation steps and the number of times of ion implantation can be increased when forming the V driver 5 as compared with the case where the V driver 5 is configured with n-channel transistors and p-channel transistors. The number of ion implantation masks can be reduced. Thereby, while being able to suppress that a manufacturing process becomes complicated, it can suppress that manufacturing cost increases.

  In the first embodiment, in the logic synthesis circuit unit, the shift signal SR2 (SR3, SR4) input to the gate of the transistor NT81 (NT91, NT101) and the gate of the transistor NT82 (NT92, NT102) are input. By configuring the transistors NT83 (NT93, NT103) to be in an off state when the shift signal SR3 (SR4, SR5) is at the H level, the transistors NT81 (NT91, NT101) and the transistors NT82 (NT92, NT102) The transistor NT83 (NT93, NT103) can be turned off when is turned on. As a result, a through current flows between the enable signal line (ENB) and the negative potential VBB through the transistors NT81 (NT91, NT101), the transistors NT82 (NT92, NT102), and the transistors NT83 (NT93, NT103). Can be suppressed. Thereby, it is possible to suppress an increase in current consumption of the liquid crystal display device including the V driver.

(Second Embodiment)
FIG. 4 is a plan view illustrating a liquid crystal display device according to a second embodiment of the present invention. FIG. 5 is a circuit diagram inside the V driver of the liquid crystal display device according to the second embodiment shown in FIG. With reference to FIGS. 4 and 5, in the second embodiment, a case will be described in which the V driver of the first embodiment is configured by a p-channel transistor.

  First, referring to FIG. 4, in the second embodiment, a display unit 2a is provided on a substrate 1a. In the display unit 2a, pixels 20a are arranged in a matrix. Note that in FIG. 4, only one pixel 20 a is illustrated for simplification of the drawing. Each pixel 20a includes a p-channel transistor 21a (hereinafter referred to as a transistor 21a), a pixel electrode 22a, a counter electrode 23a common to each pixel 20a arranged to face the pixel electrode 22a, and a space between the pixel electrode 22a and the counter electrode 23a. The liquid crystal 24a is sandwiched between the liquid crystal 24a and the auxiliary capacitor 25a. The source of the transistor 21a is connected to the drain line, and the drain is connected to the pixel electrode 22a and the auxiliary capacitor 25a. The gate of the transistor 21a is connected to the gate line.

  A horizontal switch (HSW) 3a and an H driver 4a for driving (scanning) the drain line of the display unit 2a are provided on the substrate 1a along one side of the display unit 2a. A V driver 5a for driving (scanning) the gate line of the display unit 2a is provided on the substrate 1a along the other side of the display unit 2a. Note that only two switches are shown in the horizontal switch 3a in FIG. 4, but in actuality, the number of switches corresponding to the number of pixels is arranged. Further, each of the H driver 4a and the V driver 5a of FIG. 4 shows only two shift register circuit portions, but actually, the number of shift register circuit portions corresponding to the number of pixels is arranged. In addition, a drive IC 10 including a signal generation circuit 11 and a power supply circuit 12 is installed outside the substrate 1a as in the first embodiment.

  Referring to FIG. 5, in the second embodiment, a plurality of stages of shift register circuit units 501 to 505, a scan direction switching circuit unit 600, an input signal switching circuit unit 700, A plurality of stages of logic synthesis circuit portions 801 to 803 are provided. In FIG. 5, only the shift register circuit units 501 to 505 for five stages and the logic synthesis circuit units 801 to 803 for three stages are illustrated for simplification of the drawing. A number of shift register circuit sections and logic synthesis circuit sections are provided.

  The first-stage shift register circuit portion 501 includes a first circuit portion 501a and a second circuit portion 501b. First circuit portion 501a includes p-channel transistors PT1 and PT2, a diode-connected p-channel transistor PT3, and a capacitor C1. Second circuit portion 501b includes p-channel transistors PT4, PT5, PT6 and PT7, a diode-connected p-channel transistor PT8, and a capacitor C2. Hereinafter, the p-channel transistors PT1 to PT8 are referred to as transistors PT1 to PT8, respectively.

  The transistors PT1 to PT8 provided in the first circuit portion 501a and the second circuit portion 501b are all configured by TFTs made of p-type MOS transistors. Transistors PT1, PT2, PT6, PT7, and PT8 have two gate electrodes that are electrically connected to each other. The transistors PT1 to PT8 constituting the first-stage shift register circuit unit 501 are respectively positions corresponding to the transistors NT1 to NT8 of the first-stage shift register circuit unit 51 of the first embodiment shown in FIG. It is connected to the. However, unlike the first embodiment, the source of the transistor PT1 is connected to the positive potential VDD, and the drain of the transistor PT4 is connected to the negative potential VBB. The sources of the transistors PT5 and PT6 are connected to the positive potential VDD.

  The shift register circuit units 502 to 505 in the second and subsequent stages have the same circuit configuration as the shift register circuit unit 501 in the first stage. Specifically, the second and subsequent stages of shift register circuit units 502 to 505 have first circuit units 502a to 505a having the same circuit configuration as the first circuit unit 501a of the first stage shift register circuit unit 501, respectively. And second circuit portions 502b to 505b having the same circuit configuration as the second circuit portion 501b.

  Second-stage shift register circuit unit 502 includes p-channel transistors PT11 to PT18 corresponding to transistors PT1 to PT8 of first-stage shift register circuit unit 501 and capacitors C11 and C12 corresponding to capacitors C1 and C2. . The p-channel transistor PT14 is an example of the “sixth transistor” in the present invention, and the capacitor C12 is an example of the “second capacitor” in the present invention. Hereinafter, p-channel transistors PT11 to PT18 are referred to as transistors PT11 to PT18, respectively. The third-stage shift register circuit unit 503 includes p-channel transistors PT21 to PT28 corresponding to the transistors PT1 to PT8 of the first stage shift register circuit unit 501, and capacitors C21 and C22 corresponding to the capacitors C1 and C2. including. The p-channel transistor PT24 is an example of the “sixth transistor” or “seventh transistor” in the present invention, and the capacitor C22 is an example of the “second capacitor” in the present invention. Hereinafter, p-channel transistors PT21 to PT28 are referred to as transistors PT21 to PT28, respectively.

  The fourth-stage shift register circuit portion 504 includes p-channel transistors PT31 to PT38 corresponding to the transistors PT1 to PT8 of the first-stage shift register circuit portion 501 and capacitors C31 and C32 corresponding to the capacitors C1 and C2. including. The p-channel transistor PT34 is an example of the “sixth transistor” or “seventh transistor” in the present invention, and the capacitor C32 is an example of the “second capacitor” in the present invention. Hereinafter, p-channel transistors PT31 to PT38 are referred to as transistors PT31 to PT38, respectively. The fifth-stage shift register circuit unit 505 includes p-channel transistors PT41 to PT48 corresponding to the transistors PT1 to PT8 of the first-stage shift register circuit unit 501 and capacitors C41 and C42 corresponding to the capacitors C1 and C2. including. The p-channel transistor PT44 is an example of the “sixth transistor” or the “seventh transistor” in the present invention, and the capacitor C42 is an example of the “second capacitor” in the present invention. Hereinafter, p-channel transistors PT41 to PT48 are referred to as transistors PT41 to PT48, respectively.

  Scan direction switching circuit unit 600 includes p-channel transistors PT51 to PT60. Hereinafter, p-channel transistors PT51 to PT60 are referred to as transistors PT51 to PT60, respectively. The transistors PT51 to PT60 are all constituted by TFTs composed of p-type MOS transistors. The transistors PT51 to PT60 constituting the scan direction switching circuit unit 600 are respectively connected to positions corresponding to the transistors NT51 to NT60 of the scan direction switching circuit unit 60 of the first embodiment shown in FIG.

  Input signal switching circuit unit 700 includes p-channel transistors PT61 to PT80. Hereinafter, p-channel transistors PT61 to PT80 are referred to as transistors PT61 to PT80, respectively. The transistors PT61 to PT80 are all constituted by TFTs composed of p-type MOS transistors. The transistors PT61 to PT80 constituting the input signal switching circuit unit 700 are respectively connected to positions corresponding to the transistors NT61 to NT80 of the input signal switching circuit unit 70 of the first embodiment shown in FIG. However, unlike the first embodiment, the other of the source / drain of the transistor PT71 is connected to the negative potential VBB.

  The logic synthesis circuit units 801 to 803 are connected to a dummy gate line, a first-stage gate line, and a second-stage gate line, respectively. Logic synthesis circuit portion 801 connected to the dummy gate line includes p-channel transistors PT81 to PT84, diode-connected p-channel transistors PT85 and PT86, and a capacitor C81. The p-channel transistor PT81 is an example of the “first transistor” in the present invention, and the p-channel transistor PT82 is an example of the “second transistor” in the present invention. The p-channel transistor PT83 is an example of the “third transistor” in the present invention, the p-channel transistor PT84 is an example of the “fifth transistor” in the present invention, and the p-channel transistors PT85 and PT86 are in the present invention. This is an example of the “fourth transistor”. The capacitor C81 is an example of the “first capacitor” in the present invention. Hereinafter, p-channel transistors PT81 to PT86 are referred to as transistors PT81 to PT86, respectively.

  The potential fixing circuit portion 801a is configured by the transistors PT83 to PT86 and the capacitor C81. The transistors PT81 to PT86 constituting the logic synthesis circuit unit 801 are all constituted by TFTs made of p-type MOS transistors. The transistors PT81 to PT86 constituting the logic synthesis circuit unit 801 connected to the dummy gate line are the transistors NT81 of the logic synthesis circuit unit 81 connected to the dummy gate line of the first embodiment shown in FIG. -It is connected to a position corresponding to NT86. However, the source of the transistor PT83 is connected to the positive potential VDD.

  The logic synthesis circuit unit 802 connected to the first-stage gate line has the same circuit configuration as the logic synthesis circuit unit 801 connected to the dummy gate line. Specifically, the logic synthesis circuit unit 802 connected to the first-stage gate line includes p-channel transistors PT91 to PT96 corresponding to the transistors PT81 to PT86 of the logic synthesis circuit unit 801 connected to the dummy gate line, And a capacitor C91 corresponding to the capacitor C81. The p-channel transistor PT91 is an example of the “first transistor” in the present invention, and the p-channel transistor PT92 is an example of the “second transistor” in the present invention. The p-channel transistor PT93 is an example of the “third transistor” in the present invention, the p-channel transistor PT94 is an example of the “fifth transistor” in the present invention, and the p-channel transistors PT95 and PT96 are in the present invention. This is an example of the “fourth transistor”. The capacitor C91 is an example of the “first capacitor” in the present invention. Hereinafter, p-channel transistors PT91 to PT96 are referred to as transistors PT91 to PT96, respectively. Further, a potential fixing circuit portion 802a corresponding to the potential fixing circuit portion 801a of the logic synthesis circuit portion 801 connected to the dummy gate line is constituted by transistors PT93 to PT96 and a capacitor C91. The transistors PT91 to PT96 constituting the logic synthesis circuit unit 802 connected to the first-stage gate line are respectively connected to the first-stage gate line of the first embodiment shown in FIG. The circuit portion 82 is connected to a position corresponding to the transistors NT91 to NT96. However, the source of the transistor PT93 is connected to the positive potential VDD.

  Further, the logic synthesis circuit unit 803 connected to the second-stage gate line has the same circuit configuration as the logic synthesis circuit unit 801 connected to the dummy gate line. Specifically, the logic synthesis circuit unit 803 connected to the second-stage gate line includes p-channel transistors PT101 to PT106 corresponding to the transistors PT81 to PT86 of the logic synthesis circuit unit 801 connected to the dummy gate line, And a capacitor C101 corresponding to the capacitor C81. The p-channel transistor PT101 is an example of the “first transistor” in the present invention, and the p-channel transistor PT102 is an example of the “second transistor” in the present invention. The p-channel transistor PT103 is an example of the “third transistor” in the present invention, the p-channel transistor PT104 is an example of the “fifth transistor” in the present invention, and the p-channel transistors PT105 and PT106 are in the present invention. This is an example of the “fourth transistor”. The capacitor C101 is an example of the “first capacitor” in the present invention. Hereinafter, p-channel transistors PT101 to PT106 are referred to as transistors PT101 to PT106, respectively. Further, a potential fixing circuit portion 803a corresponding to the potential fixing circuit portion 801a of the logic synthesis circuit portion 801 connected to the dummy gate line is configured by transistors PT103 to PT106 and a capacitor C101. The transistors PT101 to PT106 constituting the logic synthesis circuit unit 803 connected to the second-stage gate line are respectively connected to the second-stage gate line of the first embodiment shown in FIG. The circuit portion 803 is connected to a position corresponding to the transistors NT101 to NT106. However, the source of the transistor PT103 is connected to the positive potential VDD.

  FIG. 6 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the second embodiment of the present invention. Next, the operation of the V driver 5a according to the second embodiment will be described with reference to FIGS. In the V driver 5a according to the second embodiment, a signal having a waveform obtained by inverting the H level and the L level of the start signal STV, the clock signals CKV1 and CKV2, and the enable signal ENB of the first embodiment shown in FIG. These are input as a start signal STV, clock signals CKV1 and CKV2, and an enable signal ENB, respectively. Accordingly, the shift register circuit units 501 to 505 according to the second embodiment shift the shift signals SR1 to SR5 and the output signals SR11 to SR15 output from the shift register circuit units 51 to 55 according to the first embodiment shown in FIG. Signals having waveforms obtained by inverting the H level and the L level are respectively output. Further, the logic synthesis circuit units 801 to 803 according to the second embodiment have the H level of the shift output signals Dummy, Gate1 and Gate2 output from the logic synthesis circuit units 81 to 83 according to the first embodiment shown in FIG. A signal having a waveform obtained by inverting the L level is output. The other operations of the V driver 5a according to the second embodiment are the same as the operations of the V driver 5 according to the first embodiment shown in FIG.

  In the second embodiment, the following operations are performed by connecting capacitors C2, C12, C22, C32, and C42 between the gates and sources of the transistors PT4, PT14, PT24, PT34, and PT44, respectively. Is done. For example, in the second-stage shift register circuit portion 502, the gate potential (shift of the transistor PT14 is shifted as the source potential of the transistor PT14 decreases so that the gate-source voltage of the transistor PT14 to which the capacitor C12 is connected is maintained. The potential of the signal SR2 is reduced. In the third-stage shift register circuit portion 503, the gate potential (shift of the transistor PT24 is shifted as the source potential of the transistor PT24 decreases so that the gate-source voltage of the transistor PT24 to which the capacitor C22 is connected is maintained. The potential of the signal SR3 decreases. As described above, a predetermined voltage (Vα) in which the gate potential of the transistor PT14 (the potential of the shift signal SR2) and the gate potential of the transistor PT24 (the potential of the shift signal SR3) are equal to or higher than the threshold voltage (Vt) than VBB. ) Since the voltage drops to a lower potential, shift signals SR2 and SR3 having potentials (VBB-Vα) lower than VBB-Vt at the gates of the transistors PT81 and PT82 of the logic composition circuit portion 801 connected to the dummy gate line, respectively. Is supplied. As a result, the potential of the shift output signal Dummy output to the dummy gate line via the transistors PT81 and PT82 of the logic synthesis circuit unit 801 increases from VBB by the threshold voltage (Vt) of the transistors PT81 and PT82. Is suppressed.

  Further, in the second embodiment, by configuring as described above, it is possible to obtain the same effects as those of the first embodiment, such as simplifying the circuit configuration of the liquid crystal display device including the V driver. .

(Third embodiment)
FIG. 7 is a circuit diagram inside the V driver of the liquid crystal display device according to the third embodiment of the present invention. Referring to FIG. 7, in the third embodiment, in the configuration of the first embodiment, the drain of the transistor connected to the node from which the output signal of the third and subsequent stages of the shift register circuit section is output is connected to the positive electrode. A case will be described in which an enable signal is supplied instead of the side potential and a shift output signal output from the logic synthesis circuit unit is held at an L level by using an inverted enable signal.

  That is, in the V driver according to the third embodiment, as shown in FIG. 7, a plurality of stages of shift register circuit units 511 to 515, a scan direction switching circuit unit 610, an input signal switching circuit unit 710, and a plurality of stages Logic synthesis circuit units 811 to 813 are provided. In FIG. 7, for simplification of the drawing, only five stages of shift register circuit units 511 to 515 and three stages of logic synthesis circuit units 811 to 813 are shown. A number of shift register circuit sections and logic synthesis circuit sections are provided.

  The first-stage shift register circuit unit 511 has the same circuit configuration as the first circuit unit 51a and the second circuit unit 51b of the first-stage shift register circuit unit 51 of the first embodiment shown in FIG. The first circuit portion 511a and the second circuit portion 511b are provided. The second-stage shift register circuit section 512 has the same circuit configuration as the first circuit section 52a and the second circuit section 52b of the second-stage shift register circuit section 52 of the first embodiment shown in FIG. The first circuit portion 512a and the second circuit portion 512b are provided.

  In the third embodiment, an enable signal line (ENB) is connected to each of the third-stage shift register circuit unit 513, the fourth-stage shift register circuit unit 514, and the fifth-stage shift register circuit unit 515. Has been. Specifically, the third-stage shift register circuit unit 513 includes a first circuit unit 513a and a second circuit unit 513b. The first circuit unit 513a and the second circuit unit 513b are respectively the same circuits as the first circuit unit 53a and the second circuit unit 53b of the third-stage shift register circuit unit 53 of the first embodiment shown in FIG. It has a configuration. In the third embodiment, an enable signal line (ENB) is connected to the drain of the transistor NT24.

  The fourth-stage shift register circuit unit 514 includes a first circuit unit 514a and a second circuit unit 514b. The first circuit unit 514a and the second circuit unit 514b are respectively the same circuits as the first circuit unit 54a and the second circuit unit 54b of the fourth-stage shift register circuit unit 54 of the first embodiment shown in FIG. It has a configuration. In the third embodiment, an enable signal line (ENB) is connected to the drain of the transistor NT34.

  The fifth-stage shift register circuit portion 515 includes a first circuit portion 515a and a second circuit portion 515b. The first circuit portion 515a and the second circuit portion 515b are respectively the same circuits as the first circuit portion 55a and the second circuit portion 55b of the fifth-stage shift register circuit portion 55 of the first embodiment shown in FIG. Having a configuration. In the third embodiment, an enable signal line (ENB) is connected to the drain of the transistor NT44.

  The scan direction switching circuit unit 610 has the same circuit configuration as the scan direction switching circuit unit 60 of the first embodiment shown in FIG. However, in the third embodiment, one of the source / drain of the transistor NT56 and one of the source / drain of the transistor NT57 are not connected. The input signal switching circuit unit 710 of the third embodiment has the same circuit configuration as the input signal switching circuit unit 70 of the first embodiment shown in FIG.

  The logic composition circuit portion 811 connected to the dummy gate line includes transistors NT81 to NT84, a diode-connected transistor NT85, and a capacitor C81. That is, the logic synthesis circuit unit 811 of the third embodiment has a circuit configuration in which the diode-connected transistor NT86 is not provided in the circuit configuration of the logic synthesis circuit unit 81 of the first embodiment shown in FIG. Further, a potential fixing circuit portion 811a is configured by the transistors NT83 to NT85 and the capacitor C81. In the third embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor NT83 via the diode-connected transistor NT85.

  The logic composition circuit portion 812 connected to the first-stage gate line includes transistors NT91 to NT94, a diode-connected transistor NT95, and a capacitor C91. That is, the logic synthesis circuit unit 812 of the third embodiment has a circuit configuration in which the diode-connected transistor NT96 is not provided in the circuit configuration of the logic synthesis circuit unit 82 of the first embodiment shown in FIG. Further, the potential fixing circuit portion 812a is configured by the transistors NT93 to NT95 and the capacitor C91. In the third embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor NT93 via the diode-connected transistor NT95.

  The logic composition circuit portion 813 connected to the second-stage gate line includes transistors NT101 to NT104, a diode-connected transistor NT105, and a capacitor C101. That is, the logic synthesis circuit unit 813 of the third embodiment has a circuit configuration in which the diode-connected transistor NT106 is not provided in the circuit configuration of the logic synthesis circuit unit 83 of the first embodiment shown in FIG. Further, the potential fixing circuit portion 813a is configured by the transistors NT103 to NT105 and the capacitor C101. In the third embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor NT103 via the diode-connected transistor NT105.

  In the third embodiment, in addition to the multiple stages of shift register circuit units 511 to 515, the scan direction switching circuit unit 610, the input signal switching circuit unit 710, and the multiple stages of logic synthesis circuit units 811 to 813. A circuit portion 910 is provided. Circuit portion 910 includes n-channel transistors NT111 to NT113, a diode-connected n-channel transistor NT114, and a capacitor C111. Hereinafter, n-channel transistors NT111 to NT114 are referred to as transistors NT111 to NT114, respectively. The transistors NT111 to NT114 constituting the circuit unit 910 are all constituted by TFTs made of n-type MOS transistors.

  The drain of the transistor NT111 is connected to the enable signal line (ENB), and the source is connected to the node ND6. The gate of the transistor NT111 is connected to the node ND2 of the second-stage shift register circuit unit 512. The source of the transistor NT112 is connected to the negative potential VBB, and the drain is connected to the node ND6. The gate of the transistor NT112 is connected to the node ND7. The source of the transistor NT113 is connected to the negative potential VBB, and the drain is connected to the node ND7. The gate of the transistor NT113 is connected to the node ND6. One electrode of the capacitor C111 is connected to the negative potential VBB, and the other electrode is connected to the node ND7. The node ND6 is connected to the other of the source / drain of the transistor NT56 of the scan direction switching circuit unit 610. The node ND7 is connected to the inverted enable signal line (XENB) through the transistor NT114.

  FIG. 8 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the third embodiment of the present invention. Next, the operation of the V driver according to the third embodiment will be described with reference to FIGS.

  The operation of the V driver according to the third embodiment is basically the same as the operation of the V driver according to the first embodiment. However, in the V driver according to the third embodiment, unlike the first embodiment, the transistor NT24 connected to the node ND3 to which the output signals SR13 to SR15 of the shift register circuit units 513 to 515 at the third and subsequent stages are output. The enable signal ENB is supplied to the drains of .about.NT44 instead of the positive potential VDD. Inversion enable is applied to the gates of the transistors NT83, NT93 and NT103 connected between the negative potential VBB of the logic synthesis circuit units 811 to 813 in each stage and the node ND4 which outputs the shift output signals Dummy, Gate1 and Gate2. The signal XENB is input.

  Specifically, the operations in the first-stage and second-stage shift register circuit sections 511 and 512 (see FIG. 7) are the same as the first-stage and second-stage shift register circuits according to the first embodiment shown in FIG. The operation in the units 51 and 52 is the same. Then, an H level (VDD + Vα) shift signal SR2 is input from the second-stage shift register circuit portion 512 to the drain of the transistor NT66. As a result, the source potential of the transistor NT66 which is turned on when the scan direction switching signal CSV having the VDD potential is input to the gate becomes the potential of (VDD−Vt). Therefore, the potential of (VDD−Vt) is input to the gate of the transistor NT27 of the third-stage shift register circuit portion 513. Further, the output signal SR12 of H level (VDD) is input to the gate of the transistor NT21. The L-level shift signal SR4 is input from the fourth-stage shift register circuit unit 514 to the gate of the transistor NT22. Thereby, transistors NT21 and NT27 are turned on, and transistor NT22 is turned off. Therefore, the L level potential is supplied from the negative potential VBB via the transistor NT21, whereby the potential of the node ND1 of the third-stage shift register circuit portion 513 is lowered to the L level. Thereby, transistors NT25 and NT26 are turned off. In this state, the clock signal CKV1 input to the drain of the transistor NT27 rises from the L level to the H level. As a result, the potential of the node ND2 of the third-stage shift register circuit portion 513 rises to H level, so that the transistor NT24 is turned on. At this time, since the L level enable signal ENB is supplied to the drain of the transistor NT24, the source potential of the transistor NT24 (the potential of the node ND3) is held at the L level.

  Thereafter, in the third embodiment, the potential of the enable signal ENB rises from the L level to the H level. As a result, the potential of the node ND3 of the third-stage shift register circuit portion 513 rises to H level. At this time, the potential of the node ND2 of the third-stage shift register circuit portion 513 is booted as the potential of the node ND3 increases so that the gate-source voltage of the transistor NT24 is maintained by the capacitor C22. Will rise. As a result, the potential of the node ND2 of the third-stage shift register circuit portion 513 rises to a potential (VDD + Vβ> VDD + Vt) higher than the VDD by a predetermined voltage (Vβ) that is equal to or higher than the threshold voltage (Vt). Note that the potential (VDD + Vβ) of the node ND2 at this time is higher than the potential (VDD + Vα) of the node ND2 after the rise in the first embodiment. Then, an H-level shift signal SR3 having a potential (VDD + Vβ) of VDD + Vt or higher is output from the node ND2 of the third-stage shift register circuit portion 513. The shift register circuit units 514 and 515 in the fourth and subsequent stages also operate at the H level output from the shift register circuit unit according to the first embodiment by the same operation as the above-described third shift register circuit unit 513. H-level shift signals SR4 and SR5 having a potential (VDD + Vβ) higher than VDD + Vt that is higher than the shift signal of (VDD + Vα) are output.

  Then, the shift signal SR3 of H level (VDD + Vβ> VDD + Vt) of the third-stage shift register circuit portion 513 is input to the drains of the transistors NT63 and NT68, respectively. As a result, the source potentials of the transistors NT63 and NT68 which are turned on when the scan direction switching signal CSV having the potential of VDD is input to the gate are both set to the potential of (VDD−Vt). Therefore, the potential of (VDD−Vt) is input to the gate of the transistor NT12 of the second-stage shift register circuit unit 512 and the gate of the transistor NT37 of the fourth-stage shift register circuit unit 514. In this state, when the clock signal CKV2 rises from the L level (VBB) to the H level (VDD), the transistor NT12 of the second-stage shift register circuit unit 512 causes the gate-source voltage to be reduced by the MOS capacitance of the transistor NT12. While being held, the gate potential increases from (VDD−Vt) to the potential difference between VDD and VBB. As a result, the potential generated on the node ND1 side of the transistor NT12 is prevented from decreasing from VDD by the threshold voltage (Vt) of the transistor NT12. For this reason, the H-level potential generated at the node ND1 of the second-stage shift register circuit portion 512 is suppressed from decreasing. Further, the clock signal CKV2 rises from the L level (VBB) to the H level (VDD) in a state where the potential of (VDD−Vt) is input to the gate of the transistor NT37 of the fourth-stage shift register circuit portion 514. In the transistor NT37, the gate potential increases from (VDD−Vt) to the potential difference between VDD and VBB while the gate-source voltage is held by the MOS capacitance of the transistor NT37. This suppresses the potential generated on the node ND2 side of the transistor NT37 from dropping from VDD by the threshold voltage (Vt) of the transistor NT37. For this reason, it is possible to suppress the H-level potential generated at the node ND2 of the fourth-stage shift register circuit portion 514 from being lowered. As described above, when the potential of the node ND1 or ND2 rises as the potential of the clock signal CKV1 or CKV2 rises to the H level (VDD) in the shift register circuit portion of each stage, the node ND1 In addition, a decrease in the H level potential generated in ND2 is suppressed.

  The H level (VDD + Vβ) shift signal SR3 of the third-stage shift register circuit portion 513 is also input to the gate of the transistor NT91 of the logic composition circuit portion 812 connected to the first-stage gate line. Further, the H level (VDD + Vβ) shift signal SR4 of the fourth-stage shift register circuit section is input to the gate of the transistor NT92 of the logic synthesis circuit section 812 connected to the first-stage gate line. As a result, in the logic composition circuit unit 812 connected to the first-stage gate line, when the potential of the enable signal ENB input to the drain of the transistor NT91 rises to the H level (VDD) potential, this occurs at the node ND4. The potential is suppressed from dropping from VDD by the threshold voltage (Vt) of transistors NT91 and NT92. Similarly, in the logic synthesis circuit unit connected to the second and subsequent gate lines, the potential of the node ND4 rises as the potential of the enable signal ENB rises to the H level (VDD). Further, the H level potential generated at the node ND4 is suppressed from decreasing. As a result, the H level potential of the shift output signals Gate1 and Gate2 output to the gate line of each stage is suppressed from decreasing.

  In the third embodiment, when the potentials of the shift output signals Dummy, Gate1, and Gate2 output from the logic synthesis circuit units 811 to 813 to the gate lines of the respective stages are fixed to the L level, the potential is set using the inverted enable signal XENB. To fix. For example, in the logic synthesis circuit unit 812 connected to the first-stage gate line, the H-level enable signal ENB is supplied via the transistors NT91 and NT92 which are both turned on, thereby the first-stage gate line. The shift output signal Gate1 to be output to is at the H level. Thereafter, the potential of the enable signal ENB decreases to the L level, and the potential of the inverted enable signal XENB increases to the H level. Thus, the L level enable signal ENB is supplied via the transistors NT91 and NT92, whereby the potential of the shift output signal Gate1 output to the first-stage gate line is lowered to the L level.

  In the third embodiment, when the potential of the inversion enable signal XENB rises to the H level, the inversion enable signal XENB at the H level is connected to the gate of the transistor NT93 via the diode-connected transistor NT95 of the logic synthesis circuit unit 812. Is input. Thereby, the transistor NT93 is turned on. Then, an L level potential is supplied from the negative potential VBB to the node ND4 via the transistor NT93. As a result, the potential of the shift output signal Gate1 output from the logic synthesis circuit unit 812 to the first-stage gate line is fixed to the L level.

  In the third embodiment, the capacitor C91 is charged when the H level inversion enable signal XENB is supplied to the gate of the transistor NT93. As a result, the gate potential of the transistor NT93 (the potential of the node ND5) is kept at the H level until the transistor NT94 is turned on, and the L level potential is supplied from the negative potential VBB through the transistor NT94. Retained. For this reason, the transistor NT93 is held in the on state until the transistor NT94 is turned on next time. Therefore, the shift output signal Gate1 is set to L by the L level potential supplied from the negative potential VBB via the transistor NT93. It is held in a fixed state.

  Then, in the logic synthesis circuit unit of each stage, the potential of the shift output signal is set to the L level using the inverted enable signal XENB by the same operation as the operation of the logic synthesis circuit unit 812 connected to the first-stage gate line. Fixed. Other operations of the V driver according to the third embodiment are the same as those of the V driver according to the first embodiment.

  In the third embodiment, as described above, in the shift register circuit units 513 to 515, the enable signal line is connected to the drains of the transistors NT24, NT34, and NT44, and the clock signal CKV1 (CKV2) is supplied to the gate to enable The signal ENB is configured such that the clock signal CKV1 (CKV2) is switched from the L level to the H level after the clock signal CKV1 (CKV2) rises from the L level to the H level, for example, in the third stage shift register circuit unit 513. As the gate potential of the transistor NT24 is increased from the L level (VBB) to the H level (VDD) by CKV1, the transistor NT24 is turned on, and then the source potential of the transistor NT24 is set to the L level (enable signal ENB). VB ) From can be raised to the H level (VDD). As a result, the gate potential of the transistor NT24 can be increased by the increase (Vβ) of the source potential of the transistor NT24 at that time. In the fourth-stage shift register circuit portion 514, the transistor NT34 is turned on as the gate potential of the transistor NT34 is increased from the L level (VBB) to the H level (VDD) by the clock signal CKV2. Thereafter, the source potential of the transistor NT34 can be raised from the L level (VBB) to the H level (VDD) by the enable signal ENB. As a result, the gate potential of the transistor NT34 can be increased by the increase (Vβ) of the source potential of the transistor NT34 at that time. As a result, the potentials of the shift signals SR3 and SR4 (VDD + Vβ> VDD + Vt) can be made higher than in the case where the drains of the transistors NT24 and NT34 are connected to the fixed positive side potential VDD. In addition, the potentials of the shift signals SR3 and SR4 can be higher than the threshold voltage (Vt) by VDD. Therefore, shift signals SR3 and SR4 having a potential equal to or higher than VDD + Vt can be supplied to the gates of the transistors NT91 and NT92 of the logic composition circuit portion 812 connected to the first-stage gate line, respectively. . As a result, the potential of the shift output signal Gate1 output to the first-stage gate line via the transistors NT91 and NT92 of the logic composition circuit unit 812 is further suppressed from decreasing by the threshold voltage (Vt). be able to.

  In the third embodiment, in addition to the effects described above, the same effects as in the first embodiment can be obtained such that the circuit configuration of the liquid crystal display device including the V driver can be simplified.

(Fourth embodiment)
FIG. 9 is a circuit diagram inside the V driver of the liquid crystal display device according to the fourth embodiment of the present invention. With reference to FIG. 9, in the fourth embodiment, a case where the V driver of the third embodiment is configured by a p-channel transistor will be described.

  That is, in the V driver according to the fourth embodiment, as shown in FIG. 9, a plurality of stages of shift register circuit units 521 to 525, a scan direction switching circuit unit 620, an input signal switching circuit unit 720, and a plurality of stages Logic synthesis circuit units 821 to 823 and a circuit unit 920 are provided. In FIG. 9, for simplification of the drawing, only five stages of shift register circuit units 521 to 525 and three stages of logic synthesis circuit units 821 to 823 are shown. A number of shift register circuit sections and logic synthesis circuit sections are provided.

  The first-stage shift register circuit unit 521 has the same circuit configuration as the first circuit unit 501a and the second circuit unit 501b of the first-stage shift register circuit unit 501 of the second embodiment shown in FIG. The first circuit portion 521a and the second circuit portion 521b are provided. The second-stage shift register circuit unit 522 has the same circuit configuration as the first circuit unit 502a and the second circuit unit 502b of the second-stage shift register circuit unit 502 of the second embodiment shown in FIG. The first circuit portion 522a and the second circuit portion 522b are provided.

  Here, in the fourth embodiment, an enable signal line (ENB) is connected to each of the third-stage shift register circuit section 523, the fourth-stage shift register circuit section 524, and the fifth-stage shift register circuit section 525. Has been. Specifically, the third-stage shift register circuit portion 523 includes a first circuit portion 523a and a second circuit portion 523b. The first circuit unit 523a and the second circuit unit 523b are respectively the same circuits as the first circuit unit 503a and the second circuit unit 503b of the third-stage shift register circuit unit 503 of the second embodiment shown in FIG. It has a configuration. In the fourth embodiment, an enable signal line (ENB) is connected to the drain of the transistor PT24.

  The fourth-stage shift register circuit unit 524 includes a first circuit unit 524a and a second circuit unit 524b. The first circuit unit 524a and the second circuit unit 524b are respectively the same circuits as the first circuit unit 504a and the second circuit unit 504b of the fourth-stage shift register circuit unit 504 of the second embodiment shown in FIG. It has a configuration. In the fourth embodiment, an enable signal line (ENB) is connected to the drain of the transistor PT34. Further, the fifth-stage shift register circuit portion 525 includes a first circuit portion 525a and a second circuit portion 525b. The first circuit unit 525a and the second circuit unit 525b are respectively the same circuits as the first circuit unit 505a and the second circuit unit 505b of the fifth-stage shift register circuit unit 505 of the second embodiment shown in FIG. It has a configuration. In the fourth embodiment, an enable signal line (ENB) is connected to the drain of the transistor PT44.

  The scan direction switching circuit unit 620 has a circuit configuration similar to that of the scan direction switching circuit unit 600 of the second embodiment shown in FIG. However, in the fourth embodiment, one of the source / drain of the transistor PT56 and one of the source / drain of the transistor PT57 are not connected. Further, the input signal switching circuit unit 720 has the same circuit configuration as the input signal switching circuit unit 700 of the second embodiment shown in FIG.

  The logic composition circuit portion 821 connected to the dummy gate line includes transistors PT81 to PT84, a diode-connected transistor PT85, and a capacitor C81. That is, the logic synthesis circuit unit 821 of the fourth embodiment has a circuit configuration in which the diode-connected transistor PT86 is not provided in the circuit configuration of the logic synthesis circuit unit 801 of the second embodiment shown in FIG. The potential fixing circuit portion 821a is configured by the transistors PT83 to PT85 and the capacitor C81. In the fourth embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor PT83 via the diode-connected transistor PT85.

  The logic composition circuit portion 822 connected to the first-stage gate line includes transistors PT91 to PT94, a diode-connected transistor PT95, and a capacitor C91. That is, the logic synthesis circuit unit 822 of the fourth embodiment has a circuit configuration in which the diode-connected transistor PT96 is not provided in the circuit configuration of the logic synthesis circuit unit 802 of the second embodiment shown in FIG. Further, the potential fixing circuit portion 822a is configured by the transistors PT93 to PT95 and the capacitor C91. In the fourth embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor PT93 via the diode-connected transistor PT95.

  The logic composition circuit portion 823 connected to the second-stage gate line includes transistors PT101 to PT104, a diode-connected transistor PT105, and a capacitor C101. That is, the logic synthesis circuit unit 823 of the fourth embodiment has a circuit configuration in which the diode-connected transistor PT106 is not provided in the circuit configuration of the logic synthesis circuit unit 803 of the second embodiment shown in FIG. In addition, the potential fixing circuit portion 823a is configured by the transistors PT103 to PT105 and the capacitor C101. In the fourth embodiment, the inversion enable signal line (XENB) is connected to the gate (node ND5) of the transistor PT103 via the diode-connected transistor PT105.

  The circuit unit 920 of the fourth embodiment includes p-channel transistors PT111 to PT113, a diode-connected p-channel transistor PT114, and a capacitor C111. Hereinafter, p-channel transistors PT111 to PT114 are referred to as transistors PT111 to PT114, respectively. The transistors PT111 to PT114 constituting the circuit unit 920 are respectively connected to positions corresponding to the transistors NT111 to NT114 of the third embodiment shown in FIG. However, the source of the transistor PT112 is connected to the positive potential VDD.

  FIG. 10 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the fourth embodiment of the present invention. Next, the operation of the V driver according to the fourth embodiment will be described with reference to FIGS. In the V driver according to the fourth embodiment, a waveform obtained by inverting the H level and the L level of the start signal STV, the clock signals CKV1 and CKV2, the enable signal ENB, and the inverted enable signal XENB of the third embodiment shown in FIG. Are input as a start signal STV, clock signals CKV1, CKV2, an enable signal ENB, and an inverted enable signal XENB, respectively. Thus, the shift register circuit units 521 to 525 according to the fourth embodiment cause the shift signals SR1 to SR5 output from the shift register circuit units 511 to 515 according to the third embodiment shown in FIG. And a signal having a waveform obtained by inverting. Further, the logic synthesis circuit units 821 to 823 according to the fourth embodiment have the H level of the shift output signals Dummy, Gate1 and Gate2 output from the logic synthesis circuit units 811 to 813 according to the third embodiment shown in FIG. A signal having a waveform obtained by inverting the L level is output. Other operations of the V driver according to the fourth embodiment are the same as those of the V driver according to the third embodiment shown in FIG.

  In the fourth embodiment, by configuring as described above, it is possible to obtain the same effects as in the third embodiment, such as simplifying the circuit configuration of the liquid crystal display device including the V driver.

  In the fourth embodiment, the clock signals CKV1 (CKV2) are supplied to the gates of the transistors PT24, PT34, and PT44 of the shift register circuit units 523 to 525, and the H level (VDD) and the L level (VBB) are supplied to the drains. The following operation is performed by supplying the enable signal ENB for switching to. For example, in the third-stage shift register circuit portion 523, after the transistor PT24 is turned on by the clock signal CKV1, the source potential of the transistor PT24 is lowered from VDD to VBB by the enable signal ENB. The gate potential of the transistor PT24 drops by (Vβ). In the fourth-stage shift register circuit portion 524, after the transistor PT34 is turned on by the clock signal CKV2, the source potential of the transistor PT34 is decreased from VDD to VBB by the enable signal ENB. The gate potential of the transistor PT24 drops by (Vβ). As a result, the potentials of shift signals SR3 and SR4 (VBB−Vβ <VBB−Vt) can be made lower than when the drains of transistors PT24 and PT34 are connected to fixed negative side potential VBB. Therefore, the potentials of shift signals SR3 and SR4 can be more easily made lower than the threshold voltage (Vt) by VBB. Therefore, shift signals SR3 and SR4 having a potential (VBB-Vβ) equal to or lower than VBB-Vt are supplied to the gates of transistors PT91 and PT92 of logic synthesis circuit unit 822 connected to the first-stage gate line, respectively. can do. As a result, the potential of the shift output signal Gate1 output to the first-stage gate line via the transistors PT91 and PT92 of the logic synthesis circuit unit 822 is further suppressed from rising by the threshold voltage (Vt). be able to.

(Fifth embodiment)
FIG. 11 is a circuit diagram inside the V driver of the liquid crystal display device according to the fifth embodiment of the present invention. Referring to FIG. 11, in the fifth embodiment, in the configuration of the third embodiment, the timing is applied to the drain of the transistor connected to the node to which the output signal of the third and subsequent stages of the shift register circuit unit is output. A case where two enable signals having different values are alternately supplied one by one will be described.

  That is, in the fifth embodiment, as shown in FIG. 11, a plurality of stages of shift register circuit units 531 to 535, a scan direction switching circuit unit 630, an input signal switching circuit unit 730, and a logic synthesis circuit unit 831 833 and a circuit portion 930 are provided. In FIG. 11, for simplification of the drawing, only five stages of shift register circuit units 531 to 535 and three stages of logic synthesis circuit units 831 to 833 are illustrated. There are provided as many shift register circuit portions and logic synthesis circuit portions as the number of stages.

  The first-stage shift register circuit unit 531 has the same circuit configuration as the first circuit unit 51a and the second circuit unit 51b of the first-stage shift register circuit unit 51 of the first embodiment shown in FIG. The first circuit portion 531a and the second circuit portion 531b are provided. The second-stage shift register circuit section 532 has the same circuit configuration as the first circuit section 52a and the second circuit section 52b of the second-stage shift register circuit section 52 of the first embodiment shown in FIG. The first circuit portion 532a and the second circuit portion 532b are provided.

  Here, in the fifth embodiment, the enable signal lines (ENB1) and the enable signal lines (ENB2) are alternately connected to the shift register circuit units 533 to 535 in the third and subsequent stages one by one. The enable signal line (ENB1) is an example of the “third signal line” in the present invention, and the enable signal line (ENB2) is an example of the “fourth signal line” in the present invention. An enable signal ENB1 whose potential is switched from L level to H level at a predetermined timing is supplied via the enable signal line (ENB1), and at a different timing from the enable signal ENB1 via the enable signal line (ENB2). An enable signal ENB2 for switching the potential from the L level to the H level is supplied.

  The third-stage shift register circuit portion 533 includes a first circuit portion 533a and a second circuit portion 533b. The first circuit unit 533a and the second circuit unit 533b are respectively the same circuits as the first circuit unit 53a and the second circuit unit 53b of the third-stage shift register circuit unit 53 of the first embodiment shown in FIG. It has a configuration. In the fifth embodiment, the enable signal line (ENB1) is connected to the drain of the transistor NT24.

  The fourth-stage shift register circuit portion 534 includes a first circuit portion 534a and a second circuit portion 534b. The first circuit unit 534a and the second circuit unit 534b are respectively the same circuits as the first circuit unit 54a and the second circuit unit 54b of the fourth-stage shift register circuit unit 54 of the first embodiment shown in FIG. It has a configuration. In the fifth embodiment, the enable signal line (ENB2) is connected to the drain of the transistor NT34.

  The fifth-stage shift register circuit portion 535 includes a first circuit portion 535a and a second circuit portion 535b. The first circuit unit 535a and the second circuit unit 535b are respectively the same circuits as the first circuit unit 55a and the second circuit unit 55b of the fifth-stage shift register circuit unit 55 of the first embodiment shown in FIG. It has a configuration. In the fifth embodiment, the enable signal line (ENB1) is connected to the drain of the transistor NT44.

  Scan direction switching circuit unit 630 includes transistors NT51 to NT55 and transistors NT57 to NT60. That is, the scan direction switching circuit unit 630 of the fifth embodiment has a circuit configuration in which the transistor NT56 is not provided in the circuit configuration of the scan direction switching circuit unit 610 of the third embodiment shown in FIG. Further, the input signal switching circuit unit 730 has the same circuit configuration as the input signal switching circuit unit 70 of the third embodiment shown in FIG. The logic synthesis circuit units 831 to 833 have the same circuit configuration as the logic synthesis circuit units 811 to 813 of the third embodiment shown in FIG. The circuit unit 930 has a circuit configuration similar to that of the circuit unit 910 of the third embodiment illustrated in FIG.

  FIG. 12 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the fifth embodiment of the present invention. Next, with reference to FIGS. 11 and 12, the operation of the V driver of the liquid crystal display device according to the fifth embodiment will be described.

  The operation of the V driver according to the fifth embodiment is basically the same as the operation of the V driver according to the third embodiment. However, unlike the third embodiment, the V driver according to the fifth embodiment is connected to the node ND3 from which the output signals SR13 to SR15 of the shift register circuit units 533 to 535 in the third and subsequent stages are output. The enable signals ENB1 and ENB2 having different timings are alternately supplied to the drains of the transistors NT24 to NT44.

  Specifically, the operations in the first-stage and second-stage shift register circuit units 531 and 532 (see FIG. 11) are the same as the first-stage and second-stage shift register circuits according to the third embodiment shown in FIG. The operations in the units 511 and 512 are the same. Then, an H level (VDD + Vα) shift signal SR2 is input from the second-stage shift register circuit portion 532 to the drain of the transistor NT66. As a result, the source potential of the transistor NT66 which is turned on when the scan direction switching signal CSV having the VDD potential is input to the gate becomes the potential of (VDD−Vt). Therefore, the potential of (VDD−Vt) is input to the gate of the transistor NT27 of the third-stage shift register circuit portion 533. Further, the output signal SR12 of H level (VDD) is input to the gate of the transistor NT21. The L-level shift signal SR4 is input from the fourth-stage shift register circuit unit 534 to the gate of the transistor NT22. Thereby, transistors NT21 and NT27 are turned on, and transistor NT22 is turned off. Therefore, the L level potential is supplied from the negative potential VBB via the transistor NT21, so that the potential of the node ND1 of the third-stage shift register circuit portion 533 is lowered to the L level. Thereby, transistors NT25 and NT26 are turned off. In this state, the clock signal CKV1 input to the drain of the transistor NT27 rises from the L level to the H level. As a result, the potential of the node ND2 of the third-stage shift register circuit portion 533 rises to the H level, so that the transistor NT24 is turned on. At this time, since the L level enable signal ENB1 is supplied to the drain of the transistor NT24, the source potential of the transistor NT24 (the potential of the node ND3) is held at the L level.

  Thereafter, in the fifth embodiment, the potential of the enable signal ENB1 rises from the L level to the H level. As a result, the potential of the node ND3 of the third-stage shift register circuit portion 533 rises to H level. At this time, the potential of the node ND2 of the third-stage shift register circuit portion 533 is booted as the potential of the node ND3 increases so that the gate-source voltage of the transistor NT24 is maintained by the capacitor C22. Will rise. As a result, the potential of the node ND2 of the third-stage shift register circuit portion 533 rises to a potential (VDD + Vβ> VDD + Vt) that is higher by a predetermined voltage (Vβ) than the threshold voltage (Vt). Note that the potential (VDD + Vβ) of the node ND2 at this time is higher than the potential (VDD + Vα) of the node ND2 after the rise in the first embodiment. Then, an H-level shift signal SR3 having a potential (VDD + Vβ) of VDD + Vt or higher is output from the node ND2 of the third-stage shift register circuit portion 533.

  Shift signal SR3 at H level (VDD + Vβ) is input to the drain of transistor NT68. As a result, the source potential of the transistor NT68 that is turned on when the scan direction switching signal CSV having the VDD potential is input to the gate becomes the potential of (VDD−Vt). Therefore, the potential of (VDD−Vt) is input to the gate of the transistor NT37 in the fourth-stage shift register circuit portion 534. Further, the output signal SR13 of H level (VDD) is input to the gate of the transistor NT31. The L-level shift signal SR5 is input from the fifth-stage shift register circuit unit 535 to the gate of the transistor NT32. Thereby, transistors NT31 and NT35 are turned on, and transistor NT32 is turned off. Therefore, the L level potential is supplied from the negative potential VBB through the transistor NT31, so that the potential of the node ND1 is lowered to the L level. Thereby, transistors NT34 and NT38 are turned off. Thereafter, the clock signal CKV2 input to the drain of the transistor NT35 rises from the L level to the H level. Accordingly, the potential of the node ND2 of the fourth-stage shift register circuit portion 534 rises to the H level, so that the transistor NT37 is turned on. At this time, since the L level enable signal ENB2 is supplied to the drain of the transistor NT37, the source potential of the transistor NT37 (the potential of the node ND3) is held at the L level.

  Thereafter, in the fifth embodiment, the potential of the enable signal ENB2 rises from the L level to the H level. As a result, the potential of the node ND3 of the fourth-stage shift register circuit portion 534 rises to the H level. At this time, the potential of the node ND2 of the fourth-stage shift register circuit portion 534 is booted as the potential of the node ND3 rises so that the gate-source voltage of the transistor NT37 is maintained by the capacitor C2. Will rise. As a result, the potential of the node ND2 of the fourth-stage shift register circuit portion 534 rises to a potential (VDD + Vβ> VDD + Vt) that is higher than the threshold voltage (Vt) by a predetermined voltage (Vβ). Then, an H-level shift signal SR4 having a potential (VDD + Vβ) of VDD + Vt or higher is output from the node ND2 of the fourth-stage shift register circuit portion 534.

  In the shift register circuit units in the fifth and subsequent stages, the same operation as that performed by the third and fourth shift register circuit units 533 and 534 is performed. That is, in the shift register circuit portion at a predetermined stage, the potential of the node ND2 is raised by raising the enable signal ENB1 to H level after raising the potential of the node ND2 by raising the clock signal CKV1 to H level. The voltage is further increased to a potential of H level (VDD + Vβ> VDD + Vt). Then, in the shift register circuit portion of the next stage of the predetermined stage, the potential of the node ND2 is raised by raising the clock signal CKV2 to the H level, and then the enable signal ENB2 is raised to the H level, whereby the node ND2 Is further raised to a potential of H level (VDD + Vβ> VDD + Vt). This operation is alternately performed in the shift register circuit portion of each stage. As a result, the potential of the shift signal output from the shift register circuit portion of each stage is sequentially raised to the H level (VDD + Vβ> VDD + Vt).

  Other operations of the V driver according to the fifth embodiment are the same as those of the V driver according to the third embodiment.

  In the fifth embodiment, as described above, in the shift register circuit portions 533 to 535, the clock signals CKV1 and CKV2 are alternately supplied to the gates of the transistors NT24, NT34 and NT44, and the enable signals ENB1 having different timings are supplied to the drains. By alternately supplying ENB2, for example, in the third-stage shift register circuit unit 533, the gate potential of the transistor NT24 is raised from the L level (VBB) to the H level (VDD) by the clock signal CKV1. After the transistor NT24 is turned on, the source potential of the transistor NT24 can be raised from the L level (VBB) to the H level (VDD) by the enable signal ENB1. As a result, the gate potential of the transistor NT24 can be increased by the increase (Vβ) of the source potential of the transistor NT24 at that time. In the fourth-stage shift register circuit portion 534, the transistor NT34 is turned on as the gate potential of the transistor NT34 is increased from the L level (VBB) to the H level (VDD) by the clock signal CKV2. Thereafter, the source potential of the transistor NT34 can be raised from the L level (VBB) to the H level (VDD) by the enable signal ENB2. As a result, the gate potential of the transistor NT34 can be increased by the increase (Vβ) of the source potential of the transistor NT34 at that time. As a result, the potentials of the shift signals SR3 and SR4 (VDD + Vβ> VDD + Vt) can be made higher than in the case where the drains of the transistors NT24 and NT34 are connected to the fixed positive side potential VDD. In addition, the potentials of the shift signals SR3 and SR4 can be higher than the threshold voltage (Vt) by VDD. Therefore, shift signals SR3 and SR4 having a potential equal to or higher than VDD + Vt can be supplied to the gates of the transistors NT91 and NT92 of the logic composition circuit portion 832 connected to the first-stage gate line, respectively. . As a result, the potential of the shift output signal Gate1 output to the first-stage gate line via the transistors NT91 and NT92 of the logic synthesis circuit portion 832 is further suppressed from decreasing by the threshold voltage (Vt). be able to.

  In the fifth embodiment, by using two enable signals ENB1 and ENB2 having different timings, for example, the transistor NT27 of the third-stage shift register circuit unit 533 and the transistor of the fourth-stage shift register circuit unit 534 The source potentials of the transistors NT27 and NT37 can be raised from the L level (VBB) to the H level (VDD) in accordance with the timing when the NT37 is turned on. Further, the source potentials of the transistors NT27 and NT37 can be held at the H level until the transistor NT27 of the shift register circuit portion 533 and the transistor NT37 of the shift register circuit portion 534 are turned off. As a result, the gate potentials of the transistors NT27 and NT37 are lowered due to the source potentials of the transistors NT27 and NT37 being lowered to the L level (VBB) before the transistors NT27 and NT37 are turned off. Can be suppressed. In this case, the potential of the shift signal SR3 output from the node ND2 of the third-stage shift register circuit portion 533 and the potential of the shift signal SR4 output from the node ND2 of the fourth-stage shift register circuit portion 534 are lowered. Can be suppressed. As a result, the operation of the transistor NT91 of the logic synthesis circuit unit 832 to which the shift signal SR3 is input to the gate and the operation of the transistor NT92 of the logic synthesis circuit unit 832 to which the shift signal SR4 is input to the gate become unstable. Can be suppressed.

  The effects of the fifth embodiment other than those described above are the same as the effects of the third embodiment.

(Sixth embodiment)
FIG. 13 is a circuit diagram inside the V driver of the liquid crystal display device according to the sixth embodiment of the present invention. With reference to FIG. 13, in the sixth embodiment, a case will be described in which the V driver of the fifth embodiment is configured by a p-channel transistor.

  That is, in this sixth embodiment, as shown in FIG. 13, a plurality of stages of shift register circuit units 541 to 545, a scan direction switching circuit unit 640, an input signal switching circuit unit 740, and a plurality of stages of logic synthesis circuit. Portions 841 to 843 and a circuit portion 940 are provided. In FIG. 13, only the shift register circuit units 541 to 545 for five stages and the logic synthesis circuit parts 841 to 843 for three stages are illustrated for simplification of the drawing. There are provided as many shift register circuit portions and logic synthesis circuit portions as the number of stages.

  The first-stage shift register circuit unit 541 has the same circuit configuration as the first circuit unit 501a and the second circuit unit 501b of the first-stage shift register circuit unit 501 of the second embodiment shown in FIG. The first circuit portion 541a and the second circuit portion 541b are provided. The second-stage shift register circuit unit 542 has the same circuit configuration as the first circuit unit 502a and the second circuit unit 502b of the second-stage shift register circuit unit 502 of the second embodiment shown in FIG. The first circuit portion 542a and the second circuit portion 542b are provided.

  Here, in the sixth embodiment, the enable signal line (ENB1) and the enable signal line (ENB2) are alternately connected to the shift register circuit units 543 to 545 in the third and subsequent stages. An enable signal ENB1 whose potential is switched from L level to H level at a predetermined timing is supplied via the enable signal line (ENB1), and at a different timing from the enable signal ENB1 via the enable signal line (ENB2). An enable signal ENB2 for switching the potential from the L level to the H level is supplied.

  Specifically, the third-stage shift register circuit portion 543 includes a first circuit portion 543a and a second circuit portion 543b. The first circuit unit 543a and the second circuit unit 543b are respectively the same circuits as the first circuit unit 503a and the second circuit unit 503b of the third-stage shift register circuit unit 503 of the second embodiment shown in FIG. It has a configuration. In the sixth embodiment, the enable signal line (ENB1) is connected to the drain of the transistor PT24.

  The fourth-stage shift register circuit portion 544 includes a first circuit portion 544a and a second circuit portion 544b. The first circuit unit 544a and the second circuit unit 544b are respectively the same circuits as the first circuit unit 504a and the second circuit unit 504b of the fourth-stage shift register circuit unit 504 of the second embodiment shown in FIG. It has a configuration. In the sixth embodiment, the enable signal line (ENB2) is connected to the drain of the transistor PT34.

  The fifth-stage shift register circuit portion 545 includes a first circuit portion 545a and a second circuit portion 545b. The first circuit unit 545a and the second circuit unit 545b are respectively the same circuits as the first circuit unit 505a and the second circuit unit 505b of the fifth-stage shift register circuit unit 505 of the second embodiment shown in FIG. It has a configuration. In the sixth embodiment, an enable signal line (ENB1) is connected to the drain of the transistor PT44.

  Scan direction switching circuit unit 640 includes transistors PT51 to PT55 and transistors PT57 to PT60. That is, the input signal switching circuit unit 640 of the sixth embodiment has a circuit configuration in which the transistor PT56 is not provided in the circuit configuration of the scan direction switching circuit unit 620 of the fourth embodiment shown in FIG. Further, the input signal switching circuit unit 740 has the same circuit configuration as the input signal switching circuit unit 720 of the fourth embodiment shown in FIG. The logic synthesis circuit units 841 to 843 have the same circuit configuration as the logic synthesis circuit units 821 to 823 of the fourth embodiment shown in FIG. The circuit unit 940 has a circuit configuration similar to that of the circuit unit 920 of the fourth embodiment illustrated in FIG.

  FIG. 14 is a voltage waveform diagram for explaining the operation of the V driver of the liquid crystal display device according to the sixth embodiment of the present invention. Next, the operation of the V driver according to the sixth embodiment will be described with reference to FIGS. In the V driver according to the sixth embodiment, the start signal STV, the clock signals CKV1, CKV2, the enable signals ENB, ENB1, ENB2, and the inverted enable signal XENB of the fifth embodiment shown in FIG. The inverted waveform signals are input as start signal STV, clock signals CKV1, CKV2, enable signals ENB, ENB1, ENB2, and inverted enable signal XENB, respectively. As a result, the shift register circuit units 541 to 545 according to the sixth embodiment shift the shift signals SR1 to SR5 and the output signals SR11 to SR15 output from the shift register circuit units 531 to 535 according to the fifth embodiment shown in FIG. A signal having a waveform obtained by inverting the H level and the L level is output. Further, the logic synthesis circuit units 841 to 843 according to the sixth embodiment have the H level of the shift output signals Dummy, Gate1 and Gate2 output from the logic synthesis circuit units 831 to 833 according to the fifth embodiment shown in FIG. A signal having a waveform obtained by inverting the L level is output. The other operations of the V driver according to the sixth embodiment are the same as the operations of the V driver according to the fifth embodiment shown in FIG.

  In the sixth embodiment, the clock signals CKV1 and CKV2 are alternately supplied to the gates of the transistors PT24, PT34, and PT44 of the shift register circuit units 543 to 545, and the enable signals ENB1 and ENB2 having different timings are alternately supplied to the drains. By supplying, the following operation is performed. For example, in the shift register circuit portion 543 at the third stage, after the transistor PT24 is turned on by the clock signal CKV1, the source potential of the transistor PT24 is decreased from VDD to VBB by the enable signal ENB1, so that the decrease in the potential is reduced. The gate potential of the transistor PT24 drops by (Vβ). In the shift register circuit portion 544 at the fourth stage, after the transistor PT34 is turned on by the clock signal CKV2, the source potential of the transistor PT34 is lowered from VDD to VBB by the enable signal ENB2, so The gate potential of the transistor PT34 drops by (Vβ). As a result, the potentials of shift signals SR3 and SR4 (VBB−Vβ <VBB−Vt) can be made lower than when the drains of transistors PT24 and PT34 are connected to fixed negative side potential VBB. Therefore, the potentials of shift signals SR3 and SR4 can be more easily made lower than the threshold voltage (Vt) by VBB. Therefore, shift signals SR3 and SR4 having a potential (VBB-Vβ) equal to or lower than VBB-Vt are supplied to the gates of transistors PT91 and PT92 of logic synthesis circuit portion 842 connected to the first-stage gate line, respectively. can do. As a result, the potential of the shift output signal Gate1 output to the first-stage gate line via the transistors PT91 and PT92 of the logic synthesis circuit unit 842 is further suppressed from rising by the threshold voltage (Vt). be able to.

  The effects of the sixth embodiment other than those described above are the same as the effects of the fifth embodiment.

(Seventh embodiment)
FIG. 15 is an internal circuit diagram of the horizontal switch and the H driver of the liquid crystal display device according to the seventh embodiment of the present invention. Referring to FIG. 15, in the seventh embodiment, the case where the present invention is applied to an H driver for driving (scanning) a drain line in the liquid crystal display device of the first embodiment shown in FIG. To do.

  As shown in FIG. 15, the H driver 4 of the liquid crystal display device according to the seventh embodiment has a plurality of stages of shift register circuit units 51 to 51, as in the V driver 5 of the first embodiment shown in FIG. 55, a scan direction switching circuit unit 60, an input signal switching circuit unit 70, and a plurality of stages of logic synthesis circuit units 81 to 83 are provided. In FIG. 15, for simplification of the drawing, only the five-stage shift register circuit sections 51 to 55 and the three-stage logic synthesis circuit sections 81 to 83 are shown. There are provided as many shift register circuit portions and logic synthesis circuit portions as the number of stages. In the seventh embodiment, the logic synthesis circuit units 81 to 83 and the horizontal switch 3 are connected. Specifically, the horizontal switch 3 includes a number of n-channel transistors NT121 to NT123 corresponding to the number of stages of the logic synthesis circuit units 81 to 83. Hereinafter, n-channel transistors NT121 to NT123 are referred to as transistors NT121 to NT123, respectively.

  The source of the transistor NT121 is connected to the dummy drain line, and the drain is connected to the video signal line (Video). The gate of the transistor NT121 is connected to the node ND4 of the logic synthesis circuit unit 81. The source of the transistor NT122 is connected to the first-stage drain line, and the drain is connected to the video signal line (Video). The gate of the transistor NT122 is connected to the node ND4 of the logic synthesis circuit unit 82. The source of the transistor NT123 is connected to the second-stage drain line, and the drain is connected to the video signal line (Video). The gate of the transistor NT123 is connected to the node ND4 of the logic synthesis circuit unit 83.

  Next, the operation of the shift register circuit of the H driver according to the seventh embodiment will be described with reference to FIG. In the H driver 4 according to the seventh embodiment, the H level shift output signals Dummy, Gate1 and Gate2 sequentially output from the logic synthesis circuit units 81 to 83 of each stage are supplied to the transistors NT121 to NT123 of the corresponding horizontal switch 3. Each is input to the gate. Thereby, the transistors NT121 to NT123 in each stage of the horizontal switch 3 are sequentially turned on. Therefore, a video signal is sequentially output from the video signal line (Video) to the drain line of each stage via the transistors NT121 to NT123 of each stage of the horizontal switch 3. Other operations of the H driver 4 according to the seventh embodiment are the same as those of the V driver 5 according to the first embodiment shown in FIG.

  In the seventh embodiment, by configuring as described above, it is possible to obtain the same effects as in the first embodiment, such as simplifying the circuit configuration of the liquid crystal display device including the H driver.

(Eighth embodiment)
FIG. 16 is a plan view showing an organic EL display device according to an eighth embodiment of the present invention. Referring to FIG. 16, in the eighth embodiment, a case where the present invention is applied to an organic EL display device including a pixel having an n-channel transistor will be described.

  That is, in the eighth embodiment, as shown in FIG. 16, the display unit 6 is formed on the substrate 1b. The display unit 6 includes n-channel transistors 61 and 62 (hereinafter referred to as transistors 61 and 62), an auxiliary capacitor 63, an anode 64, a cathode 65, and an organic material sandwiched between the anode 64 and the cathode 65. Pixels 60 including EL elements 66 are arranged in a matrix. Note that the display unit 6 in FIG. 16 shows a configuration for one pixel. The source of the transistor 61 is connected to the gate of the transistor 62 and one electrode of the auxiliary capacitor 63, and the drain is connected to the drain line. The gate of the transistor 61 is connected to the gate line. Further, the transistor 62 has a source connected to the anode 64 and a drain connected to a current supply line (not shown).

  The circuit configuration inside the H driver 4 is the same as the circuit configuration of the H driver 4 of the seventh embodiment shown in FIG. The circuit configuration inside the V driver 5 is the same as the circuit configuration of the V driver 5 of the first embodiment shown in FIG. The structure of the other parts of the organic EL display device according to the eighth embodiment is the same as that of the liquid crystal display device according to the first embodiment shown in FIG.

  In the eighth embodiment, by configuring as described above, in the organic EL display device, the circuit configuration of the V driver and the H driver can be simplified, and the same effects as in the first and seventh embodiments described above. Can be obtained.

(Ninth embodiment)
FIG. 17 is a plan view showing an organic EL display device according to the ninth embodiment of the present invention. Referring to FIG. 17, in the ninth embodiment, a case where the present invention is applied to an organic EL display device including a pixel having a p-channel transistor will be described.

  That is, in the ninth embodiment, as shown in FIG. 17, the display portion 6a is formed on the substrate 1c. The display unit 6a includes p-channel transistors 61a and 62a (hereinafter referred to as transistors 61a and 62a), an auxiliary capacitor 63a, an anode 64a, a cathode 65a, and an organic material sandwiched between the anode 64a and the cathode 65a. Pixels 60a including EL elements 66a are arranged in a matrix. Note that the display unit 6a in FIG. 17 shows a configuration for one pixel. The source of the transistor 61a is connected to the drain line, and the drain is connected to the gate of the transistor 62a and one electrode of the auxiliary capacitor 63a. The gate of the transistor 61a is connected to the gate line. The source of the transistor 62a is connected to a current supply line (not shown), and the drain is connected to the anode 64a.

  The circuit configuration inside the V driver 5a is the same as the circuit configuration of the V driver 5a of the second embodiment shown in FIG. The structure of the other parts of the organic EL display device according to the ninth embodiment is the same as that of the liquid crystal display device according to the second embodiment shown in FIG.

  In the ninth embodiment, by configuring as described above, in the organic EL display device, it is possible to obtain the same effects as those of the second embodiment, such as that the circuit configuration of the V driver can be simplified.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first to ninth embodiments, an example in which the present invention is applied to a liquid crystal display device or an organic EL display device has been described. It can also be applied to a display device.

  In the first to seventh embodiments, the example in which the present invention is applied to only one of the V driver and the H driver has been described. However, the present invention is not limited to this and is applied to both the V driver and the H driver. The present invention may be applied.

  In the seventh embodiment, the example in which all the transistors used in the H driver according to the present invention are n-channel transistors has been shown. However, the present invention is not limited to this, and all the transistors used in the H driver according to the present invention are p. You may comprise a channel transistor.

  In the first, third, fifth, seventh, and eighth embodiments using n-channel transistors, all the capacitors may be configured by n-channel transistors. In the second, fourth, sixth, and ninth embodiments using p-channel transistors, all the capacitors may be configured by p-channel transistors.

1 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram inside a V driver of the liquid crystal display device according to the first embodiment shown in FIG. 1. It is a voltage waveform diagram for demonstrating operation | movement of V driver of the liquid crystal display device by 1st Embodiment of this invention. It is the top view which showed the liquid crystal display device by 2nd Embodiment of this invention. FIG. 5 is a circuit diagram inside a V driver of the liquid crystal display device according to the second embodiment shown in FIG. 4. It is a voltage waveform diagram for demonstrating operation | movement of V driver of the liquid crystal display device by 2nd Embodiment of this invention. It is a circuit diagram inside the V driver of the liquid crystal display device by 3rd Embodiment of this invention. It is a voltage waveform diagram for demonstrating operation | movement of V driver of the liquid crystal display device by 3rd Embodiment of this invention. It is a circuit diagram inside the V driver of the liquid crystal display device by 4th Embodiment of this invention. It is a voltage waveform diagram for demonstrating operation | movement of V driver of the liquid crystal display device by 4th Embodiment of this invention. It is a circuit diagram inside the V driver of the liquid crystal display device by 5th Embodiment of this invention. It is a voltage waveform diagram for demonstrating operation | movement of V driver of the liquid crystal display device by 5th Embodiment of this invention. It is a circuit diagram inside the V driver of the liquid crystal display device by 6th Embodiment of this invention. It is a voltage waveform diagram for demonstrating operation | movement of the V driver of the liquid crystal display device by 6th Embodiment of this invention. It is a circuit diagram inside the H driver of the liquid crystal display device by 7th Embodiment of this invention. It is the top view which showed the organic electroluminescence display by 8th Embodiment of this invention. It is the top view which showed the organic electroluminescence display by 9th Embodiment of this invention. It is a circuit diagram of a shift register circuit including a conventional resistance load type inverter circuit. FIG. 19 is a waveform diagram for explaining the operation of the conventional shift register circuit shown in FIG. 18.

Explanation of symbols

52, 53, 54, 55, 502, 503, 504, 505, 512, 513, 514, 515, 522, 523, 524, 525, 532, 533, 534, 535, 542, 543, 544, 545 Shift register circuit Part (first shift register circuit part, second shift register circuit part)
81, 82, 83, 801, 802, 803, 811, 812, 813, 821, 822, 823, 831, 832, 833, 841, 842, 843 Logic synthesis circuit units 81a, 82a, 83a, 801a, 802a, 803a 811a, 812a, 813a, 821a, 822a, 823a, 831a, 832a, 833a, 841a, 842a, 843a Potential fixing circuit part NT14, NT24, NT34, NT44 n-channel transistors (sixth transistor, seventh transistor)
PT14, PT24, PT34, PT44 p-channel transistors (sixth transistor, seventh transistor)
NT81, NT91, NT101 n-channel transistors (first transistor, second transistor)
PT81, PT91, PT101 p-channel transistors (first transistor, second transistor)
NT83, NT93, NT103 n-channel transistor (third transistor)
PT83, PT93, PT103 p-channel transistor (third transistor)
NT84, NT94, NT104 n-channel transistor (fifth transistor)
PT84, PT94, PT104 p-channel transistor (fifth transistor)
NT85, NT86, NT95, NT96, NT105, NT106 n-channel transistor (fourth transistor)
PT85, PT86, PT95, PT96, PT105, PT106 p-channel transistor (fourth transistor)
C12, C22, C32, C42 capacity (second capacity, third capacity)
C81, C91, C101 Capacity (first capacity)

Claims (10)

A first shift register circuit unit configured by a first conductivity type transistor and outputting a first shift signal;
A second shift register circuit unit configured by a transistor of the first conductivity type and outputting a second shift signal and disposed in a stage subsequent to the first shift register circuit unit;
A display device including a shift register circuit including a logic synthesis circuit unit that logically synthesizes the first shift signal and the second shift signal and outputs a shift output signal;
The logic synthesis circuit unit is connected to a first signal line that supplies a first signal for switching one of a source / drain to a first potential and a second potential, and the first shift signal is input to a gate. A first transistor of a first conductivity type;
A second transistor of the first conductivity type in which one of the source / drain is connected to the other of the source / drain of the first transistor and the second shift signal is input to the gate;
A potential fixing circuit unit for fixing the output signal to the second potential after the first shift signal changes from the first potential to the second potential;
The potential fixing circuit unit is connected between the second potential side and the second transistor, and when the first shift signal is the second potential, a predetermined signal of the first potential is input to the gate. A display device comprising a third transistor of the first conductivity type that is turned on by this. The shift register circuit includes a third shift register circuit portion that is the next stage of the second shift register circuit portion,
The output signal of the first potential is input to the gate of the third transistor from the third shift register circuit unit when the first shift signal changes from the first potential to the second potential. The display device according to 1. The second signal is supplied to a gate of the third transistor from a second signal line that supplies a second signal that switches between the first potential and the second potential,
3. The display device according to claim 2, wherein when the first shift signal is the second potential, the second signal having the first potential is input from the second signal line to the gate of the third transistor. The display device according to claim 1, wherein a first capacitor is connected between a gate and a source of the third transistor. The potential fixing circuit unit includes a fourth transistor of the first conductivity type connected to the gate of the third transistor and diode-connected.
5. The display device according to claim 1, wherein the predetermined signal is input to a gate of the third transistor via the fourth transistor. 6. The display device according to claim 1, wherein the third transistor is turned off when the first shift signal and the second shift signal are at the first potential. The potential fixing circuit unit is connected between the second potential side and a gate of the third transistor, and when the first shift signal and the second shift signal are at the first potential, The display device according to claim 6, further comprising: a fifth transistor of a first conductivity type that is turned on when the output signal of the first potential is input to a gate through the transistor and the second transistor. The first shift register circuit section includes a sixth transistor having the drain supplied with the first potential and a gate connected to a node from which the first shift signal is output; and a gate and a source of the sixth transistor A second capacitor connected between and
The second shift register circuit unit includes a seventh transistor having a drain connected to the first potential and a gate to which the second shift signal is output, and a gate and a source of the seventh transistor. A third capacitor connected between and
The gate potential of the sixth transistor increases or decreases as the source potential of the sixth transistor increases or decreases so as to maintain the gate-source voltage of the sixth transistor to which the second capacitor is connected. And
The gate potential of the seventh transistor increases or decreases as the source potential of the seventh transistor increases or decreases so as to maintain the gate-source voltage of the seventh transistor to which the third capacitor is connected. The display device according to any one of claims 1 to 6. A third signal line for supplying a third signal for switching between the first potential and the second potential is connected to the drain of the sixth transistor, and a first clock signal is supplied to the gate.
The third signal line for supplying the third signal is connected to the drain of the seventh transistor, and the second clock signal is supplied to the gate.
The third signal is generated after the first clock signal is changed from the second potential to the first potential and after the second clock signal is changed from the second potential to the first potential, respectively. The display device according to claim 8, wherein the second potential is switched to the first potential. A third signal line for supplying a third signal for switching between the first potential and the second potential is connected to the drain of the sixth transistor, and a first clock signal is supplied to the gate.
A fourth signal line for supplying a fourth signal for switching between the first potential and the second potential is connected to the drain of the seventh transistor, and a second clock signal is supplied to the gate.
The third signal is switched from the second potential to the first potential after the first clock signal is changed from the second potential to the first potential.
The display device according to claim 8 , wherein the fourth signal is switched from the second potential to the first potential after the second clock signal is changed from the second potential to the first potential.

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