JP4786403B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4786403B2 JP4786403B2 JP2006116541A JP2006116541A JP4786403B2 JP 4786403 B2 JP4786403 B2 JP 4786403B2 JP 2006116541 A JP2006116541 A JP 2006116541A JP 2006116541 A JP2006116541 A JP 2006116541A JP 4786403 B2 JP4786403 B2 JP 4786403B2
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- passivation film
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- 239000004065 semiconductor Substances 0.000 title claims description 131
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000002161 passivation Methods 0.000 claims description 46
- 238000000227 grinding Methods 0.000 claims description 44
- 238000001020 plasma etching Methods 0.000 claims description 30
- 229920001721 polyimide Polymers 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 23
- 239000004642 Polyimide Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 10
- 239000002184 metal Substances 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
2 主表面
3 半導体素子
4 ポリイミド被膜
5 救済用ヒューズ(あるいは電極用パッド部分)
6 表面保護シート
7 開口部
8 気泡
9 真空処理装置
10 半導体ウエハ
11 エッチングステージ
12 プラズマ
13 搬送系
14 凸部(間隙)
15 半導体ウエハ
20 壁
Claims (17)
- 少なくとも半導体ウエハの主表面に形成された半導体素子と、当該半導体素子を覆うように設けられたパッシベーション膜とを有する半導体装置において、
前記パッシベーション膜は、少なくとも1つの開口部と凹部とを含み、当該パッシベーション膜の上に表面保護シートが貼り付けられたときに、前記凹部と前記表面保護シートとの間に前記開口部から前記半導体ウエハの外周部まで延伸する間隙が形成される前記パッシベーション膜であることを特徴とする半導体装置。 - 前記間隙は、前記半導体ウエハの全面において連続して形成されることを特徴とする請求項1に記載の半導体装置。
- 前記半導体ウエハの周辺のパッシベーション膜において、前記半導体ウエハの中央側から伸びた前記間隙の端部に壁を設けたことを特徴とする請求項1に記載の半導体装置。
- 前記パッシベーション膜は、ポリイミド被膜であることを特徴とする請求項1乃至請求項3のいずれか1項に記載の半導体装置。
- 前記パッシベーション膜の前記開口部は、自身の側面が前記パッシベーション膜に完全に囲まれていることを特徴とする請求項1に記載の半導体装置。
- 前記パッシベーション膜の前記凹部は、前記パッシベーション膜の一部を自身の底部として残して形成されることを特徴とする請求項1又は5に記載の半導体装置。
- 半導体ウエハを有する半導体装置の製造方法において、
前記半導体ウエハの主表面に半導体素子を形成し、
前記半導体素子を覆うようにパッシベーション膜を形成し、
前記パッシベーション膜を貫通するよう開口部を形成し、
前記パッシベーション膜の表面に凹部を形成し、
前記パッシベーション膜の上面に、前記パッシベーション膜の前記凹部と自身との間に前記パッシベーション膜の前記開口部から前記半導体ウエハの外周部まで延伸する間隙を形成するように表面保護シートを形成し、
前記表面保護シートが存在する状態で前記半導体ウエハの裏面研削を行い、
前記表面保護シートが存在する状態で前記半導体ウエハの裏面をプラズマエッチングすることを特徴とする半導体装置の製造方法。 - 前記間隙は、前記半導体ウエハの全面において連続して形成されることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記プラズマエッチングにおいて気泡の原因となる前記開口部内の空気は、前記間隙を通り、前記半導体ウエハの外周部から放出されることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記プラズマエッチングは、真空処理装置内で裏面研削後の研削ストレスを除去するために行われることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記凹部は、前記開口部を形成した後に、凹凸を有する治具を押し付けて形成することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記半導体ウエハの周辺の前記パッシベーション膜において、前記半導体ウエハの中央側から伸びた前記間隙の端部に壁を形成することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記壁は、裏面研削時に研削水が前記半導体ウエハの周辺に達した間隙から入りこむことを防止するために形成されることを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記パッシベーション膜は、ポリイミド被膜であることを特徴とする請求項7乃至請求項13のいずれか1項に記載の半導体装置の製造方法。
- 半導体ウエハを有する半導体装置の製造方法において、
前記半導体ウエハの主表面に半導体素子を形成し、
前記半導体素子を覆うようにパッシベーション膜を形成し、
前記パッシベーション膜を貫通するよう開口部を形成し、
前記パッシベーション膜の上面に、前記パッシベーション膜と自身との間に前記パッシベーション膜の前記開口部から前記半導体ウエハの外周部まで延伸する間隙を形成するように、凹部を備える表面保護シートを形成し、
前記表面保護シートが存在する状態で前記半導体ウエハの裏面研削を行い、
前記表面保護シートが存在する状態で前記半導体ウエハの裏面をプラズマエッチングすることを特徴とする半導体装置の製造方法。 - 前記プラズマエッチングは、真空処理装置内で裏面研削後の研削ストレスを除去するために行われることを特徴とする請求項15に記載の半導体装置の製造方法。
- 前記パッシベーション膜は、ポリイミド被膜であることを特徴とする請求項15又は請求項16に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006116541A JP4786403B2 (ja) | 2006-04-20 | 2006-04-20 | 半導体装置及びその製造方法 |
US11/736,991 US20070249118A1 (en) | 2006-04-20 | 2007-04-18 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006116541A JP4786403B2 (ja) | 2006-04-20 | 2006-04-20 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2007288092A JP2007288092A (ja) | 2007-11-01 |
JP4786403B2 true JP4786403B2 (ja) | 2011-10-05 |
Family
ID=38619978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006116541A Expired - Fee Related JP4786403B2 (ja) | 2006-04-20 | 2006-04-20 | 半導体装置及びその製造方法 |
Country Status (2)
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US (1) | US20070249118A1 (ja) |
JP (1) | JP4786403B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014138143A (ja) * | 2013-01-18 | 2014-07-28 | Toyota Motor Corp | 半導体装置の製造方法、半導体ウエハ、及び、半導体装置 |
JP5811110B2 (ja) * | 2013-01-31 | 2015-11-11 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
GB201620680D0 (en) * | 2016-12-05 | 2017-01-18 | Spts Technologies Ltd | Method of smoothing a surface |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4187952B2 (ja) * | 1998-01-20 | 2008-11-26 | ローム株式会社 | 半導体装置 |
US6162703A (en) * | 1998-02-23 | 2000-12-19 | Micron Technology, Inc. | Packaging die preparation |
DE19962763C2 (de) * | 1999-07-01 | 2001-07-26 | Fraunhofer Ges Forschung | Verfahren zum Vereinzeln eines Wafers |
DE60033218T2 (de) * | 1999-07-02 | 2007-11-15 | Canon K.K. | Verfahren zur Herstellung eines Flüssigkeitsausstosskopfes, damit hergestellter Flüssigkeitsausstosskopf, Kopfkassette, Flüssigkeitsausstossvorrichtung, Verfahren zur Herstellung einer Siliziumplatte und damit hergestellte Siliziumplatte |
JP3866073B2 (ja) * | 2001-10-10 | 2007-01-10 | 株式会社フジクラ | 半導体パッケージ |
US7169685B2 (en) * | 2002-02-25 | 2007-01-30 | Micron Technology, Inc. | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive |
US7087452B2 (en) * | 2003-04-22 | 2006-08-08 | Intel Corporation | Edge arrangements for integrated circuit chips |
JP2006100413A (ja) * | 2004-09-28 | 2006-04-13 | Tokyo Seimitsu Co Ltd | フィルム貼付方法およびフィルム貼付装置 |
-
2006
- 2006-04-20 JP JP2006116541A patent/JP4786403B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-18 US US11/736,991 patent/US20070249118A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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JP2007288092A (ja) | 2007-11-01 |
US20070249118A1 (en) | 2007-10-25 |
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