JP4784842B2 - Multiprocessor and multiprocessor system - Google Patents

Description

The present invention relates to an architecture of a multiprocessor having a plurality of CPUs (particularly, a single chip processor in which a plurality of CPUs are contained in a single chip) , and more specifically, a multigrain compiler cooperative single-chip multiprocessor. The present invention relates to architectures and high-performance multiprocessor system architectures connecting them.

  Currently, Japanese supercomputer manufacturers have the world's top hardware technology, and the peak performance at the present time exceeds several TFLOPS, and in the beginning of the 21st century machines with peak performance of several tens of TFLOPS will be developed. It is expected to be. However, with current supercomputers, the difference between the peak performance and the effective performance when the program is executed is large, that is, the price-performance ratio is not necessarily excellent. In terms of usability, the user must extract the parallelism in question and create a program that can use the hardware effectively using an extended language or library such as HPF, MPI, PVM, etc. The problem is that it is difficult or impossible to use for users. Furthermore, due to these reasons, the inability to expand the world's high-performance computer market is a major problem.

  To solve this price-performance ratio and ease-of-use problem and expand the supercomputer market, programs written in sequential languages such as Fortran and C, which users are accustomed to, are automatically parallelized. Development of an automatic parallelizing compiler is important.

  In particular, it is important to study a single-chip multiprocessor that is considered to be one of the main architectures of general-purpose and embedded microprocessors in the early 21st century and multiprocessor systems ranging from home servers to supercomputers. Furthermore, even with a single-chip multiprocessor, a conventional main memory sharing architecture cannot provide sufficient performance and an excellent price / performance ratio. Therefore, the system extracts more parallelism from the instruction sequence to be executed truly, like multi-grain parallel processing that can fully use instruction level parallelism, loop parallelism, and coarse grain parallelism in the program. It is important to develop a new automatic parallel compilation technology that can improve the price-performance ratio of the system and to build a user-friendly system that can be used by anyone, and an architecture that can make use of it.

  Accordingly, it is an object of the present invention to provide a compiler-cooperative single-chip multiprocessor that supports multigrain parallelization and a high performance multiprocessor system that combines them.

  The present invention is connected to a CPU, a network interface connected to the CPU, a distributed shared memory for storing data, a local data memory accessible only from the processing element, and one port of the distributed shared memory A multiprocessor comprising: a plurality of processing elements comprising: a data transfer controller; and a centralized shared memory connected to each processing element and shared by each processing element, the compiler for the multiprocessor Generates a data transfer instruction to the data transfer controller at the time of compilation and stores it in the local data memory before execution of the compiled program, and the CPU executes the execution of the compiled program. Sometimes instructing a data transfer instruction to be executed, and the data transfer controller receives an instruction of the data transfer instruction to be executed, reads the data transfer instruction from the local data memory according to the received instruction, and reads the read data transfer instruction In accordance with the present invention, a multiprocessor is provided that reads data from the distributed shared memory and transfers the data to the distributed shared memory of the processing element that consumes the data.

  Further, according to the present invention, the distributed shared memory and the local data memory are configured by a dual port memory, and the data transfer controller is connected to one port of the distributed shared memory and / or the local data memory, The multiprocessor according to claim 1, wherein the CPU is connected to another port of the distributed shared memory and / or the local data memory.

  As described above, according to the single chip multiprocessor of the present invention, it is possible to improve the price / performance ratio and to improve the performance scalable to the increasing degree of semiconductor integration. The present invention also provides a system including a plurality of such single-chip multiprocessors, but such a system enables higher-speed processing.

  The present invention provides a single chip multiprocessor that supports multigrain parallelism. FIG. 1 shows the architecture of a single chip multiprocessor according to an embodiment of the present invention. 1, a plurality (m + 1) of single-chip multiprocessors (SCM0, SCM1, SCM2,..., SCMm,..., SCMm, including a plurality of processing elements (PE0, PE1,..., PEn). ) 10 and a plurality (j + 1) of centralized shared memory chips (CSM0,..., CSMj) consisting only of shared memory (however, there may not be one CSM depending on the required system conditions) , An input / output chip (I / O SCM0,..., I / O SCMk) composed of a plurality of (k + 1) single-chip multiprocessors that perform input / output control Are also connected by the inter-chip connection network 12. The inter-chip connection network 12 can be realized by using existing network technologies such as a crossbar, a bus, and a multistage network.

  In the form shown in FIG. 1, the I / O device is connected to an input / output control chip composed of k + 1 SCMs according to required input / output functions. Furthermore, j + 1 centralized shared memory (CSM) chips 14 composed only of memories shared by all processing elements in the system are connected to the inter-chip connection network 12. This serves to complement the centralized shared memory in the SCM 10.

  Multi-grain parallel processing is a hierarchy of coarse-grained parallelism between subroutines, loops and basic blocks, medium-grained parallelism between loop type iterations (loop parallelism), and (near) fine-grained parallelism between statements or instructions. This is a parallel processing method that is used in an automated manner. This method is different from local parallel processing of single-granularity such as loop parallelization used in the conventional automatic parallelizing compiler for commercial multiprocessor systems, or instruction level parallelization in superscalar and VLIW, Flexible parallel processing with global and multiple granularity over the entire program is possible.

[Coarse grain task parallel processing (macro data flow processing)]
Coarse-grain parallel processing that uses parallelism between subroutines, loops, and basic blocks in a single program is also called macro data flow processing. For example, a Fortran program as a source is a coarse-grained task (macro task), and is a repetition block (RB), a subroutine block (SB), a pseudo assignment statement (BPA) block 3 Break down into types of macrotasks (MT). RB is the outermost natural loop in each layer, SB is a subroutine, and BPA is a basic block that is merged or divided in consideration of scheduling overhead or parallelism. Here, BPA is basically a normal basic block, but a single basic block is divided into a plurality of parts for parallelism extraction, or conversely, the processing time of one BPA is short, and dynamic scheduling If the overhead is not negligible, a plurality of BPAs can be merged to generate one BPA. When the RB that is the outermost loop is a Doall loop, the loop index is divided into a plurality of partial Doall loops, and the divided partial Doall loop is newly defined as an RB. Subroutine SB is expanded inline as much as possible, but a subroutine that cannot be effectively expanded inline is defined as SB as it is in consideration of the code length. Furthermore, in the case of RBs and RBs that cannot be dealt with, hierarchical macro data flow processing is applied to the internal parallelism.

  Next, the control flow and data dependency between macro tasks are analyzed, and a macro flow graph (MFG) as shown in FIG. 2 is generated. In the MFG, each node is a macrotask (MT), a dotted edge represents a control flow, a solid line edge represents data dependence, and a small circle in the node represents a conditional branch sentence. The MT7 loop (RB) indicates that MT and MFG can be defined hierarchically inside.

  Next, the condition that each macrotask can be executed earliest than the control dependency between macrotasks and data dependency (early executable condition), that is, the parallelism between macrotasks is detected. A macrotask graph (MTG) shown in FIG. 3 expresses this parallelism in a graph. Even in MTG, a node is MT, a solid line edge is data-dependent, and a small circle in the node represents a conditional branch sentence. However, the dotted edge represents the extended control dependence, the edge with the arrow represents the branch destination in the original MFG, the solid arc represents the AND relationship, and the dotted arc represents the OR relationship. For example, the edge to MT6 indicates that MT6 can execute the earliest when the conditional branch in MT2 branches in the direction of MT4 or when the execution of MT3 ends.

  Then, the compiler assigns MT on MTG to a processor cluster (a compiler or a group of processors realized by software by a user) at the time of compilation (static scheduling) or dynamic scheduling code for assigning at the time of execution. The dynamic CP algorithm is generated and embedded in the program. This is to avoid the overhead of several thousand to several tens of thousands of clocks when the OS or library is requested to generate and schedule coarse-grained tasks as in the conventional multiprocessor. During this dynamic scheduling, it is not known which processor will execute the task until the execution time, so the shared data between tasks is allocated to a centralized shared memory that appears equidistant from all the processors.

  In addition, when generating the static scheduling and dynamic scheduling code, a data localization method for effectively using the local memory or the distributed shared memory on each processor and minimizing the data transfer amount between the processors is also used.

  Data localization analyzes data dependence between iterations over multiple different loops with data dependence on MTG (inter-loop data dependence analysis), and splits loops and data to minimize data transfer (loop-consistent division) ) Later, either a task fusion method that fuses these loops at compile time so that the loop and data are scheduled to the same processor, or a partial static scheduling algorithm that the compiler specifies to be assigned to the same processor at runtime To generate dynamic scheduling code. Using this data localization function, each local memory can be effectively used.

  At this time, preload / poststore scheduling algorithms that attempt to conceal the data transfer overhead by overlapping the data transfer and macrotask processing are also used for data transfer between processors that could not be removed by data localization. Is done. Based on the scheduling result, data transfer using the data transfer controller on each processor is realized.

[Loop parallel processing (medium grain parallel processing)]
In multi-grain parallelization, a loop (RB) assigned to a processor cluster (PC) by macro data flow processing is an iteration level with respect to a processing element (PE) in the PC when the RB is a Doall or Doacross loop. Parallelized (divided).

For loop structuring, the following conventional techniques can be used as they are.
(A) Statement execution order change (b) Loop distribution (c) Node splitting scalar expansion (d) Loop interchange (e) Loop unrolling (f) Strip mining (g) Array privateization (h) Unimodular Transformation (loop reversal, permutation, skewing)
For loops to which loop parallelization processing cannot be applied, the loop body part is described as follows (near) fine-grain parallel processing as shown in FIG. 4, or the body part is hierarchically divided into macro tasks and macro data flow processing ( Coarse grain task parallel processing) is applied.

[(Near) Fine Grain Parallel Processing]
When the MT assigned to the PC is BPA, loop parallelization, or RB that cannot apply the macro data flow processing hierarchically, a statement or instruction inside the BPA is processed in parallel by a processor in the PC as a near-fine-grain task.

  In near-fine-grain parallel processing on a multiprocessor system or single-chip multiprocessor, efficient parallel processing can be achieved if tasks are not scheduled to the processor to minimize not only the load balance between processors but also the data transfer between processors. Cannot be realized. Furthermore, in the scheduling required for this near-fine-grain parallel processing, as shown in the task graph of FIG. 4, there is a restriction of the execution order due to data dependence between tasks, which makes a strong NP complete and very difficult scheduling problem. . This graph is a non-cycle directed graph. In the figure, each task corresponds to each node. The number in the node represents the task number i, and the number beside the node represents the task processing time ti on the processing element. An edge drawn from the node Ni to Nj represents a partial order constraint that the task Ti precedes Tj. When considering the data transfer time between tasks, each edge generally has a variable weight. When tasks Ti and Tj are assigned to different processing elements, this weight tij becomes the data transfer time. In FIG. 4, it is assumed that the time required for data transfer and synchronization is 9 clocks. Conversely, when these tasks are assigned to the same processing element, the weight tij is zero.

  The task graph generated in this manner is statically scheduled to each processor. At this time, as a scheduling algorithm, a heuristic algorithm that minimizes execution time in consideration of data transfer overhead, for example, four methods of CP / DT / MISF method, CP / ETF / MISF method, ETF / CP method, or DT / CP method Can be applied automatically to choose the best schedule. In addition, by assigning tasks to processors in this way, the optimization of data in memory such as local memory, distributed shared memory, and register allocation of data used in BPA, and minimum data transfer / synchronization overhead Various optimizations such as optimization are possible.

  After scheduling, the compiler arranges the instruction sequences of tasks assigned to the processing elements in order, and inserts data transfer instructions and synchronization instructions at necessary locations, thereby generating machine code for each processor. The version number method is used for synchronization between near-fine-grain tasks, and the synchronization flag is received by the busy wait of the receiving processing element. Here, the data transfer and the setting of the synchronization flag can be performed with low overhead by the transmitting processor directly writing to the distributed shared memory on the receiving processor.

  When generating machine code, the compiler can perform code optimization using static scheduling information. For example, when different tasks using the same data are assigned to the same processing element, the data can be passed through a register. Further, in order to minimize synchronization overhead, redundant synchronization can be removed from the task assignment status and execution order. In particular, in single-chip multiprocessors, strict code execution scheduling is performed during code generation, so that the compiler controls all instruction execution including data transfer timing during execution, and all synchronous code is removed to execute in parallel. Ultimate optimization such as asynchronous parallelization that enables

  In order to realize the multigrain parallel processing as described above on a multiprocessor system, as an example, a single chip multiprocessor (SCM) 10 has an architecture as shown in FIG.

  In the architecture shown in FIG. 1, in addition to the CPU 20, a distributed shared memory (DSM) 22 and an adjustable prefetch instruction cache 24 are provided in each SCM 10. The CPU 20 used here is not particularly limited as long as it can perform integer arithmetic and floating point arithmetic. For example, a simple single issue RISC architecture CPU having a load / store architecture can be used, and a superscalar processor, a VLIW processor, or the like can also be used. The distributed shared memory 22 is composed of a dual port memory, and can be directly read / written from other processing elements, and is used for data transfer between near-fine-grain tasks described above.

  The adjustable prefetch instruction cache 24 prefetches an instruction to be executed in the future from a memory or a low level cache in accordance with an instruction from a compiler or a user. This adjustable prefetch instruction cache 24 is a multi-way set associative cache that can fetch a line (instruction string) to be executed in the future in a way designated by software such as a compiler or predetermined by hardware. To do. At that time, as a fetch unit, a continuous transfer instruction of a plurality of lines can also be given. The adjustable prefetch instruction cache 24 is a cache system that enables adjustment and control by a compiler that minimizes miss hits to the instruction cache and enables high-speed instruction execution.

  In other words, this adjustable prefetch instruction cache 24 can be adapted to a large program, unlike a local program memory that assumes that all programs (instruction sequences) are smaller than the memory size. It can be used as a normal cache without prefetching, or conversely, can be used as a prefetch cache under compiler control, and can be used as a cache with no miss (no miss).

  An example of the structure of such an adjustable prefetch instruction cache is shown in FIG. The n-way set associative cache shown in FIG. 5 can be used as an area for prefetching (pre-reading) the j-way designated by the compiler or the user according to the program. The prefetch instruction inserted by the compiler (prefetching of a plurality of lines instead of each line is possible) enables necessary instructions to be present on the instruction cache before the instruction is executed, thereby realizing high speed. The processing element can read all n ways in the same way as a normal cache. The replacement of the line is performed by a normal LRU (least recently used) method. A way in each set (aggregation) can normally store freely transferred lines, but a way designated for prefetch stores only lines transferred from the CSM by a prefetch instruction. The other ways are assigned lines in the same way as a normal cache. The prefetch cache controller prefetches instructions from the CSM according to instructions from the compiler. The unit of transfer at this time is from one line to a plurality of lines. The compiler designates a prefetch area for j ways, and the other (n−j) way areas are used as a normal cache.

  Further, in the architecture of FIG. 1, a local data memory (LDM) 26 is provided. The local data memory 26 is a memory that can be accessed only within each processing element 16 and is used to hold local data used between tasks assigned to each processing element 16 by a data localization technique or the like. . The local data memory 26 is used as a local memory when the compiler or the user can divide the data into the local memory for the target application program, and when the local memory cannot be used effectively. Is preferably switched to a level 1 cache (D cache). In addition, when used exclusively for real-time applications such as game machines, it is also possible to design as a local memory only. Since the memory is basically used in each processing element, the chip area is not consumed as compared with the shared memory, so that a relatively large capacity can be obtained.

  In coarse grain parallel processing, dynamic scheduling is used to deal with conditional branches. In this case, it is not known at the time of compilation which processor the macrotask is executed on. Therefore, it is preferable that shared data between dynamically scheduled macrotasks can be placed in a centralized shared memory (CSM). Therefore, in this embodiment, a centralized shared memory 28 for storing data shared by the processing elements 16 is provided in each SCM, and a centralized shared memory 14 connected to the inter-chip connection network 12 is further provided. This centralized shared memory 28 in the chip is a memory for storing data shared by all the processing elements 16 in the chip 10 and also by processing elements on other chips in a multi-chip configuration. Similarly, the central shared memory 14 outside the chip is a memory shared by the processing elements. Therefore, in the actual design, the centralized shared memories 28 and 14 are physically distributed in each chip, but logically can be shared equally from any processing element. It can be implemented so that all processing elements appear equidistant, or it can be implemented so that it appears close to the processing elements in its own chip.

  In a system composed of a single SCM chip, this centralized shared memory 28 can be used as an equidistance shared memory shared between processing elements (PE) 16 in the chip. If optimization of the compiler is difficult, it can be used as an L2 cache. The memories 28 and 14 mainly store data shared between tasks during dynamic task scheduling. In addition, if the capacity of the centralized shared memory 28 in the SCM chip 10 is insufficient, the centralized shared memory 14 that is a separate chip can be connected to an arbitrary number of large-capacity centralized shared memory chips that include only the memory as necessary. can do.

  In addition, when static scheduling can be applied regardless of the granularity, it is possible to know which processor needs shared data defined by a macrotask at compile time, so that the processor on the production side distributes the shared shared memory of the processor on the consumption side. It is preferable to directly write data and a synchronization flag.

  The data transfer controller (DTC) 30 performs data transfer between the DSM 22 on its own processing element, the CSM 28 in itself or another SCM 10, or the DSM on another processing element, according to a compiler or user instruction. When adopting a configuration composed of a plurality of SCMs, data transfer with CSMs and DSMs on other SCMs or data transfer with independent CSMs is performed.

  The dotted line between the local data memory 26 and the data transfer controller 30 in FIG. 1 indicates that the data transfer controller 30 may be able to access the local data memory (D cache) 26 depending on the application. In such a case, it can be configured that the CPU 20 gives a transfer instruction to the data transfer controller 30 via the local data memory 26 or checks the end of the transfer.

  The data transfer instruction to the data transfer controller 30 is made via the local data memory 26, the DSM 22, or a dedicated buffer (not shown), and the end of data transfer from the data transfer controller 30 to the CPU 20 is reported to the local memory, This is done through DSM or a dedicated buffer. At this time, which one is used is determined at the time of designing the processor according to the use of the processor, or a plurality of hardware methods are prepared so that the compiler or the user can use the software properly according to the characteristics of the program.

  The data transfer instruction to the data transfer controller 30 (for example, from where to store and load the internal byte data, the data transfer mode (continuous data transfer, stride, stride / stride transfer, etc.), etc.) However, it is possible to reduce the overhead for driving the data transfer controller 20 by storing the data transfer instruction in a memory or a dedicated buffer and issuing only an instruction on which data transfer instruction is executed at the time of execution. preferable.

  The connection between the processing elements 16 in each SCM chip 10 is achieved by an in-chip connection network (consisting of a multibus, a crossbar, etc.) 34 via a network interface 32 provided in each processing element. Processing elements are connected to a common centralized shared memory 28 via the intra-chip connection network 34. The centralized shared memory 28 is connected to the inter-chip connection network 12 outside the chip. The inter-chip connection network is particularly preferably a crossbar network or a bus (including a plurality of buses), but may be a multi-stage connection network or the like, and can be selected according to the budget, the number of SCMs, and application characteristics. . Further, it is possible to connect the external inter-chip connection network 12 and the network interface 32 without going through the intra-chip connection network 34. With such a configuration, all the processing elements in the system are equally connected to each chip. In addition to making it possible to access the centralized shared memory and distributed shared memory distributed above, if there is a lot of data transfer between chips, providing this direct connection path greatly increases the data transfer capacity of the entire system. Can be increased.

  The global register file 36 is a multi-port register, and is a register shared by processing elements in the chip. For example, it can be used for data transfer and synchronization of near fine-grain tasks (such as when using distributed shared memory). This global register file can be omitted depending on the use of the processor.

  In FIG. 1, a dotted line means that a communication line can be prepared as needed, and if it is unnecessary or difficult considering the cost or the number of pins, it can be operated without a dotted line connection. It is shown.

  As described above, the present invention has been described based on specific embodiments. However, the technical scope of the present invention is not limited to such embodiments, and various modifications that are easy for those skilled in the art can be made. Is included.

It is a block diagram which shows the system for multi-grain parallel processing which is one Embodiment of this invention. It is a graph which shows an example of the macro flow graph for the coarse grain parallel processing in the compiler which can be used in this invention. It is a graph which shows an example of the macrotask graph for the coarse grain parallel processing in the compiler which can be used in this invention. It is a graph which shows an example of the near fine grain task graph for the near fine grain parallel processing in the compiler which can be used in this invention. It is a block diagram which shows the structure of the adjustable prefetch instruction cache which can be used in this invention.

Explanation of symbols

10 Single-chip multiprocessor 12 Inter-chip connection network 14 Centralized shared memory (chip)
16 Processing element 20 CPU
22 Distributed Shared Memory 24 Adjustable Prefetch Instruction Cache 26 Local Data Memory 28 Centralized Shared Memory 30 Data Transfer Controller 32 Network Interface 34 Intra-Chip Connection Network

Claims (4)

CPU, network interface connected to the CPU, distributed shared memory for storing data, local data memory accessible only from the processing element, and data transfer connected to one port of the distributed shared memory A plurality of processing elements comprising a controller;
A multi-processor comprising: a centralized shared memory connected to each processing element and shared by each processing element;
The multiprocessor compiler generates a data transfer instruction to the data transfer controller at the time of compilation, and stores it in the local data memory before executing the compiled program,
The CPU instructs a data transfer instruction to be executed when the compiled program is executed,
The data transfer controller receives an instruction of a data transfer instruction to be executed, reads a data transfer instruction from the local data memory according to the received instruction, reads data from the distributed shared memory according to the read data transfer instruction , A multiprocessor, wherein the data is transferred to a distributed shared memory of a processing element that consumes the data . The distributed shared memory is composed of a dual port memory,
The data transfer controller is connected to one port of the distributed shared memory,
The multiprocessor according to claim 1, wherein the CPU is connected to another port of the distributed shared memory. The local data memory is a dual port memory,
The data transfer controller is connected to one port of the local data memory,
The multiprocessor according to claim 1, wherein the CPU is connected to another port of the local data memory. The data transfer controller notifies the CPU of the end of data transfer by the read data transfer instruction to the CPU via the local data memory . Multiprocessor.

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