JP4768476B2 - Drive device for self-extinguishing semiconductor element - Google Patents

Description

  The present invention relates to a drive device for a self-extinguishing semiconductor element such as a MOS (Metal Oxide Semiconductor) gate self-extinguishing semiconductor element represented by an IGBT (Insulated Gate Bipolar Transistor).

  When driving the gate of a MOS gate self-extinguishing semiconductor device typified by IGBT, in order to charge and discharge the gate charge in a short time and to increase the switching speed of the MOS gate self-extinguishing semiconductor device, The output current of the gate drive circuit to be driven, that is, the current that the gate drive circuit gives to the gate needs to be sufficiently large.

  Therefore, a complementary emitter follower circuit with low output impedance is used for the output stage of the gate drive circuit when a bipolar transistor is used, and a complementary type is used when a field effect transistor (abbreviated as FET) is used. A source follower circuit is used (for example, see Non-Patent Document 1).

"Revised power control circuit design know-how" co-authored by Yasunobu Saita, Satoshi Mori and Yoshinori Yuu, CQ Publishing Company, June 1, 1997, pp. 84-85

  When a complementary emitter follower circuit or a complementary source follower circuit is used at the output stage of the gate drive circuit, there is a problem in that the power supply utilization rate decreases.

  In order to improve the use efficiency of the power supply voltage, it is conceivable to connect the drain of the N-channel FET and the drain of the P-channel FET and the drain to configure the output stage of the gate drive circuit. When the drain and the P-channel FET are connected to the drain, there is a problem that a short-circuit current passing through the two FETs easily flows during a switching transient. By connecting a resistor that limits the current flowing into the gate to the gate drive circuit of the two FETs, it is possible to prevent the occurrence of a short-circuit current through the two FETs during a switching transient. As a result, there is a problem that the switching speed of the FET by the gate drive circuit is lowered. In order to drive an N-channel FET and a P-channel FET, a level conversion circuit that supplies two in-phase signals having different average levels of DC voltages is required. Such a level conversion circuit can be realized by, for example, a grounded-emitter circuit. However, if the level conversion circuit is realized by a grounded-emitter circuit, the signal delay time is large, and the drive timings of the two FETs are aligned by this delay time. There is a problem that it is difficult to promote the short-circuit current. As a result, there is a problem that it is necessary to further increase the resistance of the resistor and further reduce the switching speed.

  An object of the present invention is to improve power supply utilization, prevent a short-circuit current in a field effect transistor in an output stage, and improve the switching speed of a driving self-extinguishing semiconductor device. Type semiconductor device drive device.

The present invention includes a signal input unit for inputting a drive signal;
The first NPN type and the first PNP type bipolar transistor, each emitter of the first NPN type and the first PNP type bipolar transistor is connected, and the first NPN type and the first PNP type bipolar transistor Are connected to the signal input unit, the collector of the first NPN bipolar transistor is connected to the positive voltage source, and the collector of the first PNP bipolar transistor is connected to the negative voltage source. A complementary emitter follower circuit of
Connecting the emitters of the second NPN-type and second PNP-type bipolar transistors, the first NPN-type and first PNP-type bipolar transistors and the emitters of the second NPN-type and second PNP-type bipolar transistors Connecting the collector of the second NPN bipolar transistor and the positive voltage source, and connecting the collector and negative voltage source of the second PNP bipolar transistor. A complementary base ground circuit having a negative collector load resistor and connected to the emitters of the second NPN-type and second PNP-type bipolar transistors;
A third NPN type and a third PNP type bipolar transistor, each emitter being connected to the third NPN type and the third PNP type bipolar transistor; Is connected to the positive voltage source via the positive collector load resistor, the collector of the third NPN bipolar transistor is connected to the positive voltage source, and the collector of the third PNP bipolar transistor is connected to the ground. A second complementary emitter follower circuit connected;
A fourth NPN-type and a fourth PNP-type bipolar transistor, each emitter being connected to the fourth NPN-type and the fourth PNP-type bipolar transistor; Are connected to the negative voltage source via the negative collector load resistor, the collector of the fourth NPN bipolar transistor is connected to the ground, and the collector of the fourth PNP bipolar transistor is connected to the negative voltage source. A third complementary emitter follower circuit connected to
P-channel and N-channel field effect transistors are provided, the drains of the P-channel and N-channel field effect transistors are connected, and the gate of the P-channel field effect transistor is connected to the emitter of the third NPN bipolar transistor. The gate of the N-channel field effect transistor is connected to the emitter of the fourth PNP-type bipolar transistor, the source of the P-channel field effect transistor is connected to the positive voltage source, and the source of the N-channel field effect transistor is the negative electrode A self-extinguishing field effect transistor circuit connected to the side voltage source and connected to the drain of each of the P-channel and N-channel field effect transistors and the control terminal of the self-extinguishing semiconductor element. Type semiconductor device drive device.

  According to the present invention, the drive signal input from the signal input unit is applied to each gate of the first NPN-type and first PNP-type bipolar transistors constituting the first complementary emitter follower. In the first complementary emitter follower and the complementary base ground circuit to which the output signal of the first complementary emitter follower is input, the first NPN bipolar transistor operates, that is, the first NPN bipolar transistor is turned on. The second PNP bipolar transistor operates when the current flows between the collector and the emitter of the first NPN bipolar transistor, that is, the second NPN bipolar transistor is turned on, and the second NPN bipolar transistor is turned on. A current flows between the collector and emitter of the PNP type bipolar transistor. When the first PNP type bipolar transistor operates, that is, when the first PNP type bipolar transistor is turned on and current flows between the collector and emitter of the first PNP type bipolar transistor, the second NPN type bipolar transistor Operates, that is, the second NPN type bipolar transistor is turned on, and a current flows between the collector and emitter of the second NPN type bipolar transistor. That is, when one of the first PNP type and the first NPN type bipolar transistor is in the ON state, the other is in the OFF state, and one of the second PNP type and the second NPN type bipolar transistor is When in the ON state, the other is in the OFF state. Further, when one of the first PNP type and the second PNP type bipolar transistor is in an ON state, the other is in an OFF state. When one of the first NPN type and the second NPN type bipolar transistor is in an ON state, The other is in the OFF state.

  When the first PNP-type bipolar transistor and the second NPN-type bipolar transistor are turned on, a current flows through the positive collector load resistor, so that the second complementary is caused by the voltage effect of the positive collector load resistor. The base potentials of the third NPN-type and third PNP-type bipolar transistors constituting the type emitter follower circuit are lowered from the potential of the positive-side power supply. As a result, the third PNP bipolar transistor operates, that is, the third PNP bipolar transistor is turned on. As a result, the potential of the gate of the P-channel field effect transistor connected to the emitter of the PNP-type bipolar transistor via the resistor is lowered. When the gate potential of the P-channel field effect transistor decreases, a predetermined potential difference is generated between the gate and source of the P-channel field effect transistor, the P-channel field effect transistor is turned on, and the P-channel field effect transistor is turned on. A current flows through the source and drain of the transistor, and the potential of the positive voltage source can be applied to the control terminal of the self-extinguishing semiconductor element connected to the drain.

  Further, when the first NPN type bipolar transistor and the second PNP type bipolar transistor are in the OFF state, no current flows through the negative side collector load resistor, so that the fourth NPN type and the fourth PNP type The potential of each base of the bipolar transistor is substantially equal to the potential of the negative voltage source. At this time, the fourth NPN type bipolar transistor is in the OFF state, and the potential of the gate of the N-channel field effect transistor becomes the potential (V−) of the negative side power supply Vss. Therefore, the gate and source of the N-channel field effect transistor Since the potential difference between them becomes almost 0 V, the voltage becomes lower than the on-voltage of the N-channel field effect transistor, so that the N-channel field effect transistor is in the OFF state.

  When the first NPN-type bipolar transistor and the second PNP-type bipolar transistor are turned on, a current flows through the negative collector load resistor, so that the second complementary is caused by the voltage effect of the negative collector load resistor. The base potentials of the fourth NPN-type and fourth PNP-type bipolar transistors constituting the type emitter follower circuit rise from the potential of the negative power supply. As a result, a voltage is applied between the base and emitter of the fourth NPN type bipolar transistor, and the fourth NPN type bipolar transistor operates, that is, the fourth NPN type bipolar transistor is turned on. As the fourth NPN bipolar transistor is turned on, the potential of the gate of the N-channel field effect transistor connected to the emitter of the fourth NPN bipolar transistor through the resistor rises. When the gate potential of the N-channel field effect transistor increases, a predetermined potential difference is generated between the gate and source of the N-channel field effect transistor, the N-channel field effect transistor is turned on, and the N-channel field effect transistor is turned on. A current flows through the source and drain of the transistor, and the potential of the negative voltage source can be applied to the control terminal of the self-extinguishing semiconductor element connected to the drain.

  Further, when the first NPN type bipolar transistor and the second PNP type bipolar transistor are in the ON state, no current flows through the positive collector load resistor, so that the third NPN type and the third PNP type The potential of each base of the bipolar transistor is substantially equal to the potential of the positive voltage source. At this time, the third PNP-type bipolar transistor is in an OFF state, and the potential of the gate of the P-channel field effect transistor becomes the potential (V +) of the positive power supply Vcc, and therefore, between the gate and the source of the P-channel field effect transistor. Since the potential difference between the first and second transistors becomes approximately 0 V, the ON voltage of the P-channel field effect transistor becomes smaller, so that the N-channel field effect transistor is in the OFF state.

  The P-channel field effect transistor transitions from the OFF state to the ON state in the process of lowering the base potential of the third PNP type and the third NPN type bipolar transistor, and the third PNP type and the third NPN type In the process of increasing the potential of the base of the bipolar transistor, the state transits from the ON state to the OFF state. That is, when the first PNP type and the second NPN type bipolar transistor are turned on, a current flows to the positive collector load resistor, and the voltage drop due to the positive collector load resistor increases. The P-channel field effect transistor transitions from the ON state to the OFF state in the process in which the voltage drop due to the positive collector load resistor decreases. Accordingly, the P-channel field effect transistor is turned on only when a current flows through the positive collector load resistor and the voltage drop caused by the positive collector load resistor is equal to or higher than a predetermined voltage.

  The N-channel field effect transistor transitions from the OFF state to the ON state in the process of increasing the base potential of the fourth PNP type and the fourth NPN type bipolar transistor, and the fourth PNP type and the fourth NPN type Transition from the ON state to the OFF state in the process of lowering the potential of the base of the bipolar transistor. That is, when the first NPN-type and second PNP-type bipolar transistors are turned on, current flows into the negative collector load resistor, and the voltage drop due to the negative collector load resistor increases. The N-channel field effect transistor transitions from the ON state to the OFF state in the process in which the voltage drop due to the negative collector load resistor is reduced. Therefore, the N-channel field effect transistor is turned on only when a current flows through the negative collector load resistor and the voltage drop due to the negative collector load resistor is equal to or higher than a predetermined voltage.

  The P-channel field effect transistor is turned on only when a current flows through the positive collector load resistor and the voltage drop caused by the positive collector load resistor is equal to or higher than a predetermined voltage. Only when the current flows through the negative collector load resistor and the voltage drop due to the negative collector load resistor is equal to or higher than a predetermined voltage, the ON state is established, and the first complementary emitter follower circuit and the complementary base ground circuit Are connected as described above, a current can be selectively passed through either the positive collector load resistor or the positive collector load resistor, so that a P-channel and an N-channel field effect transistor are connected. One of them can be selectively turned on and the other can be turned off.

  When the P-channel field effect transistor is turned on, the control terminal of the self-extinguishing semiconductor element can be applied up to the potential of the positive voltage source connected to the source of the P-channel field effect transistor, When the field effect transistor is turned on, the potential of the negative voltage source connected to the source of the N-channel field effect transistor can be applied to the control terminal of the self-extinguishing semiconductor element.

  As described above, the first to fourth NPN bipolar transistors and the first to fourth PNP bipolar transistors are all unsaturated by connecting the first to fourth NPN bipolar transistors and the first to fourth PNP bipolar transistors. It operates in the region, that is, the voltage between the collector and the emitter does not become 0V.

  According to the present invention, the signal input unit includes a photocoupler, and a drive signal is supplied to each base of the first PNP type and the first NPN type bipolar transistor through the photocoupler.

  According to the present invention, the signal input unit applies the drive signal to the respective bases of the first PNP type and the first NPN type bipolar transistor through the photocoupler. The signal line can be electrically insulated from the output side connected to the arc type semiconductor element.

  Further, the present invention is connected between the emitters of the third NPN type and the third PNP type bipolar transistor and at least one of the emitters of the fourth NPN type and the fourth PNP type bipolar transistor. A resistor for limiting the current is included.

  According to the present invention, a current limiting resistor R7 is connected between the emitters of the third NPN-type and third PNP-type bipolar transistors, so that the third NPN-type and third PNP-type bipolar transistors are connected. The short-circuit current that flows when the transistor is in a transient state between an ON state and an OFF state can be reduced. Further, since the magnitude of the discharge current of the gate of the P-channel field effect transistor can be adjusted by the resistor R7, the response speed when the P-channel field effect transistor is turned from the OFF state to the ON state can be adjusted. As the resistance value of the current limiting resistor increases, the turn-on time of the P-channel field effect transistor can be increased. Further, a current limiting resistor R8 is connected between the emitters of the fourth NPN-type and fourth PNP-type bipolar transistors, so that the fourth NPN-type and fourth PNP-type bipolar transistors are turned on. It is possible to reduce the short-circuit current that flows in the transient state with the OFF state. In addition, since the magnitude of the discharge current of the gate of the N-channel field effect transistor can be adjusted by the resistor R8, the response speed when the N-channel field effect transistor changes from the OFF state to the ON state can be adjusted. As the resistance value of the current limiting resistor increases, the turn-on time of the N-channel field effect transistor can be increased.

  According to the present invention, the drains of the P-channel and N-channel field effect transistors are connected to form the output stage of the driving device, so that the N-channel and P-channel field effect transistors are rail-to-rail. The operating terminal, that is, the control terminal of the self-extinguishing semiconductor element can be supplied from the potential of the positive-side voltage source to the potential of the negative-side voltage source, and the power supply voltage utilization efficiency can be improved.

  In addition, since one of the P-channel and N-channel field effect transistors can be selectively turned on and the other can be turned off, the switching operation of the P-channel and N-channel field effect transistors is in a transient state. Sometimes, both the P-channel and N-channel field effect transistors are prevented from being turned on, and a short circuit between the positive-side voltage source and the negative-side voltage source is prevented, and the P-channel and N-channel field effects are prevented. The breakdown of the transistor can be prevented.

  The first to fourth NPN bipolar transistors and the first to fourth PNP bipolar transistors all operate in the non-saturated region, that is, operate in the active region. Therefore, the delay time due to the minority carrier accumulation effect in each bipolar transistor is shortened. Thus, the operation speed of each bipolar transistor can be improved. As a result, a signal based on the input drive signal can be given to the control terminal of the self-extinguishing semiconductor element at high speed, and the switching operation of the self-extinguishing semiconductor element can be speeded up.

  Further, as described above, since both the P-channel and N-channel field effect transistors are not turned on at the same time, a current limiting transistor for limiting the current applied to the control terminal of the self-extinguishing semiconductor element is used. Even when a resistor is provided, it is not necessary to increase the resistance value of the current limiting resistor for the purpose of preventing both the P-channel and N-channel field effect transistors from being turned on simultaneously. The switching speed of the arc type semiconductor element is not reduced.

  Further, according to the present invention, since the signal line can be insulated between the input side to which the drive signal is input and the output side connected to the self-extinguishing semiconductor element, the input side and the output side Even when the signal voltage is different, the low-voltage circuit is not easily affected by the high-voltage circuit, and the low-voltage circuit can be protected, improving the reliability of the drive device. Can do. Therefore, for example, when a signal output from a microcomputer or the like is input from a signal input unit, a large current used for an inverter device, a chopper device, or the like flows, and a self-extinguishing semiconductor element to which a high voltage is applied is stabilized. Can be driven.

  According to the present invention, since the current limiting resistor is connected, the turn-on time of at least one of the P-channel field effect transistor and the P-channel field effect transistor can be adjusted. The degree of freedom in design can be improved by selecting the resistance value of the current limiting resistor according to the characteristics of the self-extinguishing semiconductor element.

  FIG. 1 is a circuit diagram showing a self-extinguishing semiconductor device driving apparatus 1 according to an embodiment of the present invention. FIG. 1 also shows a self-extinguishing semiconductor element. Hereinafter, the self-extinguishing semiconductor element driving device 1 is simply referred to as a driving device 1. The self-extinguishing type semiconductor element is realized by a MOS (Metal Oxide Semiconductor) gate self-extinguishing type semiconductor element such as an IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a power MOSFET. The drive device 1 of the present embodiment drives an IGBT element 10 that constitutes an inverter device 40 described later. The drive device 1 inputs a PWM (Pulse Width Modulation) signal that is a drive signal for driving the IGBT device 10 constituting the inverter device 40, and an IGBT device that is a self-extinguishing semiconductor device based on the drive signal 10 is driven.

The driving device 1 includes a photocoupler insulation circuit 2 that is a signal input unit, a voltage / current conversion circuit 3 that converts an output voltage from the photocoupler insulation circuit 2 into a current, and an output current from the voltage / current conversion circuit 3. FET (Field Effect) which is a signal output unit for driving IGBT based on
Transistor) drive circuit 4, positive side conductive path 5 connected to positive side voltage source Vcc, negative side conductive path 6 connected to negative side voltage source Vss, and ground conduction connected to ground (GND). Road 7 is included. The positive voltage source Vcc and the negative voltage source Vss are DC voltage sources that output a DC voltage. The positive side voltage source Vcc gives a potential higher than the ground potential to the positive side conductive path 5, and gives a positive potential in the present embodiment. The negative electrode side voltage source Vss applies a potential lower than the ground potential to the negative electrode side conductive path 6, and in this embodiment, applies a negative potential. A positive potential that the positive voltage source Vcc gives to the positive conductive path 5 is V +, and a negative potential that the negative voltage source Vss gives to the negative conductive path 6 is V−. Here, the potential of the ground conductive path 7 connected to the ground (GND) is selected to be, for example, zero (0) volts (V), the V + is selected to be, for example, 15V, and V− is, for example, −7.5V. Is selected.

  The positive electrode side conductive path 5 and the ground conductive path 7 are connected via positive power supply side decoupling capacitors C1 and Cp1. Positive power supply side decoupling capacitors C1 and Cp1 are configured to include two capacitors having different capacities. Of the positive power supply side decoupling capacitors C1 and Cp1, the first positive power supply side decoupling capacitor C1 having a large capacity is realized by, for example, an electrolytic capacitor, and has a smaller capacity than the first positive power supply side decoupling capacitor C1. The two positive power supply side decoupling capacitors Cp1 are realized by, for example, a film capacitor. Positive power supply side decoupling capacitors C1 and Cp1 are connected in parallel. The positive power supply side decoupling capacitors C1 and Cp1 can suppress fluctuations in voltage between the positive electrode side conductive path 5 and the ground conductive path 7, and the impedance of the positive voltage source voltage source Vcc to the ground over a wide frequency range. Therefore, the driving device 1 can be operated stably. The capacity of the first positive power supply side decoupling capacitor C1 is selected to be 220 μF, for example, and the second positive power supply side decoupling capacitor Cp1 is selected to be 0.1 μF, for example.

  Negative potential conductive path 6 and ground conductive path 7 are connected via positive power supply side decoupling capacitors C2 and Cp2. Negative power supply side decoupling capacitors C2 and Cp2 are configured to include two capacitors having different capacities. Of the negative power supply side decoupling capacitors C2 and Cp2, the first negative power supply side decoupling capacitor C2 having a large capacity is realized by, for example, an electric field capacitor and has a capacity larger than that of the first negative power supply side decoupling capacitor C2 having a large capacity. The second negative power supply side decoupling capacitor Cp2 having a small size is realized by, for example, a film capacitor. Negative power supply side decoupling capacitors C2 and Cp2 are connected in parallel. The negative power supply side decoupling capacitors C2 and Cp2 can suppress fluctuations in the voltage between the negative potential conductive path 6 and the ground conductive path 7, and the impedance of the negative voltage source Vss to the ground over a wide frequency range. Therefore, the driving device 1 can be operated stably. The capacity of the first negative power supply side decoupling capacitor C2 is selected to be 220 μF, for example, and the second negative power supply side decoupling capacitor Cp2 is selected to be 0.1 μF, for example.

  The photocoupler insulation circuit 2 includes a photocoupler PC1, a first resistor R1, and an insulation circuit capacitor Cp3. The photocoupler PC1 includes a diode 11, a photodiode 12, an amplifier 13, and an insulating circuit bipolar transistor 14. The anode of the diode 11 is connected to the photocoupler insulation circuit voltage source Pcc via the first resistor R1. A signal input terminal 15 is connected to the cathode of the diode 11, and a PWM signal is given to the signal input terminal 15 from the control unit of the inverter device 40. The diode 11 emits light based on the PWM signal, and the light of the diode 11 is received by the photodiode 12. The photodiode 12 outputs a current according to the amount of received light. An amplifier 13 is connected to the photodiode 12, and the amplifier 13 amplifies the current output from the photodiode 12 and supplies it to the base of the insulating circuit bipolar transistor 14. The amplifier 13 is connected to the positive-side conductive path 5 and the ground conductive path 7 and operates by being supplied with electric power. The insulating circuit capacitor Cp3 is connected in parallel with the amplifier 13 and connected to the positive electrode side conductive path 5 and the ground conductive path 7. The insulation circuit capacitor Cp3 can suppress the voltage fluctuation of the DC voltage applied to the amplifier 13, and the amplifier 13 can be operated stably. The insulating circuit bipolar transistor 14 is an NPN type, and an emitter is connected to the ground conductive path 7. The photocoupler insulation circuit 2 outputs a drive signal as a voltage signal. That is, the potential of the emitter of the insulating circuit bipolar transistor 14 varies based on the drive signal.

  The voltage / current conversion circuit 3 includes a first complementary emitter follower circuit 21, a complementary base ground circuit 22, a second resistor R2, a first diode D1, and first and second Zener diodes ZD1, ZD2. And first and second capacitors Cp4 and Cp5.

  The first complementary emitter-follower circuit 21 includes first NPN-type and first PNP-type bipolar transistors Q1, Q2. The first NPN-type and first PNP-type bipolar transistors Q1, Q2 are complementary. The emitter E1 of the first NPN type bipolar transistor Q1 and each emitter E2 of the first PNP type bipolar transistor Q2 are connected. The gate G1 of the first NPN bipolar transistor Q1 and the gate G2 of the first PNP bipolar transistor Q2 are connected. The gates G 1 and G 2 of the first NPN type and first PNP type bipolar transistors Q 1 and Q 2 are connected to the collector of the insulating circuit bipolar transistor 14. The collector C1 of the first NPN bipolar transistor Q1 is connected to the positive side voltage source Vcc, that is, the collector C1 is connected to the positive side conductive path 5. The collector C2 of the first PNP bipolar transistor Q2 is connected to the negative side voltage source Vss, that is, the collector C2 is connected to the negative side conductive path 6. The first complementary emitter follower circuit 21 is a so-called push-pull type emitter follower circuit.

Between the positive electrode side conductive path 5 and the ground conductive path 7, the second resistor R2, the first Zener diode ZD1, and the second Zener diode ZD2 are connected in series to the positive electrode side conductive path 5 and the ground conductive path 7. Is done. The second resistor R2 connects the positive-side conductive path 5 and the first Zener diode ZD1. The cathode of the first Zener diode ZD1 is connected to the second resistor R2, and the anode of the first Zener diode ZD1 is connected to the cathode of the second Zener diode ZD2. The anode of the second Zener diode ZD2 is connected to the ground conductive path 7. The first Zener diode ZD1 and the second Zener diode ZD2 have the same characteristics, and the breakdown voltage V _ZD is selected to be 1/3 of the potential difference between the ground potential and the potential V + of the positive voltage source Vcc. The second resistor R2 prevents an excessive voltage from being applied to the first and second Zener diodes ZD1, ZD2.

  A first capacitor Cp4 is connected in parallel to the first Zener diode ZD1, and a second capacitor Cp5 is connected in parallel to the second Zener diode ZD2. The first and second capacitors Cp4 and Cp5 are connected in series between the second resistor R2 and the ground conductive path 7. The first capacitor Cp4 can prevent voltage fluctuation between the anode and the cathode of the first Zener diode ZD1, and the second capacitor Cp5 can prevent sudden voltage fluctuation between the anode and the cathode of the second Zener diode ZD2. .

The cathode of the first diode D1 is connected to the connection portion between the cathode of the first Zener diode ZD1 and the second resistor R2. The anode of the first diode D1 is connected to the collector of the insulating circuit bipolar transistor 14 and the gates G1, G2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2. The first NPN when the insulating circuit bipolar transistor 14 is in the OFF state, that is, when no current flows between the collector and the emitter, by the first diode D1 and the first and second Zener diodes ZD1 and ZD2. The potential V1 of each of the gates G1 and G2 of the type and first PNP type bipolar transistors Q1 and Q2 is determined. The potential V1 from the ground potential, and the breakdown voltage _{V ZD} of the first and second Zener diodes ZD1, ZD2, a voltage of as high a potential obtained by adding the forward voltage drop _{V D1} of the first diode D1.

  The third resistor R3 connects the positive-side conductive path 5 to the collector of the insulating circuit bipolar transistor 14 and the gates G1, G2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2. The third resistor R3 is for supplying a base current for turning on the first NPN bipolar transistor Q1.

  The complementary base ground circuit 22 includes second NPN and second PNP bipolar transistors Q3 and Q4, an emitter load resistor R4, a positive collector load resistor R5, and a negative collector load resistor R6. Have The second NPN type and second PNP type bipolar transistors Q3 and Q4 are complementary. The emitters E3 and E4 of the second NPN type and second PNP type bipolar transistors Q3 and Q4 are connected. The emitter load resistor R4 includes emitters E1, E2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2, and emitters E3 of the second NPN-type and second PNP-type bipolar transistors Q3, Q4. , E4. That is, the emitters E3 and E4 of the second NPN-type and second PNP-type bipolar transistors Q3 and Q4 are connected to one end of the emitter load resistor R4, and the first NPN-type and first PNP-type bipolar transistor Q1. , Q2 are connected to the other end of the emitter load resistor R4. The positive collector load resistor R5 connects the collector C3 of the second NPN bipolar transistor Q3 and the positive voltage source Vcc, that is, connects the collector C3 and the positive conductive path 5. The negative collector load resistor R6 connects the collector C4 of the second PNP bipolar transistor Q4 and the negative voltage source Vss, that is, connects the collector C4 and the negative conductive path 7.

  The resistance value of the emitter load resistor R4 is the collector current of the first NPN type bipolar transistor Q1 and the first PNP type bipolar transistor Q2, and the second NPN type bipolar transistor Q3 and the second PNP type bipolar transistor Q4. Is selected so that a current of the same magnitude as the collector current flows through the emitter load resistor R4.

The bases B3 and B4 of the second NPN-type and second PNP-type bipolar transistors Q3 and Q4 are connected to the connection portion of the first Zener diode ZD1 and the second Zener diode ZD2 and the connection portion of the capacitor Cp4 and the capacitor Cp5. Connected. Accordingly, the potential V2 of each of the bases B3 and B4 of the second NPN type and second PNP type bipolar transistors Q3 and Q4 is higher than the ground potential by the breakdown voltage V _ZD of the second Zener diode ZD2. .

  The third Zener diode DZ3 is connected in parallel to the positive collector load resistor R5. The cathode of the third Zener diode DZ3 is connected to the positive-side conductive path 5, and the anode is connected to the collector C3 of the second NPN bipolar transistor Q3. The fourth Zener diode DZ4 is connected in parallel with the negative collector load resistor R6. The cathode of the fourth Zener diode DZ4 is connected to the collector C3 of the second PNP bipolar transistor Q4, and the anode is connected to the negative-side conductive path 6. The third and fourth Zener diodes DZ3, DZ4 have the same characteristics. In the present embodiment, the breakdown voltages of the third and fourth Zener diodes DZ3 and DZ4 are selected to be the gate-source voltages when the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are turned on. .

The FET drive circuit 4 includes a second complementary emitter follower circuit 31, a third complementary emitter follower circuit 32, a complementary field effect transistor circuit 33, a positive current limiting resistor R7, and a negative current. The limiting resistor R8, the signal output terminal 34 connected to the control terminal of the IGBT element 10, and the first and second output resistors R _G1 and R _G2 are configured.

  The second complementary emitter follower circuit 31 includes third NPN type and third PNP type bipolar transistors Q5 and Q6. The third NPN-type and third PNP-type bipolar transistors Q5 and Q6 are complementary. The emitter E5 of the third NPN bipolar transistor Q5 and the emitter E6 of the third PNP bipolar transistor Q6 are electrically connected. The gates G5 and G6 of the third NPN type and third PNP type bipolar transistors Q5 and Q6 are connected to the positive voltage source Vcc via the positive collector load resistor R5, that is, the gates G5 and G6 are connected to each other. Are connected to the collector C3 of the second NPN bipolar transistor Q3.

  The positive-side current limiting resistor R7 is provided between the emitter E5 of the third NPN bipolar transistor Q5 and the emitter E6 of the third PNP bipolar transistor Q6, and the emitter of the third NPN bipolar transistor Q5. E5 is connected to the emitter E6 of the third PNP bipolar transistor Q6. The collector C5 of the third NPN bipolar transistor Q5 is connected to the positive side voltage source Vcc, that is, the collector C5 is connected to the positive side conductive path 5. The collector C6 of the third PNP bipolar transistor Q6 is connected to the ground, that is, the collector C6 is connected to the ground conductive path 7. The second complementary emitter follower circuit 31 has a characteristic that the input impedance is large and the output impedance is small.

  The third complementary emitter follower circuit 32 includes fourth NPN-type and fourth PNP-type bipolar transistors Q7 and Q8. The fourth NPN type and fourth PNP type bipolar transistors Q7 and Q8 are complementary. The emitter E7 of the fourth NPN bipolar transistor Q7 and the emitter E8 of the fourth PNP bipolar transistor Q8 are electrically connected. The gates G7, G8 of the fourth NPN type and fourth PNP type bipolar transistors Q7, Q8 are connected to the negative voltage source via the negative collector load resistor R6, that is, the gates G7, G8 are Connected to the collector C4 of the second PNP type bipolar transistor Q4.

  The negative side current limiting resistor R8 is provided between the emitter E7 of the fourth NPN type bipolar transistor Q7 and the emitter Q8 of the fourth PNP type bipolar transistor Q8, and is connected to the fourth NPN type bipolar transistor Q7. The emitter E7 is connected to the emitter Q8 of the fourth PNP bipolar transistor Q8.

  The collector C7 of the fourth NPN bipolar transistor Q7 is connected to the collector C6 of the third PNP bipolar transistor Q6 and connected to the ground, that is, the collector C7 is connected to the ground conductive path 7. The collector C8 of the fourth PNP bipolar transistor Q8 is connected to the negative side voltage source Vss, that is, the collector C8 is connected to the negative side conductive path 6. The third complementary emitter follower circuit 32 has a characteristic that the input impedance is large and the output impedance is small.

  The complementary field effect transistor circuit 33 includes P-channel and N-channel field effect transistors M1 and M2. P-channel and N-channel field effect transistors M1 and M2 are complementary. In the present embodiment, the P-channel and N-channel field effect transistors M1, M2 are enhancement type. The drain D1 of the P-channel field effect transistor M1 and the drain D2 of the N-channel field effect transistor M2 are connected. The gate G1 of the P-channel field effect transistor M1 is connected to the connection portion between the emitter E5 of the third NPN bipolar transistor Q5 and the positive current limiting resistor R7, that is, the emitter E5 of the third NPN bipolar transistor Q5. Connected. The gate G2 of the N-channel field effect transistor M2 is connected to the connection portion between the emitter E8 of the fourth PNP bipolar transistor Q8 and the negative current limiting resistor R8, that is, the emitter E8 of the fourth PNP bipolar transistor Q8. Connected. The source S 1 of the P-channel field effect transistor M 1 is connected to the positive side voltage source Vcc, that is, the source S 1 is connected to the positive side conductive path 5. The source S2 of the N-channel field effect transistor M2 is connected to the negative side voltage source Vss, that is, the source S2 is connected to the negative side conductive path.

An IGBT element gate G0, which is a control terminal of the IGBT element 10, is electrically connected to the drains D1, D2 of the P-channel and N-channel field effect transistors M1, M2. Specifically the drain D1 of the field-effect transistor M1 of the P-channel, is connected via a first output resistor R _G1 to the signal output terminal 34, the drain D2 of the field-effect transistor M2 of N channel, the second output resistor Connected to the signal output terminal 34 via the device _RG2 . The first and second output resistors R _G1 and R _G2 are connected in series between the drains D1 and D2 of the P-channel and N-channel field effect transistors M1 and M2. The signal output terminal 34 is connected to the IGBT element gate G. The resistance values of the first and second output resistors R _G1 and R _G2 are small and are selected to be about 1Ω. The first and second output resistors R _G1 and R _G2 are for limiting the gate current of the IGBT element 10, and the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are in the ON state. This is to reduce the short-circuit current that flows in the transient state with the OFF state. The first and second output resistors R _G1 and R _G2 have predetermined resistance values, which are determined when the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are in the ON state. The drain current is selected to be smaller than the maximum allowable current of the P-channel field-effect transistor M1 and the N-channel field-effect transistor M2, and the ON / OFF response speed of the IGBT element 10 is not slowed down. .

  A rectifier diode D0 is connected to the IGBT element 10 in parallel with the collector C0 and the emitter E0 of the IGBT element 10. The cathode of rectifier diode D0 and collector C0 of IGBT element 10 are connected, and the anode of rectifier diode D0 and emitter E0 of IGBT element 10 are connected. The emitter E 0 of the IGBT element 10 is connected to the ground conductive path 7. A predetermined high voltage of about 1000 V, for example, is applied between the collector C0 and the emitter E0 of the IGBT element 10.

  The IGBT element 10 can be regarded as a capacitive load when viewed from the driving device 1, that is, it can be regarded as a capacitor formed between the gate G0 and the emitter E0 of the IGBT element 10. In order for the driving device 1 to turn on the IGBT element 10, that is, to allow a predetermined current to flow between the collector C 0 and the emitter E 0 of the IGBT element 10, a charge is generated between the gate G 0 and the emitter E 0 of the IGBT element 10. Store, that is, charge. The driving device 1 releases the electric charge between the gate G0 and the emitter E0 of the IGBT element 10 in order to turn off the IGBT element 10 and prevent the current from flowing between the collector C0 and the emitter E0 of the IGBT element 10. That is, it discharges.

In the driving apparatus 1, the P-channel and N-channel field effect transistors M1 and M2 are selectively turned on based on the PWM signal, that is, a current flows between the source S1 and the drain D1 of the P-channel field effect transistor M1. Alternatively, a current flows between the source S2 and the drain D2 of the N-channel field effect transistor M2. When the field effect transistor M1 of the P-channel is turned ON, a current flows from the field effect transistor M1 of the P-channel to the first output resistor R _G1. The magnitude of the current flowing through the first output resistor R _G1 is Ip. When the N-channel field effect transistor M2 is turned on, a current flows from the second output resistor _RG2 to the N-channel field effect transistor M2. The magnitude of the current flowing through the second output resistor R _G2 and In. A drive current is applied from the signal output terminal 34 to the gate G0 of the IGBT element 10, and Ig = Ip or −In, where Ig is the magnitude of this drive current.

  The first to fourth NPN type bipolar transistors Q1, Q3, Q5, Q7 have the same characteristics, and the first to fourth PNP type bipolar transistors Q2, Q4, Q6, Q8 have the same characteristics. In the present embodiment, the first to fourth NPN type bipolar transistors and the first to fourth PNP type bipolar transistors Q1 to Q8 are formed of silicon (Si).

  2 (1) to (9) are waveform diagrams showing potentials of respective parts of the driving device 1 when the driving device 1 is operated. 2 (1) to (9), the horizontal axis represents time, and the vertical axis represents potential.

  FIG. 2 (1) shows the potential at the connection site (point A in FIG. 1) between the cathode of the diode 11 of the photocoupler PC1 and the signal input terminal 15. FIG. Hereinafter, the connection part between the cathode of the diode 11 of the photocoupler PC1 and the signal input terminal 15 is referred to as point A.

  FIG. 2B is a connection portion (point B in FIG. 1) between the collector of the insulating circuit bipolar transistor 14 and the gates G1 and G2 of the first NPN-type and first PNP-type bipolar transistors Q1 and Q2. Represents potential. Hereinafter, a connection site between the collector of the insulating circuit bipolar transistor 14 and the gates G1, G2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2 will be referred to as point B.

  FIG. 2 (3) shows the potential at the connection site (point C in FIG. 1) between the emitters E1 and E2 of the first NPN type and first PNP type bipolar transistors Q1 and Q2 and the emitter load resistor R4. To express. Hereinafter, the connection site between the emitters E1, E2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2 and the emitter load resistor R4 will be referred to as point C.

  FIG. 2 (4) shows the potential at the connection site (point D in FIG. 1) between the emitter load resistor R4 and the emitters E3 and E4 of the second NPN-type and second PNP-type bipolar transistors Q3 and Q4. To express. Hereinafter, a connection site between the emitter load resistor R4 and each of the emitters E3 and E4 of the second NPN-type and second PNP-type bipolar transistors Q3 and Q4 is referred to as a D point.

  FIG. 2 (5) shows a connection portion (point E in FIG. 1) between the positive collector load resistor R5 and the gates G5 and G6 of the third NPN-type and third PNP-type bipolar transistors Q5 and Q6. Represents potential. Hereinafter, a connection site between the positive collector load resistor R5 and the gates G5 and G6 of the third NPN-type and third PNP-type bipolar transistors Q5 and Q6 is referred to as an E point.

  FIG. 2 (6) shows a connection portion (point F in FIG. 1) between the negative collector load resistor R6 and the gates G7, G8 of the fourth NPN-type and fourth PNP-type bipolar transistors Q7, Q8. Represents potential. Hereinafter, a connection site between the negative collector load resistor R6 and the gates G7 and G8 of the fourth NPN-type and fourth PNP-type bipolar transistors Q7 and Q8 is referred to as an F point.

  FIG. 2 (7) shows the potential at the connection site (point G in FIG. 1) between the gate G1 of the P-channel field effect transistor M1 and the emitter E5 of the third NPN bipolar transistor Q5. Hereinafter, a connection site between the gate G1 of the P-channel field effect transistor M1 and the emitter E5 of the third NPN bipolar transistor Q5 is referred to as a point G.

  FIG. 2 (8) shows the potential at the connection site (point H in FIG. 1) between the gate G2 of the N-channel field effect transistor M2 and the emitter E8 of the fourth PNP bipolar transistor Q8. Hereinafter, a connection site between the gate G2 of the N-channel field effect transistor M2 and the emitter E8 of the fourth PNP bipolar transistor Q8 is referred to as an H point.

FIG. 2 (9) shows the potential of the signal output terminal 34, that is, the potential at the connection portion (point I in FIG. 1) between the first and second output resistors R _G1 and R _G2 and the IGBT element gate G. Hereinafter, a connection site between the first and second output resistors R _G1 and R _G2 and the IGBT element gate G is referred to as an I point.

  First, the operation of the driving device 1 when the IGBT element 10 is transitioned from the OFF state to the ON state will be described. At time t0, the IGBT element 10 is in an OFF state, the first NPN bipolar transistor Q1, the second PNP bipolar transistor Q4, and the fourth NPN bipolar transistor Q7 are in an ON state, and an N-channel electric field is generated. The effect transistor M2 is in the ON state, and the IGBT element gate G of the IGBT element 10 is reverse-biased by the potential V− of the negative power supply Vss. At this time, the first PNP bipolar transistor Q2, the second NPN bipolar transistor Q3, the third NPN bipolar transistor Q5, and the third PNP bipolar transistor Q6 are in the OFF state, and the P channel The field effect transistor M1 is in an OFF state. At time t0, a PWM signal representing a gate OFF command for turning off the IGBT element 10 is given to the signal input terminal 15.

  When a PWM signal representing a gate OFF command for turning off the IGBT element 10 is applied to the signal input terminal 15, the potential at the point A becomes the potential Vp of the photocoupler insulation circuit voltage source Pcc. When a PWM signal indicating a gate ON command for turning on the IGBT element 10 is given, the potential at the point A becomes the ground potential, here 0V.

The potential at point A at time t0 is the potential Vp of the photocoupler insulation circuit voltage source Pcc. The potential at point B at time t0 is the breakdown voltage V _{ZD of} the first Zener diode ZD1 and the second Zener diode ZD2 and the forward drop voltage V of the first diode D1 from the potential of the ground conductive path 7, in other words, the ground potential. _The potential (V1) is higher by the voltage obtained by adding _D1 . The potential at point C at time t0 is a voltage (V3) that is lower than the potential (V +) of the positive voltage source Vcc by the voltage between the collector C1 and the emitter E1 of the first NPN bipolar transistor Q1.

  The potential at point D at time t0 is higher than the ground potential by a voltage obtained by adding the voltage between the base B4 and the emitter E4 of the second PNP bipolar transistor Q4 to the breakdown voltage of the second Zener diode ZD2 (V4). ). The potential at point E at time t0 is the potential (V +) of the positive voltage source Vcc. The potential at point F at time t0 is a potential (V5) obtained by adding the breakdown voltage of the fourth Zener diode ZD4 to the potential of the negative voltage source Vss. The potential at point G at time t0 is the potential (V +) of the positive voltage source Vcc. The potential at the point H at time t0 is the voltage between the base B7 and the emitter E7 of the fourth NPN bipolar transistor Q7 and the negative current limiting resistor R8 from the potential of the base B8 of the fourth PNP bipolar transistor Q8. The potential (V7) is lower by the voltage obtained by adding the voltage drop due to. The potential at the point I at time t0 is substantially the potential (V−) of the negative voltage source Vss.

  At time t0, in the emitter load resistor R4, the second NPN-type and second PNP-type bipolar transistors Q3, Q2 from the emitters E1, E2 of the first NPN-type and first PNP-type bipolar transistors Q1, Q2, respectively. A current flows in the direction indicated by the arrow X1 toward the emitters E3 and E4 of Q4.

  When the PWM signal representing the gate ON command for turning on the IGBT element 10 is applied to the signal input terminal 15 at the time t1 after the time t0 has elapsed, the potential at the point A drops to the ground potential.

  When the potential at the point A decreases at time t1, a current flows through the base of the insulating circuit bipolar transistor 14 of the photocoupler PC1, and the voltage between the collector and emitter of the insulating circuit bipolar transistor 14 decreases. The potential begins to drop gradually. When the potential at the point B decreases, the potential at the base B1 of the first NPN bipolar transistor Q1 decreases, so the potential at the point C representing the potential of the emitter E1 of the first NPN bipolar transistor Q1 also decreases from time t1. Begin to. When the potential at point B decreases, the potential at point C decreases, and the potential at point D connected to point C via emitter load resistor R4 also begins to decrease from time t1. Further, when the potential at the point B decreases, the current flowing through the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 decreases, so that the voltage drop due to the negative collector load resistor R6 decreases. The potential at point F also begins to drop from time t0. Further, when the potential at the point F decreases, the potential at the base B7 of the fourth NPN type bipolar transistor Q7 decreases accordingly, so that the potential at the point H connected to the emitter E7 of the fourth NPN type bipolar transistor Q7. Starts to decrease at time t1.

  The potentials at points C, D, F, and H drop in proportion to the potential at point B from time t1. At time t1, the potential at point E and the potential at point G do not change. At time t1, the potential at point I is substantially the potential (V−) of the negative voltage source Vss. Therefore, at time t1, the P-channel field effect transistor M1 is in the OFF state and the N-channel field effect transistor M2 is in the ON state.

  When the potential at point F gradually decreases after time t1, the potential at point H also gradually decreases. The potential at the point F is gradually lowered, the fourth NPN bipolar transistor Q7 is turned off, and the potential difference between the potential at the point H and the potential V− of the negative voltage source Vss is the N-channel field effect transistor M2. Below the ON voltage, the N-channel field effect transistor M2 is turned off at time t2. Thus, after time t1 has elapsed, at time t2, both the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are turned off. The on-voltage of the N-channel field effect transistor M2 is about 4V. At time t2, when the N-channel field effect transistor M2 is turned off, the potential at the point I rises to Vm of the GND potential. Also at time t2, the potential at point E and the potential at point G do not change.

  At time t3 when the time t2 has elapsed and the potential at the point D has dropped to V2, both the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 transition from the ON state to the OFF state. When the potential at the point D becomes V2 or less, voltages are applied between the base B2 and the emitter E2 of the first PNP bipolar transistor Q2 and between the base E3 and the emitter E2 of the second NPN bipolar transistor Q3. Thus, both the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 transition from the OFF state to the ON state. When the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 are turned on at time t3, the direction of the current flowing through the emitter load resistor R4 is reversed, that is, the second NPN type and the second NPN type In the direction indicated by the arrow X2 from the emitters E3 and E4 of the two PNP-type bipolar transistors Q3 and Q4 toward the emitters E1 and E2 of the first NPN-type and first PNP-type bipolar transistors Q1 and Q2, Current flows. After both the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 transition from the ON state to the OFF state, the first PNP bipolar transistor Q2, the second NPN bipolar transistor Q3, In actuality, there is a little time until both of the transistors transition from the OFF state to the ON state, but the first NPN type bipolar transistor Q1 and the second PNP type bipolar transistor Q4 are OFF from the ON state. The transition to the state and the transition from the OFF state to the ON state of the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 can be regarded as occurring almost simultaneously.

  At time t3, the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 are turned on, so that a current starts to flow through the positive collector load resistor R5. When the time t3 elapses and current starts to flow through the positive collector load resistor R5, the potential at the point E gradually decreases due to the voltage drop caused by the positive collector load resistor R5. Further, when the potential at the point E gradually decreases, the potential at the base B6 of the third PNP bipolar transistor Q6 decreases, so that the third PNP bipolar transistor Q6 starts to shift from the OFF state to the ON state. The potential of the emitter E6 of the PNP type bipolar transistor Q6 begins to drop. When the potentials of the bases B5 and B6 of the third NPN-type and third PNP-type bipolar transistors Q5 and Q6 are lowered and the third PNP-type bipolar transistor Q6 is turned on, the potential at the point G becomes the third potential. Is higher than the potential of the emitter E6 of the PNP bipolar transistor Q6 by the voltage across the positive-side current limiting resistor R7. At time t3, the potential at point H is a potential (V8) that is higher than the potential at the base B8 of the fourth PNP bipolar transistor Q8 by the voltage between the base B8 and the emitter E8 of the fourth PNP bipolar transistor Q8. Become.

  After the time t3, the potential at the point G decreases, and the potential difference between the potential at the point G and the potential V + of the positive voltage source Vcc, that is, the voltage between the gate G1 and the source S1 of the P-channel field effect transistor M1 is When the ON voltage of the P-channel field effect transistor M1 is exceeded, the P-channel field effect transistor M1 transitions from the OFF state to the ON state at time t4. The on-voltage of the P-channel field effect transistor M1 is about 4V.

  During a period T1 from time t2 to time t4, both the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are in the OFF state. Both the effect transistors M2 are turned on, and the positive voltage source Vcc and the negative voltage source Vss are not short-circuited. Therefore, the destruction of the P-channel field effect transistor M1 and the N-channel field effect transistor M2 due to the short circuit can be prevented. The period T1 is selected to be about 200 nanoseconds, for example.

  The potentials at points B, C, D, E, and G continue to decrease until time t5. At time t5, the potential at the point B becomes the potential of the ground conductive path 7, and the potential at the point C is changed from the potential of the base B2 of the first PNP bipolar transistor Q2 to the base of the first PNP bipolar transistor Q2. The potential at the point D is higher than the potential between the base B3 of the second NPN type bipolar transistor Q3 and the potential of the base B3 of the second NPN type bipolar transistor Q3. The potential becomes lower (V10) by the voltage between the emitters E3. At time t5, the point E becomes a potential (V11) that is lower than the potential V + of the positive side voltage source Vcc by the voltage drop due to the positive side collector load resistor R5, that is, the breakdown voltage of the third Zener diode ZD3. At time t5, the potential at point G changes from the potential at the base B6 of the third PNP bipolar transistor Q6 to the voltage between the base B6 and the emitter E6 of the third PNP bipolar transistor Q6 and the positive current limiting resistor. This is a potential (V12) that is higher by the voltage obtained by adding the voltage drop caused by the resistor R7. The potential at the point I becomes substantially the potential V + of the positive voltage source Vcc after time t4, and this potential is maintained even at time t5.

  By the operation as described above, the driving device 1 can cause the IGBT element 10 to transition from the OFF state to the ON state.

  Next, the operation of the driving device 1 when the IGBT element 10 is transitioned from the ON state to the OFF state will be described. At time t5, when the IGBT element 10 is in the ON state, the first PNP bipolar transistor Q2, the second NPN bipolar transistor Q3, and the fourth NPN bipolar transistor Q7 are in the ON state, and the electric field of the P channel The effect transistor M1 is in the ON state, and the IGBT element gate G of the IGBT element 10 is biased by the potential V + of the positive power supply Vcc.

  Between time t5 and time t6, a PWM signal indicating a gate ON command for turning on the IGBT element 10 is given to the signal input terminal 15, the point B becomes the ground potential, and the potential at the point C is V9. The potential at point D is V10, the potential at point E is V11, the potential at point F is V-, the potential at point G is V12, the potential at point H is V8, and the potential at point I is V +. It has become.

  At time t6, when a PWM signal representing a gate OFF command for turning off the IGBT element 10 is applied to the signal input terminal 15, the potential at the point A rises from the ground potential, and the photocoupler insulation circuit voltage source Pcc The potential is Vp.

  When the potential at point A decreases at time t6, the current decreases in the base of the insulating circuit bipolar transistor 14 of the photocoupler PC1, the voltage between the collector and emitter of the insulating circuit bipolar transistor 14 increases, and from time t1 to B The point potential begins to rise gradually. When the potential at the point B rises, the potential at the base B1 of the first NPN bipolar transistor Q1 rises, so the potential at the point C representing the potential of the emitter E2 of the first PNP bipolar transistor Q2 also rises from time t6. Begin to. As the potential at the point C rises, the potential at the point D connected to the point C via the emitter load resistor R4 also starts to rise from time t6. Further, when the potential at the point B rises, the current flowing through the first PNP type bipolar transistor Q2 and the second NPN type bipolar transistor Q3 becomes small, so that the voltage drop due to the positive collector load resistor R5 becomes small, The potential at point E also starts to rise from time t6. When the potential at the point E further increases, the potential at the base B6 of the third PNP bipolar transistor Q6 increases, so that the potential at the point G connected to the emitter E6 of the third NPN bipolar transistor Q6 also increases from time t6. Begins to rise. At time t6, the P-channel field effect transistor M1 is in the ON state and the N-channel field effect transistor M2 is in the OFF state.

  The potentials at points C, D, E, and G rise in proportion to the potential at point B from time t1. At time t6, the potential at point F and the potential at point H do not change. At time t6, the potential at point I is substantially the potential V + of the positive voltage source Vcc.

  When the potential at point E gradually rises after time t6 has elapsed, the potential at point G also gradually rises. The potential at the point E gradually rises and the third NPN bipolar transistor Q6 is turned off, and the potential difference between the potential at the point G and the potential V + of the positive voltage source Vcc is the N channel field effect transistor M1. When the voltage is lower than the ON voltage, the P-channel field effect transistor M1 is turned OFF at time t6. As a result, at time t7, both the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are turned off. At time t7, when the P-channel field effect transistor M1 is turned off, the potential at the point I is lowered to the GND potential Vm.

  At time t8 when the time point t6 has elapsed and the potential at the point D has increased to V2, both the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 transition from the ON state to the OFF state. When the potential at the point D becomes V2 or more, voltages are applied between the base B1 and the emitter E1 of the first NPN bipolar transistor Q1 and between the base E4 and the emitter E4 of the second PNP bipolar transistor Q4, respectively. As a result, both the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 transition from the OFF state to the ON state. When the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 are turned on at time t8, the direction of the current flowing through the emitter load resistor R4 is reversed, that is, the first NPN type and the first NPN type Current from the emitters E1, E2 of one PNP-type bipolar transistor Q1, Q2 toward the emitters E3, E4 of the second NPN-type and second PNP-type bipolar transistors Q3, Q4 in the direction indicated by the arrow X1 Flows. After both the first PNP bipolar transistor Q2 and the second NPN bipolar transistor Q3 transition from the ON state to the OFF state, the first NPN bipolar transistor Q1 and the second NPN bipolar transistor Q4 In actuality, there is a slight time until both of the first and second NPN bipolar transistors Q2 and Q3 are switched from the OFF state to the ON state. The transition to the OFF state and the transition from the OFF state to the ON state of the first NPN bipolar transistor Q1 and the second PNP bipolar transistor Q4 can be regarded as occurring simultaneously.

  At time t8, the first NPN-type bipolar transistor Q1 and the second PNP-type bipolar transistor Q4 are turned on, so that current starts to flow to the negative collector load resistor R6 from time t8. When the time t3 passes and the current starts to flow through the negative collector load resistor R6, the potential at the point F gradually increases due to the voltage drop caused by the negative collector load resistor R6. Further, when the potential at the point F gradually increases, the potential at the base B8 of the fourth NPN type bipolar transistor Q8 increases, so that the potential at the point H representing the potential of the emitter E8 of the fourth NPN type bipolar transistor Q8 increases. To do. When the potential at the point F rises and the fourth NPN type bipolar transistor Q7 is turned on, the potential at the point H changes from the potential of the emitter E7 of the fourth NPN type bipolar transistor Q7 to the negative potential current limiting resistor. The potential becomes lower by the voltage across R8. At time t8, the potential at point E becomes the potential V + of the positive voltage source Vcc, and the potential at point G becomes the potential V + of the positive power source Vcc.

  After the time t8, the potential at the H point rises, and the potential difference between the potential at the H point and the potential V− of the negative voltage source Vss, that is, the voltage between the gate G2 and the source S2 of the N-channel field effect transistor M2 is When the ON voltage of the N-channel field effect transistor M2 is exceeded, the N-channel field effect transistor M2 transitions from the OFF state to the ON state at time t9.

  In a period T2 from time t7 to time t8, both the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are in the OFF state, and therefore, the P-channel field effect transistor M1 and the N-channel electric field are in a switching transient. Both the effect transistors M2 are turned on, and the positive voltage source Vcc and the negative voltage source Vss are not short-circuited. Therefore, the destruction of the P-channel field effect transistor M1 and the N-channel field effect transistor M2 due to the short circuit can be prevented. The period T2 is selected to be about 200 nanoseconds, for example.

  The potentials at points B, C, D, F, and H continue to rise until time t10. At time t10, the potential at point B is V1, the potential at point C is V3, and the potential at point D is V4. At time t10, the point F becomes a potential (V5) higher than the potential V− of the negative side voltage source Vss by the voltage drop due to the negative side collector load resistor R6, that is, the breakdown voltage of the fourth Zener diode ZD4. At time t10, the potential at point H is changed from the potential at the base B7 of the fourth NPN bipolar transistor Q7 to the voltage between the base B7 and the emitter E7 of the fourth NPN bipolar transistor Q7 and the negative-side current limiting resistor. It is a potential (V7) that is lower by the voltage obtained by adding the voltage drop due to the device R8. The potential at the point I becomes substantially the potential V− of the negative voltage source Vss after time t9, and this potential is maintained even at time t10.

  By the operation as described above, the drive device 1 can transition the IGBT element 10 from the ON state to the OFF state.

FIG. 3 is a waveform diagram obtained by measuring the potentials at points A, G, I, and H of the driving device 1 with an oscilloscope when the IGBT element 10 is changed from the OFF state to the ON state, that is, when turned on. FIG. 4 is a waveform diagram in which the potentials at points E, G, F, and H of the driving device 1 when the IGBT element 10 is turned on are measured with an oscilloscope. 3 and 4, the horizontal axis represents time, and the vertical axis represents potential. Here, the breakdown voltage V _ZD of the first to fourth Zener diodes ZD1 to ZD4 of the driving device 1 is 5V, the resistance value of the emitter load resistor R4 is 560Ω, and the resistance value of the positive collector load resistor R5 is The resistance value of the negative side current limiting resistor R8 is 10Ω, the resistance values of the first and second output resistors R _G1 and R _G2 are 1.1Ω, respectively, and the negative side collector load resistor R6 In addition, measurement is performed on the short-circuited positive-side current limiting resistor R7.

  Further, the time for one square on the horizontal axis in FIG. 3 is 250 nanoseconds (nsec), and the time for one square on the horizontal axis in FIG. 4 is 100 nanoseconds (nsec). In FIG. 3, the waveform at point A is measured on a different channel from the waveforms at other points G, I, and H, so the reference value of the potential is different. In FIG. 3, at points A, G and H, the waveform is represented by 5 V / div, but at point I, the waveform is represented by 10 V / div. In FIG. 4, the waveforms at points E, G, F, and H are represented by 5 V / div.

  In the waveform diagrams of FIGS. 3 and 4, the potential at the point A changes from Vp to the ground potential at time t1. At time t2 when time t1 has elapsed, the waveform of the potential at point I rises, that is, the potential at point I begins to rise. The time from time t1 to time t2 is about 500 nanoseconds (nsec), and after the drive signal is given to the signal input terminal 15, the drive signal is given from the signal output terminal 34 to the IGBT element gate G0 of the IGBT element 10. It was possible to speed up the time.

  FIG. 5 is a waveform diagram in which the potentials at points A, G, I, and H of the driving device 1 when the IGBT element 10 is transitioned from the ON state to the OFF state, that is, turned off, are measured with an oscilloscope. FIG. 6 is a waveform diagram in which the potentials at points E, G, F, and H of the driving apparatus 1 when the IGBT element 10 is turned on are measured by an oscilloscope. 5 and 6, the horizontal axis represents time, and the vertical axis represents potential. In FIGS. 5 and 6, the measurement conditions of the drive device 1 are the same as those for obtaining the waveform diagrams shown in FIGS.

  Further, the time for one square on the horizontal axis in FIG. 5 is 250 nanoseconds (nsec), and the time for one square on the horizontal axis in FIG. 6 is 100 nanoseconds (nsec). In FIG. 5, the waveform at point A is measured on a different channel from the waveforms at other points G, I, and H, so the reference value of the potential is different. In FIG. 5, at points A, G and H, the waveform is represented by 5 V / div, but at point I, the waveform is represented by 10 V / div. In FIG. 6, waveforms at points E, G, F, and H are represented by 5 V / div.

  In the waveform diagrams of FIGS. 5 and 6, the potential at the point A changes from the ground potential to Vp at time t6.

  At time t7 when time t1 has elapsed, the waveform of the potential at point I rises, that is, the potential at point I begins to rise. The time from time t1 to time t2 is about 500 nanoseconds (nsec), and after the drive signal is given to the signal input terminal 15, the drive signal is given from the signal output terminal 34 to the IGBT element gate G0 of the IGBT element 10. It was possible to speed up the time.

  As described above, according to the driving apparatus 1 of the present invention, as described above, the drains D1 and D2 of the P-channel and N-channel field effect transistors M1 and M2 are connected to form the output stage of the driving apparatus 1. Thus, the N-channel and P-channel field effect transistors M1 and M2 operate on a rail-to-rail basis, that is, the signal output terminal 34 is substantially at the potential V + of the positive voltage source Vcc to the potential of the negative voltage source Vss. A potential up to V- can be applied, and the utilization efficiency of the power supply voltage can be improved.

  The P-channel field effect transistor M1 changes from the OFF state to the ON state in the process in which the potentials of the gates G5 and G6 of the third PNP-type and third NPN-type bipolar transistors Q5 and Q6 decrease, and the third PNP In the process in which the potentials of the gates G5 and G6 of the n-type and third NPN-type bipolar transistors Q5 and Q6 rise, the ON state changes to the OFF state. That is, when the first PNP-type and second NPN-type bipolar transistors are turned on, current flows out to the positive collector load resistor R5, and the voltage drop due to the positive collector load resistor R5 increases. The P-channel field effect transistor M1 transitions from the OFF state to the ON state, and the P-channel field effect transistor M1 transitions from the ON state to the OFF state in the process of decreasing the voltage drop due to the positive collector load resistor R5. To do. Therefore, the P-channel field effect transistor M1 is turned on only when a current flows through the positive collector load resistor R5 and the voltage drop across the positive collector load resistor R5 is equal to or higher than a predetermined voltage.

  The N-channel field effect transistor M2 changes from the OFF state to the ON state in the process in which the potentials of the gates G7 and G8 of the fourth PNP type and fourth NPN type bipolar transistors Q7 and Q8 rise, and the fourth PNP In the process in which the potentials of the gates G7 and G8 of the n-type and fourth NPN-type bipolar transistors Q7 and Q8 are lowered, the state changes from the ON state to the OFF state. That is, when the first NPN-type and second PNP-type bipolar transistors Q1 and Q4 are turned on, a current flows to the negative collector load resistor R6, and the voltage drop due to the negative collector load resistor R6 increases. In the process, the N-channel field effect transistor M2 transitions from the OFF state to the ON state, and the N-channel field effect transistor M2 is switched from the ON state to the OFF state in the process of decreasing the voltage drop due to the negative collector load resistor R6. Transition to the state. Therefore, the N-channel field effect transistor M2 is turned on only when a current flows through the negative collector load resistor R6 and the voltage drop caused by the negative collector load resistor is equal to or higher than a predetermined voltage.

  The P-channel field effect transistor M1 is turned on only when a current flows through the positive collector load resistor R5, and the voltage drop due to the positive collector load resistor R5 is equal to or higher than a predetermined voltage. The effect transistor M2 is in an ON state only when a current flows through the negative collector load resistor R6 and the voltage drop across the negative collector load resistor R6 is equal to or higher than a predetermined voltage, and the first complementary emitter follower circuit. 21 and the complementary base ground circuit 22 are connected as described above, so that a current can selectively flow through either the positive collector load resistor R5 or the positive collector load resistor R6. , P-channel and N-channel field effect transistors are selectively turned on and the other is turned on It is possible to the state. Therefore, when the switching operation of the P-channel and N-channel field effect transistors M1 and M2 is in a transient state, both the P-channel and N-channel field effect transistors M1 and M2 are prevented from being turned on. The short-circuit between the side voltage source Vcc and the negative side voltage source Vss can be prevented, and the destruction of the P-channel and N-channel field effect transistors M1 and M2 can be prevented.

  In addition, since the voltage / current conversion circuit 22 converts the voltage signal into a current signal, the voltage / current conversion circuit 22 is hardly affected by fluctuations in the potentials V + and V− of the positive and negative voltage sources Vcc and Vss. The application of an excessive voltage to the first and second NPN bipolar transistors Q1 and Q3 and the first and second NPN bipolar transistors Q2 and Q4 constituting the circuit 22 can be suppressed. Can be improved.

  Further, as described above, the first to fourth NPN type bipolar transistors Q1, Q3, Q5, Q7 and the first to fourth PNP type bipolar transistors Q2, Q4, Q5, Q8 are connected to each other, so that the first to fourth NPN type bipolar transistors are connected. The first to fourth PNP bipolar transistors Q1 to Q8 all operate in the non-saturated region, that is, the voltage between the collectors C1 to C8 and the emitters E1 to E8 does not become 0V. Since the first to fourth NPN bipolar transistors and the first to fourth PNP bipolar transistors Q1 to Q8 all operate in a non-saturated region, the delay time due to the minority carrier accumulation effect in each bipolar transistor Q1 to Q8 is shortened. That is, the delay time when each of the bipolar transistors Q1 to Q8 is turned off can be shortened to improve the switching speed of each of the bipolar transistors Q1 to Q8, whereby the drive signal is transmitted to the IGBT element gate of the IGBT element 10. The switching operation of the IGBT element 10 can be speeded up by applying G0 at high speed.

  In the driving device 1, the signal line can be electrically isolated by the photocoupler PC 1 between the signal input terminal 15 to which the driving signal is input and the signal output terminal 34 connected to the IGBT element 10. Even when the signal voltage differs between the input side and the output side, the low voltage side circuit is not easily affected by the high voltage side circuit, and the low voltage side circuit can be protected. 1 reliability can be improved. Therefore, for example, when a signal output from a microcomputer or the like is input from the signal input terminal 15, a large current used in the inverter device 40 flows, and the IGBT element 10 to which a high voltage is applied can be driven stably. .

  In the driving device 10, the positive-side current adjustment resistor R7 is connected to adjust the response speed when the P-channel field-effect transistor M1 is turned from the OFF state to the ON state. Since the response speed when the N-channel field effect transistor M2 is switched from the OFF state to the ON state can be adjusted by connecting the device R8, the positive-side current adjusting resistor can be adjusted according to the characteristics of the IGBT element 10 to be driven. The degree of freedom in design can be improved by adjusting the resistance values of the resistor R7 and the negative current adjusting resistor R8.

  The drive device 10 does not need to use an integrated circuit such as an amplifier and a buffer in order to configure the voltage / current drive circuit 3 and the FET drive circuit 4, and the voltage / current drive circuit 3 and the FET drive circuit 4 are discrete elements. The bipolar transistor, the field effect transistor, the resistor, the capacitor, and the Zener diode can be configured. Therefore, it is possible to realize a highly reliable driving device that has a simple configuration and few failures.

  FIG. 7 is a diagram schematically illustrating the configuration of the inverter device 40 configured to include the drive device 1. Inverter device 40 converts a DC voltage into a three-phase AC voltage. FIG. 3 also shows a load 41 to which a three-phase AC voltage output from the inverter device 40 is applied. The load 41 is realized by a three-phase induction motor.

  The inverter device 40 includes first to sixth IGBT elements 10A to 10F, first to sixth drive devices 1A to 1F for driving the IGBT elements 10A to 10F, respectively, and a control unit 42. The The first to sixth IGBT elements 10A to 10F are the same as the IGBT element 10, and the first to sixth driving devices 1A to 1F are the driving device 1 described above. The emitter of the first IGBT element 10A and the collector of the second IGBT element 10B are connected, the emitter of the third IGBT element 10C and the collector of the fourth IGBT element 10D are connected, and the fifth IGBT. The emitter of the element 10E and the collector of the sixth IGBT element 10F are connected. The first, third, and fifth IGBT elements 10A, 10C, and 10E are connected to the positive electrode of the DC voltage source 43, and the second, fourth, and fifth IGBT elements 10B, 10D, and 10F are connected to the DC voltage source 43. Connected to the negative electrode. Rectifier diodes are connected in parallel to the first to sixth IGBT elements 10A to 10F, respectively. The connection portion of the first and second IGBT elements 10A, 10B is connected to the first output terminal 44, the connection portion of the third and fourth IGBT elements 10C, 10D is connected to the second output terminal 45, and the fifth And the connection part of 6th IGBT element 10D, 10F is connected to the 3rd output terminal 45. FIG. The input terminals of the load 10 are connected to the first to third output terminals 43, 44, and 45, respectively.

  The signal output terminals 34 of the first to sixth driving devices 1A to 1F are individually connected to the gates G0 of the first to sixth IGBT elements 10A to 10F. The ground conductive paths 7 of the first to sixth driving devices 1A to 1F are connected to the emitters E0 of the first to sixth IGBT elements 10A to 10F to be driven, respectively. A PWM signal is given from the control unit 42 to each signal input unit 15 of the first to sixth driving devices 1A to 1F. Accordingly, the first to sixth driving devices 1A to 1F drive the first to sixth IGBT elements 10A to 10F based on the PWM signal, and the first to third output terminals 44, 45, 46 to 3 Phase alternating voltage is output.

  In the inverter device 40, since the driving device 1 described above is used as the first to sixth driving devices 1A to 1F, the first to sixth IGBT elements 10A to 10F can be switched at high speed based on the PWM signal. It is possible to generate a three-phase AC voltage with little distortion.

  In the present embodiment, drive device 1 drives IGBT element 10 constituting inverter device 40, but drive device 1 may drive a self-extinguishing semiconductor element used in a chopper device. By driving the self-extinguishing semiconductor element included in the chopper device with the driving device 1, the switching operation of the self-extinguishing semiconductor element can be speeded up, so that the output voltage from the chopper device can be easily adjusted. .

  In the embodiment of the present invention, the photocoupler insulating circuit 2 is provided. However, when it is not necessary to insulate the input side and the output side, in another embodiment of the present invention, the driving device 1 of the above embodiment is used. It is good also as a structure except the photocoupler insulation circuit 2. FIG. In the driving device having such a configuration, the driving signal is directly applied to the bases B1 and B2 of the first NPN type bipolar transistor Q1 and the first PNP type bipolar transistor Q2 of the first complementary emitter follower circuit 21. . Also in the drive device having such a configuration, the same effect as that of the drive device 1 described above can be achieved.

  In still another embodiment of the present invention, the positive side current limiting resistor R7 and the negative side current limiting resistor R8 may be omitted from the driving device 1 of the above embodiment. Then, the number of parts constituting the drive device is reduced, and the connection of the device can be simplified. Even with such a configuration, it is possible to achieve the same effect as that of the drive device 1 described above.

It is a circuit diagram which shows the drive device 1 of the self-extinguishing type semiconductor element of one Embodiment of this invention. FIG. 4 is a waveform diagram showing the potential of each part of the drive device 1 when the drive device 1 is operated. FIG. 6 is a waveform diagram in which the potentials at points A, G, I, and H of the driving apparatus 1 when the IGBT element 10 is transitioned from an OFF state to an ON state, that is, turned on, are measured with an oscilloscope. FIG. 6 is a waveform diagram in which the potentials at points E, G, F, and H of the driving device 1 when the IGBT element 10 is turned on are measured by an oscilloscope. FIG. 6 is a waveform diagram in which the potentials at points A, G, I, and H of the driving apparatus 1 when the IGBT element 10 is transitioned from an ON state to an OFF state, that is, turned off, are measured with an oscilloscope. FIG. 6 is a waveform diagram in which the potentials at points E, G, F, and H of the driving device 1 when the IGBT element 10 is turned on are measured by an oscilloscope. It is a figure which shows typically the structure of the inverter apparatus 40 comprised including the drive device 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Driver 2 Photocoupler insulation circuit 3 Voltage / current conversion circuit 4 EFT drive circuit 21 1st complementary emitter follower circuit 22 Complementary base ground circuit 31 2nd complementary emitter follower circuit 32 3rd complementary emitter follower Circuit 33 complementary field effect transistor circuit Q1 first PNP bipolar transistor Q2 first NPN bipolar transistor Q3 second PNP bipolar transistor Q4 second NPN bipolar transistor Q5 third PNP bipolar transistor Q6 first 3 NPN bipolar transistor Q7 4th PNP bipolar transistor Q8 4th NPN bipolar transistor M1 P-channel field effect transistor M2 N-channel field effect transistor Vcc Positive side power Source Vss negative side voltage supply R4 emitter load resistor R5 positive side collector load resistor R6 anode side collector load resistor R7 positive side current limiting resistor R8 negative current limiting resistor

Claims (3)

A signal input unit for inputting a drive signal;
The first NPN type and the first PNP type bipolar transistor, each emitter of the first NPN type and the first PNP type bipolar transistor is connected, and the first NPN type and the first PNP type bipolar transistor Are connected to the signal input unit, the collector of the first NPN bipolar transistor is connected to the positive voltage source, and the collector of the first PNP bipolar transistor is connected to the negative voltage source. A complementary emitter follower circuit of
Connecting the emitters of the second NPN-type and second PNP-type bipolar transistors, the first NPN-type and first PNP-type bipolar transistors and the emitters of the second NPN-type and second PNP-type bipolar transistors Connecting the collector of the second NPN bipolar transistor and the positive voltage source, and connecting the collector and negative voltage source of the second PNP bipolar transistor. A complementary base ground circuit having a negative collector load resistor and connected to the emitters of the second NPN-type and second PNP-type bipolar transistors;
A third NPN type and a third PNP type bipolar transistor, each emitter being connected to the third NPN type and the third PNP type bipolar transistor; Is connected to the positive voltage source via the positive collector load resistor, the collector of the third NPN bipolar transistor is connected to the positive voltage source, and the collector of the third PNP bipolar transistor is connected to the ground. A second complementary emitter follower circuit connected;
A fourth NPN-type and a fourth PNP-type bipolar transistor, each emitter being connected to the fourth NPN-type and the fourth PNP-type bipolar transistor; Are connected to the negative voltage source via the negative collector load resistor, the collector of the fourth NPN bipolar transistor is connected to the ground, and the collector of the fourth PNP bipolar transistor is connected to the negative voltage source. A third complementary emitter follower circuit connected to
P-channel and N-channel field effect transistors are provided, the drains of the P-channel and N-channel field effect transistors are connected, and the gate of the P-channel field effect transistor is connected to the emitter of the third NPN bipolar transistor. The gate of the N-channel field effect transistor is connected to the emitter of the fourth PNP-type bipolar transistor, the source of the P-channel field effect transistor is connected to the positive voltage source, and the source of the N-channel field effect transistor is the negative electrode A self-extinguishing field effect transistor circuit connected to the side voltage source and connected to the drain of each of the P-channel and N-channel field effect transistors and the control terminal of the self-extinguishing semiconductor element. Type semiconductor device drive device.   2. The self-extinguishing system according to claim 1, wherein the signal input unit includes a photocoupler, and supplies a drive signal to each base of the first PNP type and the first NPN type bipolar transistor through the photocoupler. Type semiconductor device drive device. A current limiting resistor connected between at least one of the emitters of the third NPN-type and third PNP-type bipolar transistors and between the emitters of the fourth NPN-type and fourth PNP-type bipolar transistors. 3. The drive device for a self-extinguishing semiconductor element according to claim 1 or 2, further comprising a device.

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