JP4765127B1 - Tray unit and semiconductor device inspection device - Google Patents

Abstract

A tray unit capable of improving positioning accuracy is provided.
A tray unit in which a plurality of semiconductor devices to be inspected can be mounted, and includes a bottom plate member that forms a bottom portion, and is placed on the bottom plate member and is divided into a plurality of pieces in a horizontal direction. Each having a semiconductor device mounting tray for mounting and holding a plurality of the semiconductor devices, and collectively testing the electrical characteristics of each semiconductor device with the terminals provided in the semiconductor device facing the upper surface side. It is detachably mounted on a semiconductor device inspection apparatus.
[Selection] Figure 8

Description

  The present invention relates to a tray unit and a semiconductor device inspection apparatus for performing various characteristic tests of semiconductor devices.

  2. Description of the Related Art Conventionally, there is a semiconductor device inspection apparatus that applies a desired high or low temperature stress to a semiconductor device to be tested.

  As an inspection device for semiconductor devices, for example, a thermostatic chamber that applies high-temperature or low-temperature stress to a semiconductor device and a semiconductor device that is subjected to thermal stress in this thermostatic chamber are in electrical contact with a test head. There are some test chambers for testing electrical characteristics and a heat removal tank for removing a given thermal stress from a semiconductor device tested in the test chamber.

  In such a semiconductor device inspection apparatus, in order to simultaneously test a plurality of semiconductor devices, a socket board having a plurality of sockets on which the semiconductor devices are mounted is used.

  Various techniques relating to a semiconductor device inspection apparatus using such a socket board have been proposed.

  For example, Japanese Patent Laid-Open No. 2000-304808 discloses that the number of semiconductor devices that can be inspected at a time is increased, the cost of the inspection device is reduced, and the inspection process can be performed stably. An inspection apparatus for a semiconductor device is disclosed.

  In this semiconductor device inspection apparatus, a heater, a multilayer wiring board, and an anisotropic conductive rubber sheet are sequentially provided on a printed board, and the anisotropic conductive rubber sheet is provided on the multilayer wiring board of the semiconductor package. A position restricting member for restricting the position is disposed, a press plate having a press member is provided above the position restricting member, and an annular seal member is provided at a peripheral portion of the press plate, the press plate, the seal member, When the sealed space is formed by the multilayer wiring board and the sealed space is decompressed, the sealing member is deformed, and the bumps of the semiconductor package and the electrodes of the multilayer wiring board are electrically and reliably connected via the anisotropic conductive rubber sheet. It is supposed to be.

  Japanese Patent Laid-Open No. 2007-309787 discloses a test tray structure in which all semiconductor devices mounted on an IC tray can be collectively transferred to a dedicated tray that can be easily tested.

JP 2000-304808 A JP 2007-309787 A

  By the way, semiconductor devices in recent years tend to require a longer time to test one semiconductor device as the density and circuit complexity of the semiconductor device increase. Is desired.

  In addition, since there is an increasing tendency to produce a variety of semiconductor devices in small quantities, there is an increasing need to frequently change test conditions such as temperature conditions according to the type of semiconductor device.

  However, the conventional technique disclosed in Japanese Patent Laid-Open No. 2000-304808 has a problem that the wiring board (contact board) is fixed and cannot quickly cope with semiconductor devices having different terminal arrangements.

  In addition, since the terminal arrangement differs depending on the configuration of the semiconductor device, conventionally, it has been necessary to prepare a socket or a socket board adapted to the terminal arrangement for each configuration of each semiconductor device, resulting in an increase in cost.

  Further, as the number of inspection pins increases, the socket itself becomes expensive, and there is a problem that the cost of the inspection device and the inspection cost increase. In particular, devices that require a long time for testing due to miniaturization, high integration, and the like are increasing, and a decrease in inspection efficiency and an increase in inspection cost are serious problems.

  Also, in recent semiconductor device burn-in tests and final tests, an automatic machine called a handler is used to transfer from a tray to a socket on the burn-in board, or to a carrier socket on the tester carrier board. Inspection is performed at the test stage.

  For this reason, the limit of the processing quantity that can be inspected at a time and the increase in test cost due to expensive sockets and boards that are used in large quantities are becoming major issues.

  Also, some parts of the logic are tested on the assembly process line, but many devices including the memory are inspected with a dedicated process for inspection, and a system integrated with the dedicated test handler is used for efficiency. There is also a problem that a typical production line has not been realized.

  On the other hand, in a tray (IC tray) on which a semiconductor device as a comparison object is placed, a resin part constituting a mounting part of the semiconductor device and a base plate formed of a metal having a relatively high thermal conductivity on which the resin part is placed. Was composed.

  In addition, the alignment between the semiconductor device and the contact substrate that electrically connects the test board is performed, for example, through positioning holes formed at the four corners of the tray.

  However, there is a problem that the resin portion is likely to be thermally deformed when it is molded with a relatively thin resin plate due to the difference in linear expansion coefficient between resin and metal.

  In particular, when the length of the substrate and the tray is relatively large, for example, about 300 mm, there is a problem that it is difficult to align (alignment means) the terminals of the contact substrate and the terminals of the semiconductor device in the tray, and the semiconductor in the tray and the tray There is also a problem that there is no means for suppressing variations in gaps between devices and it is difficult to perform high-precision alignment.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a tray unit and a semiconductor device inspection apparatus that can test a semiconductor device more efficiently and at a low cost and can improve the alignment accuracy in the tray. .

In order to solve the above problems, a tray unit according to the invention of claim 1 is a tray unit in which a plurality of semiconductor devices to be inspected can be mounted, and includes a bottom plate member that forms a bottom portion, and the bottom plate A semiconductor device mounting tray mounted on the member and divided into a plurality of parts in the horizontal direction, each of which mounts and holds a plurality of the semiconductor devices, and the terminals provided in the semiconductor devices face the upper surface side The semiconductor device mounting tray is detachably mounted on a semiconductor device inspection apparatus for testing the electrical characteristics of each semiconductor device in a state, and the respective semiconductor device mounting trays are placed on the bottom plate member until positioning by a separately provided positioning means is performed. On the other hand, it is held in a state in which the movement in the horizontal direction is allowed within a predetermined range. Protrusion that regulates the position of the semiconductor device or a square hole that regulates the movement of the semiconductor device, the semiconductor device is moved in the same direction at the same time as the semiconductor device tray is pressed in a predetermined direction, and is orthogonal to the bottom plate member. e Bei means to eliminate the clearance between the semiconductor device mounted tray and the semiconductor device by being pressed against the two sides of the protrusion, the positioning means along said predetermined direction provided in the semiconductor device mounting tray oval An alignment hole having a shape, and a cross-sectional shape similar to the alignment hole having the oval shape, provided on the contact substrate side provided to face the semiconductor device mounting tray; When the alignment pin inserted into the alignment hole and the alignment pin are removed from the alignment hole Characterized in that the elastic force and a pressing means for restoring said semiconductor device mounted tray to its original position in the direction opposite to the predetermined direction.

According to a second aspect of the present invention, there is provided an inspection apparatus for a semiconductor device , wherein an electrical continuity is established between a mounting portion for mounting the tray unit according to the first aspect and an electrode terminal of the semiconductor device mounted on the tray unit. A test board connected to a device inspection means for testing electrical characteristics of the semiconductor device, and provided between the test board and the semiconductor device mounting tray, and mounted on a semiconductor device mounting tray included in the tray unit. Contact substrate provided with conductive means for electrically connecting electrode terminals of each semiconductor device and electrode terminals included in the test board, and the semiconductor device and the device connected to the test boat via the contact substrate A connection mechanism for electrically connecting the inspection means, and the connection mechanism includes both of the mounting portions. And when the mounting portion is relatively moved to a predetermined position by the lifting means, the terminals of the semiconductor device, the contact substrate, and the contact substrate and the test board are in close contact with each other. The pressure reducing means is provided around the contact substrate frame surrounding the contact substrate, or the seal member provided at the end of the mounting portion and the mounting portion. In the decompression chamber formed by the contact substrate frame or the mounting portion, and the contact substrate frame, the contact substrate, the mounting portion and the sealing member when the is moved. And a vacuum pump for sucking the atmosphere.

  According to the present invention, the following effects can be obtained.

That is, according to the first aspect of the invention, since the electrical characteristics of each semiconductor device mounted using the semiconductor device mounting tray are tested, the test efficiency can be improved and the test cost can be reduced. An excellent effect can be achieved.

  The tray unit includes a bottom plate member that forms a bottom portion, and a semiconductor device mounting tray that is placed on the bottom plate member and divided into a plurality of portions in the horizontal direction, each holding a plurality of semiconductor devices. Therefore, it is possible to more reliably perform the electrical connection between the semiconductor device and the device inspection means by suppressing thermal deformation and the like.

According to the first aspect of the present invention, each semiconductor device mounting tray is held in a state in which horizontal movement with respect to the bottom plate member is allowed within a predetermined range until positioning by the positioning means is performed. Since it has a so-called floating structure, the positioning accuracy by the positioning means can be improved.

Furthermore, according to the first aspect of the present invention, since alignment can be performed in a state where there is no gap between the tray and the semiconductor device, further alignment accuracy is improved and electrical connection is more reliably performed. be able to.

According to the first aspect of the present invention, it is possible to improve the alignment accuracy between the terminal and the contact substrate included in the semiconductor device with a simple configuration, and to perform electrical connection more reliably.

According to the first aspect of the present invention, the semiconductor device mounting tray can be returned to the original position with a simple configuration.

According to the second aspect of the invention, it is possible to cope with semiconductor devices having different terminal arrangements and semiconductor devices having different configurations, and there is an effect that the test efficiency can be increased and the test cost can be reduced.

In addition, according to the second aspect of the present invention, the electrical connection between the terminal provided in the semiconductor device and the contact substrate can be reliably performed.

It is the side view (a) which shows schematic structure of the test | inspection apparatus of the semiconductor device which concerns on the 1st Embodiment of this invention, an AA arrow (b), and a BB arrow (c). It is explanatory drawing which shows schematic structure of the test | inspection apparatus of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a partially enlarged view of a semiconductor device inspection apparatus according to a first embodiment of the present invention; It is a disassembled perspective view which shows schematic structure of the test | inspection apparatus of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram which shows the structural example of the 1 layer structure vacuum chamber in the test | inspection apparatus of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram which shows the structural example of the 2 tank structure vacuum chamber in the test | inspection apparatus of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a block diagram of the alignment pin of a semiconductor device mounting tray. It is the top view (a) and side view (b) which show the structural example of a test tray. It is the top view (a) and side view (b) which show the detail of the device storage part of a tray. It is explanatory drawing which shows the state after a tray and a contact board | substrate are aligned. It is explanatory drawing which shows the state after a device is mounted in the tray (before alignment). It is explanatory drawing (a) of the alignment hole of a contact board | substrate and the whole tray, explanatory drawing (b) of the alignment hole of a contact board | substrate and tray upper frame, and explanatory drawing (c) of the floating mechanism of a tray upper frame. It is explanatory drawing which shows the structural example of the test | inspection system of a semiconductor device. It is explanatory drawing which shows the structural example of the test | inspection system of a semiconductor device.

  Hereinafter, the best mode for carrying out the present invention will be described more specifically with reference to the drawings. Here, in the accompanying drawings, the same reference numerals are given to the same members, and duplicate descriptions are omitted. In addition, since description here is the best form by which this invention is implemented, this invention is not limited to the said form.

  The semiconductor device inspection apparatus M1 according to the first embodiment shown in FIG. 1 to FIG. 3 and the like has a tray unit (semiconductor device mounting) shown in FIGS. 8 and 9 on which a semiconductor device D as an inspection target is mounted. An example of a tray) U1 and a tester unit 200 (an example of a device inspection means) that tests electrical characteristics of the semiconductor device D by conducting electrical continuity with the electrode terminals 101 of the semiconductor device D mounted on the tray unit U1. A tester mother board TM (an example of a test board) and a contact pin 102 (an example of a conductive means) provided to face the tester mother board TM and corresponding to the arrangement of terminals provided in the tester mother board TM are provided. The first contact substrate C1 and the first contact substrate C1 are provided so as to be interchangeable and are provided in the semiconductor device D. Corresponding to the difference in the arrangement of the child 101 and the arrangement of the terminals provided in the tester mother board TM, the conversion board 300 having a terminal arrangement having an electrode and a wiring structure for electrically connecting both, and the conversion board 300 and the tray unit U1 A contact pin 103 (an example of a conductive means) provided in between and corresponding to the arrangement of the terminals 101 included in the semiconductor device D, and a second contact substrate C2 in which the contact pin 103 is directly connected to the semiconductor device D; A connection mechanism 400 (an example of connection means) that electrically connects the semiconductor device D and the tester unit 200 connected to the tester mother substrate TM via the first contact substrate C1, the conversion substrate 300, and the second contact substrate C2. ).

  The semiconductor device mounting tray (frame 2002) mounts a plurality of semiconductor devices D to be inspected, and mounts a plurality of frames 2002 on the tray unit U1.

  The semiconductor device-mounted tray U1 has a memory, RFID (IC tag), barcode or the like (not shown) that stores information (for example, including ID data for identifying the tray unit U1) related to the inspection result by the tester unit 200. ) May be provided.

  Thus, for example, based on the tray ID (identification number), a defective product can be replaced with a non-defective product or a defective product can be classified, thereby improving convenience.

  Further, the conductive means may be constituted by a membrane sheet, an anisotropic conductive sheet or the like instead of the contact pin.

  The tester unit 200 may be provided immediately above the tester mother substrate TM as shown in FIG. 2, or may be provided on the front surface side 200 'or the back surface side 200 "of the extension of the tester mother substrate TM.

  Further, the tester unit 200 may be provided outside by connecting a coaxial cable or the like.

  Moreover, in this Embodiment, the semiconductor device D is hold | maintained at the tray unit U1 so that the terminal 101 side with which the said semiconductor device D is provided becomes an upper surface.

  In addition, a connection mechanism 400 is provided that electrically connects the semiconductor device D and the tester unit 200 connected to the tester mother substrate TM via the first contact substrate C1, the conversion substrate 300, and the second contact substrate C2. Yes.

  In the present embodiment, the connection mechanism 400 includes a placement portion 401 on which the tray unit U1 is placed, and an actuator (for example, an air cylinder or the like) that raises and lowers the placement portion 401 with respect to the second contact substrate C2. Lifting and lowering means 402).

  Further, in the present embodiment, the connection mechanism 400 includes the lifting / lowering means 402 provided on both sides of the mounting portion 401 and the semiconductor device D when the mounting portion 401 is raised to a predetermined position by the lifting / lowering means 402. The vacuum pump 500 (an example of a decompression unit) that sucks negative pressure so that the terminal 101 and the contact substrate C2 are in close contact with each other is configured.

  Further, the decompression means is provided in the contact substrate frame 403 surrounding the second contact substrate C2, or is provided at the end of the mounting portion 401, and when the mounting portion 401 is raised, the contact substrate frame 403 or A decompression chamber 550 is formed by the seal member 404 that is in contact with the placement unit 401, the contact substrate frame 403, the first contact substrate C 1, the placement unit 401, and the seal member 404, and the atmosphere in the decompression chamber 550 Is sucked by a vacuum pump 500.

  The vacuum pump 500 includes a pressure reducing valve 560 that adjusts the amount of pressure reduction.

  That is, by pressurizing the contact substrate frame 403 with the elevating means 402, the surface of the semiconductor device D and the upper surface of the tray unit U 1 are pushed down, preload is applied to the seal member 404, and then the pressure reducing valve 560 connected to the vacuum pump 500. Is turned on, the decompression chamber 550 is decompressed, the semiconductor device D and the tray unit U1 are further pressed by the hot plate 701, and the second contact substrate C2, the conversion substrate 300, and the second contact substrate C2 become the tester mother substrate. All contacts between the semiconductor device D and the tester mother substrate TM which are pressurized by TM and stored in the tray unit U1 are collectively connected with a predetermined force.

  As described above, according to the semiconductor device inspection apparatus M1 according to the present embodiment, it is possible to flexibly cope with a semiconductor device D having a different terminal arrangement or a semiconductor device D having a different configuration, thereby improving the test efficiency and performing the test. Cost can be reduced.

  Note that the decompression means is not limited to the above configuration, and the semiconductor device D and the tester mother substrate TM are brought into close contact with each other via the first contact substrate C1, the conversion substrate 300, and the second contact substrate C2. Any structure can be adopted as long as the structure can be connected to each other.

  In addition, alignment holes 600 are formed at a plurality of positions (four corners in the example shown in FIGS. 1 to 3) at the corners of the base plate 2001 of the tray and are extended downward from the tester mother substrate TM. Are engaged for alignment (see FIGS. 1A, 3 and 4).

  The semiconductor device inspection apparatus M1 further includes temperature adjusting means for adjusting the ambient temperature of the semiconductor device D mounted on each tray unit U1 to a predetermined test environment temperature.

  In the present embodiment, the temperature adjusting means is, for example, disposed below the tray base plate 2001 and includes a heat source 800 such as a Peltier module or a heater via a heat transfer plate 700 and a heat plate 702. .

  Although not particularly limited, the heat transfer plate 700 is formed of aluminum, copper, stainless steel, brass plate or the like having a thickness of about several millimeters.

  The heat source 800 may be a refrigerant or a heat medium supplied from a chiller, LN2, or the like, or may be a combination of cooling and heating by a Peltier module, a heater, a refrigerant (including LN2), and a heat medium.

  With the temperature adjusting means having such a configuration, it is possible to easily adjust the test environment temperature without accommodating the tray unit U1 in a constant temperature bath or the like as in the prior art, improving convenience and increasing the speed of the test. And the test cost can be reduced.

  Further, by mounting a Peltier module as the heat source 800, a high temperature test and a low temperature test, or a cycle test between a high temperature and a low temperature can be easily realized.

  Reference numeral 900 denotes a receiving portion that supports the tray unit U1 from below.

  Next, the operation of the semiconductor device inspection apparatus M1 according to the present embodiment will be described.

  First, in the semiconductor device inspection apparatus M1, the second contact substrate C2 and the conversion substrate 300 are exchanged so as to correspond to the characteristics (terminal arrangement, configuration, etc.) of the semiconductor device D to be inspected.

  Next, the tray unit U1 on which the semiconductor device D to be inspected is mounted is set on the placement unit 401.

  Subsequently, the elevating means 402 is operated, and the tray unit U1 is raised together with the placement unit 401.

  When the predetermined height is reached, the vacuum pump 500 is driven, and the atmosphere in the decompression chamber 550 is sucked.

  As a result, the terminal 101 included in the semiconductor device D and the first contact substrate C1, the second contact substrate C2, the conversion substrate 300, and the tester mother substrate TM are brought into close contact and electrically connected.

  Next, after the semiconductor device D is heated or cooled to a predetermined temperature by the temperature adjusting means, the inspection process of each semiconductor device D is executed by the operation of the tester mother substrate TM and the tester unit 200.

  When inspecting a semiconductor device having another configuration, the contact substrate C2 and the conversion substrate 300 are replaced with corresponding ones, and then the inspection is performed according to the above-described procedure.

  As described above, according to the semiconductor device inspection apparatus M1 according to the present embodiment, it is possible to flexibly cope with a semiconductor device D having a different terminal arrangement or a semiconductor device D having a different configuration, thereby improving the test efficiency and performing the test. Costs can be reduced.

  In the present embodiment, the case where the terminal of the semiconductor device D is directed upward is shown, but the present invention can also be applied to the case where the terminal of the semiconductor device D is directed downward.

  Next, a semiconductor device inspection apparatus M3 according to the third embodiment will be described with reference to FIGS.

  In the semiconductor device inspection apparatus M3, one or two or more tray units U1 on which a plurality of semiconductor devices D to be inspected are mounted in parallel are used, and terminals provided in the semiconductor device D are provided on each tray unit U1 on the upper surface side. A test board (one example of device inspection means: not shown in FIG. 8) for collectively testing the electrical characteristics of each semiconductor device D in a state of being mounted towards the tray, and the tray unit U1 is made of a metal such as aluminum. A bottom plate member (base plate) 2001 to be formed, and a semiconductor device mounting tray (for example, resin) placed on the base plate 2001 and divided into a plurality of parts in the horizontal direction, each holding a plurality of semiconductor devices D Or a frame made of metal) 2002a, 2002b, 2002c.

  Each frame 2002a, 2002b, 2002c is moved in the horizontal direction with respect to the base plate 2001 (for example, in the direction of arrow A) until positioning is performed by a positioning device (see FIGS. 5 to 12) provided separately. It is a so-called floating structure that is held in a state in which the movement is allowed in a predetermined range (for example, a range up to contact with the corner of the alignment hole 2003 shown in FIG. 9C).

  The constituent material of the base plate 2001 is not limited to aluminum, but a material having a thermal conductivity of 100 W / (m · K) or more is preferable.

  In this embodiment, the frame is divided into three. However, the present invention is not limited to this, and the frame may be divided into two as long as it is two or more.

  Alignment holes 2003 are formed at the edges of the frames 2002a, 2002b, and 2002c for aligning the frames 2002a, 2002b, and 2002c with a contact substrate (not shown).

  In addition, alignment holes 2005 are formed at the four corners of the base plate 2001 to align the entire tray unit U1.

  A corresponding alignment pin (see FIG. 7) in the apparatus is engaged with the alignment hole 2003 and the alignment hole 2005 to align the respective members.

  Thereby, position correction can be performed by the alignment pins.

  Further, it is possible to suppress thermal deformation in the tray unit U1.

  In the present embodiment, as shown in FIGS. 5 to 9, two frames 2002 (2002a, 2002b, 2002c) are provided horizontally on one tray unit U1.

  In the present embodiment, a plurality of semiconductor devices D (for example, DDR3, BGA package) are mounted on each frame 2002 with the terminals 2500 facing upward.

  In the upper and lower peripheral portions of each frame 2002, three alignment holes 2003 and three floating holes 2004 are provided.

  The alignment hole 2003 and the floating hole 2004 have an oval shape formed along the direction of arrow A as shown in FIGS.

  As shown in FIGS. 5 to 7, the contact substrate 1022 is provided with alignment pins 1024 that are inserted into the alignment holes 2003.

  The shape of the alignment pin 1024 is not particularly limited. For example, as shown in FIG. 7, the alignment pin 1024 has a cross-sectional shape similar to the oval shape of the alignment hole 2003.

  As shown in FIGS. 9A and 9B, two orthogonal projections 2006 for guiding the device D are provided at predetermined positions where the device D on the upper part of the base plate 2001 is accommodated. .

  When the alignment pin 1024 is inserted into the alignment hole 2003, each frame 2002 moves in the direction of arrow A due to the engagement between the alignment pin 1024 and the alignment hole 2003 (FIG. 8 to FIG. 8). At the same time, the semiconductor device mounted on the frame 2002 is also moved in the same direction, and pressed against two orthogonal projections 2006 provided on the base plate 2001, so that a gap between the device D and the frame 2002 is formed. Loss (see FIGS. 10 to 12), high-accuracy alignment is performed.

  In this embodiment, as shown in FIGS. 8 and 9, when a plate spring 2009 is provided at a predetermined position of the base plate 2001 and the alignment pin 1024 is removed from the alignment hole 2003. Furthermore, each frame 2002 is returned in the direction opposite to the arrow A by the elastic force of the leaf spring 2009, and the device D is also returned to the original position at the same time.

  On the other hand, a fixing hole 2008 is formed in the base plate 2001, a floating pin 2007 is inserted through the hole for floating 2004, and a tip portion is press-fitted into the fixing hole 2008 to be fixed ((( see c)).

  Next, a semiconductor device inspection apparatus M2 according to the second embodiment will be described with reference to FIGS.

  The semiconductor device inspection apparatus M2 conducts electrical continuity with the tray unit U1 and the electrode terminal 2007 (see FIGS. 10 to 12) of the semiconductor device D mounted on the tray unit U1 to determine the electrical characteristics of the semiconductor device D. A semiconductor device provided in a tray unit U1 provided between a test board 1021 connected to a test unit to be tested (an example of device inspection means: not shown) and a frame 1010 constituting the lower vacuum chamber. A contact substrate 1022 provided with a wiring structure (conductive means) for electrically connecting the electrode terminals 2007 of each semiconductor device D mounted on the mounting tray 2002 and the electrode terminals included in the test board 1021, and the contact substrate 1022 Connected to the semiconductor device D and the test boat 1021 And a connection mechanism for electrically connecting (see FIGS. 5 to 7) and a test unit was.

  Further, the test board 1021 can be replaced according to the type of the semiconductor device D or the arrangement of the electrode terminals 2007 provided in the semiconductor device D.

  Next, an outline of the alignment operation in the semiconductor device inspection apparatus M2 according to the present embodiment will be described.

  First, the tray unit U1 is installed on the lower vacuum chamber base plate 1010, and then alignment is performed by the alignment pins 1023 of the contact substrate 1022 and the alignment holes 2005 of the tray base plate 2001. Thereby, the position of the tray unit U1 is determined.

  Next, alignment is performed by the alignment hole 2003 on the divided frame 2002 and the contact pin 1024 provided in the contact substrate 1022.

  Finally, alignment between the tip of the terminal 1026 of the contact substrate 1022 and the terminal 2007 of the semiconductor device D is performed.

  Thereby, the thermal deformation of the frame 2002 and the like can be suppressed, and the electrical connection between the semiconductor device D and the test board can be more reliably performed.

  Further, instead of the mechanism for moving the frame 2002 by the engagement of the alignment pin 1024 and the alignment hole 2003, a mechanism for pressing the frame 2002 itself in the direction of arrow A may be provided outside the frame 2002. Good.

  Next, a semiconductor device inspection apparatus M2 according to the second embodiment will be described with reference to FIGS.

  As shown in FIGS. 4 to 6, in the upper structure, three divided contact substrates 1022 are arranged below the test board 1021.

  Guide holes 1023 through which guide pins 1014 described later are inserted are provided at four corners of the test board 1021.

  Reference numeral 1004 denotes a mounting area for various circuit members and connection connectors.

  Further, an edge connector may be provided on one side of the test board 1021.

  A contact substrate frame (upper vacuum chamber frame) 1006 is provided below the test board 1021.

  As shown in FIGS. 4 to 6, a seal member 1012 such as an O-ring is provided around the contact substrate frame 1006.

  On the other hand, in the lower structure, the tray unit U1 shown in FIG. 8 is placed on a placing portion (lower vacuum chamber) 1010 made of metal (for example, aluminum).

  At the four corners of the base plate 1010, guide pins 1014 that are inserted into the guide holes 1007 on the test board 1021 side are provided upright.

  A mounting portion 1013 for a vacuum valve is formed in a part of the lower mounting portion base plate 1010.

  A temperature adjustment unit 1015 configured by a heat sink or a heat source is provided below the placement unit base plate.

  The details of the tray unit U1 have been described in the semiconductor device inspection apparatus M3 according to the third embodiment, and a description thereof will be omitted.

  Further, as shown in FIGS. 5 to 9, as a connection mechanism, a decompression mechanism (negative pressure suction (so that the terminal 2007 and the contact substrate 1022 provided in the semiconductor device D) and the contact substrate 1022 and the test board 1021 are in close contact with each other is provided. Pressure reducing means) 1000.

  In the present embodiment, the decompression mechanism 1000 includes a first decompression chamber 1001 formed by the test board 1021, the contact substrate 1022, and the seal member 1025, and a vacuum valve 1016 that sucks an atmosphere in the first decompression chamber 1002. A first vacuum pump (not shown) to be connected, a contact substrate frame 1006 surrounding the contact substrate 1022, and a contact substrate provided at the end of the mounting portion 1010 when the mounting portion 1010 is moved A second vacuum pump connected to a second vacuum chamber 1002 formed by a seal member 1012 interposed between the frame 1006 and a vacuum valve 1013 for sucking the atmosphere in the second vacuum chamber 1002 (Not shown).

  Although not particularly limited, for example, first, the first vacuum chamber 1001 is depressurized by the first vacuum pump, and then the second depressurization chamber 1002 is depressurized by the second vacuum pump. A reliable electrical connection between D and the test board 1021 can be made.

  Further, instead of the first vacuum pump and the second vacuum pump, a single vacuum pump is provided, and the atmosphere in the first decompression chamber 1001 and the second decompression chamber 1002 is sucked by switching valves. May be.

  Further, for example, a bottom plate may be provided on the test tray U1, and the bottom plate may be made of a material having a thermal conductivity of 100 W / (m · K) or more.

More specifically, the bottom plate is made of copper (thermal conductivity 385 W / (m · K), specific gravity 8.9 g / cm ³ ) or aluminum (thermal conductivity 200 W / (m · K), specific gravity 2.7 g / cm ^3. ) Or brass (thermal conductivity 105 W / (m · K), specific gravity 8.7 g / cm ³ ).

  Thereby, the thermal conductivity of the bottom plate of the tray unit U1 can be increased and the inspection efficiency of the semiconductor device can be improved.

  Further, plate springs 2009 as shown in FIGS. 8 to 12 are provided at a plurality of locations on the base plate 2001 of the tray, and the frame 2002 is urged in the direction opposite to the arrow A direction to return the position. Good.

  9A and 9B, as an example, protrusions are provided on two sides on the side where the semiconductor device D is to be pressed, but a square hole for restricting the position of the device on the base plate 2001 (not shown). ) May be used.

  Next, the semiconductor device inspection system S1 will be briefly described with reference to FIGS.

  As shown in FIG. 13, a semiconductor device inspection system S1 applies a semiconductor device inspection apparatus M1 according to the present invention to collectively measure the electrical characteristics and the like of a semiconductor device D for each tray unit U1. It comprises a measuring apparatus M10, a semiconductor device tray transfer apparatus M11 that inverts and transfers the semiconductor device D, and a semiconductor device automatic sorter M12 that sorts the quality of the semiconductor device D.

  The semiconductor device measuring apparatus M10 includes a test unit 200.

  In the semiconductor device measuring apparatus M10, the tray unit U1 transferred from the semiconductor device tray transfer apparatus M11 is preheated by the preheating unit 3001, and then the tray is formed by the semiconductor device inspection apparatus M1 having the configuration shown in FIGS. The semiconductor device D mounted on the unit U1 is collectively tested for electrical characteristics.

  Next, the tray unit U1 is transferred to the heat removal unit 3002, removed heat, and then transferred to the semiconductor device tray transfer device M11.

  In the semiconductor device tray transfer device M11, the tray unit U1 is transferred to the semiconductor device measuring device M10 in the process of the pre-test shipping tray → the tray transfer of the semiconductor device D → the tray handling device 3003, and the test tray is transferred to the conductor device measuring device M10. For the tray unit U1 returned from U1, the tray handling device 3004 → inversion and transfer of the semiconductor device D → transfer to the semiconductor device automatic sorter M12 in the process of the shipping tray after the test, or the tray handling device 3004 → semiconductor Tray transfer for device D → Transfer in empty test tray flow.

  Also, in the semiconductor device automatic sorter M12, the semiconductor device D transferred through the post-test shipping tray is removed based on the inspection result, the defective product is removed, the non-defective product is filled, and the semiconductor device is passed through the non-defective product shipping tray. Sort D based on test results.

  Regarding the removed defective products, when the tray unit U1 is provided with a memory for storing identification information, an RFID (IC tag), or a barcode, the defective products are classified based on the information. It may be.

  Alternatively, a semiconductor device inspection system S2 having a multistage structure in which test stages to which the semiconductor device inspection apparatus M1 is applied is stacked over 1 to N (N is an integer) may be configured.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the embodiments disclosed herein are illustrative in all respects and are not limited to the disclosed technology. Should not be considered. That is, the technical scope of the present invention should not be construed restrictively based on the description in the above embodiment, but should be construed according to the description of the scope of claims. All modifications that fall within the scope of the claims and the equivalent technology are included.

  A semiconductor device inspection apparatus and a semiconductor device inspection system using the inspection apparatus according to the present invention can be applied to various semiconductor device inspection apparatuses that require a characteristic test. SDRAM, static RAM, flash memory, logic Various semiconductor devices such as devices and mixed logic / analog devices can be applied as test targets.

M1 to M3 Semiconductor device inspection apparatus C1 First contact substrate C2 Second contact substrate 101 Electrode terminal 102 Contact pin 103 Contact pin 200 Tester unit 300 Conversion substrate 301 Preheating unit 400 Connection mechanism 401 Mounting unit 402 Lifting unit 403 Contact substrate Frame 404 Seal member 500 Vacuum pump 550 Pressure reducing chamber 560 Pressure reducing valve 600 Positioning hole 601 Alignment pin 700 Heat transfer plate 701 Heat plate 702 Heat plate 800 Heat source U1 Tray unit 1000 Pressure reduction mechanism 1001 First pressure reduction chamber 1002 Second pressure reduction Chamber 1004 Circuit component and coaxial connector mounting area 1005 Edge connector 1006 Contact substrate frame 1007 Guide hole 1010 Base plate (lower vacuum chamber)
1012 Seal member 1013 Mounting port 1014 Guide pin 1015 Temperature control unit 1016 Mounting port 1021 Test board (tester mother board)
1022 Contact substrate 1023 Alignment pin (between contact substrate and tray unit)
1024 Alignment pin (between contact substrate and semiconductor mounting tray)
1025 Sealing member 1026 Contact substrate terminal 2001 Tray base plate 2002 Frame (divided semiconductor device mounting tray)
2003 Alignment hole (between contact substrate and semiconductor mounting tray)
2004 Floating hole 2005 Alignment hole (between contact substrate and tray unit)
2006 Position restriction projection 2007 Semiconductor device terminal 2008 Floating pin hole 2009 Leaf spring 3001 Preheating unit 3002 Heat removal unit 3003 Tray handling device 3004 Tray handling device 3005 Power supply device for tester D Semiconductor device M10 Semiconductor device measuring device M11 Semiconductor device Tray transfer device M12 Semiconductor device automatic sorter S1, S2 Inspection system 5002 First vacuum valve 5003 Second vacuum valve

Claims (2)

A tray unit on which a plurality of semiconductor devices to be inspected can be mounted, and a bottom plate member that forms a bottom portion, is placed on the bottom plate member, and is divided into a plurality of portions in the horizontal direction. A semiconductor device mounting tray for mounting and holding a plurality of the semiconductor devices, and being attached to and detached from a semiconductor device inspection apparatus for testing the electrical characteristics of each semiconductor device with the terminals provided on the semiconductor device facing the upper surface side Placed freely,
Each of the semiconductor device mounting trays is held in a state allowing horizontal movement within a predetermined range with respect to the bottom plate member until positioning by positioning means provided separately is performed,
The upper surface of the bottom plate member has a protrusion that restricts the position of two orthogonal sides of the semiconductor device, or a square hole that restricts the movement of the semiconductor device, and simultaneously presses the semiconductor device tray in a predetermined direction. also moved in the same direction, e Bei means to eliminate the clearance between the semiconductor device and the semiconductor device mounted tray by being pressed against the orthogonal two sides projections provided on the bottom plate member,
The positioning means includes
An alignment hole provided in the semiconductor device mounting tray and having an oval shape along the predetermined direction;
Positioning provided on the contact substrate side facing the semiconductor device mounting tray, having a cross-sectional shape similar to the positioning hole having the oval shape, and being inserted through the positioning hole And pins for
A pressing means for returning the semiconductor device mounting tray to an original position in a direction opposite to the predetermined direction by an elastic force when the alignment pin is pulled out of the alignment hole;
A tray unit characterized by that. A placement unit for placing the tray unit according to claim 1;
  A test board connected to a device inspection means for testing electrical characteristics of the semiconductor device by conducting electrical continuity with electrode terminals of the semiconductor device mounted on the tray unit; the test board; and the semiconductor device mounting tray; A contact substrate provided with conductive means for electrically connecting the electrode terminal of each semiconductor device mounted on the semiconductor device mounting tray provided in the tray unit and the electrode terminal provided in the test board; A connection mechanism for electrically connecting the semiconductor device and the device inspection means connected to the test boat via the contact substrate;
  The connection mechanism includes lifting and lowering means provided on both sides of the mounting portion, and when the mounting portion is relatively moved to a predetermined position by the lifting and lowering means, the terminals included in the semiconductor device, the contact substrate, and the contact It comprises pressure reducing means for sucking negative pressure so that the substrate and the test board are in close contact with each other,
  The pressure reducing means is provided around the contact substrate frame surrounding the contact substrate, or a seal member provided at an end of the mounting portion and the contact substrate frame or the front when the mounting portion is moved. A seal member that is in contact with the placement portion; and a vacuum pump that sucks an atmosphere in the decompression chamber formed by the contact substrate frame, the contact substrate, the placement portion, and the seal member. A semiconductor device inspection apparatus.