JP4742407B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

【００６８】
表１から、第１の配線導電層２１にスリットを設けることでＳＯＧ膜の厚さむらが抑制され、特に第１の配線導電層のＬ／Ｓ比を５０％、より好ましくは３３％とした時に、上記の厚さむらが著しく抑制されることが確認された。
【００６９】
第２実施形態
本実施形態に係る半導体装置は、フォトダイオードＩＣであり、図７（ａ）は、本実施形態に係るフォトダイオードＩＣの要部であるフォトダイオード部分の平面図であり、図７（ｂ）は図７（ａ）中のＡ−Ａ’における断面図である。
第１実施形態と同様に、フォトダイオードＰＤの形成領域において、シリコン半導体基体１中に、例えばｐ型不純物を高濃度に含有する第１ｐ型半導体層２とｐ型不純物を低濃度に含有する第２ｐ型半導体層（アノード層）３が形成されており、第２ｐ型半導体層３の表層領域にｎ型不純物を高濃度に含有するｎ型半導体層（カソード層）４が形成されており、ＰＩＮ型のフォトダイオードが形成されている。
また、フォトダイオードＰＤの外周領域において、第１ｐ型半導体層２および第２ｐ型半導体層３に接続するように、上記ｎ型半導体層４よりも深くまで、ｐ型不純物を高濃度に含有する第３ｐ型半導体層５が形成されて、フォトダイオードＰＤ領域を素子分離している。
【００７０】
上記のＰＩＮ型のフォトダイオードが形成されたシリコン半導体基体１の表面に、例えば酸化シリコンからなる表層絶縁層６が形成され、第３ｐ型半導体層５に達するコンタクト窓が穿設されている。
上記コンタクト窓内に埋め込まれて、第３ｐ型半導体層５にオーミックコンタクトする下側導電層２０が形成されている。
上記下側導電層２０は、好ましくは２００ｎｍ以下、例えば膜厚１００ｎｍ程度であり、８０Ω／□程度のシート抵抗を有するポリシリコンなどから構成される。
上記の表層絶縁層６に形成された第３ｐ型半導体層５に達するコンタクト窓は、フォトダイオードＰＤの受光領域となるｎ型半導体層４の領域を包囲する連続的パターンで穿設されており、下側導電層２０もｎ型半導体層４の領域を包囲する連続した堰堤のパターンで形成されている。
【００７１】
上記の下側導電層２０の上層に、例えば酸化シリコンからなる第１の絶縁層３１が形成されており、下側導電層２０に達するコンタクト窓３１Ｗが穿設されている。
上記コンタクト窓３１Ｗ内に埋め込まれて、下側導電層２０にオーミックコンタクトする第１の配線導電層２１が８００ｎｍ以上の膜厚で形成されている。
上記第１の配線導電層２１は、例えばアルミニウムあるいはその合金などから構成される。
図７（ｂ）の断面図は、第１の配線導電層２１の形成領域を横切る位置での断面ではないので、図面上に第１の配線導電層２１は描かれていない。
【００７２】
上記の第１の配線導電層２１のパターンとしては、フォトダイオードＰＤ領域を包囲するパターンにおいて、例えば距離ＬＳＡの間隔のスリットＳＬが形成されている。上記のスリットＳＬは、第１の配線導電層２１によって包囲される領域に対し、当該領域を５０％以上開放する間隔で設けられていることが好ましい。
【００７３】
上記の構成において、上記第１の配線導電層が、受光素子に対する電極を構成する導電体層であることが好ましく、さらに、第１の配線導電層が、上記受光素子のグランド（接地）側の電極を構成する導電層であり、第２の配線導電層が、受光素子の受光面を区画する遮光体として用いられ、グランドに接続している構成とすることが好ましい。
【００７４】
上記の第１の配線導電層２１の上層に、例えば酸化シリコンからなる第２の絶縁層３２が形成され、第２の絶縁層３２の表面に発生した段部（不図示）の側面に、当該段部を平坦化するように、無機系あるいは有機系ＳＯＧ（Spin on Glass ）などからなる無機系あるいは有機系の第３の絶縁層が形成されている。
第３の絶縁層は全面にエッチバックされており、第１の配線導電層２１に起因する第２の絶縁層３２の表面に発生した段部（不図示）の側面に残されるのみとなっているが、図７（ｂ）の断面図は、第２の絶縁層３２の表面に発生した段部の形成領域を横切る位置での断面ではないので、図面上に第３の絶縁層は描かれていない。
さらに、その上層に全面に例えば酸化シリコンからなる第４の絶縁層３４が形成されている。
上記の第２の絶縁層３２、第３の絶縁層３３および第４の絶縁層３４から、層間絶縁層３０が構成されている。
【００７５】
上記の層間絶縁層３０（具体的には第１の絶縁層３１および第３の絶縁層３３が形成された部分）を貫通して、第１の配線導電層２１に達するコンタクト窓が穿設され、当該コンタクト窓に埋め込まれて、第４の絶縁層３４上に所定のパターンで、即ち、スリットＳＬにより分断された第１の配線導電層２０相互を電気的に連結するように、第１の配線導電層２１に接続する第２の配線導電層２２が形成されている。
以上のようにして、下側導電層２０、第１の配線導電層２１、および第２の配線導電層２２から、ＰＩＮ型のフォトダイオードの第３ｐ型半導体層５に接続するアノード電極Ｅ_A が形成されている。
【００７６】
また、上記のＰＩＮ型のフォトダイオードのｎ型半導体層４に達するコンタクト窓が穿設され、ｎ型半導体層４にオーミックコンタクトするカソード電極Ｅ_Cが形成されている。
【００７７】
上記の本実施形態の半導体装置は、第１の配線導電層２１によって包囲された領域に対し、当該領域を例えば５０％以上開放する間隔で、第１の配線導電層にスリットが形成され、スリット間が第２の配線導電層によって、電気的に連結しており、さらに第１の配線導電層の下層に形成されている下側導電層によっも電気的に連結されている構成となっている。
従って、上記の本実施形態の半導体装置によれば、その製造工程における無機系あるいは有機系ＳＯＧ膜などの無機系あるいは有機系の第３の絶縁層を塗布して平坦化処理を行う工程において、フォトダイオードＰＤ領域を包囲してパターンの第１の配線導電層２１によるいわば堰堤が配置されているにもかかわらず、上記スリットＳＬが設けられていることにより、この無機系あるいは有機系の第３の絶縁層の流延を阻害することなく、塗布される絶縁層の厚さむらの程度を低減することが可能である。
上記において、第１の配線導電層の８００ｎｍに対して、第１の導電層は１００ｎｍ程度に薄く形成しているので、堰堤としての機能は低く、第３の絶縁層の流延を妨げない。
【００７８】
上記の本実施形態の半導体装置の製造方法について説明する。
まず、図８（ａ）に示すように、フォトダイオードＰＤの形成領域において、シリコン半導体基体１中に、イオン注入などにより、例えばｐ型不純物を高濃度に含有する第１ｐ型半導体層２とｐ型不純物を低濃度に含有する第２ｐ型半導体層（アノード層）３を形成し、第２ｐ型半導体層３の表層領域にｎ型不純物を高濃度に含有するｎ型半導体層（カソード層）４を形成して、ＰＩＮ型のフォトダイオードを形成する。
また、フォトダイオードＰＤの外周領域において、イオン注入などにより上記ｎ型半導体層４よりも深くまでｐ型不純物導入し、第１ｐ型半導体層２および第２ｐ型半導体層３に接続するように第３ｐ型半導体層５を形成して、フォトダイオードＰＤ領域を素子分離する。
【００７９】
次に、例えばＣＶＤ（Chemical Vapor Deposition ）法により、上記のＰＩＮ型のフォトダイオードが形成されたシリコン半導体基体１の表面に酸化シリコンを０．５μｍの膜厚で堆積させ、表層絶縁層６を形成する。
次に、フォトリソグラフィー工程により、表面絶縁層６上に第３ｐ型半導体層５領域を開口するパターンのレジスト膜（不図示）をパターン形成し、ＲＩＥ（反応性イオンエッチング）などのエッチングを施し、第３ｐ型半導体層５に達するコンタクト窓を穿設する。
次に、例えばＣＶＤ法により、上記コンタクト窓内を埋め込んで全面にポリシリコンを、好ましくは２００ｎｍ以下、例えば１００ｎｍの膜厚で堆積させる。このポリシリコンのシート抵抗は、例えば８０Ω／□程度とする。
次に、上記ポリシリコン膜をパターン加工して、下側導電層２０とする。
ここで、上記の上記の表層絶縁層６に形成する第３ｐ型半導体層５に達するコンタクト窓は、フォトダイオードＰＤの受光領域となるｎ型半導体層４の領域を包囲する連続的パターンで穿設し、下側導電層２０もｎ型半導体層４の領域を包囲する連続した堰堤のパターンで形成する。
【００８０】
次に、図８（ｂ）に示すように、例えばＣＶＤ法により、下側導電層２０を被覆して全面に酸化シリコンを堆積させ、第１の絶縁層３１を形成する。
次に、フォトリソグラフィー工程により、第１の絶縁層３１上に下側導電層２０領域を開口するパターンのレジスト膜（不図示）をパターン形成し、ＲＩＥ（反応性イオンエッチング）などのエッチングを施し、下側導電層２０に達するコンタクト窓（不図示）を穿設する。
次に、例えばスパッタリング法により、上記コンタクト窓内を埋め込んで全面にアルミニウムあるいはその合金を例えば８００ｎｍ以上の膜厚で堆積させ、パターン加工して、第１の配線導電層（不図示）とする。
ここで、第１の配線導電層２１は、図７に示すように距離ＬＳＡの間隔のスリットをもって分断されるように形成する。
上記のスリットＳＬは、第１の配線導電層２１によって包囲される領域に対し、当該領域を５０％以上開放する間隔で設けることが好ましい。
図８（ｂ）の断面図は、第１の配線導電層２１の形成領域を横切る位置での断面ではないので、図面上に第１の配線導電層２１は描かれていない。
【００８１】
次に、図８（ｃ）に示すように、上記の第１の配線導電層２１の上層に、例えばＴＥＯＳ（tetraethylorthosilicate ）を原料とするＣＶＤ法により、全面に酸化シリコンを０．５μｍの膜厚で堆積させ、第２の絶縁層３２を形成する。
このとき、下層に第１の配線導電層２１が形成されていることに起因して、第２の絶縁層３２の表面には一部に段部が発生するが、図８（ｃ）の断面図は、第２の絶縁層３２の表面に発生した段部の形成領域を横切る位置での断面ではないので、図面上に段部は描かれていない。
【００８２】
次に、図９（ｄ）に示すように、例えばスピンコート法により、上記段部を埋める膜厚で無機系あるいは有機系ＳＯＧ（Spin on Glass ）などを塗布し、上記段部を平坦化するように、無機系あるいは有機系の第３の絶縁層３３を形成する。
この工程において、スピンコート法によると遠心力により塗膜がウェーハ外方方向（例えば図面上Ｆ方向）に流延するが、フォトダイオードＰＤ領域を包囲して第１の配線導電層２１によるいわば堰堤が配置されているにもかかわらず、上記スリットＳＬが設けられていることにより、この無機系あるいは有機系の第３の絶縁層の流延を阻害することなく、塗布される第３の絶縁層３３の厚さむらの程度を低減することが可能である。
【００８３】
次に、図９（ｅ）に示すように、無機系あるいは有機系ＳＯＧなどからなる無機系あるいは有機系の第３の絶縁層３３に対して、全面にエッチバックを行う。この結果、第２の絶縁層３２の表面に形成されている段部の側面部の第３の絶縁層３３が残され、急峻な段差の緩和、すなわち平坦化がなされる。
図９（ｅ）の断面図のような、第２の絶縁層３２の表面に発生した段部の形成領域を横切る位置ではない断面においては、第３の絶縁層３３は上記エッチバックにより全て除去されてしまう。
【００８４】
次に、図９（ｆ）に示すように、上記エッチバックにより平坦化された表面上に、例えばＴＥＯＳを原料とするプラズマＣＶＤ法により全面に酸化シリコンを堆積させ、第４絶縁層３４を形成する。以上で、第２の絶縁層３２、第３の絶縁層３３および第４の絶縁層３４から構成される層間絶縁層３０が形成される。
次に、フォトリソグラフィー工程により不図示のレジスト膜をパターン形成し、ＲＩＥなどのエッチングを行って、上記の層間絶縁層３０（具体的には第２の絶縁層３２および第４の絶縁層３４が形成された部分）を貫通して、第１の配線導電層（不図示）に達するコンタクト窓を穿設し、さらに、例えば蒸着やスパッタリング法により、コンタクト窓に埋め込んでＡｌなどの導電性材料を全面に堆積させ、フォトリソグラフィー工程により所定のパターン、即ち、層間絶縁層３０に穿設されたコンタクト窓を通じて、スリットＳＬにより分断された第１の配線導電層相互を電気的に連結するパターンに加工して、第１の配線導電層２１に接続する第２の配線導電層２２を第４の絶縁層３４上に所定のパターンで形成する。
以上で、図７に示す本実施形態の半導体装置を製造することができる。
【００８５】
本実施形態に係る半導体装置の製造方法によれば、第１の配線導電層にスリットを形成するので、無機系あるいは有機系の第３絶縁層を塗布して平坦化処理を行う工程において、この絶縁層の流延を阻害することなく、塗布される絶縁層の厚さむらの程度を低減することが可能である。
上記において、第１の配線導電層の８００ｎｍに対して、第１の導電層は１００ｎｍ程度に薄く形成しているので、堰堤としての機能は低く、第３の絶縁層の流延を妨げない。
【００８６】
また、本実施形態に係る半導体装置の製造方法は、第１の配線導電層２１にスリットＳＬを設けるが、このスリットＳＬのパターン加工は第１の配線導電層２１のパターン加工と同時に行うものであり、また、このスリットＳＬ間を電気的に接続する連結部の形成も、従来における第２の配線導電層の形成工程と同様の工程にて形成できるので、従来方法に対して何ら工程数を増やすことなく実施することができる。
【００８７】
上記の本実施形態に係るフォトダイオードを有する半導体装置は、例えばＣＤやＤＶＤなおの光ディスク装置に搭載される受光素子、あるいはその他の受光素子として用いることができる。
【００８８】
本発明は、上記の実施の形態に限定されない。
例えば、上記の実施形態においてｐ型不純物とｎ型不純物を入れ替え、即ち、ｎ^- 型半導体領域の表層部にｐ型半導体領域を有するＰＩＮフォトダイオードに適用することができる。
また、フォトダイオードが受光する光の波長は、７８０ｎｍから６５０ｎｍ、さらには４００ｎｍ帯の青色光など、特に限定されない。
また、ＰＩＮフォトダイオードに限らず、フォトダイオード全般に適用可能である。
この他、本発明の要旨を逸脱しない範囲で種々の変更を行うことができる。
【００８９】
【発明の効果】
本発明の半導体装置は、第１の配線導電層にスリットが形成されているので、その製造工程における無機系あるいあ有機系などの絶縁層を塗布して平坦化処理を行う工程において、この絶縁層の流延を阻害することなく、塗布される絶縁層の厚さむらの程度を低減することが可能である。
【００９０】
また、本発明の半導体装置の製造方法は、第１の配線導電層にスリットを形成するので、有機系あるいは無機系などの絶縁層を塗布して平坦化処理を行う工程において、この絶縁層の流延を阻害することなく、塗布される絶縁層の厚さむらの程度を低減することが可能である。
【図面の簡単な説明】
【図１】図１は第１実施形態に係る半導体装置の平面図である。
【図２】図２は図１に示す半導体装置のＡ−Ａ’における断面図である。
【図３】図３は図１に示す半導体装置の製造方法の製造工程を示す断面図であり、第２の絶縁層の塗布工程までを示す。
【図４】図４は図３の続きの工程を示す断面図であり、第２の絶縁層のエッチバック工程までを示す。
【図５】図５は第１実施形態に係る半導体装置の第１の配線導電層のパターンを示す平面図である。
【図６】図６は実施例において半導体ウェーハに作成した第１の配線導電層のパターンを示す平面図である。
【図７】図７（ａ）は第２実施形態に係る半導体装置の平面図であり、図７（ｂ）は図７（ａ）中のＡ−Ａ’における断面図である。
【図８】図８は図７に示す半導体装置の製造方法の製造工程を示す断面図であり、（ａ）は第１の導電層の形成工程まで、（ｂ）は第１の配線導電層の形成工程まで、（ｃ）は第２の絶縁層の形成工程までを示す。
【図９】図９は図８の続きの工程を示す断面図であり、（ｄ）は第３の絶縁層の形成工程まで、（ｅ）は第３の絶縁層のエッチバック工程まで、（ｆ）は第４の絶縁層の形成工程までを示す。
【図１０】図１０は第１従来例における第２絶縁層を形成する工程までを示す断面図である。
【図１１】図１１は第１従来例における第２絶縁層をエッチバックする工程までを示す断面図である。
【図１２】図１２は第１従来例における第３絶縁層を形成する工程までを示す断面図である。
【図１３】図１３は第１従来例に係る半導体装置の平面図である。
【図１４】図１４（ａ）は第２従来例に係る半導体装置の平面図であり、図１４（ｂ）は図１４（ａ）中のＡ−Ａ’における断面図である。
【図１５】図１５は図１４に示す半導体装置の製造方法の製造工程を示す断面図であり、（ａ）は第２の絶縁層の形成工程まで、（ｂ）は第３の絶縁層の形成工程まで、（ｃ）は第３の絶縁層のエッチバック工程までを示す。
【符号の説明】
１…半導体基体、２…第１ｐ型半導体層、３…第２ｐ型半導体層（アノード層）、４…ｎ型半導体層（カソード層）、５…第３ｐ型半導体層、６…表層絶縁層、６ＷＡ，６ＷＣ…コンタクト窓、７Ａアノード電極、７Ｃ…カソード電極、２０…第１の導電層、２１…第１の配線導電層、２２…第２の配線導電層、２２Ｓ…連結部、３０…層間絶縁層、３０Ｗ…コンタクト窓、３１…第１の絶縁層、３１Ａ，３２Ａ…段部、３１Ｗ…コンタクト窓、３２…第２の絶縁層、３３…第３の絶縁層、３４…第４の絶縁層、４１…ウェーハ、１０１…半導体基体、１０２…絶縁層、１０３…第１の配線導電層、１０４…第１の絶縁層、１０５…有機系絶縁層、１０６…段部、１０７…第２の絶縁層、１０８…層間絶縁層、ＳＬ…スリット、ＰＤ…フォトダイオード、Ｅ_A …アノード電極、Ｅ_C …カソード電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which two wiring conductive layers are stacked with an interlayer insulating layer interposed therebetween and a manufacturing method thereof.
[0002]
[Prior art]
In a semiconductor integrated circuit device such as a large integrated circuit LSI, for example, a semiconductor integrated circuit having a photodiode, a so-called photodiode IC or the like, two or more wiring conductive layers, for example, a metal wiring layer are stacked via an interlayer insulating layer. Are often adopted.
In this case, in the formation of the wiring conductive layer, especially the upper wiring conductive layer, if there is a step corresponding to the pattern of the lower wiring conductive layer, this causes a disconnection in the upper wiring conductive layer, which causes a problem in reliability and yield. Occurs.
[0003]
In view of this, the surface of the interlayer insulating layer, which is the deposition surface of the upper wiring conductive layer, can be flattened. A method for manufacturing a semiconductor device according to this method will be described below with reference to the drawings.
[0004]
First, as shown in FIG. 10, for example, an insulating layer 102 made of silicon oxide is formed on the surface of a semiconductor substrate 101 on which a semiconductor element (not shown) is formed, and a lower wiring conductive layer (first layer) on which, for example, an electrode is formed. The first insulating layer 104 is formed by depositing silicon oxide on the entire surface by, for example, a CVD (Chemical Vapor Deposition) method, for example.
Next, an organic insulating layer 105 such as an organic SOG (Spin on Glass) film is formed by a spin coating method or the like so as to embed the step 106 formed on the surface of the first insulating layer 104.
[0005]
Next, as shown in FIG. 11, the organic insulating layer 105 is etched back. As described above, when etch back is performed to the extent that the organic insulating layer 105 in the flat portion of the first insulating layer 104 is removed, a portion where the substantial film thickness of the side surface portion of the step portion 106 remains is left. As a result, the stepped portion 106 is filled with the organic insulating layer 105, and the surface is flattened with a gentle inclination.
[0006]
Next, as shown in FIG. 12, a second insulating layer 107 is formed by depositing silicon oxide over the entire surface of the organic insulating layer 105, for example, by the CVD method. As a result, the interlayer insulating layer 108 is configured by the first insulating layer 104, the organic insulating layer 105, and the second insulating layer 107.
The interlayer insulating layer 108 formed in this manner has the step 106 relaxed by the organic insulating layer 105, and the surface of the interlayer insulating layer 108 is improved by the second insulating layer 107 formed by a so-called CVD method with good coverage. Flattened. In addition, the organic insulating layer 105 is protected by the second insulating layer 107.
[0007]
Although not shown, an upper wiring conductive layer (referred to as a second wiring conductive layer) is formed in a predetermined pattern on the interlayer insulating layer 108 flattened in this manner, and is formed in the interlayer insulating layer 108. It is electrically connected to a predetermined portion of the first wiring conductive layer 103 through the contact hole.
[0008]
[Problems to be solved by the invention]
However, in the case where the surface of the interlayer insulating layer that is the deposition surface of the second wiring conductive layer is planarized by the above-described method, there is a case where satisfactory planarization is not necessarily performed. Further, it has been found that the cause depends on the pattern of the lower first wiring conductive layer.
[0009]
That is, when the pattern of the first wiring conductive layer surrounds or sandwiches a certain part, the casting of the organic insulating layer paint during the application of the organic insulating layer is obstructed. It has been investigated that the unevenness of the thickness of the organic insulating layer is remarkably generated, and that the remaining organic insulating layer is excessive or deficient in the etch back of the organic insulating layer. In the manufacture of semiconductor devices, a method is used in which a plurality of semiconductor chips (semiconductor devices) are simultaneously formed on a semiconductor wafer, and these are separated (diced) from the wafer. Unevenness occurs remarkably around the periphery of the wafer.
[0010]
FIG. 13 is a plan view of a photodiode having a structure in which the first wiring conductive layer pattern surrounds or is sandwiched as described above.
In the formation region of the photodiode PD, for example, an anode layer containing a p-type impurity is formed in the silicon semiconductor substrate 1, and a cathode layer 4 containing an n-type impurity is formed in the surface layer region. In the outer peripheral region of the diode PD, a p-type semiconductor layer 5 is formed to isolate the photodiode PD region.
A surface insulating layer made of, for example, silicon oxide is formed on the surface of the silicon semiconductor substrate 1 on which the photodiode is formed, and a contact window 6WA reaching the anode layer 5 and a contact window 6WC reaching the cathode layer 4 are formed, An anode electrode 7A and a cathode electrode 7C are formed by being embedded in contact windows (6WA, 6WC), respectively, and the anode wiring 7A and the cathode electrode 7C constitute a first wiring conductive layer.
[0011]
A predetermined interlayer insulating layer is formed on the first wiring conductive layer, and the second wiring conductive layer 22 is formed on the interlayer insulating layer through a contact window formed in the interlayer insulating layer. It is connected to the first wiring conductive layer and formed in a predetermined pattern.
The above-mentioned interlayer insulating layer can be constituted by, for example, a first insulating layer made of silicon oxide, a second insulating layer made of SOG or the like, and a third insulating layer 33 made of silicon oxide. In the step of applying SOG to form the second insulating layer, the pattern of the first wiring conductive layer is in a state of sandwiching the photodiode region. In other words, it becomes a dam and obstructs the casting of the insulating layer coating material as the second insulating layer, resulting in significant unevenness in the thickness of the organic insulating layer.
[0012]
An example of another photodiode in which the above problem occurs will be described below.
FIG. 14A is a plan view of the photodiode portion, and FIG. 14B is a cross-sectional view taken along line A-A ′ in FIG.
In the formation region of the photodiode PD, for example, a first p-type semiconductor layer 2 containing a high concentration of p-type impurities and a second p-type semiconductor layer (anode layer) containing a low concentration of p-type impurities in the silicon semiconductor substrate 1. 3 is formed, an n-type semiconductor layer (cathode layer) 4 containing an n-type impurity at a high concentration is formed in the surface layer region of the second p-type semiconductor layer 3, and a PIN photodiode is formed. Yes.
In addition, in the outer peripheral region of the photodiode PD, a p-type impurity containing a high concentration of p-type impurities deeper than the n-type semiconductor layer 4 is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A 3p type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0013]
A surface insulating layer 6 made of, for example, silicon oxide is formed on the surface of the silicon semiconductor substrate 1 on which the PIN type photodiode is formed, and a contact window reaching the third p-type semiconductor layer 5 is formed, so that the third p A lower conductive layer 20 in ohmic contact with the type semiconductor layer 5 is formed in a continuous dam pattern surrounding the region of the n type semiconductor layer 4.
A first insulating layer 31 made of, for example, silicon oxide is formed on the lower conductive layer 20, and a contact window 31W reaching the lower conductive layer 20 is formed in the contact window 31W. A first wiring conductive layer 21 that is buried and is in ohmic contact with the lower conductive layer 20 is formed in a continuous dam pattern surrounding the region of the n-type semiconductor layer 4 with a film thickness of, for example, 800 nm or more. .
[0014]
A second insulating layer 32 made of, for example, silicon oxide is formed on the upper layer of the first wiring conductive layer 21, and a step portion (not shown) generated on the surface of the second insulating layer 32 is formed on the side surface of the step. A third insulating layer made of organic SOG (Spin on Glass) or the like is formed so as to flatten the stepped portion.
The third insulating layer is etched back on the entire surface, and is only left on the side surface of the step portion 32 </ b> A generated on the surface of the second insulating layer 32 caused by the first wiring conductive layer 21.
Further, a fourth insulating layer 34 made of, for example, silicon oxide is formed on the entire upper layer.
The second insulating layer 32, the third insulating layer 33, and the fourth insulating layer 34 constitute an interlayer insulating layer 30.
As described above, the anode electrode E connected from the lower conductive layer 20 and the first wiring conductive layer 21 to the third p-type semiconductor layer 5 of the PIN type photodiode._A On the other hand, a contact window reaching the n-type semiconductor layer 4 of the PIN type photodiode is formed, and the cathode electrode E is in ohmic contact with the n-type semiconductor layer 4._C Is formed.
[0015]
A method for manufacturing the photodiode will be described.
First, as shown in FIG. 15A, in the formation region of the photodiode PD, the first p-type semiconductor layer 2 and the p-type semiconductor layer 2 containing a high concentration of p-type impurities, for example, by ion implantation into the silicon semiconductor substrate 1. A second p-type semiconductor layer (anode layer) 3 containing a low concentration of type impurities is formed, and an n-type semiconductor layer (cathode layer) 4 containing a high concentration of n-type impurities in the surface layer region of the second p-type semiconductor layer 3 is formed. To form a PIN type photodiode.
Further, in the outer peripheral region of the photodiode PD, p-type impurities are introduced deeper than the n-type semiconductor layer 4 by ion implantation or the like, and the third p is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0016]
Next, the surface insulating layer 6 is formed by depositing silicon oxide with a film thickness of 0.5 μm on the surface of the silicon semiconductor substrate 1 on which the above-described PIN type photodiode is formed by, for example, CVD (Chemical Vapor Deposition). To do.
Next, a resist film (not shown) having a pattern that opens the third p-type semiconductor layer 5 region is formed on the surface insulating layer 6 by photolithography, and etching such as RIE (reactive ion etching) is performed. A contact window reaching the third p-type semiconductor layer 5 is formed.
Next, for example, CVD is used to fill the inside of the contact window, deposit polysilicon on the entire surface, pattern the lower conductive layer 20 in a continuous dam pattern surrounding the region of the n-type semiconductor layer 4. Form.
[0017]
Next, for example, by CVD, the lower conductive layer 20 is covered and silicon oxide is deposited on the entire surface to form a first insulating layer 31 and a contact window (not shown) reaching the lower conductive layer 20 is formed. Then, the contact window is buried, aluminum or an alloy thereof is deposited on the entire surface with a film thickness of, for example, 800 nm or more, and patterned to form the first wiring conductive layer 21.
Next, silicon oxide is deposited on the entire surface to a thickness of 0.5 μm on the entire surface of the first wiring conductive layer 21 by, for example, a CVD method using TEOS (tetraethylorthosilicate) as a raw material. Form.
At this time, a step 32A is generated on the surface of the second insulating layer 32 due to the formation of the first wiring conductive layer 21 in the lower layer.
[0018]
Next, as shown in FIG. 15B, for example, by spin coating, an inorganic or organic SOG (Spin on Glass) or the like is applied with a film thickness to fill the stepped portion 32A, and the stepped portion is flattened. Thus, the inorganic or organic third insulating layer 33 is formed.
In this process, according to the spin coating method, the coating film is cast in the wafer outward direction (for example, F direction on the drawing) by centrifugal force. However, the so-called dam by the first wiring conductive layer 21 surrounds the photodiode PD region. Therefore, the casting of the third insulating layer is hindered, and the uneven thickness P of the third insulating layer 33 to be applied is generated.
[0019]
Next, as shown in FIG. 15C, the entire surface of the third insulating layer 33 is etched back. As a result, the third insulating layer 33 on the side surface of the step portion 32A is left, and the steep step is alleviated, that is, flattened.
[0020]
As the subsequent steps, for example, silicon oxide is deposited on the entire surface by a plasma CVD method using TEOS as a raw material to form the fourth insulating layer 34. Thus, the semiconductor device of this embodiment shown in FIG. 14 is manufactured. Can do.
[0021]
In the above-described photodiode manufacturing method, when the SOG is applied as the third insulating layer, the pattern of the first wiring conductive layer surrounds the photodiode region. The step portion by the layer becomes a so-called dam, and the casting of the insulating layer coating as the third insulating layer is hindered, and as a result, the uneven thickness of the insulating layer is remarkably generated.
[0022]
The present invention has been made in view of the above-described problems, and therefore the object of the present invention is to manufacture a semiconductor device such as a photodiode in which two wiring conductive layers are laminated via an interlayer insulating layer. In addition, in the process of applying an organic or inorganic insulating layer and performing a flattening process, the thickness of the applied insulating layer is reduced without obstructing the casting of the insulating layer. It is an object of the present invention to provide a semiconductor device that can be used and a manufacturing method thereof.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device of the present invention includes a first wiring conductive layer formed on a semiconductor substrate, a first insulating layer formed to cover the first wiring conductive layer, On the first insulating layer, an inorganic second insulating layer formed on the side surface of the step formed on the surface of the first insulating layer so as to flatten the step, and the first A third insulating layer formed on the second insulating layer, and a second wiring conductive layer formed on the third insulating layer, and a slit is formed in the first wiring conductive layer. The slits are electrically connected by the second wiring conductive layer.
[0024]
In the semiconductor device of the present invention, preferably, the second insulating layer is an inorganic SOG film.
[0025]
In the semiconductor device of the present invention, preferably, the slit of the first wiring conductive layer is an interval that opens at least 50% or more of the region surrounded or sandwiched by the first wiring conductive layer. And
[0026]
In the semiconductor device of the present invention, preferably, the first wiring conductive layer is a conductor layer that constitutes an electrode for the light receiving element.
More preferably, the first wiring conductive layer is a conductive layer constituting an electrode on the ground (ground) side of the light receiving element, and the second wiring conductive layer defines a light receiving surface of the light receiving element. It is used as a shading body that connects to the ground.
[0027]
In the semiconductor device of the present invention, preferably, the first wiring conductive layer is formed in the first, second and third insulating layers or the first and third insulating layers. The second wiring conductive layer is connected through the first contact hole.
[0028]
In the above-described semiconductor device of the present invention, the first wiring conductive layer is formed on the semiconductor substrate, the first insulating layer is formed thereon, and the step portion is formed on the side surface of the step portion generated on the surface. A structure in which an inorganic second insulating layer such as an inorganic SOG film formed so as to be flattened is formed, and a third insulating layer and a second wiring conductive layer are formed thereon. In FIG. 2, a slit is formed in the first wiring conductive layer at an interval of, for example, 50% or more of the region surrounded or sandwiched by the first wiring conductive layer, and the second wiring conductive layer is formed between the slits. Therefore, it is electrically connected.
[0029]
According to the semiconductor device of the present invention, since the slit is formed in the first wiring conductive layer, this insulating layer is applied in the step of applying the inorganic insulating layer and performing the planarization process in the manufacturing process. It is possible to reduce the degree of unevenness of the thickness of the insulating layer to be applied without hindering the casting.
[0030]
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first wiring conductive layer having a slit in a semiconductor substrate, and a whole surface on the first wiring conductive layer. Forming a first insulating layer; forming an inorganic second insulating layer on the surface of the first insulating layer; and planarizing the surface of the first insulating layer; Forming a third insulating layer, and forming a second wiring conductive layer on at least the interlayer insulating layer formed of the first and third insulating layers. A layer is formed so as to straddle between the slits of the first wiring conductive layer, and the first wiring conductive layers separated by the slit are mutually connected through a first contact hole formed in the interlayer insulating layer. A connection wiring portion to be connected to is formed.
[0031]
In the method for manufacturing a semiconductor device according to the present invention, preferably, the slit of the first wiring conductive layer is open at least 50% or more around the region surrounded or sandwiched by the wiring layer. To do.
[0032]
In the semiconductor device manufacturing method of the present invention, preferably, the first wiring conductive layer is a conductive layer that constitutes an electrode for the light receiving element.
[0033]
In the method of manufacturing a semiconductor device according to the present invention, the first wiring conductive layer having a slit is formed in the semiconductor substrate, the first insulating layer is formed on the entire upper layer, and the inorganic second layer is formed on the surface. An insulating layer is formed. Next, the surface of the first insulating layer is planarized, and a third insulating layer is formed over the entire surface. Next, a second wiring conductive layer is formed on the interlayer insulating layer including at least the first and third insulating layers. Here, the first wiring conductive layer is formed so as to straddle between the slits of the first wiring conductive layer, and is divided by the slit through the first contact hole formed in the interlayer insulating layer. The layers are formed to be interconnected.
[0034]
According to the semiconductor device manufacturing method of the present invention, since the slit is formed in the first wiring conductive layer, the insulating layer is cast in the step of applying the inorganic insulating layer and performing the planarization treatment. It is possible to reduce the degree of unevenness in the thickness of the applied insulating layer without hindering the above.
[0035]
In order to achieve the above object, a semiconductor device of the present invention includes a first conductive layer formed on a semiconductor substrate, a first insulating layer formed to cover the first conductive layer, A first wiring conductive layer formed on the first insulating layer; a second insulating layer formed covering the first wiring conductive layer; and the second insulating layer on the second insulating layer. Formed on the side surface of the step portion generated on the surface of the second insulating layer on the third insulating layer and the organic or inorganic third insulating layer formed so as to flatten the step portion. A fourth insulating layer and a second wiring conductive layer formed on the fourth insulating layer, wherein a slit is formed in the first wiring conductive layer, and the gap between the slits is The two wiring conductive layers or both the first conductive layer and the second wiring conductive layer are electrically connected.
[0036]
In the semiconductor device of the present invention, preferably, the third insulating layer is an organic or inorganic SOG film.
[0037]
In the semiconductor device of the present invention, preferably, the slit of the first wiring conductive layer is an interval that opens at least 50% or more of the region surrounded or sandwiched by the first wiring conductive layer. And
[0038]
In the above-described semiconductor device of the present invention, preferably, the first conductive layer and the first wiring conductive layer are conductor layers constituting electrodes for the light receiving element.
More preferably, the first conductive layer and the first wiring conductive layer are conductive layers constituting an electrode on the ground (ground) side of the light receiving element, and the second wiring conductive layer is the light receiving element. It is used as a light shield that partitions the light receiving surface of the element, and is connected to the ground.
[0039]
In the semiconductor device of the present invention, preferably, the first wiring conductive layer is connected to the first conductive layer through a first contact hole formed in the first insulating layer. .
[0040]
In the semiconductor device of the present invention, preferably, the first wiring conductive layer is formed in the second, third, and fourth insulating layers, or the second and fourth insulating layers. The second wiring conductive layer is connected through the second contact hole.
[0041]
In the semiconductor device of the present invention, preferably, the first conductive layer has a thickness of 200 nm or less, and the first wiring conductive layer has a thickness of 800 nm or more.
[0042]
In the semiconductor device of the present invention described above, the first conductive layer is formed on the semiconductor substrate, the first insulating layer is formed thereon, the first wiring conductive layer is formed thereon, and the upper layer is formed thereon. A second insulating layer is formed, and an organic or inorganic third layer such as an organic or inorganic SOG film formed so as to flatten the step on the side surface of the step generated on the surface thereof. In the configuration in which the insulating layer is formed and the fourth insulating layer and the second wiring conductive layer are formed thereon, the region is surrounded by or sandwiched by the first wiring conductive layer. For example, slits are formed in the first wiring conductive layer at intervals of 50% or more, and the slits are electrically connected by the second wiring conductive layer.
[0043]
According to the semiconductor device of the present invention, since the slit is formed in the first wiring conductive layer, this insulating layer is applied in the step of applying the inorganic insulating layer and performing the planarization process in the manufacturing process. It is possible to reduce the degree of unevenness of the thickness of the insulating layer to be applied without hindering the casting.
[0044]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive layer on a semiconductor substrate, and forming a first insulating layer on the first conductive layer. A step of forming a first wiring conductive layer having a slit on the first insulating layer, and a step of forming a second insulating layer on the entire surface of the first wiring conductive layer. A step of forming an organic or inorganic third insulating layer on the surface of the second insulating layer and planarizing the surface of the second insulating layer; and a fourth insulating layer on the entire surface. And a step of forming a second wiring conductive layer on at least the interlayer insulating layer formed of the second and fourth insulating layers, and the first conductive layer and the second wiring conductive layer. A layer is formed so as to straddle the slits of the first wiring conductive layer, and is drilled in the first insulating layer. The first contact hole divided by the slit through the second contact hole formed in the second, third and fourth insulating layers or the second and fourth insulating layers. A connecting wiring portion for connecting the wiring conductive layers is formed.
[0045]
In the method for manufacturing a semiconductor device according to the present invention, preferably, the slit of the first wiring conductive layer is open at least 50% or more around the region surrounded or sandwiched by the wiring layer. To do.
[0046]
In the method for manufacturing a semiconductor device according to the present invention, preferably, the first conductive layer and the first wiring conductive layer are conductive layers constituting an electrode for a light receiving element.
[0047]
In the method of manufacturing a semiconductor device according to the present invention, the first conductive layer is formed on the semiconductor substrate, and the first insulating layer is formed thereon. Next, a first wiring conductive layer having a slit is formed on the upper layer, and a second insulating layer is formed on the entire upper layer. An organic or inorganic third insulating layer is formed on the surface of the second insulating layer, and the surface of the second insulating layer is planarized. Further, a second wiring conductive layer is formed on the entire surface of the fourth insulating layer and on an interlayer insulating layer made up of at least the second and fourth insulating layers. Here, the first conductive layer and the second wiring conductive layer are formed so as to straddle the slits of the first wiring conductive layer, and the first contact hole formed in the first insulating layer, and Formed so as to interconnect the first wiring conductive layers separated by the slits through the second, third and fourth insulating layers or the second contact holes formed in the second and fourth insulating layers. To do.
[0048]
According to the semiconductor device manufacturing method of the present invention, since the slit is formed in the first wiring conductive layer, this insulating layer is applied in the step of applying an organic or inorganic insulating layer and performing a planarization process. It is possible to reduce the degree of unevenness of the thickness of the insulating layer to be applied without hindering the casting.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0050]
First embodiment
The semiconductor device according to this embodiment is a photodiode IC.
FIG. 1 is a plan view of a photodiode portion that is a main part of the photodiode IC according to the present embodiment, and FIG. 2 is a sectional view taken along line A-A ′ in FIG. 1.
In the formation region of the photodiode PD, for example, a first p-type semiconductor layer 2 containing a high concentration of p-type impurities and a second p-type semiconductor layer (anode layer) containing a low concentration of p-type impurities in the silicon semiconductor substrate 1. 3 is formed, an n-type semiconductor layer (cathode layer) 4 containing an n-type impurity at a high concentration is formed in the surface layer region of the second p-type semiconductor layer 3, and a PIN photodiode is formed. Yes.
In addition, in the outer peripheral region of the photodiode PD, a p-type impurity containing a high concentration of p-type impurities deeper than the n-type semiconductor layer 4 is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A 3p type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0051]
A surface insulating layer 6 made of, for example, silicon oxide is formed on the surface of the silicon semiconductor substrate 1 on which the PIN photodiode is formed.
In the surface insulating layer 6, a contact window 6WA reaching the third p-type semiconductor layer 5 and a contact window 6WC reaching the n-type semiconductor layer 4 are formed.
An anode electrode 7A and a cathode electrode 7C that are in ohmic contact with the third p-type semiconductor layer 5 and the n-type semiconductor layer 4 are embedded in contact windows (6WA and 6WC), respectively. A first wiring conductive layer 21 is formed from the electrode 7C.
[0052]
A first insulating layer 31 made of, for example, silicon oxide is formed on the first wiring conductive layer 21, and the stepped portion is formed on the side surface of the stepped portion 31 </ b> A generated on the surface of the first insulating layer 31. An inorganic second insulating layer 32 made of inorganic SOG (Spin on Glass) or the like is formed so as to be planarized.
Furthermore, a third insulating layer 33 made of, for example, silicon oxide is formed on the entire upper layer.
The first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 constitute an interlayer insulating layer 30.
[0053]
A contact window 30W that penetrates the interlayer insulating layer 30 (specifically, the portion where the first insulating layer 31 and the third insulating layer 33 are formed) and reaches the first wiring conductive layer 21 is formed. Has been.
The second wiring conductive layer 22 connected to the first wiring conductive layer 21 is embedded in the contact window 30W and formed on the third insulating layer 33 in a predetermined pattern.
[0054]
In the above configuration, it is preferable that the first wiring conductive layer is a conductor layer that constitutes an electrode for the light receiving element, and further, the first wiring conductive layer is on the ground (ground) side of the light receiving element. The conductive layer that constitutes the electrode, and the second wiring conductive layer is preferably used as a light shielding body that partitions the light receiving surface of the light receiving element and is connected to the ground.
[0055]
In the above configuration, the pattern of the first wiring conductive layer 21 is a pattern in which the anode electrode 7A and the cathode electrode 7C constituting the first wiring conductive layer 21 are opposed to both sides of the photodiode PD region. However, here, in the present embodiment, the slit SL is formed in the first wiring conductive layer 21. That is, slits with a distance LSA are formed in the anode electrode 7A, and slits with a distance LSC are formed in the cathode electrode 7C. The slit SL is preferably provided at an interval that opens 50% or more of the region sandwiched between the first wiring conductive layers 21.
The anode electrode 7A and the cathode electrode 7C divided by the slit SL are in ohmic contact with the third p-type semiconductor layer 5 and the n-type semiconductor layer 4 respectively, and the anode electrodes 7A separated by the slit SL and The cathode electrodes 7C are electrically connected to each other by a connecting portion 22S formed as a part of the second wiring conductive layer 22 formed thereon. That is, the connecting portion 22S electrically connects the anode electrode 7A and the cathode electrode 7C to each other through the contact window 30W formed in the interlayer insulating layer 30.
[0056]
In the semiconductor device of the present embodiment described above, slits are formed in the first wiring conductive layer with respect to a region sandwiched between the first wiring conductive layers 21 at intervals that open the region, for example, by 50% or more. Are electrically connected by the second wiring conductive layer.
Therefore, according to the semiconductor device of the present embodiment, the photodiode PD region is sandwiched in the step of applying the inorganic second insulating layer such as the inorganic SOG film and performing the planarization process in the manufacturing process. In this case, the slit SL is provided in spite of the fact that the first wiring conductive layer 21 composed of the anode electrode 7A and the cathode electrode 7C is disposed on both sides. It is possible to reduce the degree of uneven thickness of the applied insulating layer without hindering the casting of the insulating layer.
[0057]
A method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 3, in the formation region of the photodiode PD, the first p-type semiconductor layer 2 and the p-type impurity containing a high concentration of, for example, a p-type impurity are introduced into the silicon semiconductor substrate 1 by ion implantation or the like. A second p-type semiconductor layer (anode layer) 3 containing a low concentration is formed, and an n-type semiconductor layer (cathode layer) 4 containing a high concentration of n-type impurities is formed in the surface region of the second p-type semiconductor layer 3. Thus, a PIN type photodiode is formed.
Further, in the outer peripheral region of the photodiode PD, p-type impurities are introduced deeper than the n-type semiconductor layer 4 by ion implantation or the like, and the third p is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0058]
Next, the surface insulating layer 6 is formed by depositing silicon oxide with a film thickness of 0.5 μm on the surface of the silicon semiconductor substrate 1 on which the above-described PIN type photodiode is formed by, for example, CVD (Chemical Vapor Deposition). To do.
Next, a resist film (not shown) having a pattern opening the third p-type semiconductor layer 5 region and the n-type semiconductor layer 4 region is formed on the surface insulating layer 6 by a photolithography process, and RIE (reactive ion etching) is performed. The contact window 6WA reaching the third p-type semiconductor layer 5 and the contact window 6WC reaching the n-type semiconductor layer 4 are formed.
[0059]
Next, for example, by sputtering, the contact window 6WA and the contact window 6WC are filled and an Al alloy is deposited to a thickness of 0.8 μm on the entire surface, and the Al alloy film is patterned by a photolithography process and an etching process. Then, the first wiring conductive layer 21 including the anode electrode 7A and the cathode electrode 7C that are in ohmic contact with the third p-type semiconductor layer 5 and the n-type semiconductor layer 4 through the contact window 6WA and the contact window 6WC is formed.
Here, the anode electrode 7A and the cathode electrode 7C are formed, for example, in the pattern shown in FIG. That is, the anode electrode 7A is divided into two parts with a slit having a distance LSA, and the cathode electrode 7C is similarly divided into two parts with a slit having a distance LSC. The photodiodes are formed so as to be opposed to each other with a central region therebetween.
The slit SL is preferably provided at an interval that opens 50% or more of the region sandwiched between the first wiring conductive layers 21 (the anode electrode 7A and the cathode electrode 7C).
[0060]
Next, on the first wiring conductive layer 21 (the anode electrode 7A and the cathode electrode 7C), a silicon oxide film having a thickness of 0.5 μm is formed on the entire surface by a CVD method using, for example, TEOS (tetraethylorthosilicate) as a raw material. A first insulating layer 31 is formed by deposition.
At this time, a step portion 31 </ b> A is generated on the surface of the first insulating layer 31 due to the formation of the first wiring conductive layer 21 in the lower layer.
[0061]
Next, for example, by spin coating, an inorganic SOG (Spin on Glass) or the like is applied with a film thickness to fill the step portion 31A, and the inorganic second insulating layer 32 so as to flatten the step portion 31A. Form.
In this step, the slit SL is provided in spite of the fact that the so-called dam by the first wiring conductive layer 21 composed of the anode electrode 7A and the cathode electrode 7C is disposed on both sides of the photodiode PD region. Thus, it is possible to reduce the degree of uneven thickness of the applied second insulating layer 32 without hindering the casting of the inorganic second insulating layer.
[0062]
Next, as shown in FIG. 4, the entire surface of the inorganic second insulating layer 32 made of inorganic SOG is etched back. As a result, the second insulating layer 32 on the side surface portion of the step portion 31A formed on the surface of the first insulating layer 31 is left, and the steep step 31A is relaxed, that is, flattened.
[0063]
Next, on the surface flattened by the second insulating layer 32, silicon oxide is deposited on the entire surface by, for example, a plasma CVD method using TEOS as a raw material to form a third insulating layer 33. Thus, the interlayer insulating layer 30 composed of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 is formed.
Next, a resist film (not shown) is patterned by a photolithography process, and etching such as RIE is performed, so that the interlayer insulating layer 30 (specifically, the first insulating layer 31 and the third insulating layer 33 are formed). A contact window 30W that penetrates through the formed portion) and reaches the first wiring conductive layer 21, and is embedded in the contact window 30W by, for example, vapor deposition or sputtering to cover the entire surface with a conductive material such as Al. The anode electrode 7A and the cathode electrode 7C separated by the slit SL are electrically connected to each other through a predetermined window, that is, a contact window 30W formed in the interlayer insulating layer 30 by a photolithography process. The second wiring conductive layer 22 connected to the first wiring conductive layer 21 is processed into a pattern including the portion 22S to form the third wiring Forming a predetermined pattern on the upper edge layer 33.
As described above, the semiconductor device of this embodiment shown in FIGS. 1 and 2 can be manufactured.
[0064]
According to the manufacturing method of the semiconductor device according to the present embodiment, since the slit is formed in the first wiring conductive layer, the insulating layer is cast in the step of applying the inorganic insulating layer and performing the planarization process. It is possible to reduce the degree of unevenness in the thickness of the applied insulating layer without hindering the above.
[0065]
In the semiconductor device manufacturing method according to the present embodiment, the slits SL are provided in the first wiring conductive layer 21. The patterning of the slits SL is performed simultaneously with the patterning of the first wiring conductive layer 21. In addition, since the connecting portion 22S for electrically connecting the slits SL can be formed in the same process as the conventional process for forming the second wiring conductive layer, the number of processes is different from that of the conventional method. Can be implemented without increasing
[0066]
(Example)
In the method of manufacturing a semiconductor device according to the above-described embodiment, a method is usually employed in which a plurality of semiconductor chip equivalent circuits are formed on one semiconductor wafer and divided into individual semiconductor chips by a dicing process. However, a rectangular ring-shaped first wiring conductive layer pattern (short side 30 μm, long side 90 μm) is formed on the central portion of the semiconductor wafer 41 shown in FIG. Sample 1 in which SOG was applied by spin coating and etched back on the entire surface was prepared, and the thickness of the SOG film was measured. The measurement is performed using P in each first wiring conductive layer pattern.₁ , P₂ , And P_Three I went in three places.
In addition, the above-described rectangular ring-shaped first wiring conductive layer 21 has a slit (SL) size and an L / S ratio shown in Table 1 (with respect to a region surrounded or sandwiched by the first wiring conductive layer). Samples 2 to 4 provided with slits having a predetermined pattern such as the ratio of opening were prepared, and the thickness of the SOG film was measured in the same manner as described above.
The results are shown in Table 1.
[0067]
[Table 1]

[0068]
From Table 1, by providing slits in the first wiring conductive layer 21, uneven thickness of the SOG film is suppressed, and in particular, the L / S ratio of the first wiring conductive layer is set to 50%, more preferably 33%. At times, it was confirmed that the thickness unevenness was significantly suppressed.
[0069]
Second embodiment
The semiconductor device according to the present embodiment is a photodiode IC, FIG. 7A is a plan view of a photodiode portion that is a main part of the photodiode IC according to the present embodiment, and FIG. It is sectional drawing in AA 'in Fig.7 (a).
As in the first embodiment, in the formation region of the photodiode PD, the silicon semiconductor substrate 1 includes, for example, a first p-type semiconductor layer 2 containing a high concentration of p-type impurities and a low concentration of p-type impurities. A 2p-type semiconductor layer (anode layer) 3 is formed, and an n-type semiconductor layer (cathode layer) 4 containing n-type impurities at a high concentration is formed in a surface layer region of the second p-type semiconductor layer 3. A type photodiode is formed.
In addition, in the outer peripheral region of the photodiode PD, a p-type impurity containing a high concentration of p-type impurities deeper than the n-type semiconductor layer 4 is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A 3p type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0070]
A surface insulating layer 6 made of, for example, silicon oxide is formed on the surface of the silicon semiconductor substrate 1 on which the PIN photodiode is formed, and a contact window reaching the third p-type semiconductor layer 5 is formed.
A lower conductive layer 20 that is buried in the contact window and is in ohmic contact with the third p-type semiconductor layer 5 is formed.
The lower conductive layer 20 is preferably 200 nm or less, for example, about 100 nm in thickness, and is made of polysilicon having a sheet resistance of about 80Ω / □.
The contact window reaching the third p-type semiconductor layer 5 formed in the surface insulating layer 6 is perforated in a continuous pattern surrounding the region of the n-type semiconductor layer 4 serving as the light receiving region of the photodiode PD. The lower conductive layer 20 is also formed in a continuous dam pattern surrounding the region of the n-type semiconductor layer 4.
[0071]
A first insulating layer 31 made of, for example, silicon oxide is formed on the lower conductive layer 20, and a contact window 31 </ b> W reaching the lower conductive layer 20 is formed.
A first wiring conductive layer 21 embedded in the contact window 31W and making ohmic contact with the lower conductive layer 20 is formed with a film thickness of 800 nm or more.
The first wiring conductive layer 21 is made of, for example, aluminum or an alloy thereof.
The cross-sectional view of FIG. 7B is not a cross-section at a position crossing the formation region of the first wiring conductive layer 21, and therefore the first wiring conductive layer 21 is not drawn on the drawing.
[0072]
As the pattern of the first wiring conductive layer 21, slits SL having a distance LSA, for example, are formed in the pattern surrounding the photodiode PD region. The slit SL is preferably provided at an interval that opens 50% or more of the region surrounded by the first wiring conductive layer 21.
[0073]
In the above configuration, it is preferable that the first wiring conductive layer is a conductor layer that constitutes an electrode for the light receiving element, and further, the first wiring conductive layer is on the ground (ground) side of the light receiving element. The conductive layer that constitutes the electrode, and the second wiring conductive layer is preferably used as a light shielding body that partitions the light receiving surface of the light receiving element and is connected to the ground.
[0074]
A second insulating layer 32 made of, for example, silicon oxide is formed on the upper layer of the first wiring conductive layer 21, and a step portion (not shown) generated on the surface of the second insulating layer 32 is formed on the side surface of the step. An inorganic or organic third insulating layer made of inorganic or organic SOG (Spin on Glass) or the like is formed so as to flatten the stepped portion.
The third insulating layer is etched back over the entire surface, and is only left on the side surface of the step (not shown) generated on the surface of the second insulating layer 32 due to the first wiring conductive layer 21. However, since the cross-sectional view of FIG. 7B is not a cross-section at the position crossing the step formation region generated on the surface of the second insulating layer 32, the third insulating layer is drawn on the drawing. Not.
Further, a fourth insulating layer 34 made of, for example, silicon oxide is formed on the entire upper layer.
The second insulating layer 32, the third insulating layer 33, and the fourth insulating layer 34 constitute an interlayer insulating layer 30.
[0075]
A contact window reaching the first wiring conductive layer 21 is formed through the interlayer insulating layer 30 (specifically, the portion where the first insulating layer 31 and the third insulating layer 33 are formed). The first wiring conductive layers 20 embedded in the contact window and in a predetermined pattern on the fourth insulating layer 34, that is, separated by the slit SL, are electrically connected to each other. A second wiring conductive layer 22 connected to the wiring conductive layer 21 is formed.
As described above, the anode electrode E connected from the lower conductive layer 20, the first wiring conductive layer 21, and the second wiring conductive layer 22 to the third p-type semiconductor layer 5 of the PIN photodiode._A Is formed.
[0076]
In addition, a contact window reaching the n-type semiconductor layer 4 of the PIN photodiode is formed, and the cathode electrode E is in ohmic contact with the n-type semiconductor layer 4._CIs formed.
[0077]
In the semiconductor device of the present embodiment described above, slits are formed in the first wiring conductive layer with respect to the region surrounded by the first wiring conductive layer 21 at intervals that open the region, for example, by 50% or more. The space is electrically connected by the second wiring conductive layer, and is also electrically connected by the lower conductive layer formed below the first wiring conductive layer. Yes.
Therefore, according to the above-described semiconductor device of the present embodiment, in the step of performing the planarization process by applying the inorganic or organic third insulating layer such as the inorganic or organic SOG film in the manufacturing process. Even though a so-called dam by the first wiring conductive layer 21 surrounding the photodiode PD region is arranged, the above-described slit SL is provided, so that this inorganic or organic third layer is provided. It is possible to reduce the degree of unevenness of the thickness of the applied insulating layer without hindering the casting of the insulating layer.
In the above, since the first conductive layer is formed as thin as about 100 nm with respect to 800 nm of the first wiring conductive layer, the function as a dam is low and does not hinder the casting of the third insulating layer.
[0078]
A method for manufacturing the semiconductor device of the present embodiment will be described.
First, as shown in FIG. 8A, in the formation region of the photodiode PD, the first p-type semiconductor layer 2 and the p-type semiconductor layer 2 containing a high concentration of p-type impurities, for example, by ion implantation into the silicon semiconductor substrate 1. A second p-type semiconductor layer (anode layer) 3 containing a low concentration of type impurities is formed, and an n-type semiconductor layer (cathode layer) 4 containing a high concentration of n-type impurities in the surface layer region of the second p-type semiconductor layer 3 is formed. To form a PIN type photodiode.
Further, in the outer peripheral region of the photodiode PD, p-type impurities are introduced deeper than the n-type semiconductor layer 4 by ion implantation or the like, and the third p is connected to the first p-type semiconductor layer 2 and the second p-type semiconductor layer 3. A type semiconductor layer 5 is formed to isolate the photodiode PD region.
[0079]
Next, the surface insulating layer 6 is formed by depositing silicon oxide with a film thickness of 0.5 μm on the surface of the silicon semiconductor substrate 1 on which the above-described PIN type photodiode is formed by, for example, CVD (Chemical Vapor Deposition). To do.
Next, a resist film (not shown) having a pattern that opens the third p-type semiconductor layer 5 region is formed on the surface insulating layer 6 by photolithography, and etching such as RIE (reactive ion etching) is performed. A contact window reaching the third p-type semiconductor layer 5 is formed.
Next, for example, by CVD, polysilicon is deposited on the entire surface by filling the inside of the contact window, preferably with a film thickness of 200 nm or less, for example, 100 nm. The sheet resistance of this polysilicon is, for example, about 80Ω / □.
Next, the polysilicon film is patterned to form the lower conductive layer 20.
Here, the contact window reaching the third p-type semiconductor layer 5 formed in the surface insulating layer 6 is drilled in a continuous pattern surrounding the region of the n-type semiconductor layer 4 serving as the light receiving region of the photodiode PD. The lower conductive layer 20 is also formed in a continuous dam pattern surrounding the region of the n-type semiconductor layer 4.
[0080]
Next, as shown in FIG. 8B, the first insulating layer 31 is formed by covering the lower conductive layer 20 and depositing silicon oxide on the entire surface by, for example, the CVD method.
Next, a resist film (not shown) having a pattern opening the lower conductive layer 20 region is formed on the first insulating layer 31 by photolithography, and etching such as RIE (reactive ion etching) is performed. A contact window (not shown) reaching the lower conductive layer 20 is formed.
Next, the contact window is buried, for example, by sputtering, and aluminum or an alloy thereof is deposited on the entire surface to a thickness of, for example, 800 nm or more, and patterned to form a first wiring conductive layer (not shown).
Here, as shown in FIG. 7, the first wiring conductive layer 21 is formed so as to be divided by slits having a distance LSA.
The slit SL is preferably provided at an interval that opens 50% or more of the region surrounded by the first wiring conductive layer 21.
The cross-sectional view of FIG. 8B is not a cross-section at a position crossing the formation region of the first wiring conductive layer 21, and therefore the first wiring conductive layer 21 is not drawn on the drawing.
[0081]
Next, as shown in FIG. 8C, a silicon oxide film having a thickness of 0.5 μm is formed on the entire surface of the first wiring conductive layer 21 by CVD using, for example, TEOS (tetraethylorthosilicate) as a raw material. To form a second insulating layer 32.
At this time, due to the formation of the first wiring conductive layer 21 in the lower layer, a part of the step is generated on the surface of the second insulating layer 32, but the cross section of FIG. Since the figure is not a cross section at a position crossing the step forming region generated on the surface of the second insulating layer 32, the step is not drawn on the drawing.
[0082]
Next, as shown in FIG. 9D, for example, by spin coating, an inorganic or organic SOG (Spin on Glass) or the like is applied with a film thickness to fill the step portion, and the step portion is flattened. As described above, the inorganic or organic third insulating layer 33 is formed.
In this process, according to the spin coating method, the coating film is cast in the wafer outward direction (for example, F direction on the drawing) by centrifugal force. However, the so-called dam by the first wiring conductive layer 21 surrounds the photodiode PD region. The third insulating layer is applied without hindering the casting of the inorganic or organic third insulating layer by providing the slit SL despite the fact that the slit SL is provided. It is possible to reduce the thickness unevenness of 33.
[0083]
Next, as shown in FIG. 9E, the entire surface of the inorganic or organic third insulating layer 33 made of inorganic or organic SOG is etched back. As a result, the third insulating layer 33 on the side surface portion of the step portion formed on the surface of the second insulating layer 32 is left, and a steep step is relaxed, that is, flattened.
In the cross section that does not cross the step forming region generated on the surface of the second insulating layer 32 as shown in the cross-sectional view of FIG. 9E, the third insulating layer 33 is completely removed by the etch back. Will be.
[0084]
Next, as shown in FIG. 9F, silicon oxide is deposited on the entire surface by the plasma CVD method using TEOS as a raw material, for example, on the surface flattened by the etch back, thereby forming a fourth insulating layer 34. To do. As described above, the interlayer insulating layer 30 including the second insulating layer 32, the third insulating layer 33, and the fourth insulating layer 34 is formed.
Next, a resist film (not shown) is patterned by a photolithography process, and etching such as RIE is performed, so that the interlayer insulating layer 30 (specifically, the second insulating layer 32 and the fourth insulating layer 34 are formed). A contact window reaching the first wiring conductive layer (not shown) through the formed portion), and further embedded with a conductive material such as Al by vapor deposition or sputtering, for example. Deposited on the entire surface and processed into a predetermined pattern by a photolithography process, that is, a pattern for electrically connecting the first wiring conductive layers separated by the slit SL through a contact window drilled in the interlayer insulating layer 30 Then, the second wiring conductive layer 22 connected to the first wiring conductive layer 21 is formed on the fourth insulating layer 34 with a predetermined pattern.
Thus, the semiconductor device of this embodiment shown in FIG. 7 can be manufactured.
[0085]
According to the method for manufacturing a semiconductor device according to the present embodiment, since the slit is formed in the first wiring conductive layer, in the step of applying the inorganic or organic third insulating layer and performing the planarization process, It is possible to reduce the degree of uneven thickness of the applied insulating layer without hindering the casting of the insulating layer.
In the above, since the first conductive layer is formed as thin as about 100 nm with respect to 800 nm of the first wiring conductive layer, the function as a dam is low and does not hinder the casting of the third insulating layer.
[0086]
In the semiconductor device manufacturing method according to the present embodiment, the slits SL are provided in the first wiring conductive layer 21. The patterning of the slits SL is performed simultaneously with the patterning of the first wiring conductive layer 21. In addition, since the connecting portion for electrically connecting the slits SL can be formed in the same process as the conventional process for forming the second wiring conductive layer, the number of processes is less than that of the conventional method. It can be implemented without increasing.
[0087]
The semiconductor device having the photodiode according to the above-described embodiment can be used as a light receiving element mounted on, for example, a CD or DVD optical disk device, or other light receiving element.
[0088]
The present invention is not limited to the above embodiment.
For example, in the above embodiment, the p-type impurity and the n-type impurity are interchanged, that is, n^- The present invention can be applied to a PIN photodiode having a p-type semiconductor region in the surface layer portion of the type semiconductor region.
In addition, the wavelength of light received by the photodiode is not particularly limited, such as blue light in a band of 780 nm to 650 nm and 400 nm.
Further, the present invention is applicable not only to PIN photodiodes but also to photodiodes in general.
In addition, various changes can be made without departing from the scope of the present invention.
[0089]
【The invention's effect】
In the semiconductor device of the present invention, since the slit is formed in the first wiring conductive layer, this insulation is performed in the step of applying an insulating layer such as inorganic or organic in the manufacturing process and performing the planarization process. It is possible to reduce the degree of uneven thickness of the applied insulating layer without hindering the casting of the layer.
[0090]
In the method of manufacturing a semiconductor device according to the present invention, a slit is formed in the first wiring conductive layer. Therefore, in the step of applying an organic or inorganic insulating layer and performing a planarization process, It is possible to reduce the thickness unevenness of the insulating layer to be applied without hindering casting.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment.
2 is a cross-sectional view taken along line A-A ′ of the semiconductor device shown in FIG. 1;
FIG. 3 is a cross-sectional view showing a manufacturing process of the manufacturing method of the semiconductor device shown in FIG. 1, showing a process up to a second insulating layer coating process;
4 is a cross-sectional view showing a continuation process of FIG. 3 and showing a process up to an etch-back process of a second insulating layer. FIG.
FIG. 5 is a plan view showing a pattern of a first wiring conductive layer of the semiconductor device according to the first embodiment.
FIG. 6 is a plan view showing a pattern of a first wiring conductive layer formed on a semiconductor wafer in an example.
7A is a plan view of a semiconductor device according to a second embodiment, and FIG. 7B is a cross-sectional view taken along line A-A ′ in FIG. 7A.
8 is a cross-sectional view showing a manufacturing process of the manufacturing method of the semiconductor device shown in FIG. 7, wherein (a) shows the first conductive layer forming process, and (b) shows the first wiring conductive layer; (C) shows up to the formation process of the second insulating layer.
9 is a cross-sectional view showing a continuation process of FIG. 8, wherein (d) is a process up to a third insulating layer forming process, (e) is a process up to an etch back process of a third insulating layer; f) shows up to the step of forming the fourth insulating layer.
FIG. 10 is a cross-sectional view showing a process up to forming a second insulating layer in the first conventional example.
FIG. 11 is a cross-sectional view showing a process up to etching back a second insulating layer in the first conventional example.
FIG. 12 is a cross-sectional view showing a process until a third insulating layer is formed in the first conventional example.
FIG. 13 is a plan view of a semiconductor device according to a first conventional example.
14A is a plan view of a semiconductor device according to a second conventional example, and FIG. 14B is a cross-sectional view taken along line A-A ′ in FIG. 14A.
15 is a cross-sectional view showing a manufacturing process of the manufacturing method of the semiconductor device shown in FIG. 14, wherein (a) shows a process up to the formation of the second insulating layer, and (b) shows a process of the third insulating layer; Up to the forming process, (c) shows the process up to the etch back process of the third insulating layer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... 1st p-type semiconductor layer, 3 ... 2nd p-type semiconductor layer (anode layer), 4 ... n-type semiconductor layer (cathode layer), 5 ... 3rd p-type semiconductor layer, 6 ... Surface insulating layer, 6WA, 6WC ... contact window, 7A anode electrode, 7C ... cathode electrode, 20 ... first conductive layer, 21 ... first wiring conductive layer, 22 ... second wiring conductive layer, 22S ... connecting portion, 30 ... interlayer Insulating layer, 30W ... contact window, 31 ... first insulating layer, 31A, 32A ... step, 31W ... contact window, 32 ... second insulating layer, 33 ... third insulating layer, 34 ... fourth insulation Layer, 41 ... wafer, 101 ... semiconductor substrate, 102 ... insulating layer, 103 ... first wiring conductive layer, 104 ... first insulating layer, 105 ... organic insulating layer, 106 ... step, 107 ... second Insulating layer, 108 ... interlayer insulating layer, SL ... slit, PD ... photo Diode, E_A ... Anode electrode, E_C ... Cathode electrode.

Claims (11)

A first conductive layer formed on the semiconductor substrate;
A first insulating layer formed over the first conductive layer;
A first wiring conductive layer formed on the first insulating layer;
A second insulating layer formed over the first wiring conductive layer;
An organic or inorganic third insulation formed on the second insulating layer by coating so as to flatten the stepped portion on the side surface of the stepped portion generated on the surface of the second insulating layer. Layers,
A fourth insulating layer formed on the third insulating layer, and a second wiring conductive layer formed on the fourth insulating layer,
It said first slit is formed in the wiring conductive layer, between the slits, by both the upper Symbol first conductive layer and the second wiring conductor layer, a semi-thin body devices that are electrically connected. The semiconductor device according to claim 1 , wherein the third insulating layer is an organic or inorganic SOG film. The slits of the first wiring conductive layer, the relative enclosing or a region sandwiched by the first wiring conductive layer, the semiconductor device according to claim 1, wherein an interval for opening the region of at least 50% or more. The semiconductor device according to claim 1 , wherein the first conductive layer and the first wiring conductive layer are conductive layers constituting electrodes for the light receiving element. The first conductive layer and the first wiring conductive layer are conductive layers constituting an electrode on the ground (ground) side of the light receiving element, and the second wiring conductive layer is a light receiving surface of the light receiving element. The semiconductor device according to claim 4 , wherein the semiconductor device is used as a light shielding body for partitioning and connected to a ground. The semiconductor device according to claim 1 , wherein the first wiring conductive layer is connected to the first conductive layer through a first contact hole formed in the first insulating layer. The first wiring conductive layer is connected to the second wiring conductive layer through the second, third and fourth insulating layers or the second contact hole formed in the second and fourth insulating layers. The semiconductor device according to claim 1 , wherein the semiconductor device is connected to the layer. The semiconductor device according to claim 1 , wherein the first conductive layer has a thickness of 200 nm or less, and the first wiring conductive layer has a thickness of 800 nm or more. Forming a first conductive layer on a semiconductor substrate;
Forming a first insulating layer on the first conductive layer;
Forming a first wiring conductive layer having a slit on the first insulating layer;
Forming a second insulating layer over the entire surface of the first wiring conductive layer;
The surface of the second insulating layer, the third insulating layer of an organic or inorganic formed by coating, planarizing the surface of the second insulating layer,
Forming a fourth insulating layer on the entire surface;
Forming a second wiring conductive layer on at least the interlayer insulating layer of the second and fourth insulating layers, and
Forming the first conductive layer and the second wiring conductive layer so as to straddle the slits of the first wiring conductive layer, and a first contact hole formed in the first insulating layer; The first wiring conductive layers separated by the slits are mutually connected through the second, third and fourth insulating layers or the second contact holes formed in the second and fourth insulating layers. A method for manufacturing a semiconductor device, wherein a connection wiring portion connected to a semiconductor device is formed. The method of manufacturing a semiconductor device according to claim 9 , wherein the slit of the first wiring conductive layer opens at least 50% or more around the region surrounded or sandwiched by the wiring layer. The method for manufacturing a semiconductor device according to claim 9 , wherein the first conductive layer and the first wiring conductive layer are conductive layers constituting electrodes for the light receiving element.

Images