JP4635612B2 - Sample and hold circuit - Google Patents

Description

  The present invention relates to a sample and hold circuit that samples and holds a voltage of an input signal.

  The sampling and holding circuit is a circuit widely used for sampling and holding an analog signal at a desired timing, such as an A / D converter, a signal transfer circuit of an imaging device, and a peak detector.

FIG. 6 is a diagram showing an example of a general configuration of the sampling and holding circuit.
The sampling and holding circuit shown in FIG. 6 includes n-channel MOS transistors Q1, Q2, and Q3, a capacitor C1, and an operational amplifier OPA.

Transistors Q1 and Q2 are connected in series between an input terminal Tin for inputting a signal to be sampled and a positive input terminal of the operational amplifier OPA.
A capacitor C1 for sampling the voltage of the input signal is connected between the connection point of the transistors Q1 and Q2 and the supply line of the reference voltage VREF. A transistor Q3 is connected between the positive input terminal of the operational amplifier OPA and the reference voltage VREF.
The output of the operational amplifier OPA is connected to its negative input terminal and to the output terminal Tout for outputting the sampled signal voltage.

  The operational amplifier OPA having a configuration in which the output signal is fed back to the negative input terminal functions as a non-inverting voltage amplifier having a gain of 1 ×, that is, a voltage buffer circuit. When a voltage is input to the positive input terminal, a voltage substantially equal to this is output from the operational amplifier OPA.

  FIG. 7 is a signal waveform diagram for explaining the operation of the sampling and holding circuit shown in FIG.

  In the period for sampling the input signal, as shown in FIGS. 7A and 7B, the gate voltage Vg1 of the transistors Q1 and Q3 is set to the high level, and the gate voltage Vg2 of the transistor Q2 is set to the low level. . Thereby, the transistors Q1 and Q3 are turned on, and the transistor Q2 is turned off.

  When the transistor Q1 is turned on during the sampling period, the voltage VIN of the input signal from the input terminal Tin is applied to the capacitor C1. Further, when the transistor Q3 is turned on during this period, the reference voltage VREF is input to the positive input terminal of the operational amplifier OPA. As a result, the output voltage VOUT of the operational amplifier OPA becomes substantially equal to the reference voltage VREF.

  When the sampling period ends, the gate voltage Vg1 changes to a low level, and the transistors Q1 and Q3 are turned off. When the transistor Q1 is turned off, the voltage VIN of the input signal at the time of turning off is held in the capacitor C1.

  Next, when a transition is made to a holding period for holding an input signal, the gate voltage Vg2 is set to a high level. Thereby, the transistor Q2 is turned on, and the capacitor C1 is connected to the positive input terminal of the operational amplifier OPA via the transistor Q2. Since the input impedance of the operational amplifier OPA is very large, the current flowing through the transistor Q2 is very small, and there is almost no voltage drop due to the transistor Q2. Further, even after connection to the positive input terminal, the voltage of the capacitor C1 is held substantially constant. Therefore, a voltage obtained by adding the holding voltage of the capacitor C1 to the reference voltage VREF is input to the positive input terminal of the operational amplifier OPA, and a voltage substantially equal to this is output from the operational amplifier OPA.

JP 2002-305448 A

By the way, in general, a voltage-type operational amplifier can be regarded as a differential amplifier that amplifies and outputs a voltage difference between a positive input terminal and a negative input terminal with a very high gain. In an ideal differential amplifier, if the voltage difference between the positive input terminal and the negative input terminal is zero, its output voltage should also be zero, but it is not usually zero in the circuit that is actually manufactured. . This is mainly because the positive input circuit system and the negative input circuit system do not operate completely symmetrically due to variations in transistor characteristics.
Such an unbalanced state of the circuit operation is equivalent to a state where a signal is input from the outside to the input terminal of an ideal differential amplifier via a pseudo voltage source.
A voltage artificially added to the original input voltage by this voltage source is generally called an offset voltage.

  Even in a buffer circuit configured by feeding back the output voltage VOUT of the operational amplifier OPA to its negative input terminal, an error due to this offset voltage occurs in an actual circuit. Even if the gain of the operational amplifier OPA is extremely large and the voltage obtained by dividing the output voltage VOUT by this gain can be regarded as almost zero, there is a fixed offset between the negative input terminal and the positive input terminal of the operational amplifier OPA. A voltage VOFST is generated.

  The voltage Vc1 charged in the capacitor C1 during the sampling period is expressed by the following equation.

  Vc1 = VIN−VREF (1)

  On the other hand, the voltage VOUT output from the operational amplifier OPA during the holding period is approximately expressed by the following equation.

VOUT = Vc1 + VREF + VOFST
= VIN + VOFST (2)

  As shown in Equation (2), the output voltage VOUT of the sample and hold circuit shown in FIG. 6 is obtained by adding the offset voltage VOFST to the voltage VIN of the original sampled input signal. This offset voltage is generally several mV to several tens of mV, varies from individual to individual, and varies with temperature. Therefore, when the sampling result requires accuracy, an error due to this offset voltage becomes a problem.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a sample-and-hold circuit capable of reducing an error in a sampling result.

In order to achieve the above object, a sample and hold circuit according to the present invention includes a capacitor, a buffer circuit that outputs a voltage obtained by adding an offset voltage to an input voltage, an input terminal for inputting a signal to be sampled, the first operation mode smell of the signal voltage input to the upper entry input terminal is applied to the capacitor Te, the first following the operation mode the second operation mode voltages above buffers held on SL capacitor Te smell as input to the circuit, the Capacity data, have a switch circuit for setting a connection state of the buffer circuits and the input terminal, the switch circuit, the first terminal and the buffer circuit of the capacitor A first switch connected between the output and turned on in the first operation mode and turned off in the second operation mode; A second switch connected between the second terminal of the capacitor and the input terminal and turned on in the first operation mode and turned off in the second operation mode; an input of the buffer circuit; and a predetermined reference A third switch connected between the voltage supply line and turned on in the first operation mode and turned off in the second operation mode; a second terminal of the capacitor; and an input of the buffer circuit Connected between the fourth switch which is turned off in the first operation mode and turned on in the second operation mode, and connected between the first terminal of the capacitor and the reference voltage supply line, A fifth switch that is turned off in the first operation mode and turned on in the second operation mode, and is input to the input terminal in the first operation mode. A first voltage obtained by subtracting the output voltage of the buffer circuit from the signal voltage is applied to the capacitor, the predetermined reference voltage is input to the buffer circuit, and held in the capacitor in the second operation mode. A voltage obtained by adding the first voltage and the reference voltage is input to the buffer circuit.

  According to the present invention, in the first operation mode, a voltage obtained by subtracting the offset voltage from the signal voltage input to the input terminal is applied to the capacitor. In the second operation mode, a voltage held in the capacitor is input to the buffer circuit. Therefore, in the second operation mode, a voltage obtained by adding the offset voltage to the voltage held in the capacitor is output from the buffer circuit. At this time, since the capacitor holds the voltage obtained by subtracting the offset voltage from the signal voltage input to the input terminal, the voltage obtained by adding the offset voltage to the capacitor is the first operation mode. The signal voltage input to the input terminal in FIG. Therefore, the voltage output from the buffer circuit in the second operation mode is substantially equal to the signal voltage input to the input terminal in the first operation mode.

The good suitable, the switch circuit in the first operation mode, and connects the output of the first terminal and the buffer circuit of the capacitor, connects the second terminal and the input terminal of the capacitor, connecting the supply line of the input and the predetermined reference voltage of the buffer circuit, it said in the second mode of operation, to connect the input of the second terminal and the buffer circuit of the capacitor, the first terminal of the capacitor And a reference voltage supply line may be connected .

Preferably, when shifting from the first operation mode to the second operation mode, the third switch changes from on to off after at least one of the first switch and the second switch. May be.

  According to the present invention, the error of the sampling result due to the offset voltage can be reduced by subtracting the offset voltage of the buffer circuit from the voltage of the input signal and holding it in the capacitor.

  Hereinafter, two embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of a sample and hold circuit according to the first embodiment of the present invention.
The sample and hold circuit shown in FIG. 1 has a capacitor 1, a buffer circuit 2, a switch circuit 3, an input terminal Tin, and an output terminal Tout.
The capacitor 1 is an embodiment of the capacitor of the present invention.
The buffer circuit 2 is an embodiment of the buffer circuit of the present invention.
The switch circuit 3 is an embodiment of the switch circuit of the present invention.
The input terminal Tin is an embodiment of the input terminal of the present invention.

The input terminal Tin is a terminal for inputting a signal to be sampled, and is connected to the switch circuit 3. In FIG. 1, the voltage input to the input terminal Tin is represented by the symbol “VIN”.
The output terminal Tout is a terminal for outputting a sampled signal, and is connected to the output of the buffer circuit 2. In FIG. 1, the voltage output from the output terminal Tout is represented by the symbol “VOUT”.

  The buffer circuit 2 is a circuit that outputs a voltage obtained by adding the offset voltage VOFST to the input voltage. Since the input impedance is high and the output impedance is low, it operates as an impedance conversion circuit.

  The switch circuit 3 sets the connection state among the capacitor 1, the buffer circuit 2, and the input terminal Tin according to the operation mode (first operation mode, second operation mode).

(First operation mode)
The first operation mode is a mode for sampling a signal input from the input terminal Tin.
In the first operation mode, the switch circuit 3 includes the capacitor 1 and the buffer circuit so that a voltage obtained by subtracting the offset voltage VOFST of the buffer circuit 2 from the signal voltage VIN input to the input terminal Tin is applied to the capacitor 1. 2 and the input terminal Tin are set.

For example, in the first operation mode, the switch circuit 3 applies a voltage VSMP obtained by subtracting the output voltage VOUT of the buffer circuit 2 from the signal voltage VIN input to the input terminal Tin, and applies the reference voltage VREF to the buffer. The above connection state is set so as to be input to the circuit 2.
In this case, the switch circuit 3 connects the first terminal T1 of the capacitor 1 and the output of the buffer circuit 2, connects the second terminal T2 of the capacitor 1 and the input terminal Tin, and inputs the buffer circuit 2 and the reference voltage. A VREF supply line may be connected.

(Second operation mode)
The second operation mode is a mode for holding the input signal sampled in the first operation mode and outputting the signal voltage from the output terminal Tout.
In the second operation mode, the switch circuit 3 sets the above connection state so that the voltage VSMP held in the capacitor 1 is input to the buffer circuit 2.

For example, the switch circuit 3 sets the above connection state so that a voltage obtained by adding the voltage VSMP held in the capacitor 1 and the reference voltage VREF is input to the buffer circuit 2 in the second operation mode. .
In this case, the switch circuit 3 may connect the second terminal T2 of the capacitor 1 and the input of the buffer circuit 2, and connect the first terminal T1 of the capacitor 1 and the supply line of the reference voltage VREF.

  The operation of the sample and hold circuit according to this embodiment having the above-described configuration will be described.

In the first operation mode, a voltage obtained by subtracting the offset voltage VOFST of the buffer circuit 2 from the signal voltage VIN input to the input terminal Tin is applied to the capacitor C1.
In the second operation mode following the first operation mode, the voltage VSMP held in the capacitor 1 is input to the buffer circuit 2. Thereby, the output voltage of the buffer circuit 2 is a voltage obtained by adding the offset voltage VOFST to the voltage VSMP held in the capacitor 1. At this time, since the voltage VSMP held in the capacitor is a voltage obtained by subtracting the offset voltage VOFST from the signal voltage VIN, a voltage obtained by adding the offset voltage VOFST to the signal voltage VIN is substantially equal to the signal voltage VIN.

For example, in the first operation mode, a voltage 'VIN-VOUT' obtained by subtracting the output voltage VOUT from the signal voltage VIN is applied to the capacitor 1. On the other hand, the buffer circuit 2 receives the reference voltage VREF, and the buffer circuit 2 outputs the voltage “VREF + VOFST”. As a result, the voltage 'VIN-VREF-VOFST' is applied to the capacitor C1 as the voltage VSMP.
In the second operation mode following the first operation mode, the buffer circuit 2 receives a voltage 'VSMP + VREF' obtained by adding the voltage VSMP held in the capacitor 1 and the reference voltage VREF. At this time, since the voltage 'VIN-VREF-VOFST' is held as the voltage VSMP in the capacitor 1, the voltage 'VIN-VOFST' is input to the buffer circuit 2. Therefore, the output voltage VOUT of the buffer circuit 2 is approximately equal to the voltage “VIN−VOFST” plus the offset voltage VOFST, that is, the voltage VIN of the sampled signal.

As described above, according to the sample and hold circuit according to the present embodiment, in the first operation mode, the voltage obtained by subtracting the offset voltage VOFST from the voltage VIN of the input signal at the input terminal Tin is applied to the capacitor 1. In the second operation mode following the operation mode, the voltage held in the capacitor C1 is input to the buffer circuit 2. Therefore, in the second operation mode, a voltage obtained by adding the offset voltage VOFST to the voltage VSMP held in the capacitor 1 is output from the buffer circuit 2. At this time, since the capacitor 1 holds a voltage obtained by subtracting the offset voltage VOFST from the voltage VIN of the sampled signal, the voltage obtained by adding the offset voltage VOFST to this is sampled in the first operation mode. It becomes almost equal to the voltage VIN of the signal. Therefore, the voltage VOUT output from the buffer circuit 2 in the second operation mode is substantially equal to the voltage VIN of the signal sampled in the first operation mode.
Therefore, according to the sample and hold circuit according to the present embodiment, a highly accurate sampling result in which an error due to the offset voltage VOFST is reduced can be obtained.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. The second embodiment is a more specific configuration of the switch circuit 3 in the first embodiment.

FIG. 2 is a diagram showing an example of the configuration of the sample and hold circuit according to the second embodiment of the present invention.
The sample and hold circuit shown in FIG. 2 includes a capacitor 1, an operational amplifier OP1, switches SW1,..., SW5, an input terminal Tin, and an output terminal Tout. 1 and 2 indicate the same components.
The buffer circuit composed of the operational amplifier OP1 is an embodiment of the buffer circuit of the present invention.
The switch SW1 is an embodiment of the first switch of the present invention.
The switch SW2 is an embodiment of the second switch of the present invention.
The switch SW3 is an embodiment of the third switch of the present invention.
The switch SW4 is an embodiment of the fourth switch of the present invention.
The switch SW5 is an embodiment of the fifth switch of the present invention.

The operational amplifier OP1 has its output voltage VOUT fed back to the negative input terminal, and constitutes a buffer circuit.
The output of the operational amplifier OP1 generates a voltage VOUT obtained by adding the offset voltage VOFST to the input voltage to the positive input terminal.

  The switch SW1 is connected between the first terminal T1 of the capacitor 1 and the output of the operational amplifier OP1. In response to the input control signal φ1, the signal is turned on in the first operation mode and turned off in the second operation mode.

  The switch SW2 is connected between the second terminal T2 of the capacitor 1 and the input terminal Tin. In response to the input control signal φ1, the signal is turned on in the first operation mode and turned off in the second operation mode.

  The switch SW3 is connected between the positive input terminal of the operational amplifier OP1 and the supply line of the reference voltage VREF. In response to the input control signal φ1, the signal is turned on in the first operation mode and turned off in the second operation mode.

  The switch SW4 is connected between the second terminal T2 of the capacitor 1 and the positive input terminal of the operational amplifier OP1. In response to the input control signal φ2, the signal is turned off in the first operation mode and turned on in the second operation mode.

  The switch SW5 is connected between the first terminal T1 of the capacitor 1 and the supply line of the reference voltage VREF. In response to the input control signal φ2, it is turned off in the first operation mode and turned on in the second operation mode.

  The operation of the sample and hold circuit according to the second embodiment having the above-described configuration will be described with reference to the waveform diagram shown in FIG.

FIG. 3A shows the waveform of the control signal φ1. In the example of this figure, the switches SW1 to SW3 are turned on when the control signal φ1 is at a high level and turned off when it is at a low level.
FIG. 3B shows the waveform of the control signal φ2. In the example of this figure, the switches SW4 and SW5 are turned on when the control signal φ2 is at a high level and turned off when it is at a low level.
FIG. 3C shows waveforms of the voltage VIN input to the input terminal Tin and the voltage VOUT output from the output terminal Tout.

In the first operation mode in which sampling is performed, the switches SW1 to SW3 are set on and the switches SW4 and SW5 are set off. In this case, as shown in the equivalent circuit of FIG. 4, the second terminal T2 and the input terminal Tin of the capacitor 1, the output of the first terminal T1 of the capacitor 1 and the operational amplifier OP1, and the positive input terminal of the operational amplifier OP1 and the reference A supply line for the voltage VREF is connected to each other.
At this time, a voltage VSMP represented by the following equation is applied to the capacitor 1.

  VSMP = VIN−VOUT (3)

  In addition, since the reference voltage VREF is input to the positive input terminal of the operational amplifier OP1, a voltage VOUT represented by the following expression is generated at the output of the operational amplifier OP1.

  VOUT = VREF + VOFST (4)

  Substituting equation (4) into equation (3) yields:

  VSMP = VIN−VREF−VOFST (5)

  As can be seen from comparison with equation (1) of the conventional circuit shown in FIG. 6, the offset voltage VOFST is subtracted in advance from the voltage VSMP applied to the capacitor 1.

Next, in the second operation mode in which the sampling result is held and output, the switches SW1 to SW3 are set off and the switches SW4 and SW5 are set on. In this case, as shown in the equivalent circuit of FIG. 5, the second terminal T2 of the capacitor 1 is connected to the positive input terminal of the operational amplifier, and the first terminal of the capacitor 1 is connected to the supply line of the reference potential VREF.
Since the positive input terminal of the operational amplifier OP1 has a very high impedance, the current flowing through the switches SW4 and SW5 is very small, and the voltage drop due to these switches can be ignored. Further, even after connection to the positive input terminal, the voltage VSMP of the capacitor 1 is held substantially constant. Therefore, in this case, a voltage obtained by adding the holding voltage VSMP of the capacitor 1 to the reference voltage VREF is input to the positive input terminal of the operational amplifier OP1.
In this case, a voltage VOUT expressed by the following equation is generated at the output of the operational amplifier OP1.

VOUT = VSMP + VREF + VOFST
= VIN (6)

  As can be seen from Equation (6), the offset voltage VOFST, which is an error, is canceled from the output voltage VOUT of the operational amplifier OP1, and the output voltage VOUT that is substantially equal to the voltage VIN of the signal sampled in the first operation mode. Is obtained.

  As described above, according to the sample and hold circuit according to the present embodiment, the voltage VOUT output from the operational amplifier OP1 in the second operation mode becomes a voltage obtained by canceling the offset voltage VOFST, and thus the first operation mode. Becomes approximately equal to the voltage VIN of the signal sampled at. Therefore, it is possible to obtain a highly accurate sampling result in which an error due to the offset voltage VOFST is reduced.

  According to the simulation performed by the inventors of the present invention, when the sample-and-hold circuit shown in FIG. 2 is configured using an operational amplifier having an offset voltage of about 16 mV, the error of the voltage VOUT output as the sampling result is 0. It was confirmed that the sampling error can be drastically reduced as compared with the conventional circuit shown in FIG.

In order to configure a sample and hold circuit having the same accuracy as that of the present embodiment by the conventional method shown in FIG. 6, it is necessary to significantly reduce the offset voltage of the operational amplifier OPA. Since the offset voltage of the operational amplifier is mainly caused by variations in transistor size, it is necessary to use a transistor having a considerably large size at the input stage of the operational amplifier in order to reduce the offset voltage.
For example, in order to increase the accuracy up to an error of about 0.6 mV in the sample and hold circuit shown in FIG. 6, it is necessary to increase the transistor size of the input stage of the operational amplifier OPA to several hundred times. Further, when the transistor size of the operational amplifier OPA is increased, the input offset current is increased. Therefore, it is necessary to increase the capacitance of the capacitor C1. In this respect, the circuit area is inevitably increased.
Therefore, according to the sample-and-hold circuit according to the present embodiment, when compared with the same sampling accuracy, there is an excellent effect that the circuit area can be greatly reduced as compared with the conventional sample-and-hold circuit. .

  Further, when the transistor size is increased, there are disadvantages such as an increase in power consumption and a decrease in frequency characteristics. Therefore, the sample and hold circuit according to the present embodiment is also effective in improving these performances.

  As mentioned above, although several embodiment of this invention was described, this invention is not limited only to said form, Various modifications are included.

  The switches (SW1 to SW5) used in the switch circuit may be, for example, n-channel or p-channel MOS transistors, or may be transfer gate switches in which both are connected in parallel. Further, the transistor used for the switch is not limited to the MOS type, and for example, a bipolar type or other transistors may be used. Furthermore, in addition to a switch using a semiconductor element such as a transistor, the switch may be configured using, for example, a mechanical relay.

In the above-described embodiment, the switch groups (SW1, SW2, SW3) that are turned on in the first operation mode and the switch groups (SW4, SW5) that are turned on in the second operation mode are respectively controlled by the common control signals φ1, φ2. However, the present invention is not limited to this.
For example, when shifting from the first operation mode to the second operation mode, these switches may be controlled such that the switch SW3 changes from on to off after at least one of the switches SW1 and SW2.
When the switch SW3 is turned off, the positive input terminal of the operational amplifier OP1 is in a high impedance state, and the potential of the positive input terminal is likely to fluctuate due to the influence of noise or the like. When the potential at the positive input terminal varies, the output voltage VOUT also varies accordingly. Therefore, if both the switches SW1 and SW2 remain on when the switch SW3 is turned off, the holding voltage of the capacitor 1 fluctuates due to the fluctuation of the output voltage VOUT, resulting in an error in the sampling result. Accordingly, it is desirable to control these switches so that at least one of the switches SW1 and SW2 is already turned off when the switch SW3 is turned off.
In addition, the on / off control timing of each switch described above may be appropriately adjusted according to the specific configuration of the applied circuit.

It is a figure which shows the structure of the sample hold circuit based on the 1st Embodiment of this invention. It is a figure which shows an example of a structure of the sample hold circuit based on the 2nd Embodiment of this invention. FIG. 3 is a waveform diagram for explaining the operation of the sample and hold circuit shown in FIG. 2. FIG. 3 is a diagram showing an equivalent circuit in a first operation mode of the sample and hold circuit shown in FIG. 2. FIG. 3 is a diagram showing an equivalent circuit in a second operation mode of the sample and hold circuit shown in FIG. 2. It is a figure which shows an example of the general structure of a sampling hold circuit. It is a figure for demonstrating operation | movement of the sample hold circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Capacitor, 2 ... Buffer circuit, 3 ... Switch circuit, SW1-SW5 ... Switch, OP1 ... Operational amplifier, Tin ... Input terminal, Tout ... Output terminal.

Claims (3)

A capacitor;
A buffer circuit that outputs a voltage obtained by adding an offset voltage to the input voltage; and
An input terminal for inputting a signal to be sampled;
The first operation mode smell of the signal voltage input to the upper entry input terminal is applied to the capacitor Te, the first following the operation mode the second operation mode voltages above buffers held on SL capacitor Te smell as input to the circuit, the Capacity data, and a switch circuit for setting a connection state of the buffer circuits and the input terminal possess,
The switch circuit is
A first switch connected between the first terminal of the capacitor and the output of the buffer circuit, turned on in the first operation mode, and turned off in the second operation mode;
A second switch connected between the second terminal of the capacitor and the input terminal and turned on in the first operation mode and turned off in the second operation mode;
A third switch connected between the input of the buffer circuit and a supply line of a predetermined reference voltage, which is turned on in the first operation mode and turned off in the second operation mode;
A fourth switch connected between the second terminal of the capacitor and the input of the buffer circuit and turned off in the first operation mode and turned on in the second operation mode;
A fifth switch connected between the first terminal of the capacitor and the reference voltage supply line, turned off in the first operation mode, and turned on in the second operation mode;
In the first operation mode, a first voltage obtained by subtracting an output voltage of the buffer circuit from a signal voltage input to the input terminal is applied to the capacitor, and the predetermined reference voltage is input to the buffer circuit. ,
In the second operation mode, a sample and hold circuit in which a voltage obtained by adding the first voltage held in the capacitor and the reference voltage is input to the buffer circuit. The switch circuit is
In the first operation mode, the first terminal of the capacitor and the output of the buffer circuit are connected, the second terminal of the capacitor and the input terminal are connected, the input of the buffer circuit and the predetermined reference Connect the voltage supply line,
2. The sample circuit according to claim 1, wherein, in the second operation mode, the second terminal of the capacitor is connected to an input of the buffer circuit, and the first terminal of the capacitor is connected to the reference voltage supply line. Hold circuit. When the transition from the first operation mode to said second mode of operation, the first aspect or the first switch and the second of said third switch after the at least one switch is changed from on to off 2. The sample and hold circuit according to 2.

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