JP4626349B2 - Hardware configuration device - Google Patents

Description

  The present invention relates to a hardware configuration device, and more particularly to a hardware configuration device that performs programmable hardware configuration.

  In general, programmable hardware is configured by using a dedicated memory or a general ROM. However, in this case, as the capacity of a programmable LSI such as an FPGA increases, the number of memories must be increased or a memory having a larger capacity must be used.

  In addition, there is a method to solve the need for such a large amount of memory, but it may require several configurations or other processing to configure, As a result, there is a new problem that the apparatus becomes complicated.

The following Patent Documents 1 to 5 describe techniques related to FPGA or configuration.
Japanese Unexamined Patent Publication No. 11-220413 (first page, FIG. 1) JP 2004-274727 A (first page, FIG. 1) JP-T 2004-516691 publication (first page, Fig. 1) Japanese Patent Laid-Open No. 2004-326143 (first page, FIG. 1) JP 2001-306343 A (first page, FIG. 1)

  The technique described in Patent Document 1 described above is a technique for more efficiently using a wireless band that changes with time when configuring using wireless communication, and is configured with programmable hardware configuration data ( It is not a method of communicating and configuring circuit arrangement data) using a network.

  The technique described in Patent Document 2 is a technique for updating software, and does not consider hardware configuration or reconfiguration as in the present invention.

  Moreover, although the technique of the above patent document 3 is a technique of the method of updating hardware information, it is not what makes the configuration of programmable hardware using a network like this invention.

  The technique described in Patent Document 4 described above is a technique for initializing a device by configuring programmable hardware several times, and has a problem that configuration cannot be executed in a short time. .

  Further, the technique described in Patent Document 5 described above acquires programmable hardware update information from a network, stores the acquired update information in a memory once, and reads out the memory to perform hardware configuration. . For this reason, a large-capacity memory is required, and further, there is a problem that it takes time and effort to store the entire update information in the memory.

  The present invention has been made in view of the above problems in the prior art, and provides a hardware configuration device capable of executing hardware configuration with a simple configuration and without extra processing. With the goal.

That is, the above-described problems are solved by the inventions listed below.
(1) According to the first aspect of the present invention, a field programmable gate array (FPGA) that is programmable hardware, a configuration control circuit that configures the FPGA, and a configuration that is performed on the FPGA A network unit that receives the circuit arrangement data from an external device via a network, and the configuration control circuit stores the circuit arrangement data received via the network unit in a storage unit for the circuit arrangement data The hardware configuration apparatus is characterized in that the configuration is directly executed on the FPGA while being received by the network unit.

  (2) Claim 2 Field programmable gate array (FPGA) which is programmable hardware, a configuration control circuit for configuring the FPGA, and circuit arrangement data for executing configuration for the FPGA A network unit configured to receive from an external device via a network; and a storage unit, wherein the configuration control circuit directly performs configuration on the FPGA while receiving the circuit arrangement data via the network unit. In parallel with the work to be performed, the circuit configuration data is stored in the storage means.

  (3) The invention described in claim 1 is the hardware configuration device according to (1) or (2), in which the configuration control circuit directly receives the circuit arrangement data from the network unit and performs direct access to the FPGA When configuration is executed, a reception timeout check is performed in parallel with reception.

  (4) In the hardware configuration device according to (1) or (2), the configuration control circuit directly receives the circuit arrangement data from the network unit and transmits it directly to the FPGA. When executing the configuration, a reception timeout check is performed in parallel with the reception, and when the timeout is detected, the reception of the circuit arrangement data is requested.

  (5) The invention described in claim is the hardware configuration device according to any one of (1) to (4), wherein the configuration control circuit is configured by a programmable logic device (PLD).

As described above, according to the present invention described in each claim, the following effects can be obtained.
(1) In the first aspect of the invention, when the configuration of the field programmable gate array (FPGA) which is programmable hardware is executed, the configuration control circuit receives the circuit arrangement data received via the network unit. Without being stored in the storage means for circuit arrangement data, the configuration is directly executed on the FPGA while receiving it at the network unit.

  In this hardware configuration device, configuration is directly executed using circuit arrangement data acquired from the network, so there is no need for a large capacity memory and no extra process, and there is a simple mechanism and procedure. It can be realized in a short time.

  (2) In the invention described in claim 2, when the configuration of the field programmable gate array (FPGA) which is programmable hardware is executed, the configuration control circuit receives the circuit arrangement data via the network unit. The configuration is directly executed for the FPGA while the circuit arrangement data is stored in the storage means in parallel with the execution of the configuration.

  In this hardware configuration device, since configuration is directly executed using circuit arrangement data acquired from a network, no extra process is required, and a simple mechanism and procedure can be realized in a short time. Further, by storing the circuit arrangement data in parallel with the execution of the configuration, it is possible to save the trouble of downloading again even when the configuration needs to be re-executed.

  (3) In the invention described in claim, in the hardware configuration device according to (1) or (2), without storing the circuit arrangement data received via the network unit in the storage means for the circuit arrangement data, When performing configuration directly on the FPGA while receiving at the network unit, the configuration control circuit performs a reception timeout check in parallel with reception.

  In this hardware configuration device, configuration is directly executed using circuit arrangement data acquired from the network, so there is no need for a large capacity memory and no extra process, and there is a simple mechanism and procedure. This can be realized in a short time, and reliable configuration can be executed by checking the reception timeout.

  (4) In the invention described in the claims, in the hardware configuration device of (1) or (2), the circuit arrangement data received via the network unit is not stored in the storage means for the circuit arrangement data. When directly configuring the FPGA while receiving at the network unit, the configuration control circuit performs a reception timeout check in parallel with the reception, and if a timeout is detected, receives the circuit arrangement data. Request.

  In this hardware configuration device, configuration is directly executed using circuit arrangement data acquired from the network, so there is no need for a large capacity memory and no extra process, and there is a simple mechanism and procedure. It can be realized in a short time, and a circuit configuration data reception request is issued when a timeout is detected, so that reliable configuration can be executed.

  (5) In the invention described in the claims, in the hardware configuration device of (1) to (4), the configuration control circuit is configured by a programmable logic device (PLD).

  In this hardware configuration device, since the configuration control circuit is a PLD in the above (1) to (4), it is possible to cope with various communication forms and protocols by changing the logic circuit in the PLD. Is possible.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
A preferred embodiment of the hardware configuration apparatus of the best mode for carrying out the present invention will be described. This does not limit the scope of the present invention.

The configuration device according to the present invention has the following goals.
・ Simple configuration.
・ Receive hardware configuration data (circuit layout data) from the network to enable configuration.
-Realize hardware initialization with the minimum necessary configuration.
-Simplify the process up to configuration (short time, simple).
-Reconfiguration is also possible.
-Make it easy to cope with changes in communication protocol.

<First Embodiment>
overall structure:
The hardware configuration device shown in FIG. 1 is a hardware configuration device that executes configuration of an FPGA 300 that is programmable hardware. In FIG. 1, known circuit configurations such as a power supply unit and various buses are omitted.

  The hardware configuration device is roughly divided into a minimum configuration, and a network unit 100 that receives circuit arrangement data for executing configuration for an FPGA from an external device via a network, and a circuit arrangement It has a configuration control circuit 200 that configures an FPGA using data, and a field programmable gate array (FPGA) 300 that is programmable hardware. Various devices are connected to the FPGA 300.

  Here, the configuration control circuit 200 directly configures the FPGA 300 while receiving the network arrangement data without receiving the circuit arrangement data received via the network section 100 in the storage means for the circuit arrangement data. It is characterized by performing.

  Here, as shown in FIG. 1, the network unit 100 includes an interface 110 for exchanging data with the configuration control circuit 200, and a part of the data link layer in which the network frame structure and access method are defined. A MAC (Media Access Control layer) unit 120, a PHY (Physical layer) unit 130 in which a physical connection / transmission method of the network is defined, and an RF (Radio Frequency) unit 140 for accessing the network by wireless communication. And is configured.

  In addition, the configuration control circuit 200 is configured to transmit data between the overall control unit 210 that controls the entire apparatus, the configuration control unit 220 that executes various controls and various processes for hardware configuration, and the network unit 100. An interface 230 for performing transmission and reception and an interface 240 for performing data transmission and reception with the FPGA 300 are provided.

  The FPGA 300 includes a processing unit 310 as programmable hardware in which combinations of logic blocks and wiring areas are connected by circuit arrangement data, an interface 320 that exchanges data with the configuration control circuit 200, and various devices. And an interface 330 for exchanging data with each other.

The first embodiment is an embodiment in which the FPGA 300 is configured using a network.
Here, when the network unit 100 performs network connection, either wired connection or wireless connection may be used.

  The network unit 100 may have a different configuration depending on a wired protocol, a wireless protocol, and a communication protocol. However, in the case of a wireless network, the network unit 100 may have at least the RF unit 140. Any circuit configuration such as mounting the PHY unit 130 and the MAC unit 120 can be applied.

  The configuration control circuit 200 can be applied to various communications by changing the circuit configuration to be mounted according to the communication protocol and the circuit configuration of the network unit 100. For example, when the network unit 100 is only the RF unit 140 and the PHY unit 130 and the MAC unit 120 is also required as the communication protocol, the configuration control circuit 200 incorporates the MAC unit necessary for the communication protocol. .

  The configuration control circuit 200 is preferably realized by PLD, but may be realized by ASIC. Note that another circuit other than this may be incorporated in the configuration control circuit.

  There are two main types of FPGA configuration. One is when the configuration is started by a request signal from the outside (network), and the other is the configuration data (circuit layout data) that is sent from the device to the outside. May be sent to start configuration.

<First Operation in First Embodiment>
Hereinafter, an operation (sequence # 1) when configuration is executed by a request from the outside of the hardware configuration device will be described with reference to a flowchart of FIG.

  First, when the network unit 100 receives a configuration request (configuration execution command) from the outside via a wired or wireless network (S1 in FIG. 2), configuration control is performed to determine whether the configuration request is a correct request. This is performed by the overall control unit 210 or the configuration control unit 220 of the circuit 200 (S2 in FIG. 2).

  If it is authenticated that the configuration request is correct (Y in FIG. 2), the configuration control circuit 200 (configuration control unit 220) initializes the FPGA 300 and prepares for configuration (S3 in FIG. 2).

  After initialization and preparation, the configuration control unit 220 transmits a configuration data request (circuit arrangement data request) to the external device that has sent the configuration request via the network unit 100 (see FIG. 2S4).

  The configuration control unit 220 starts a timer from the time of this transmission request (FIG. 2 S5), the configuration is not completed within a predetermined time expected until the completion of the configuration (Y in FIG. 2 S), and the configuration If the number of errors during configuration execution is equal to or greater than the specified number of times (Y in FIG. 2), the configuration work is terminated as an abnormal end.

  Further, the configuration control unit 220 starts a timer from the time of this transmission request (S5 in FIG. 2), the configuration is not completed within a predetermined time expected until the configuration is completed (Y in S2 in FIG. 2), and If the error during configuration execution is less than the specified number of times (N in FIG. 2 S13), it is determined that there is a communication failure, and the configuration work is repeated from initialization (S3 in FIG. 2).

  In addition, when the circuit arrangement data reception times out within the reception time assumed for each circuit arrangement data reception unit (packet or data of a predetermined unit) (Y in FIG. 2 S6), the configuration control unit 220 is connected to the network unit. A configuration data request (circuit arrangement data request) is transmitted from the data part for which the reception time-out has occurred to the external device that has sent the configuration request via 100 (S7 in FIG. 2).

  When circuit arrangement data is received via the network unit 100, the configuration control unit 220 performs predetermined error correction and error check on the circuit arrangement data (S8 in FIG. 2).

  Here, if an error that cannot be corrected has occurred in the received circuit arrangement data (Y in FIG. 2 S9), the configuration control unit 220 transmits to the external device that has sent the configuration request via the network unit 100. Then, a configuration data request (circuit arrangement data request) is transmitted from the data portion where the error has occurred (S7 in FIG. 2).

  If there is no uncorrectable error in the received circuit arrangement data (N in FIG. 2 S9), the configuration control unit 220 sequentially transmits the circuit arrangement data to the FPGA 300 and executes the configuration (S10 in FIG. 2). ).

  In this embodiment, the configuration control circuit 200 does not store the circuit arrangement data received via the network unit 100 in the storage unit for the circuit arrangement data, and the FPGA 300 It is characterized by executing configuration directly.

  Then, the configuration control unit 220 detects the above timeout (FIG. 2 S5, S6), data reception / error check (FIG. 2 S8), configuration execution (FIG. 2 S10), configuration data request as required (FIG. 2 S7). Is continued until the entire data area of the series of circuit arrangement data is completed (S11 in FIG. 2).

  When the entire data area of the series of circuit arrangement data has been received (Y in FIG. 2), the configuration control unit 220 detects whether the configuration has been completed normally by a status signal from the FPGA 300 (S12 in FIG. 2). ). Here, if the configuration is not normally completed (N in FIG. 2 S12), and the error during the configuration execution is equal to or greater than the specified number of times (Y in FIG. 2 S13), the configuration control unit 220 sets the configuration. The process is terminated as an abnormal end.

  In addition, when the entire data area of the series of circuit arrangement data has been received (Y in FIG. 2), the configuration has not ended normally (N in FIG. 2 S12), and an error occurred during the execution of the configuration. If it is less than the prescribed number of times (N in FIG. 2 S13), the configuration control unit 220 determines that there is a communication failure, and restarts the configuration work from initialization (FIG. 2 S3).

  When the entire data area of the series of circuit arrangement data has been received (Y in FIG. 2), if it is confirmed by the status signal from the FPGA 300 that the configuration has been completed normally (Y in FIG. 2 S12). The configuration control unit 220 transmits a configuration completion notification to the external device that has sent the configuration request via the network unit 100 (S14 in FIG. 2).

  At this time, if the configuration does not end correctly even after being repeated a certain number of times (S13 in FIG. 2), the configuration control unit 220 determines that there is a communication failure in the network and ends the configuration. However, when the process is completed in this way, the apparatus may be in a standby state until there is a configuration request from the outside again, or may be transmitted after waiting for a certain period of time.

  As described above, in the hardware configuration device of this embodiment, since configuration is directly performed using circuit arrangement data acquired from the network, a large-capacity memory is not required and an extra process is also required. It can be realized in a short time with a simple mechanism and procedure.

  Further, when performing configuration directly on the FPGA 300 while receiving the network unit 100 without storing the circuit configuration data received via the circuit 100 in the storage unit for the circuit configuration data, The configuration control circuit performs a reception timeout check in parallel with reception. Therefore, reliable configuration can be executed.

  In addition, the configuration control circuit 220 performs a reception timeout check in parallel with reception, and requests reception of circuit arrangement data when a timeout is detected. That is, when a timeout is detected, a circuit arrangement data reception request is issued, so that reliable configuration can be executed.

  In the hardware configuration device of this embodiment, the configuration control circuit 200 can be configured by a programmable logic device (PLD). By doing so, it becomes possible to cope with various communication forms and protocols by changing the logic circuit in the PLD.

<Second Operation in First Embodiment>
Hereinafter, an operation (sequence # 2) in the case where configuration is executed by a request from the inside of the hardware configuration device will be described with reference to the flowchart of FIG.

  First, the configuration control unit 220 transmits a configuration request to an external device having configuration data (circuit arrangement data) via the wired or wireless network by the network unit 100 (S1 in FIG. 3).

  When the network unit 100 receives a response to the above configuration request (S2 in FIG. 3), the overall control unit 210 or the configuration control unit 220 of the configuration control circuit 200 authenticates whether the response is correct (S2). FIG. 3S5).

  The configuration control unit 220 waits for a response according to the assumed response time (N in FIG. 3 S3), and when there is no response and times out (Y in FIG. 3 S), the configuration request is received until the specified number of times is reached. Is transmitted (N, S1 in FIG. 3 S4), and if there is no response even if the specified number of times is reached, the process ends abnormally (Y in FIG. 3 S4).

  When it is authenticated that the response received from the external device is correct (Y in FIG. 3 S), the configuration control circuit 200 (configuration control unit 220) initializes the FPGA 300 and prepares for the configuration (S6 in FIG. 3).

  After initialization and preparation, the configuration control unit 220 transmits a configuration data request (circuit arrangement data request) to the responding external device via the network unit 100 (S7 in FIG. 3).

  The configuration control unit 220 starts a timer from the time of this transmission request (S8 in FIG. 3), the configuration is not completed within a predetermined time expected until the completion of the configuration (Y in FIG. 3S), and the configuration If the error during configuration execution is equal to or greater than the specified number of times (Y in FIG. 3 S16), the configuration work is terminated as an abnormal end.

  Further, the configuration control unit 220 starts a timer from the time of this transmission request (S8 in FIG. 3), the configuration is not completed within a predetermined time expected until the configuration is completed (Y in FIG. 3S), and If the error during configuration execution is less than the specified number of times (N in FIG. 3 S16), it is determined that there is a communication failure, and the configuration work is repeated from initialization (S6 in FIG. 3).

  When the circuit arrangement data reception times out within the reception time assumed for each circuit arrangement data reception unit (packet or data of a predetermined unit) (Y in FIG. 3 S9), the configuration control unit 220 is connected to the network unit. A configuration data request (circuit arrangement data request) is transmitted from the data part whose reception timed out to the external device that has responded via 100 (S10 in FIG. 3).

  When the circuit arrangement data is received via the network unit 100, the configuration control unit 220 performs predetermined error correction and error check on the circuit arrangement data (S11 in FIG. 3).

  Here, if an error that cannot be corrected has occurred in the received circuit arrangement data (Y in FIG. 3 S12), the configuration control unit 220 generates an error for the external device that has responded via the network unit 100. A configuration data request (circuit arrangement data request) is transmitted from the data portion (S10 in FIG. 3).

  If there is no uncorrectable error in the received circuit arrangement data (N in FIG. 3 S12), the configuration control unit 220 sequentially transmits the circuit arrangement data to the FPGA 300 and executes the configuration (S13 in FIG. 3). ).

  In this embodiment, the configuration control circuit 200 does not store the circuit arrangement data received via the network unit 100 in the storage unit for the circuit arrangement data, and the FPGA 300 It is characterized by executing configuration directly.

  Then, the configuration control unit 220 detects the above timeout (FIGS. 3S8 and S9), data reception / error check (FIG. 3S11), configuration execution (FIG. 3S13), and configuration data request as needed (FIG. 3S10). Is continued until the entire data area of the series of circuit arrangement data is completed (S14 in FIG. 3).

  When the entire data area of the series of circuit arrangement data has been received (Y in FIG. 3 S14), the configuration control unit 220 detects whether the configuration is normally completed by a status signal from the FPGA 300 (S15 in FIG. 3). ).

  Here, if the configuration is not normally completed (N in FIG. 3 S15) and the error during the configuration execution is equal to or greater than the specified number of times (Y in FIG. 3 S16), the configuration control unit 220 performs the configuration. The process is terminated as an abnormal end.

  In addition, when the entire data area of the series of circuit arrangement data has been received (Y in FIG. 3 S14), the configuration has not been completed normally (N in FIG. 3 S15), and an error occurred during the execution of the configuration. If it is less than the prescribed number of times (N in FIG. 3 S16), the configuration control unit 220 determines that there is a communication failure, and restarts the configuration work from initialization (S3 in FIG. 3).

  When the entire data area of the series of circuit arrangement data is received (Y in FIG. 3 S14), if it can be confirmed that the configuration is normally completed by a status signal from the FPGA 300 (Y in FIG. 3 S15). The configuration control unit 220 transmits a configuration completion notification to the responding external device via the network unit 100 (S17 in FIG. 3).

  At this time, if the configuration does not end correctly even after being repeated a certain number of times (S16 in FIG. 3), the configuration control unit 220 determines that there is a communication failure in the network and ends the configuration. However, when the process is completed in this way, the apparatus may be set in a standby state, or after waiting for a certain period, a configuration request may be transmitted.

  As described above, in the hardware configuration device of this embodiment, since configuration is directly performed using circuit arrangement data acquired from the network, a large-capacity memory is not required and an extra process is also required. It can be realized in a short time with a simple mechanism and procedure.

  Further, when the circuit configuration data received via the network unit 100 is directly stored in the network unit 100 without being stored in the storage unit for the circuit configuration data, the configuration is performed when the FPGA 300 is directly configured. The control circuit performs a reception timeout check in parallel with reception. Therefore, reliable configuration can be executed.

  In addition, the configuration control circuit 220 performs a reception timeout check in parallel with reception, and requests reception of circuit arrangement data when a timeout is detected. That is, when a timeout is detected, a circuit arrangement data reception request is issued, so that reliable configuration can be executed.

  In the hardware configuration device of this embodiment, the configuration control circuit 200 can be configured by a programmable logic device (PLD). By doing so, it becomes possible to cope with various communication forms and protocols by changing the logic circuit in the PLD.

  In addition, an authentication sequence for confirming the normality of the data may be incorporated in the above-described sequence, or a code correction function, an encryption / decryption function, etc. may be provided for this operation.

<Operation after Configuration in First Embodiment>
Control of the network unit 100 after configuration may be performed by the FPGA 300, the configuration circuit 200 may continue to take charge of control, or another device may control.

  When controlling the FPGA 300, it may be controlled by a logic circuit (hardware) of the FPGA 300, or may be controlled by software by mounting a processor in the FPGA 300.

  Further, when the FPGA 300 or another device controls the network, the configuration control circuit 200 does not have to control the network control at all during the operation of the FPGA 300, or after configuring only a part of functions for reconfigurable. It may be operable.

That is, there are the following methods (a), (b), and (c) for network control after execution of configuration for the FPGA 300.
(a) Even after the configuration, the configuration control circuit 200 controls the network.

  (b) The FPGA 300 or another device completely performs network control, and the configuration control circuit 200 does not control the network. The configuration control circuit 200 starts the network control again when the network control right is transferred from the device performing the network control.

  (c) Although the FPGA 300 or other device controls the network, a part of the network function of the configuration control circuit 200 is operated so that it can respond to a specific command and signal from the network.

  The internal configuration of the FPGA 300 shown in FIG. 1 is an example of the logic circuit in the FPGA in the case of (a) above, or when another device (other than the FPGA) performs network control in the above (b) and (c). It is an example of logic circuit in FPGA.

  In addition, in the cases (b) and (c) described above, as an example of the logic circuit in the FPGA when the FPGA 300 performs network control, the one shown in FIG. 4 can be shown. The hardware configuration apparatus of FIG. 4 is characterized in that a network control unit 340 for performing network control is provided between the I / F 320 and the I / F 330 inside the FPGA 300. The network controller 340 enables the FPGA 300 to perform network control even after configuration in the cases (b) and (c) above.

Note that there is a case where the configuration (reconfiguration) is executed again after the FPGA 300 is configured. In the case of the reconfiguration start in that case, the following sequence (A) to (E) is performed using the above-described sequence # 1 (flowchart in FIG. 2) and the above-described sequence # 2 (flowchart in FIG. 3). A simple procedure can be considered.
(A) When there is a reconfiguration request from an external device via the network: Sequence # 1.
(B) When the configuration control circuit 200 ends the specific process: Sequence # 2.
(C) When the FPGA 300 or another device ends a specific process and transmits a reconfiguration command to a register in the configuration control circuit 200, or transmits a signal to the configuration control circuit 200 : Sequence # 2.
(D) When the configuration control circuit 200 reads the state of the FPGA 300 or another device into a register or the like and finds that the state is in the reconfiguration state: sequence # 2.
(E) When the FPGA 300 or another device terminates the specific processing and the device controlling the network directly transmits a configuration request: Sequence # 2.

  On the other hand, when the network control is not allowed to function in the configuration control circuit 200, that is, when the network control function is provided to the FPGA 300, the reconfiguration of the FPGA 300 is started and started at the above-described timing. When the configuration control circuit 200 starts network control, the FPGA 300 is put into a state in which it can be configured, thereby realizing a reconfiguration operation.

  In addition, when a part of the network control function is made operable by the configuration control circuit 200, a specific command or data from the network unit 100 or other devices, for example, a configuration request can be responded. When the configuration control circuit 200 receives the specific command or signal, the FPGA 300 is put into a configurable state and a reconfiguration operation is realized.

  Note that the above-described functions related to reconfiguration can be applied without any problem even in a hardware configuration device in which a plurality of FPGAs equivalent to the FPGA 300 are arranged.

  In the case of this embodiment, since the configuration is performed by hardware, processing can be performed simultaneously with other processing. For example, when the CPU is mounted on the hardware configuration device, the initialization of the CPU and the configuration of the FPGA 300 can be executed simultaneously.

Second Embodiment
The hardware configuration device shown in FIG. 5 is a second embodiment of the hardware configuration device that executes the configuration of the FPGA 300 that is programmable hardware. In FIG. 5, known circuit configurations such as a power supply unit and various buses are omitted.

  The hardware configuration device is roughly divided into a minimum configuration, a network unit 100 that receives circuit arrangement data when executing configuration for an FPGA from an external device, and a programmable device. A hardware field programmable gate array (FPGA) 300 and a CPU 400 as a configuration control circuit configured to configure the FPGA 300 using the received circuit arrangement data are included. Various devices are connected to the FPGA 300.

  Here, the CPU 400 as the configuration control circuit directly receives the circuit arrangement data received via the network unit 100 from the storage unit for the circuit arrangement data and directly receives the FPGA 300 while receiving the circuit arrangement data. It is characterized by executing configuration. The network unit 100 and the FPGA 300 have the same contents as in the first embodiment described above.

  The first embodiment described above is controlled by hardware, whereas the second embodiment is characterized in that control is performed by software using the CPU 400. That is, under the control of the software of the CPU 400, processing and control similar to those of the configuration control circuit 200 described above are executed. That is, since the control of the network unit 100 and the configuration control of the FPGA 300 are performed by the software of the CPU 400, the algorithm of the control of the network unit 100 and the configuration control of the FPGA 300 can be easily changed by changing the software.

  Note that the second embodiment is an embodiment in which the FPGA 300 is configured using a network. Here, when the network unit 100 performs network connection, either wired connection or wireless connection may be used. The network unit 100 may have a different configuration depending on a wired protocol, a wireless protocol, and a communication protocol. However, in the case of a wireless network, the network unit 100 may have at least the RF unit 140. Any circuit configuration such as mounting the PHY unit 130 and the MAC unit 120 can be applied.

  The CPU 400 as a configuration control circuit can be applied to various communications by changing the circuit configuration to be mounted according to the communication protocol and the circuit configuration of the network unit 100. For example, when the network unit 100 includes only the RF unit 140 and the PHY unit 130 and the MAC unit 120 is also required as a communication protocol, the CPU 400 as a configuration control circuit incorporates the MAC unit necessary for the communication protocol. To.

  There are two main types of FPGA configuration. One is when the configuration is started by a request signal from the outside (network), and the other is the configuration data (circuit layout data) that is sent from the device to the outside. May be sent to start configuration.

In the second embodiment as well, there is a case where the configuration (reconfiguration) is performed again after the FPGA 300 is configured. In the case of the start of the reconfiguration in this case, the following sequence (G) to (J) are performed using the above-described sequence # 1 (the flowchart in FIG. 2) and the above-described sequence # 2 (the flowchart in FIG. 3). A simple procedure can be considered.
(G) When there is a reconfiguration request from an external device via the network: Sequence # 1.
(H) When CPU 400 completes the specific process: Sequence # 2.
(I) When the FPGA 300 or another device ends a specific process and transmits a reconfiguration command to the CPU 400, or transmits a signal to the CPU 400: Sequence # 2.
(J) When the CPU 400 reads the state of the FPGA 300 or another device into a register or the like and finds that the state is in the reconfiguration state: Sequence # 2.

  Note that the above-described functions related to reconfiguration can be applied without any problem even in a hardware configuration device in which a plurality of FPGAs equivalent to the FPGA 300 are arranged.

<Third Embodiment>
The hardware configuration apparatus shown in FIG. 6 is a third embodiment of the hardware configuration apparatus that executes configuration of the FPGA 300 that is programmable hardware. In FIG. 6, known circuit configurations such as a power supply unit and various buses are omitted, and this hardware configuration device is roughly divided into a minimum configuration and an FPGA. A network unit 100 that receives circuit arrangement data when executing configuration from an external device via a network, a CPU 150 built in the network unit 100 to perform network control and configuration control, and programmable hardware And a field programmable gate array (FPGA) 300. Various devices are connected to the FPGA 300.

  The CPU 150 performs network-related control in the network unit 100 and configuration control for configuring the FPGA 300 using the received circuit arrangement data.

  Here, the CPU 150 functioning as a configuration control circuit does not store the circuit arrangement data received via the network unit 100 in the storage unit for the circuit arrangement data, but receives the FPGA 300 while receiving it at the network unit 100. It is characterized by executing configuration directly. Therefore, it can be realized with a simple configuration.

  The FPGA 300 has the same contents as those of the first embodiment and the second embodiment described above. The network unit 100 has the same contents as those of the first and second embodiments described above except that the CPU 150 is provided.

  While the first embodiment described above is controlled by hardware, the third embodiment is characterized in that control is performed by software using the CPU 150 as in the second embodiment described above. It is. That is, under the control of the software of the CPU 150, processing and control similar to those of the configuration control circuit 200 described above are executed. That is, since the control of the network unit 100 and the configuration control of the FPGA 300 are performed by the software of the CPU 150, the algorithm of the control of the network unit 100 and the configuration control of the FPGA 300 can be easily changed by changing the software.

  The third embodiment is an embodiment in which the FPGA 300 is configured using a network. Here, when the network unit 100 performs a network connection, either a wired connection or a wireless connection may be used. The network unit 100 may have different configurations depending on a wired protocol, a wireless protocol, and a communication protocol. In the case of a wireless network, the network unit 100 may have at least the RF unit 140. In the wired network, only the PHY unit 130 is mounted. Any circuit configuration such as mounting the PHY unit 130 and the MAC unit 120 can be applied.

  The CPU 150 as a configuration control circuit can be applied to various communications by changing the circuit configuration to be mounted according to the communication protocol and the circuit configuration of the network unit 100. For example, when the network unit 100 is only the RF unit 140 and the PHY unit 130 and the MAC unit 120 is also required as a communication protocol, the CPU 150 as a configuration control circuit incorporates the MAC unit necessary for the communication protocol. To.

  There are two main types of FPGA configuration. One is when the configuration is started by a request signal from the outside (network), and the other is the configuration data (circuit layout data) that is sent from the device to the outside. May be sent to start configuration.

Also in the third embodiment, after the configuration of the FPGA 300 is executed, the configuration (reconfiguration) may be executed again. In the case of the start of reconfiguration in this case, the following (K) to (N) are performed using the above-described sequence # 1 (the flowchart in FIG. 2) and the above-described sequence # 2 (the flowchart in FIG. 3). A simple procedure can be considered.
(K) When there is a reconfiguration request from an external device via the network: Sequence # 1.
(L) When CPU 150 completes the specific process: Sequence # 2.
(M) When the FPGA 300 or another device ends a specific process and transmits a reconfiguration command to the CPU 150, or transmits a signal to the CPU 150: Sequence # 2.
(N) When the CPU 150 reads the state of the FPGA 300 or another device into a register or the like and finds that the state is in the reconfiguration state: Sequence # 2.

  Note that the above-described functions related to reconfiguration can be applied without any problem even in a hardware configuration device in which a plurality of FPGAs equivalent to the FPGA 300 are arranged.

<Fourth embodiment>
The hardware configuration device shown in FIG. 7 is a fourth embodiment of a hardware configuration device that executes configuration of the FPGA 300 that is programmable hardware. In FIG. 7, known circuit configurations such as a power supply unit and various buses are omitted.

  The hardware configuration device is roughly divided into a minimum configuration, a network unit 100 that receives circuit arrangement data when executing configuration for an FPGA from an external device, and a programmable device. Field programmable gate array (FPGA) 300 that is hardware, CPU 400 as a configuration control circuit that configures FPGA 300 using the received circuit arrangement data, relay circuit 500 that performs I / F conversion, and A memory 600 is provided as storage means for preliminarily storing circuit arrangement data. Various devices are connected to the FPGA 300.

  Note that the relay circuit 500 performs I / F conversion work. Whether the circuit arrangement data from the CPU 400 is sent to the FPGA 300 or both the FPGA 300 and the memory 600 according to a predetermined address. , Switch.

  Here, the CPU 400 as the configuration control circuit receives the circuit arrangement data received via the network unit 100 in the network unit 100, not after storing the circuit arrangement data in the storage means or the memory 600 for the circuit arrangement data. However, the configuration is performed directly on the FPGA 300. Then, the CPU 400 executes configuration directly on the FPGA 300 while receiving the circuit arrangement data received via the network unit 100 at the network unit 100, and stores it in the memory 600 in parallel with this. It is a feature.

  In the fourth embodiment, the configuration data is stored in the memory 600 in parallel with sending the configuration data (circuit arrangement data) to the FPGA 300.

  In the conventional invention, the configuration data is once written in the memory and then the circuit arrangement data is sent to the FPGA to realize the configuration. However, in the present invention, the configuration data is not stored before the configuration. Since the storage is performed in parallel, the time until the configuration is completed can be shortened as in the first to third embodiments described above.

  In addition, as in the fourth embodiment, if data is simultaneously written in the memory 600, the configuration operation can be realized in a short time during normal configuration or reconfiguration, and an error state ( When configuration or reconfiguration cannot be performed due to a communication failure or the like, the configuration can be executed without reading data from the memory 600 and downloading it again. In this case, the memory 600 may be either a ROM type or a RAM type.

  While the first embodiment described above is controlled by hardware, the fourth embodiment is characterized in that control is performed by software using the CPU 400. That is, under the control of the software of the CPU 400, processing and control similar to those of the configuration control circuit 200 described above are executed. That is, since the control of the network unit 100 and the configuration control of the FPGA 300 are performed by the software of the CPU 400, the algorithm of the control of the network unit 100 and the configuration control of the FPGA 300 can be easily changed by changing the software.

  In the fourth embodiment, the CPU 400 is used. However, this may be realized by hardware as in the first embodiment, and in that case, the relay circuit may be realized in the PLD.

  The fourth embodiment is an embodiment in which the FPGA 300 is configured using a network. Here, when the network unit 100 performs a network connection, either a wired connection or a wireless connection may be used. The network unit 100 may have different configurations depending on a wired protocol, a wireless protocol, and a communication protocol. In the case of a wireless network, the network unit 100 may have at least the RF unit 140. In the wired network, only the PHY unit 130 is mounted. Any circuit configuration such as mounting the PHY unit 130 and the MAC unit 120 can be applied.

  Further, the CPU 400 as the configuration control circuit can be applied to various communications by changing the mounted circuit configuration according to the communication protocol and the circuit configuration of the network unit 100. For example, when the network unit 100 includes only the RF unit 140 and the PHY unit 130 and the MAC unit 120 is also required as a communication protocol, the CPU 400 as a configuration control circuit incorporates the MAC unit necessary for the communication protocol. To.

  There are two main types of FPGA configuration. One is when the configuration is started by a request signal from the outside (network), and the other is the configuration data (circuit layout data) that is sent from the device to the outside. May be sent to start configuration.

In the fourth embodiment, after the configuration of the FPGA 300 is executed, the configuration (reconfiguration) may be executed again. In the case of the start of reconfiguration in that case, the following sequence (O) to (R) is performed using the sequence # 1 (the flowchart in FIG. 2) and the sequence # 2 (the flowchart in FIG. 3). A simple procedure can be considered.
(O) When there is a reconfiguration request from an external device via the network: Sequence # 1.
(P) When CPU 400 finishes the specific process: Sequence # 2.
(Q) When the FPGA 300 or another device ends a specific process and transmits a reconfiguration command to the CPU 400, or transmits a signal to the CPU 400: Sequence # 2.
(R) When the CPU 400 reads the state of the FPGA 300 or another device into a register or the like and finds that the state is in the reconfiguration state: Sequence # 2.

  Note that the above-described functions related to reconfiguration can be applied without any problem even in a hardware configuration device in which a plurality of FPGAs equivalent to the FPGA 300 are arranged.

It is a block diagram which shows schematic structure of the hardware configuration apparatus of 1st Embodiment of this invention. It is a flowchart which shows the procedure at the time of performing configuration in embodiment of this invention. It is a flowchart which shows the procedure at the time of performing configuration in embodiment of this invention. It is a block diagram which shows the other structure of the hardware configuration apparatus of 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the hardware configuration apparatus of 2nd Embodiment of this invention. It is a block diagram which shows schematic structure of the hardware configuration apparatus of 3rd Embodiment of this invention. It is a block diagram which shows schematic structure of the hardware configuration apparatus of 4th Embodiment of this invention.

Explanation of symbols

100 Network Unit 200 Configuration Control Circuit 300 FPGA

Claims (5)

Field programmable gate array (FPGA) that is programmable hardware;
A configuration control circuit for configuring the FPGA;
A network unit for receiving circuit arrangement data when executing configuration for the FPGA from an external device via a network;
The configuration control circuit directly performs configuration on the FPGA while receiving the circuit arrangement data through the network unit without storing the circuit arrangement data in the storage unit for the circuit arrangement data. To
A hardware configuration device characterized by that. Field programmable gate array (FPGA) that is programmable hardware;
A configuration control circuit for configuring the FPGA;
A network unit for receiving circuit arrangement data when executing configuration for the FPGA from an external device via a network;
Storage means,
The configuration control circuit stores the circuit arrangement data in the storage unit in parallel with the operation of directly performing configuration on the FPGA while receiving the circuit arrangement data via the network unit.
A hardware configuration device characterized by that. The configuration control circuit performs a reception timeout check in parallel with reception when performing configuration directly on the FPGA while receiving the circuit arrangement data in the network unit.
The hardware configuration device according to claim 1, wherein the hardware configuration device is a hardware configuration device. When the configuration control circuit directly performs configuration on the FPGA while receiving the circuit arrangement data in the network unit, the configuration control circuit performs a reception timeout check in parallel with reception, and a timeout is detected. Request to receive the circuit arrangement data,
The hardware configuration device according to claim 1, wherein the hardware configuration device is a hardware configuration device. The configuration control circuit is composed of a programmable logic device (PLD),
5. The hardware configuration device according to claim 1, wherein the hardware configuration device is a hardware configuration device.

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