JP4618010B2 - Manufacturing method of ceramic electronic component - Google Patents

Description

  The present invention relates to a method for manufacturing a ceramic electronic component such as a multilayer chip varistor.

  With recent miniaturization and higher performance of electronic devices, surface mountable chip components are indispensable. Such surface-mountable chip components usually have a structure having two or more external terminal electrodes. As a method for forming external terminal electrodes on these chip components, a process of applying an external electrode paste containing conductive particles such as metal to an element body, and then drying and baking is generally used. Such external terminal electrodes are plated with Ni, Sn or the like in order to enable mounting with solder.

  As the external electrode paste for forming the external terminal electrode, a paste containing glass frit in addition to the metal powder as the conductive particles and the organic vehicle is used. By including the glass component in this manner, the glass component is heated and melted during baking, and therefore, the external terminal electrode and the ceramic layer of the element body can be bonded satisfactorily. In particular, by including a glass component, inherently difficult "ceramic-metal" bonding can be made "ceramics-glass-metal", making easy bonding industrially possible in a short time.

  On the other hand, since such a glass component melts in a short time, it is difficult to control. Therefore, when the external terminal electrodes of adjacent products are in contact with each other during baking, adjacent products are mutually connected. There has been a problem that it has adhered and cannot be separated.

  As a method of solving such a problem, for example, a method of baking after attaching ceramic powder to the surface of the external terminal electrode before baking, or a method for preventing contact between the external terminal electrodes during baking There was a method of arranging them at a distance and baking them.

  However, if the ceramic powder is attached to the surface of the external terminal electrode before baking, the ceramic powder and the glass component react and the glass component moves to the surface of the external terminal electrode. Was causing. First, there is a problem that the glass component moves to the surface of the external terminal electrode, thereby reducing the amount of the glass component in the external terminal electrode, resulting in insufficient bonding with the element body. . Second, since the ratio of the glass component on the surface of the external terminal electrode is increased, it is not possible to form a plating layer on the surface of the external terminal electrode by Ni, Sn, etc., which is formed to enable mounting with solder. There was a problem of becoming enough.

  In addition, when baking is performed at a distance between the products, it is necessary to arrange the products, so the work efficiency is reduced, and at the same time, the products that can be placed in the container when baking the products As the number of products is reduced, the number of product processes per unit time is reduced, and there is a problem that the efficiency is lowered in terms of energy and apparatus operation rate.

  On the other hand, for example, in Patent Document 1, a paste containing a predetermined amount of a metal additive having a melting point higher than that of the metal powder is used in addition to the metal powder and the glass frit as a paste for the external electrode. A method for forming an external terminal electrode is disclosed. In this document, due to the action of a metal additive having a high melting point, sintering of the metal powder in the vicinity of the metal additive particles is suppressed during baking, and a gap is formed between the particles of the metal powder. In other words, since the glass component is filled, it is described that the glass component can be prevented from exuding on the outer surface of the external terminal electrode.

  However, in this document, since a gap is formed between the particles of the metal powder, when a plating film made of Ni, Sn or the like is formed thereafter, the plating solution enters the element body through this gap. As a result, there is a problem of deteriorating electrical characteristics. Further, in this document, since the entire external terminal electrode contains a relatively expensive metal additive, it is necessary to use a large amount of such an expensive metal additive, resulting in an increase in cost. There was also a problem.

JP-A-10-12481

  The present invention has been made in view of such a situation, and when manufacturing a ceramic electronic component having an external terminal electrode such as a multilayer chip varistor, while suppressing the performance deterioration of the electronic component itself, the productivity and work It is an object of the present invention to provide a method for manufacturing a ceramic electronic component that can effectively prevent adhesion of products through external terminal electrodes without deteriorating performance.

  As a result of intensive investigations to achieve the above object, the present inventors applied metal electrode paste to the element body, and then dried the metal powder on the pre-baking electrode formed by drying. The inventors have found that the above object can be achieved by baking in a state where metal powder is adhered, and have completed the present invention.

That is, the method for producing a ceramic electronic component of the present invention includes:
A method of manufacturing a ceramic electronic component having an external terminal electrode,
A step of preparing an element body having a ceramic layer, and an external electrode paste containing a conductive powder and a glass component;
Applying the external electrode paste to the element body and then drying to form a pre-baking electrode; and
Attaching metal powder to the pre-baking electrode;
Baking the pre-baking electrode to which the metal powder is adhered to form an external terminal electrode.

In the manufacturing method of this invention, Preferably, the said metal powder consists of a metal which has melting | fusing point higher than the electrically conductive powder contained in the paste for external electrodes.
More preferably, the metal powder having a higher melting point than the conductive powder contains one or more elements selected from Ni, Cu, Ag, Fe, Pd, Pt, W and Ti.

  In the manufacturing method of this invention, Preferably, the average particle diameter of the said metal powder is larger than 0.05 micrometer and less than 60 micrometers. The average particle diameter of the metal powder can be measured, for example, by a microtrack method using a laser diffraction scattering method.

In the manufacturing method of this invention, Preferably, the ratio of the usage-amount of the said metal powder with respect to the said element main body shall be the range of 10 < ^-6 <weight of metal powder / weight of an element main body <0.225.

In the manufacturing method of the present invention, preferably, a step of forming a first plating layer mainly composed of Ni on the surface of the external terminal electrode;
Forming a second plating layer mainly composed of Sn on the surface of the first plating layer.

  The ceramic electronic component according to the present invention is not particularly limited, but preferably, the element body is a multilayer chip varistor having a structure in which zinc oxide-based voltage nonlinear resistor layers and internal electrode layers are alternately stacked. It is. The ceramic electronic component of the present invention can be manufactured by any one of the methods described above.

  In the present invention, the conductive powder contained in the external electrode paste includes various conductive materials having conductivity that constitute the fired external terminal electrode, and such a conductive material after firing. The various compounds are also included.

  According to the present invention, the metal powder is attached to the pre-baking electrode containing a glass component, and the external terminal electrode is baked in a state where the metal powder is attached, so that the element body, the external terminal electrode after baking, In addition, it is possible to effectively prevent the problem of adhesion between products during baking.

  Moreover, in this invention, since metal powder is used, the movement of the glass component to the external terminal electrode surface at the time of baking does not generate | occur | produce. Therefore, the bonding property between the element body and the external terminal electrode surface can be improved, and a plated layer made of Ni, Sn, or the like can be uniformly and satisfactorily formed on the external terminal electrode after baking.

  Furthermore, in the present invention, unlike the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 10-12481), a metal powder having a higher melting point than the conductive powder constituting the external terminal electrode is substantially contained in the external terminal electrode. Therefore, there is no such a gap as in Patent Document 1 in the external terminal electrode after baking. Therefore, the plating solution does not enter the element body, which has been a problem in Patent Document 1. Furthermore, in the present invention, such a metal powder is not contained in the entire electrode as in Patent Document 1, but is attached only to the surface of the electrode. The amount used can be reduced.

Hereinafter, the present invention will be described based on embodiments shown in the drawings.
FIG. 1 is a schematic sectional view of a multilayer chip varistor according to an embodiment of the present invention.

Multilayer Chip Varistor As shown in FIG. 1, a multilayer chip varistor 2 as an example of a ceramic electronic component includes an element body 8 in which interlayer voltage nonlinear resistance layers 4 and internal electrode layers 6 are alternately stacked. Have A pair of external terminal electrodes 10 are formed at both ends of the element body 8 so as to be electrically connected to the internal electrode layers 6 arranged alternately in the element body 8. The internal electrode layers 6 are laminated so that the end faces are alternately exposed on the surfaces of the two opposite ends of the element body 8. The pair of external terminal electrodes 10 are formed at both ends of the element body 8 and connected to the exposed end faces of the alternately arranged internal electrode layers 6 to form a varistor circuit.

  The shape of the element body 8 is not particularly limited, but is usually a rectangular parallelepiped shape. Also, there is no particular limitation on the dimensions, and it may be an appropriate dimension according to the application, but usually, length (0.6 to 5.6 mm) × width (0.3 to 5.0 mm) × thickness ( 0.3 to 1.9 mm).

  In the element body 8, outer protective layers 4 a are disposed at both outer ends in the stacking direction of the interlayer voltage nonlinear resistor layer 4 and the internal electrode layer 6 to protect the inside of the element body 8. . The material of the outer protective layer 4 a may be the same as or different from the material of the interlayer voltage nonlinear resistor layer 4. The thickness of the outer protective layer 4a is, for example, about 100 to 500 μm.

Interlayer voltage nonlinear resistor layer 4, outer protective layer 4a
The interlayer voltage nonlinear resistor layer 4 and the outer protective layer 4a are composed of a zinc oxide varistor material layer. This zinc oxide-based varistor material layer has, for example, ZnO as a main component and rare earth elements, Co, IIIb group elements (B, Al, Ga and In), Si, Cr, alkali metal elements (K, Rb and Cs) and an alkaline earth metal element (Mg, Ca, Sr, and Ba). Alternatively, it may be made of a material containing ZnO as a main component and Bi, Co, Mn, Sb, Al, etc. as subcomponents.

  The main component containing ZnO acts as a substance that exhibits excellent voltage nonlinearity in voltage-current characteristics and a large surge resistance. The voltage non-linearity is a phenomenon in which the current flowing through the element increases non-linearly when a gradually increasing voltage is applied between the pair of external terminal electrodes 10.

  The content of ZnO in the interlayer voltage nonlinear resistor layer 4 is not particularly limited, but it is usually 69 when the total material constituting the interlayer voltage nonlinear resistor layer 4 is 100% by mass. 0.0 to 99.8% by mass. The thickness of the interlayer voltage nonlinear resistor layer 4 is usually about 5 to 100 μm.

Internal electrode layer 6
The internal electrode layer 6 includes a conductive material. The conductive material contained in the internal electrode layer 6 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The thickness of the internal electrode layer 6 may be appropriately determined according to the application, but is usually about 0.5 to 5 μm.

External terminal electrode 10
The external terminal electrode 10 includes a conductive material and a glass component. By including the glass component in this way, it is possible to improve the bondability with the interlayer voltage nonlinear resistor layer 4 constituting the element body 8. The thickness of the external terminal electrode 10 may be appropriately determined according to the application, but is usually about 10 to 50 μm.

Although it does not specifically limit as a electrically conductive material contained in the external terminal electrode 10, Usually, what is comprised from Ag or an Ag-Pd alloy is preferable.
The glass component is not particularly limited, for _{example, B 2 O 3 -ZnO-Al} 2 O 3 -SrO based _glass, B ₂ O ₃ -SiO ₂ -ZnO based _glass, B ₂ O ₃ -SiO ₂ -ZnO- Al ₂ O ₃ glass, SiO ₂ —BaO—Li ₂ O glass, B ₂ O ₃ —SiO ₂ —Na ₂ O glass, B ₂ O ₃ —SiO ₂ —ZnO—Al ₂ O ₃ —SrO glass The thing comprised from etc. is mentioned.

  The content of the glass component in the external terminal electrode 10 is preferably 2 to 30 parts by weight, more preferably 5 to 20 parts by weight with respect to 100 parts by weight of the conductive material. When there is too little content of a glass component, bondability with the interlayer voltage nonlinear resistance layer 4 will fall. On the other hand, if the amount is too large, it is difficult to form a plating layer made of Ni or Sn on the external terminal electrode 10.

  A surface of the pair of external terminal electrodes 10 includes a first plating layer containing Ni as a main component, and a second plating containing Sn as a main component on the surface of the first plating layer. A layer is formed. These plated layers are formed mainly for the purpose of enabling mounting of the multilayer chip varistor 2 with solder.

Method for Manufacturing Multilayer Chip Varistor Next, an example of a method for manufacturing the multilayer chip varistor 2 according to this embodiment will be described.

  The multilayer chip varistor 2 of this embodiment is manufactured by forming a green chip by a normal printing method or sheet method using a paste, firing the chip, and then forming an external terminal electrode. Hereinafter, the manufacturing method will be specifically described.

  First, a voltage non-linear resistor layer paste for forming the interlayer voltage non-linear resistor layer 4 and the outer protective layer 4a shown in FIG. 1, and an internal electrode layer paste for forming the internal electrode layer 6 Prepare each.

  The paste for the voltage nonlinear resistor layer may be an organic paint obtained by kneading the voltage nonlinear resistor ceramic composition raw material and an organic vehicle, or may be a water-based paint. The voltage nonlinear resistor ceramic composition raw material may be appropriately adjusted using various raw materials so that the fired interlayer voltage nonlinear resistor layer 4 has a desired composition.

  The organic vehicle is obtained by dissolving a binder in an organic solvent, and the binder used in the organic vehicle is not particularly limited, and may be appropriately selected from ordinary various binders such as ethyl cellulose and polyvinyl butyral. In addition, the organic solvent used at this time is not particularly limited, and may be appropriately selected from organic solvents such as terpineol, butyl carbitol, acetone, toluene and the like according to a method to be used such as a printing method or a sheet method.

  The water-based paint is obtained by dissolving a water-soluble binder, a dispersant, etc. in water. The water-based binder is not particularly limited, and is appropriately selected from polyvinyl alcohol, cellulose, water-soluble acrylic resin, emulsion, and the like. do it.

  The internal electrode layer paste is prepared by kneading the various conductive materials described above or various oxides, organometallic compounds, resinates, and the like, which become the conductive materials described above after firing, and the above-described organic vehicle.

  The content of the organic vehicle in each paste is not particularly limited, and may be a normal content, for example, about 1 to 5% by weight for the binder and about 10 to 50% by weight for the solvent. Each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, and the like as necessary.

  When using the printing method, the voltage non-linear resistor layer paste and the internal electrode layer paste are laminated and printed on a substrate such as PET, cut into a predetermined shape, and then peeled from the substrate to obtain a green chip.

  When the sheet method is used, a green sheet is formed using a voltage non-linear resistor layer paste, an internal electrode layer paste is printed thereon, and these are stacked to form a green chip.

  Next, the green chip is subjected to binder removal processing and firing to produce a sintered body (element body 8).

  The binder removal process may be performed under normal conditions. For example, in an air atmosphere, the temperature rising rate is about 5 to 300 ° C./hour, the holding temperature is about 180 to 400 ° C., and the temperature holding time is about 0.5 to 24 hours.

  The green chip may be fired under normal conditions. For example, in an air atmosphere, the heating rate is about 50 to 500 ° C./hour, the holding temperature is about 1000 to 1400 ° C., the temperature holding time is about 0.5 to 8 hours, and the cooling rate is about 50 to 500 ° C./hour. To do. If the holding temperature is too low, densification is insufficient, and if the holding temperature is too high, there is a tendency that the electrodes are interrupted due to abnormal sintering of the internal electrodes.

  Next, the obtained sintered body (element main body 8) is subjected to end surface polishing, for example, by barrel polishing or sand blasting, and then external electrode paste is printed and transferred to the end of the sintered body (element main body 8). The electrode before baking is formed by applying by a method such as dipping and then drying.

  The external electrode paste is prepared by kneading a conductive material made of Ag or an Ag—Pd alloy, the glass frit made of the various glass components described above, and the organic vehicle described above. Note that various oxides, organometallic compounds, resinates, and the like that become Ag or an Ag-pd alloy after firing may be used instead of the conductive material made of Ag or an Ag—Pd alloy. In the present embodiment, since the glass component is contained in the external electrode paste, it is possible to improve the bonding between the external terminal electrode 10 and the interlayer voltage nonlinear resistor layer 4 of the element body 8.

  Next, the external terminal electrode 10 is formed by attaching a metal powder to the pre-baking electrode formed as described above and baking it with the metal powder attached.

  As the metal powder, it is preferable to use a metal powder made of a metal having a higher melting point than the conductive material contained in the electrode before baking (that is, the conductive material contained in the external electrode paste). Specific examples include metal powders containing one or more elements selected from Ni, Cu, Ag, Fe, Pd, Pt, W and Ti, and among these, they are relatively inexpensive. Ni, Cu are particularly preferably used.

  The present embodiment has the greatest feature in that the metal powder as described above is attached to the electrode before baking, and baking is performed in a state where the metal powder is attached. Without adversely affecting the characteristics of the chip varistor 2, it is possible to effectively prevent the problem of adhesion between products during baking.

  The metal powder used in the present embodiment preferably has an average particle size of more than 0.05 μm and less than 60 μm, more preferably 1 μm or more and 20 μm or less. When the average particle diameter of the metal powder is too large, the metal powder is not sufficiently adhered to the pre-baking electrode, and the metal powder tends to fall off the pre-baking electrode. On the other hand, if the average particle size is too small, aggregation occurs and the powder tends to be difficult to handle.

Further, the ratio of the amount of the metal powder used with respect to the element body 8 is preferably in the range of 10 ⁻⁶ <weight of metal powder / weight of element body <0.225, more preferably 10 ⁻⁵ <metal. The weight of the powder / the weight of the element body <0.01. If the amount of metal powder used is too small, the above effects tend not to be obtained. On the other hand, if the amount used is too large, sintering of the external terminal electrode becomes insufficient, and when forming a plating layer made of Ni or Sn, the plating solution enters the element body, and the varistor voltage. There may be a case where characteristic deterioration such as a decrease in the quality occurs.

  The method for attaching the metal powder to the pre-baking electrode is not particularly limited. For example, a plurality of element bodies on which the electrode before baking and the metal powder are placed in a predetermined container, and then a plurality of elements Examples include a method of stirring the main body and the metal powder in a container.

  Next, the plurality of element bodies to which the metal powder is attached are placed on a baking container, placed in a baking furnace, and baked to form the external terminal electrode 10. The baking conditions are preferably about 10 minutes to 1 hour at 600 to 900 ° C. in an air atmosphere, for example. In this embodiment, since metal powder is adhered to the electrode before baking, adhesion between products can be effectively prevented without providing a special gap in the interval between products during baking.

  Next, in the external terminal electrode 10 after baking, a first plating layer containing Ni as a main component, and a second plating layer containing Sn as a main component on the surface of the first plating layer, To obtain a multilayer chip varistor 2. Although it does not specifically limit as a plating method for forming a 1st plating layer and a 2nd plating layer, For example, electrolytic plating etc. are mentioned. Thus, by forming the first and second plating layers made of Ni and Sn, the multilayer chip varistor 2 can be mounted with solder. In the present embodiment, when the external terminal electrode 10 is baked, since the glass component does not move to the electrode surface, the above-described first and second plating layers are formed uniformly and satisfactorily. Can do.

  The multilayer chip varistor 2 of the present embodiment manufactured as described above is used to absorb or remove an external surge (abnormal voltage) such as static electricity or noise.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in various aspects. .

  For example, in the above-described embodiment, the multilayer chip varistor is exemplified as the ceramic electronic component according to the manufacturing method of the present invention, but the ceramic electronic component according to the manufacturing method of the present invention is not limited to the multilayer chip varistor, Any electronic component having an external terminal electrode may be used.

  Hereinafter, although this invention is demonstrated based on a more detailed Example, this invention is not limited to these Examples.

Example 1
First, the varistor element body 8 shown in FIG. 1 was manufactured according to the method described above. In this embodiment, the interlayer voltage nonlinear resistor layer 4 and the outer protective layer 4a are formed of a varistor material mainly composed of ZnO, and the internal electrode layer 6 is formed of Pd.

Next, an external electrode paste was prepared.
The paste for external electrodes is: Ag powder: 70 parts by weight, glass frit made of B ₂ O ₃ —SiO ₂ —ZnO—Al ₂ O ₃ —SrO-based glass: 15 parts by weight, and ethyl cellulose as a binder: 5 parts by weight And 10 parts by weight of butyl carbitol as a solvent were mixed by a ball mill to prepare a paste.

  Next, the external electrode paste prepared above was applied to the end of the element body 8 and then dried to form a pre-baking electrode, thereby obtaining an element body having the pre-baking electrode.

  Next, the element body having an electrode before baking: 400 g and Ni powder were put in a predetermined plastic container, and then the element body and Ni powder were stirred to adhere the Ni powder to the electrode before baking. . In this example, Ni powders having various average particle diameters as shown in Table 1 were used, and the amounts used thereof were also shown in Table 1, and the average particle diameters of Ni powders and Sample numbers 1 to 9 having different usage amounts were prepared (however, Ni powder was not attached to sample number 1).

  Next, a plurality of element bodies in which Ni powder is adhered to the pre-baking electrode are placed on a baking container, placed in a baking furnace, and baked at 650 ° C. for 40 minutes. Formed. Next, a Ni plating layer (first plating layer) and a Sn plating layer (second plating layer) are formed on the surface of the external terminal electrode 10 by electrolytic plating, and sample 1 of the multilayer chip varistor shown in FIG. ~ 9 were produced.

And, using the varistor sample after baking the external terminal electrode, the adhesion rate between the products at the time of baking, the Ni, Sn plating layer using the varistor sample after forming the Ni, Sn plating layer The varistor voltage (V _{1 mA} ) after the formation was evaluated by the following method.

  The adhesion rate between products at the time of baking was evaluated by placing a plurality of samples after baking on a sieve and judging that the sample remaining on the sieve was a sample in which adhesion between products occurred. Specifically, the ratio of the weight of the sample remaining on the sieve to the weight of the entire sample applied to the sieve was calculated as the adhesion rate between products. The results are shown in Table 1. In the present example, a sieve having a predetermined mesh that passes through one sample but does not pass through the adhered sample was used.

The varistor voltage (V _{1 mA} ) is obtained by connecting a varistor sample formed with a Ni plating layer and a Sn plating layer to a DC constant current power source, and measuring a voltage acting between both electrodes of the varistor sample with a voltmeter. The current flowing through was read by reading with an ammeter. Specifically, when the current flowing through the varistor sample was 1 mA, the voltage acting between the electrodes of the varistor sample was read with a voltmeter, and the value was taken as the varistor voltage. The unit was V. The results are shown in Table 1. In this example, the range of ± 10% with respect to the rated voltage of 27V, that is, the range of 27 ± 0.27V was considered good.

  Table 1 shows the type, average particle diameter and amount used of the metal powder adhered to the electrode before baking, the ratio of the weight of the metal powder to the weight of the element body, the adhesion rate between products, and the varistor voltage after plating. Indicates. The weight of the element body was 400 g in all cases, and the average particle diameter of the metal powder was measured by the microtrack method using a laser diffraction scattering method (the same applies to Table 2 below).

From Table 1, the sample 1 in which the metal powder was not attached to the electrode before baking and the sample 2 in which the amount of adhesion was reduced both resulted in a higher adhesion rate between products. Further, in the sample 8 in which the amount of the metal powder used is increased, the external terminal electrode is not sufficiently sintered at the time of baking, and the plating solution enters the element body at the time of plating. The voltage has dropped. Furthermore, in the sample 9 using the metal powder having a large average particle size, the adhesion of the metal powder to the pre-baking electrode becomes insufficient, and the metal powder falls off from the pre-baking electrode. The adhesion rate has deteriorated.
On the other hand, all of the samples 3 to 7 in which the average particle diameter of the metal powder and the amount of the metal powder used are within the preferable range of the present invention can keep the adhesion rate between products low, and by plating It was confirmed that the reduction of the varistor voltage was also suppressed.

Example 2
A laminated chip varistor sample was produced in the same manner as in Example 1 except that the type, average particle diameter, and amount used of the metal powder were as shown in Table 2, and the same evaluation as in Example 1 was performed. .

  From Table 2, it can be confirmed that the same results can be obtained when Cu powder, Ag powder, Fe powder, Pd powder, Pt powder, W powder, and Ti powder are used instead of Ni powder.

FIG. 1 is a schematic sectional view of a multilayer chip varistor according to an embodiment of the present invention.

Explanation of symbols

2 ... Multilayer chip varistor 4 ... Interlayer voltage non-linear resistance layer 4a ... Outer protective layer 6 ... Internal electrode layer 8 ... Element body 10 ... External terminal electrode

Claims (5)

A method of manufacturing a multilayer chip varistor having external terminal electrodes,
A step of preparing an element body having an interlayer voltage nonlinear resistor layer, and an external electrode paste containing conductive powder and a glass component;
Applying the external electrode paste to the element body and then drying to form a pre-baking electrode; and
Attaching metal powder to the pre-baking electrode;
A step of baking the pre-baking electrode to which the metal powder is adhered to form an external terminal electrode,
The average particle diameter of the metal powder is larger than 0.05 μm and smaller than 60 μm,
In the step of attaching the metal powder, the ratio of the amount of the metal powder used to the element body is in the range of 10 ⁻⁶ <weight of metal powder / weight of element body <0.225.
Manufacturing method of multilayer chip varistor.   The method for manufacturing a multilayer chip varistor according to claim 1, wherein the metal powder is made of a metal having a melting point higher than that of the conductive powder contained in the external electrode paste.   The method for producing a multilayer chip varistor according to claim 2, wherein the metal powder contains one or more elements selected from Ni, Cu, Ag, Fe, Pd, Pt, W, and Ti.   The method for manufacturing a multilayer chip varistor according to claim 3, wherein the metal powder contains Cu. Forming a first plating layer mainly composed of Ni on the surface of the external terminal electrode;
Wherein the surface of the first plating layer, the manufacturing method of the laminated chip varistor according to any one of claims 1 to 4, further comprising a step of forming a second plating layer mainly composed of Sn, a.

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