JP4614937B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with reduced power consumption during standby. More specifically, the present invention relates to a configuration for reducing a standby current of a semiconductor memory device having a redundant circuit for relieving a defective memory cell, and a method for testing a semiconductor memory device with low power consumption.

  FIG. 51 is a diagram showing a configuration of a memory cell of a conventional static random access memory (SRAM). 51, a memory cell is connected between a memory cell power supply line MVCC and a node ND1, and has a P channel MOS transistor (insulated gate field effect transistor) PQ1 whose gate is connected to a node ND2, and a memory cell power supply. P channel MOS transistor PQ2 connected between line MVCC and node ND2 and having its gate connected to node ND1, and connected between node ND1 and memory cell ground line MVSS and having its gate connected to node ND2. N channel MOS transistor NQ1, N channel MOS transistor NQ2 connected between node ND2 and memory cell ground line MVSS and having its gate connected to node ND1, and conductive in response to the signal potential on word line WL When conductive, the node ND1 is set to the bit line BL. Including the N-channel MOS transistor NQ3 be hermetically connected to each other, the N-channel MOS transistor NQ4 which selectively turned on in response to a signal potential on word line WL, and to connect the conductive when the node ND2 to the complementary bit line ZBL.

  In the SRAM cell shown in FIG. 51, MOS transistors PQ1 and NQ1 form a CMOS (complementary MOS) inverter, and MOS transistors PQ2 and NQ2 form a CMOS inverter. These MOS transistors PQ1, PQ2, NQ1 and NQ2 constitute a CMOS inverter latch.

  Nodes ND1 and ND2 store complementary data. Therefore, in this SRAM cell, the current path between memory power supply line MVCC and memory ground line MVSS via nodes ND1 and ND2 is cut off during data storage, so that current consumption can be reduced. .

  The memory cell shown in FIG. 51 is called a full CMOS memory cell, and is superior in operation performance and low power consumption compared to a configuration in which pull-up load elements are provided for nodes ND1 and ND2, and has a low current consumption SRAM. In general.

  FIG. 52 schematically shows a planar layout of the SRAM cell shown in FIG. In FIG. 52, since this SRAM cell is a full CMOS cell, an N well region for forming P channel MOS transistors PQ1 and PQ2 and a P well for forming N channel MOS transistors NQ1 and NQ2 are provided. . In this N well region, active regions AA1 and AA2 for forming P channel MOS transistors PQ1 and PQ2 are formed symmetrically with respect to the center line extending in the vertical direction of FIG. These active regions AA1 and AA2 are P-type impurity regions. In the P well region, active regions AA3 and AA4 for forming N channel MOS transistors NQ1 and NQ2 are formed in a Γ shape symmetrically with respect to the center line. These active regions AA3 and AA4 are N-type impurity regions.

  Gate electrode wiring GA1 is formed so as to intersect with the laterally extending regions of active regions AA1 and AA3, and gate electrode wiring GA2 is disposed so as to intersect with the laterally extending regions of active regions AA2 and AA4. The These gate electrode lines GA1 and GA2 are, for example, polysilicon lines. In addition, gate electrode wiring GA3 is formed so as to intersect with the region extending in the vertical direction of active regions AA3 and AA4. This gate electrode wiring GA3 is connected to a word line.

  Gate electrode wirings GA1 and GA2 have regions extending in the lateral direction toward the central region. Gate electrode interconnection GA1 constitutes the gate electrodes of MOS transistors PQ1 and NQ3, and gate electrode interconnection GA2 constitutes the gate electrodes of MOS transistors PQ2 and NQ4. Gate electrode wiring GA3 forms the gate electrodes of MOS transistors NQ3 and NQ4.

  In order to interconnect these MOS transistors, local wirings LI1-LI7 are formed. These local wirings LI1-LI7 are formed by a borderless process with respect to the active regions AA1-AA4, and the local wirings LI1-LI5 formed above the active regions AA1-AA4 are directly associated with each other. Electrically connected to active regions AA1-AA4. That is, the local wiring LI1 electrically connects the active areas AA1 and AA2. Local interconnection LI2 electrically connects active regions AA1 and AA3, and local interconnection LI3 electrically connects active regions AA2 and AA5.

  The local wiring LI2 corresponds to the node ND1 shown in FIG. 51, and the local wiring LI3 corresponds to the node ND2 shown in FIG. These local wirings LI1-LI7 are formed by self-alignment with respect to the gate electrode wirings GA1-GA3, respectively, and no contact is formed in a portion where the local wirings LI2 and LI3 overlap with the gate electrode wirings GA1 and GA2. That is, after forming the gate electrode wiring, the local wiring is formed using the gate electrode wiring as a mask. At this time, the gate electrode wiring is covered with an insulating film, and a contact hole is formed in a contact portion with the local wiring in a later process. Therefore, an insulating film is formed between the gate electrode wiring and the local wiring, and a contact between the local wiring and the gate electrode wiring is not formed when the local wiring is formed.

  The local wiring LI2 is electrically connected to the gate electrode wiring GA2 through the contact hole CH1, and the local wiring LI3 is electrically connected to the gate electrode wiring GA1 through the contact hole CH2.

  On the other hand, the local wiring LI4 is electrically connected to the first layer metal wiring ML1 extending in the vertical direction of the upper layer through the contact hole CH3. Further, the local wiring LI5 is connected to the first layer metal wiring ML4 disposed in the upper layer through the contact hole CH4. The first layer metal wiring ML4 corresponds to the memory cell ground line MVSS and transmits the ground voltage. Local interconnections LI6 and LI7 are electrically connected to first layer metal interconnection ML2 extending linearly in the vertical direction in the figure via contact hole CH5. Further, the local wiring LI7 is connected to the first metal wiring ML3 extending linearly above the contact hole CH6. These first metal wirings ML2 and ML3 constitute bit lines BL and ZBL, respectively.

  The contact holes CH3-CH6 are formed by self-alignment with the gate electrode wirings GA1-GA3. The local wirings LI4-LI7 are also formed by self-alignment with the gate electrode wirings GA1-GA3, and the contact holes CH3-CH6 and the local wirings LI4-LI7 can be formed with a minimum pitch.

  The gate electrode wiring GA2 is electrically connected to the local wiring LI2 through the contact CH1, and the gate electrode wiring GA1 is electrically connected to the local wiring LI3 through the contact CH2. Since these local wirings LI2 and LI3 are formed by self-alignment with respect to gate electrode wirings GA1 and GA2, no contact is formed in a region where local wirings LI2 and LI3 and gate electrode wirings GA1 and GA2 overlap. Therefore, using these contacts CH1 and CH2, these local wirings LI2 and LI3 are electrically connected to gate electrode wirings GA2 and GA1, respectively.

  Local wiring LI1 is electrically coupled to memory power supply line MVCC arranged extending in the row direction by a second layer metal wiring (not shown).

  In the layout of the vertically long memory cell as shown in FIG. 52, bit lines BL and ZBL and memory cell ground line MVSS are first metal wirings and are arranged extending in parallel to the same metal wiring layer. The Along with the miniaturization of the memory cell, the distance between the first metal wires ML2 and ML3 and the first metal wires ML1 and ML4 is shortened, and a short circuit occurs between the bit lines BL and ZBL and the memory cell ground line MVSS. Is likely to occur.

  The extending direction of the memory cell power supply line MVCC is a direction parallel to the word line, and the memory cell power supply line MVCC extends in a direction perpendicular to the bit line.

  In the memory cell having the layout as shown in FIG. 52, when a short circuit occurs due to adhesion of foreign matter or the like during the manufacturing process, not only a malfunction occurs, but also current flows through this short circuit in the standby mode. Current and standby current failure occurs. That is, even if a defective memory cell is replaced with a redundant cell, the defect itself exists, so that a current flows through this short-circuit path during standby, thereby increasing the standby current. As a kind of short circuit in the memory cell, the following short circuit can be considered.

  (1) Node-node short; (2) Node-memory cell power supply line short; (3) Node-memory cell ground line short; (4) Node-word line short; (5) Node-bit line (6) Bit line-bit line short; (7) Word line-memory cell power line short; (8) Bit line-memory cell ground line short; and (9) Memory cell power line-memory Short between cell ground lines. Here, the bit line is precharged to the power supply voltage level during standby, and the word line is maintained at the ground voltage level during standby.

  In particular, in the layout of the vertically long memory cell as shown in FIG. 52, first layer metal wirings ML2 and ML3 forming bit lines BL and ZBL and first layer metal wirings ML1 and ML4 forming memory cell ground line MVSS are used. However, since they are arranged extending in parallel with the minimum design dimension, the probability that the above-described short between the bit line and the memory cell ground line will occur is very high.

  In the full CMOS memory cell composed of six MOS transistors shown in FIG. 51, when any one of (1) to (9) above occurs, complementary data is always stored in nodes ND1 and ND2. Therefore, there is always a path through which current flows, and a standby current failure occurs.

  Now, as shown in FIG. 53, a state is considered in which the resistance component RZ exists between the nodes ND1 and ND2 due to foreign matter or the like. Complementary data is stored in nodes ND1 and ND2. If the resistance value of the resistance component RZ is sufficiently small, the nodes ND1 and ND2 are short-circuited and data cannot be stored accurately, so that the memory cell is determined to be defective.

  In the standby state, word line WL is in a non-selected state, and its voltage level is L level. Therefore, MOS transistors NQ3 and NQ4 are in the off state. Consider a state in which the node ND1 is at the H level and the node ND2 is at the L level as shown in FIG. In this state, MOS transistors PQ1 and NQ2 are on, and MOS transistors PQ2 and NQ1 are off. Therefore, in this state, a path is formed through which a current flows from memory cell power supply line MVCC to memory cell ground line MVSS via MOS transistor PQ1, resistance component RZ, and MOS transistor NQ2.

  When the resistance value of resistance component RZ is sufficiently larger than the on resistance of MOS transistors PQ1 and NQ2 in the on state, nodes ND1 and ND2 are maintained at the H level and the L level, respectively, and accurate data retention is performed. Can be performed. Therefore, when the resistance value of the resistance component RZ is large, the memory cell does not have a malfunction although it has a standby current failure.

  As the power supply voltage applied through the memory cell power supply line MVCC becomes higher as described above, the on-resistance of the memory cell transistor is lowered, so that the resistance value of the resistance component RZ is relatively increased. However, the situation in which the standby current failure state does not occur but the failure does not occur appears more remarkably.

  Usually, in a semiconductor memory device having a large storage capacity, a redundant memory cell for replacement with a defective memory cell that does not operate normally is provided in order to improve the yield. The operation of replacing the defective memory cell with the redundant memory cell is performed according to the following procedure. Identifying the address of the defective memory cell; by cutting the fuse in the redundant program circuit with an energy beam such as a laser, the address of the defective memory cell is programmed and the defective memory cell is always kept in the non-selected state.

  When a defective memory cell is addressed, the redundant memory cell is addressed according to the defective memory cell address programmed in the redundant program circuit, and the defective memory cell is replaced with the redundant memory cell.

  A memory cell that causes a standby current failure as described above but does not cause an operation failure is a defective memory cell that increases the standby current and cannot satisfy the specification value of the standby current, and thus reduces the yield. However, since such a standby current failure / normal operation memory cell operates normally, its address cannot be specified by a normal test.

  Conventionally, the following procedure has been performed as a method for detecting such a standby current failure / normal operation memory cell. The test is executed by lowering the memory cell power supply voltage than in the normal use state. In this state, the on-resistance of the memory cell transistor increases as the gate voltage decreases, so that the resistance value of the resistance component RZ becomes relatively low. As a result, a memory cell that has a standby current failure and a normal operation at a normal power supply voltage is set to an operation failure state. A test is performed in this state to identify the address of the standby current failure / normal operation memory cell and replace it with a redundant memory cell.

  However, this standby current failure / normal operation situation becomes more prominent because the on-resistance of the memory cell transistor decreases as the memory cell power supply voltage becomes higher. Therefore, in the method of performing the test by lowering the memory cell power supply voltage below the normally used voltage level, this standby current failure / normal operation state may not be made apparent. For example, when the resistance value of the resistance component RZ is relatively large, even if the on-resistance of the memory cell transistor is increased, data can still be stored normally and the standby current failure / normal operation memory cell cannot be specified. In this state, the standby current is also reduced due to the increased on-resistance, and the standby current may not be defective. Further, when the test is performed in a state where the memory cell power supply voltage is lowered from the normal use state, there is a possibility that the memory cell that normally operates normally may be in a malfunctioning state.

  The above-mentioned standby current failure / normal operation state due to adhesion of foreign matter or the like is also caused by a pattern defect. In addition to the short circuit (short circuit) between the storage nodes, the same occurs in the short circuit (1) to (9) described above.

  If such a standby defective / normally operating memory cell exists, current consumption during standby increases, and this semiconductor memory device cannot be applied in applications such as portable devices that require low standby current.

  Further, in order to detect such a standby failure / normal operation memory cell, it is necessary to accurately detect the standby current. In addition, when redundant replacement is performed on a standby defective / normally operating memory cell, it is necessary to ensure that the standby current is smaller than the specified value by this redundant replacement. Need to be measured.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device capable of reliably reducing standby current.

  Another object of the present invention is to provide a semiconductor memory device and a test method thereof capable of accurately detecting the address of a standby defective and normally operating memory cell without adversely affecting the normal memory cell.

  Still another object of the present invention is to provide a test method for a semiconductor memory device which can replace a defective standby current and normal operation memory cell with a redundant memory cell and reliably reduce the standby current.

In one embodiment, a semiconductor memory device according to the present invention includes a plurality of memory cells, a plurality of memory power supply lines , a plurality of bit line pairs, a plurality of word lines, a plurality of power supply potential control units, and a plurality of bit lines. A potential control unit, a plurality of first potential control circuits, and a plurality of second potential control circuits are included. The plurality of memory cells are arranged in a matrix. The plurality of memory power supply lines are arranged corresponding to each column of the plurality of memory cells, and are connected to the plurality of memory cells in the corresponding column. The plurality of bit line pairs are arranged corresponding to each column of the plurality of memory cells, and are connected to the plurality of memory cells in the corresponding column. The plurality of word lines are arranged corresponding to each row of the plurality of memory cells, and are connected to the plurality of memory cells in the corresponding row.

The plurality of power supply potential control units are arranged corresponding to the plurality of memory power supply lines, each supplying a power supply voltage to the corresponding memory power supply line when activated, and deactivated according to the first specific operation instruction signal Is done. The plurality of bit line potential control units are arranged corresponding to the plurality of bit line pairs, each of which charges the bit line of the corresponding column when activated, and is deactivated according to the first specific operation instruction signal The

The plurality of first potential control circuits are arranged corresponding to the plurality of memory power supply lines, each activated in response to the second specific operation instruction signal, detecting the potential of the corresponding memory power supply line, According to the detection result, the potential of the corresponding memory power supply line is set to a potential according to the detection result. The plurality of second potential control circuits are arranged corresponding to the plurality of bit line pairs, each activated in response to the second specific operation instruction signal, detecting the potential of the corresponding bit line pair, According to the detection result, the potential of the memory power supply line connected to the memory cell in the same column as the bit line is set to a potential corresponding to the detection result.

By disconnecting the memory power supply line and bit line from the power supply voltage in the specific operation mode, when there is a standby current failure in the memory cell, the potential of the memory power supply line and bit line is lowered due to leakage current. Therefore, by determining the potential levels of the memory power supply line and the bit line and setting the potential of the memory power supply line according to the determination result, it is possible to determine whether or not a standby current failure exists .

  Thereby, standby current failure can be accurately detected and redundant replacement can be performed, and a semiconductor memory device with low current consumption can be realized.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, the semiconductor memory device includes a plurality of memory cell arrays 1 arranged in a matrix. In this memory cell array 1, SRAM cells are arranged, and redundant memory cells for repairing defective cells are also arranged. In memory cell array 1, word lines are arranged corresponding to memory cell rows, and bit line pairs are arranged corresponding to memory cell columns.

  The semiconductor memory device according to the present invention further includes a word line selection circuit 2 for driving a word line arranged corresponding to an addressed row of the memory cell array 1 to a selected state according to an address signal (not shown), and the memory cell array 1 A bit line load 3 which is arranged corresponding to each bit line pair and holds the corresponding bit line pair at a predetermined voltage level in a standby state, and a fuse program circuit 4 in which defective column information of the memory cell array 1 is programmed, The switch circuit 5 selectively transmits the power supply voltage VDD to the memory power supply line MVDL according to the program information of the fuse program circuit 4, and detects the potential on the memory power supply line MVDL when activated, and the memory power supply line according to the detection result A voltage control circuit 6 for setting the voltage level of the MVDL is included.

  Switch circuit 5 and voltage control circuit 6 are activated in accordance with test instruction signals TEST1 and TEST2 from test control circuit 7, respectively.

  Memory power supply line MVDL is arranged corresponding to each column of memory cell array 1. In this memory cell array 1, as will be described in detail later, memory power supply line MVDL is arranged extending in the column direction in parallel with bit lines BL and ZBL. In memory array 1, SRAM cells are arranged in a matrix, and each memory power supply line MVDL is coupled to the power supply node of the memory cell in the corresponding column.

  The fuse program circuit 4 includes fuse elements arranged corresponding to the respective columns of the memory cell array 1, and the fuse elements are programmed according to the good / bad of the corresponding column.

  Switch circuit 5 includes a switching element provided corresponding to each of memory power supply lines MVDL, and is selectively turned on in accordance with test mode instruction signal TEST1 and the output signal of fuse program circuit 4, and power supply voltage VDD is turned on when turned on. This is transmitted to the memory power line MVDL.

  Voltage control circuit 6 is activated when test instruction signal TEST2 is activated, and drives the corresponding memory power supply line MVDL to the ground potential level when the potential level of memory power supply line MVDL is equal to or lower than a predetermined potential level.

  When all the switch circuits 5 are set in the non-conducting state in the test mode, if there is a memory cell having a defective standby current in the memory cell array 1, the voltage of the memory power supply line MVDL decreases due to the leakage current. By detecting the drop, it is possible to detect a column having a standby current failure. When the voltage level of the memory power supply line becomes the ground voltage level, the stored data of the corresponding memory cell is lost, and this memory cell enters a malfunctioning state. Next, by reading the memory cell data, the storage data of the memory cell is different from the test write data (or normal data cannot be read), and the defective column can be specified.

  After specifying the memory cell column with the standby current failure, the fuse program circuit 4 is programmed to disconnect the memory power supply line MVDL arranged corresponding to the defective column from the power supply node. Thereby, the memory cell in the standby current failure / normal operation state is reliably detected, and the corresponding memory power line is disconnected from the power supply node, so that the standby current failure / normal operation memory cell is repaired by redundant replacement, and The standby current can be reduced.

  FIG. 2 is a diagram showing an electrical equivalent circuit of the memory cells of the memory cell array 1 shown in FIG. In FIG. 2, the memory cell SMC has a full CMOS cell structure composed of six MOS transistors Q1-Q6. MOS transistors Q1, Q3 and Q6 are arranged in alignment with the extending direction of word line WL, and MOS transistors Q5, Q4 and Q2 are arranged in alignment with the extending direction of word line WL.

  N-channel MOS transistor Q1 conducts when voltage level of storage node SN2 is at H level, and electrically connects node SN1 to memory ground line MVSL. P-channel MOS transistor Q3 conducts when voltage level of node SN2 is L level, and electrically connects node SN1 and memory power supply line MVDL. N-channel MOS transistor Q6 conducts when the signal potential on word line WL is at H level, and electrically connects node SN2 to bit line ZBL.

N-channel MOS transistor Q5 conducts when the signal potential on word line WL is at H level, and electrically connects node SN1 to bit line BL. P-channel MOS transistor Q4 conducts when voltage level of node SN1 is at L level , and electrically connects memory power supply line MVDL to node SN2. N channel MOS transistor Q2 conducts when node SN1 is at H level, and electrically connects node SN2 to memory ground line MVSL.

  In the arrangement of the memory cells shown in FIG. 2, memory ground line MVSL, bit lines BL and ZBL, and memory power supply line MVDL are arranged extending in a direction crossing word line WL.

  MOS transistors Q1 and Q3 form a first CMOS inverter, and MOS transistors Q2 and Q4 form a second CMOS inverter. MOS transistors Q5 and Q6 each form an access transistor that is turned on in accordance with a signal on word line WL.

  FIG. 3 schematically shows a planar layout of memory cell SMC shown in FIG. In FIG. 3, a memory cell has an N well for forming MOS transistors Q3 and Q4, a P well for forming MOS transistors Q1 and Q5, and a P well for forming MOS transistors Q6 and Q2. Including. P wells are arranged on both sides of the N well.

  In the central N well, the active regions A2 and A3 extend in the column direction and are formed in a rectangular shape. Similarly, in the P wells on both sides of the N well, the active regions A1 and A4 are respectively formed in a rectangular shape extending in the column direction.

  A gate electrode wiring G1 is formed so as to intersect with the active regions A1-A3, and a gate electrode wiring G2 is disposed in the horizontal direction so as to intersect with the active regions A2-A4.

  Further, the gate electrode wiring G3 is formed so as to intersect with the active region A4 in a rectangular shape with the gate electrode wiring G1 interposed therebetween, and the rectangular gate electrode wiring G4 is formed so as to intersect with the active region A1. Is done. Gate electrode line G1 forms the gate electrodes of MOS transistors Q1 and Q3, and gate electrode line G2 forms the gate electrodes of MOS transistors Q2 and Q4.

  Local wirings LL1 and LL2 are formed in a self-aligned manner with the gate electrode wirings G1-G4. When forming the local wirings LL1 and LL2 for self-alignment (self-alignment) with respect to the gate electrode, after forming the gate electrode and covering the gate electrode with an insulating film such as a sidewall, the substrate surface is exposed, Local wirings LL1 and LL2 are formed. Therefore, these local wirings LL1 and LL2 are formed by a borderless process with respect to active regions A1-A4. In a region where these local wirings LL1 and LL2 and active regions A1-A4 overlap, they are electrically connected. Connected.

  On the other hand, since local wirings LL1 and LL2 and gate electrode wirings G1-G4 are formed by self-alignment with respect to the gate electrode, there is no contact in the overlapping region. A contact is formed at a connection portion between the gate electrode wiring and the local wiring. Further, the local wiring is formed by exposing the substrate surface using the gate electrode wiring as a mask.

  In addition, in the isolation oxide film region outside the active region, the local wirings LL1 and LL2 are formed by a borderless process, so that the local wirings LL1 and LL2 are formed directly on these isolation oxide films, and the isolation oxide film Will not be etched.

  Local wiring LL1 electrically connects active regions A1 and A2, and local wiring LL2 electrically connects active regions A3 and A4. That is, the local wiring LL1 connects the drains of the MOS transistors Q1, Q3, and Q5 to each other. Further, the drains of MOS transistors Q2, Q6, and Q4 are interconnected by local interconnection LL2.

  Local line LL1 is electrically connected to gate electrode line G2 through contact CHe, and gate electrode line G1 is electrically connected to local line LL2 through contact CHd. The gate electrode wiring G3 is provided with a contact CHf for connecting to the word line, and the gate electrode wiring G4 is also provided with a contact CHg for connecting to the word line.

  Also in active region A1, contact CHa for connecting to the memory ground line is provided adjacent to gate electrode wiring G1 at one end, and contact CHh for connecting to bit line BL is connected to the gate electrode at the other end. It is provided adjacent to the wiring G4. Contacts CHb and CHi for connection to memory power supply lines are provided for active regions A2 and A3, respectively. These contacts are formed by self-alignment with respect to the gate electrode wiring.

  For active region A4, contact CHc is provided for connecting to bit line ZBL in a portion adjacent to gate electrode wiring G3, and for connecting to a memory ground line in a region adjacent to gate electrode wiring G2. A contact CHj is provided. The contacts for connecting to these bit lines, memory ground lines, memory power supply lines, and word lines are all formed by self-alignment with respect to the gate electrode wiring.

  In the memory cell layout shown in FIG. 3, local interconnections LL1 and LL2 form storage nodes SN1 and SN2, respectively. The contacts CHd and CHe are formed by forming contact holes in the gate electrode wirings G1 and G2 before forming the local wirings LL1 and LL2, and filling the contact holes when forming the local wirings LL1 and LL2. The

  In the arrangement of the horizontally long memory cells, the MOS transistors are arranged symmetrically, and the local wirings LL1 and LL2 are also symmetrical in shape and can be easily patterned. The local wirings LL1 and LL2 are generated by the borderless process with respect to the active regions A1-A4 and formed by self-alignment with respect to the gate electrode wirings G1-G4, thereby reducing the number of contacts and increasing the area occupied by the memory cell. Reduced. Further, the interval between the gate electrode wirings G1 and G2 can be shortened, and the area of the memory cell can be reduced.

  FIG. 4 schematically shows a metal wiring layout with respect to the memory cell layout shown in FIG. 4, portions corresponding to the layout shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 4, rectangular first metal wires Ma, Mb, and Mc extending in the row direction are arranged for contacts CHa, CHb, and CHc, respectively. These first metal interconnections Ma, Mb, and Mc are electrically connected to active regions A1, A2, and A4 through contacts CHa, CHb, and CHc, respectively. Here, the gate electrode wiring is formed of, for example, polysilicon, the local wiring is formed of, for example, tungsten, and the first metal wiring is formed of, for example, aluminum or copper.

  Similarly, first metal wirings Me, Mf and Mg having a rectangular shape extending in the row direction are arranged for contacts CHh, CHi and CHj. These first metal interconnections Me, Mf and Mg are electrically connected to active regions A1, A3 and A4 through contacts CHh, CHi and CHj, respectively.

  Contact CHg is electrically connected to first metal interconnection Md extending in the row direction in the central region of the memory cell. First metal interconnection Md forms a word line and is electrically connected to gate electrode interconnections G4 and G3 shown in FIG. 3 through contacts CHg and CHf, respectively. In the central portion of the memory cell in the row direction, only the gate electrode wiring and the local wiring are arranged, and the first metal wiring Md constituting this word line can be provided with a sufficient margin.

  Second metal interconnections MMa-MMe are arranged in the column direction. Second metal interconnection MMa is connected to first metal interconnection Ma via via hole Va. Second metal interconnection MMb is electrically connected to first metal interconnection Me through via hole Vf. Second metal interconnection MMc is connected to first metal interconnection Mb via via hole Vb and to first metal interconnection Mf via via hole Ve. Here, the second metal wiring is a wiring formed in an upper layer than the first metal wiring.

  Second metal interconnection MMd is electrically connected to first metal interconnection Mc via via hole Vc, and second metal interconnection MMe is electrically connected to first metal interconnection Mg via via hole Vd. .

  Second metal interconnections MMa and MMe constitute a memory ground line for transmitting ground voltage VSS, second metal interconnection MMc constitutes a memory power supply line for transmitting memory power supply voltage VDD, and second metal interconnections MMb and MMD are Bit lines BL and ZBL are respectively configured.

  Using the second metal wiring MMa-MMe, a memory power supply line, a memory ground line, and a bit line are provided extending in the column direction. The memory cell SMC has a horizontally long structure, and can widen the distance Db between the bit line BL and the ground line (VSS) and between the bit line ZBL and the ground line, and short circuit failure between the bit line and the ground line. The probability of occurrence of can be reduced. Thereby, standby current failure due to a short circuit between the bit line and the ground line can be suppressed.

  When such a horizontally long memory cell is used, as shown in FIG. 4, the memory power supply line MVDL is arranged in the direction orthogonal to the word line WL, and the interval Da between the bit line and the memory power supply line is sufficiently increased. However, there is a possibility that a short circuit may occur due to a foreign substance or the like, and when such a standby current failure occurs, such a standby current failure is relieved using the configuration shown in FIG.

  FIG. 5 schematically shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the present invention. 5, in the memory cell array 1, a plurality of rows and a plurality of columns of memory cells SMC are arranged. FIG. 5 representatively shows memory cells SMC arranged in 2 rows and 2 columns. Word lines WLa and WLb are arranged for memory cells SMC arranged in the row direction. These memory cells SMC have a horizontally long cell structure shown in FIGS.

  The word line WLa is driven by the word driver WDRa, and the word line WLb is driven by the word driver WDRb. These word drivers WDRa and WDRb are included in word line selection circuit 2 shown in FIG. 1, and drive corresponding word lines to a selected state in accordance with an output signal of an address decoding circuit (not shown). In standby state or non-selection, word lines WLa and WLb are held at the ground voltage level.

  Bit line pairs BLa, ZBLa and BLb and ZBLb are arranged corresponding to the columns of memory cells SMC. Bit lines BLa and ZBLa are provided with a bit line (BL) load circuit 13a for precharging these bit lines BLa and ZBLa to the power supply voltage level in the standby state, and BL load circuit 13b is applied to bit lines BLb and ZBLb. Is provided.

  Corresponding to each column of memory cells, memory power supply lines MVDLa and MVDLb are arranged extending in the column direction. Memory ground line MVSLa is arranged in parallel to bit lines BLa and ZBLa, and memory ground line MVSLb is arranged for bit lines BLb and ZBLb. In the configuration shown in FIG. 5, memory power supply lines MVDLa and MVDLb are separately provided for each memory cell column.

  Fuse program circuit 4 includes program circuits 14a and 14b provided corresponding to each memory cell column and storing information indicating whether or not the corresponding column includes a defective memory cell. Switch circuit 5 is provided corresponding to each of memory power supply lines MVDLa and MVDLb, and selectively shows memory power supply lines MVDLa and MVDLb according to the stored information of corresponding program circuits 14a and 14b and test instruction signal TEST1. Switch gates 15a and 15b that are disconnected from the power supply node not to be included are included.

  Voltage control circuit 6 is provided corresponding to each of memory power supply lines MVDLa and MVDLb, and is activated when test instruction signal TEST2 is activated, and the voltage levels of corresponding memory power supply lines MVDLa and MVDLb are set to a predetermined potential. Detection holding circuits 16a and 16b for determining whether or not the level is higher than the level and driving these memory power supply lines MVDLa and MVDLb to a voltage level corresponding to the determination result are included. Specifically, these detection holding circuits 16a and 16b drive the corresponding memory power supply lines MMVLa and MVDLb to the ground voltage level when the corresponding memory power supply lines MMVLa and MVDLb are equal to or lower than a predetermined potential level. , Hold its ground voltage level.

  FIG. 6 is a diagram showing an example of the configuration of program circuits 14a and 14b shown in FIG. Since these program circuits 14a and 14b have the same configuration, one program circuit 14 is representatively shown in FIG.

  In FIG. 6, a program circuit 14 includes a fusible link element (fuse element) 20a coupled to a power supply node, a P-channel MOS transistor 20b that electrically connects the link element 20a to a node 20d in accordance with a reset signal RST, N channel MOS transistor 20c driving node 20d to the level of ground potential according to reset signal RST, inverter 20e receiving delayed reset signal RSTD, and selectively conducting according to the output signal of delayed reset signal RSTD and inverter 20e, node 20d Transmission gate 20f for transmitting the potential of the inverter, inverter 20g for inverting a signal applied via the CMOS transmission gate 20f to generate a fuse program signal PF, and the fuse program Inverts No. PF an inverter 20h for transmitting the input of the inverter 20e.

  Link element 20a can be fused with an energy beam such as a laser, for example. When a defective memory cell is included in the corresponding column, link element 20a is fused.

  The reset signal RST is a reset signal that is activated upon power-on or system reset, and the delayed reset signal RSTD is a signal obtained by delaying the reset signal RST for a predetermined time. Inverters 20g and 20h constitute an inverter latch, and a signal transmitted when CMOS transmission gate 20f is turned on is latched to generate fuse program signal PF.

  The reset signal RST is activated when the power is turned on or when the system is reset, and is set to the H level for a predetermined period, and is normally held at the L level. When reset signal RST is set to H level, MOS transistor 20c is rendered conductive and node 20d is initialized to the ground voltage level. Next, when the reset signal RST returns to the L level, the MOS transistor 20b becomes conductive, and the link element 20a is electrically connected to the node 20d. When link element 20a is in a conductive state, power supply voltage VDD is transmitted to node 20b. On the other hand, when link element 20a is blown, since MOS transistor 20b is disconnected from the power supply node, node 20d maintains the L level.

  When the reset signal RST becomes H level and a predetermined period elapses, the delay reset signal RSTD rises to H level, and the CMOS transmission gate 20f becomes conductive. When this CMOS transmission gate 20f is turned on, the voltage at node 20d is applied to inverter 20g. When link element 20a is blown, since node 20d is at L level, fuse program signal PF from inverter 20g is at H level. On the other hand, when link element 20a is in a conductive state, node 20d is at the H level of the power supply voltage VDD level, so that fuse program signal PF from inverter 20g is at the L level.

  When reset signal RST returns to L level and delayed reset signal RSTD returns to L level, CMOS transmission gate 20f is turned off and inverter 20g is disconnected from node 20d. The fuse program signal PF is latched by an inverter latch circuit composed of inverters 20g and 20h.

CMOS transmission gate 20f is rendered conductive when node 20d is at L level, and the input node of inverter 20g is initialized to L level. Thereafter, when the reset signal RST returns to the L level, the voltage level of the input node of the inverter 20g is set to a voltage level corresponding to the voltage level of the node 20d . Thereafter, the CMOS transmission gate 20f is turned off, and noise in the blown link element 20a is transmitted to the inverter 20g to prevent the fuse program signal PF from adversely affecting the link element 20a. A fuse program signal PF corresponding to the state is generated.

  FIG. 7 is a diagram showing an example of the configuration of switch gates 15a and 15b shown in FIG. Since these switch gates 15a and 15b have the same configuration, the configuration of one switch gate 15 is representatively shown in FIG.

  In FIG. 7, a switch gate 15 includes a NOR circuit 22a that receives a fuse program signal PF and a test mode instruction signal TEST1 from a corresponding program circuit, an inverter 22b that inverts an output signal of the NOR circuit 22a, and an output signal of the inverter 22b. P channel MOS transistor 22c for selectively coupling memory power supply line MVDL to the power supply node.

  In the normal operation mode, test mode signal TEST1 is at L level. When there is a defective memory cell in the corresponding column, fuse program signal PF is at H level and the output signal of NOR circuit 22a is at L level. Therefore, in this case, the output signal of inverter 22b becomes H level, MOS transistor 22c is turned off, and corresponding memory power supply line MVDL is disconnected from the power supply node. That is, the power supply voltage VDD is not supplied to the memory cells in the column where the standby current defective memory cells exist. This prevents leakage current from flowing through the standby current defective memory cell during standby, thereby increasing the standby current.

  When all the memory cells in the corresponding column are normal memory cells, fuse program signal PF is at L level, and in the normal operation mode, the output signal of NOR circuit 22a is at H level, and in response, the output of inverter 22b The signal becomes L level. In this state, MOS transistor 22c is turned on, and power supply voltage VDD is supplied to memory power supply line MVDL.

  In the test mode, test mode instruction signal TEST1 is set to H level, and the output signal of NOR circuit 22a is fixed to L level. In this state, the output signal of inverter 22b is at H level, and MOS transistor 22c is turned off. That is, in the test mode, whether or not the voltage level of the memory power supply line MVDL is lowered due to the leakage current when the memory array is in the standby state with the memory power supply line MVDL being forcibly disconnected from the power supply node. , And the presence of a memory cell having a defective standby current is detected according to the detection result.

  FIG. 8 is a diagram showing an example of the configuration of detection holding circuits 16a and 16b shown in FIG. Since the detection holding circuits 16a and 16b have the same configuration, one detection holding circuit 16 is representatively shown in FIG. In FIG. 8, the detection holding circuit 16 selectively outputs the output of the inverter 24b in response to the inverter 24a receiving the signal of the memory power supply line MVDL, the inverter 24b receiving the output signal of the inverter 24a, and the test mode instruction signal TEST2. N channel MOS transistor 24c for transmitting a signal to memory power supply line MVDL is included.

  The input logic threshold value of the inverter 24a is set to a voltage level at which this voltage drop can be detected when the voltage of the memory power supply line drops due to a leak current during the test. In the test mode, test mode instruction signal TEST2 is set to H level, and MOS transistor 24c is turned on. Thus, inverters 24a and 24b constitute a so-called half latch that latches the potential level of memory power supply line MVDL. When the voltage level of the memory power supply line MVDL is lowered due to the leakage current, the inverter 24a amplifies the voltage drop, the output signal becomes high level, and the output signal of the inverter 24b becomes L level accordingly. By this inverter 24b, the memory power line MVDL at the intermediate voltage level is driven to the ground voltage level, and the standby current defective memory cell is surely set to the operation defective state. That is, the power supply node of the memory cell is set to the ground potential level, and the data stored in the memory cell is lost.

  In the normal operation mode, test mode instruction signal TEST2 is at L level, MOS transistor 24c is non-conductive, the output of inverter 24b is disconnected from memory power supply line MVDL, and inverters 24a and 24b are The detection of the voltage level of memory power supply line MVDL and the operation of driving / holding the voltage level of memory power supply line MVDL according to the detection result are prohibited.

  FIG. 9 is a diagram showing an example of the configuration of BL load circuits 13a and 13b shown in FIG. In FIG. 9, since these BL load circuits 13a and 13b have the same configuration, one BL load circuit 13 is representatively shown.

  BL load circuit 13 includes a P channel MOS transistor 26a provided for bit line BL and a P channel MOS transistor 26b provided for bit line ZBL. These MOS transistors 26a and 26b couple corresponding bit lines BL and ZBL to the power supply node in the standby state. In the access mode in which data is written / read, a control signal is applied to MOS transistors 26a and 26b. For example, at the time of data writing, these MOS transistors 26a and 26b are held in a non-conductive state. In FIG. 9, the circuit connection in the standby state of the BL load circuit 13 is equivalently shown. Therefore, any configuration can be used as the BL load circuit 13 as long as the bit lines BL and ZBL are coupled to the power supply node in the standby state.

  Word drivers WDRa and WDRb hold corresponding word lines WLa and WLb at the ground voltage level in the standby state. Therefore, any configuration can be used for this word driver as long as it holds the non-selected word line WL at, for example, the L level of the ground voltage level in the standby state.

  FIG. 10 is a signal waveform diagram representing an operation during a test of the semiconductor memory device according to the first embodiment of the present invention. Hereinafter, with reference to FIG. 10, the operation of the semiconductor memory device shown in FIG. 1 and FIGS.

  In the standby state in the test mode, the power supply voltage VDD is set to a voltage level higher than the voltage level VDDn used during normal operation. As a result, the standby current failure / normal operation state of the memory cell becomes apparent. Test mode instruction signals TEST1 and TEST2 are both at L level. At the time of detecting the standby current failure, the fuse program has not yet been performed, and the output signals of program circuits 14a and 14b shown in FIG. 5 are at the L level.

  In switch gates 15a and 15b, MOS transistor 22c is in a conductive state, and supplies power supply voltage VDD to corresponding memory power supply line MVDL. MOS transistor 22c has a current supply capability that is sufficiently large (ratio of channel width to channel length) to supply a sufficiently stable operation power supply voltage to the memory cells connected to corresponding memory power supply line MVDL. Set to have.

  In this state, in memory cell SMC, the power supply voltage applied through memory power supply lines MVDCLa and MVDLb is higher than the voltage level VDDn applied during normal operation, and there is a resistance component due to foreign matter or the like. In this case, the on-resistance of the MOS transistor in the memory cell is made sufficiently small, and the influence of the resistance component due to the foreign matter or the like becomes obvious. Thereby, the memory cell that may cause the standby current failure is surely set to the standby current failure state.

  Then, test mode instruction signal TEST1 is raised to H level, MOS transistor 22c is turned off in switch gates 15a and 15b, and memory power supply lines MVDLa and MVDLb shown in FIG. 5 are disconnected from the power supply node. During the period Ta in which the memory power supply line MVDL (MVDLa, MVDLb) is disconnected from the power supply node, a large voltage drop does not occur in the standby leakage current allowed by the normal specification value, and only the abnormal current at the standby time The period is set such that a large voltage drop occurs in the power supply line MVDL.

  When there is a memory cell with a defective standby current, the voltage level of the corresponding memory power supply line MVDL is lowered due to the leakage current. On the other hand, when there is no memory cell with a defective standby current, the voltage of the corresponding memory power supply line MVDL is reduced. The voltage level substantially maintains its precharge voltage level.

  When time Ta elapses, test mode instruction signal TEST2 is raised to H level, and detection holding circuits 16a and 16b shown in FIG. 5 are activated. That is, in the detection holding circuit 16 shown in FIG. 8, the MOS transistor 24c is turned on, the inverter 24a detects the voltage level of the corresponding memory power supply line MVDL, and the state of the output signal of the inverter 24a is set according to the detection result. Then, the voltage level of memory power supply line MVDL is set according to the output signal of inverter 24b. That is, when the voltage level of the memory power supply line MVDL is lowered due to the abnormal leakage current, the output signal of the inverter 24a becomes high level, and the inverter 24b accordingly drives the memory power supply line MVDL to the ground voltage level. . On the other hand, in the memory power supply line MVDL in which the voltage drop of the memory power supply line MVDL is small and a normal standby leakage current flows, in the detection holding circuits 16a and 16b, the output signal of the inverter 24a becomes a low level. Output signal becomes H level, and the memory power supply line MVDL is held at the operating power supply voltage level of the inverter 24b. That is, inverter 24a amplifies the potential level of memory power supply line MVDL, and inverter 24b further amplifies the output signal of inverter 24a, and sets the voltage level of memory power supply line MVDL to the power supply voltage or ground voltage level.

  Therefore, for the memory cell in which the standby current failure exists, the voltage level of the corresponding memory power supply line MVDL becomes the ground voltage level, so that the voltage levels of nodes SN1 and SN2 storing the internal data are both at the L level. As a result, the stored data is lost and a malfunction occurs.

  After setting test mode instruction signals TEST1 and TEST2 to the L level, the data stored in the memory cells is read, and it is determined whether data is normally stored in these memory cells. As a result, a memory cell in which no malfunction occurs and a standby current defect occurs can be reliably detected by forcibly setting the standby current defect / normal operation memory cell to the malfunction state. Can do.

  Now, specifically, it is considered that the abnormal current during standby is 1 μA or more, and the leakage current during normal standby is 1 nA or less. The time Ta shown in FIG. 10 is, for example, 20 μs. If the parasitic capacity of the memory power supply line MVDL is 10 pF, the memory power supply line MVDL has a voltage level of VDD− (1 μA · 20 μs) / The voltage level drops to 10 pF = VDD-2V. When the power supply voltage VDD is 3.6V, the voltage level of the memory power supply line MVDL is lowered to 1.6V. In this state, the memory cell having the standby current failure cannot be set to the operation failure state sufficiently. With respect to the memory power supply line MVDL lowered to 1.6V, the inverter 24a shown in FIG. 8 detects a drop in the voltage level. By setting the input logic threshold value of the inverter 24a to, for example, 2.0V, the output signal of the inverter 24a becomes high level, and the inverter 24b amplifies the output signal of the inverter 24a and The memory power supply line MVDL for the memory cell is driven to the ground voltage level, and the voltage level is maintained during the active state of the switch gate.

  On the other hand, when a normal standby leakage current of 1 nA flows through the memory power supply line MVDL, even if the parasitic capacitance of the memory power supply line MVDL is estimated to be as small as 1 pF, the voltage level is reduced only by 1 nA · 20 μs / 1 pF = 20 mV do not do. Therefore, memory power supply line MVDL through which this normal standby leakage current flows is driven to a normal power supply voltage level by inverter 24b shown in FIG.

  Time Tb is the time required for reliably driving the memory power supply line in the standby current defective state to the ground voltage level by inverter 24b shown in FIG. For example, if the drive current amount of the discharge N-channel MOS transistor included in the inverter 24b is 1 mA, even if the parasitic capacitance of the memory power supply line MVDL is 10 pF, the voltage of 4 ns is reduced to 40 ns. Cost. Therefore, if the period Tb during which the test mode instruction signal TEST2 is at the H level is set to 100 ns, for example, the memory power supply line MVDL in the standby current defective state can be sufficiently driven to the ground voltage level.

  FIG. 11 is a flowchart showing a test method for the semiconductor memory device according to the first embodiment of the present invention. A test method for the semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIG.

  First, test data is written in the memory cell of the memory cell array 1 shown in FIG. 1 (step S1). When the writing of the test data to the memory cell is completed, the power supply voltage VDD is then held higher than the normal use state, and this memory array is held in the standby state (step S2). In step S1, when test data is written, test data is written with the power supply voltage at the voltage level during normal use. Then, when the standby state is entered in step S2, the voltage level of power supply voltage VDD is set. However, it may be raised. These operations are performed by adjusting the power supply voltage level applied to the power supply terminal under the control of an external tester. In step S2, the power supply voltage VDD is made higher than that during normal use, thereby revealing the presence of a memory cell with a standby current failure / normal operation as described above.

  Next, test mode instruction signal TEST1 is set to H level (step S3), and the memory power supply line is separated from the power supply node. When a memory cell with a defective standby current is connected to the memory power line, the voltage level of the memory power line is lowered.

  Then, test mode instruction signal TEST2 is set to H level, the voltage level of each memory power supply line is detected, and the voltage level of the corresponding memory power supply line is set according to the detection result. That is, the voltage level of the memory power supply line whose voltage level has been reduced by the abnormal standby current is driven to the ground voltage level.

  Next, both of these test mode instruction signals TEST1 and TEST2 are set to L level (step S5), and the operation step of making the standby current defective memory cell appear to be in an operation defective state is completed.

  A memory cell with a defective standby current is supplied with a ground voltage at its power supply node, and stored data is lost. Next, the data stored in the memory cells are sequentially read (step S6).

  If the read memory cell data is different from the written test data (the storage data of the memory cell is both at the storage node and the read data is indefinite data), the address (column address) of this defective memory cell Is specified (step S7). Here, the address of the memory cell causing the operation failure is detected in the test mode for detecting the operation failure, and the standby current failure / normal operation memory cell is distinguished from the operation failure memory cell. This is because a malfunctioning memory cell does not always cause a standby current failure.

  After the defective memory cell is specified in step S7, the column address of the defective memory cell is programmed, and in the program circuit shown in FIG. 1, the link element of the program circuit corresponding to the defective column is blown. As a result, the memory power supply line connected to the memory cell having the standby current failure is disconnected from the power supply node. This prevents the standby current defective memory cell from causing an abnormal standby leakage current in the normal operation mode. The defective column address is used because the memory power supply line extends in the column direction, and the memory power supply line is arranged corresponding to each column of the memory cells.

  It should be noted that a malfunctioning memory cell may be disconnected from the power supply node of the corresponding memory power line regardless of whether the standby current is defective or normal.

  By programming the defective column address in step S8, the standby current failure / normal operation memory cell in the defective column is replaced with a redundant memory cell.

  In the configuration shown in FIG. 5, a switch gate is provided corresponding to each memory cell column, and the memory power supply lines are separated in units of memory cell columns. However, one switch gate may be provided for a plurality of columns of memory power supply lines. In this case, the size (current supply capability) of the MOS transistor 22c included in the switch gate 15 is set so that a sufficient operating current can be supplied to a plurality of columns of memory cells. In this configuration, replacement relief of memory cells with defective standby current is performed in units of a plurality of columns.

  In step S6, test mode instructing signal TEST1 and TEST2 may be held in the active state when reading data from the memory cell. That is, the memory cell data may be read in a state where the voltage of the memory power supply line MVDL is latched by the detection holding circuit 16.

  As described above, according to the first embodiment of the present invention, the memory power supply line extending in the column direction is separated from the power supply node in the test mode, the voltage level of the memory power supply line is detected, and the memory When the voltage level of the power supply line is lowered, the memory power supply line is driven to the ground voltage level, and the standby current failure memory cell can be reliably set to the operation failure state. Thereby, the standby current failure / normal operation memory cell can be set to an operation failure state, and this column address can be easily specified. Further, by disconnecting the memory power supply line having the standby current failure from the power supply node, the standby current failure can be reliably remedied.

[Embodiment 2]
FIG. 12 schematically shows a whole structure of the semiconductor memory device according to the second embodiment of the present invention. 12 also includes a fuse program circuit 4, a switch circuit 5, and a voltage control circuit 6, as in the first embodiment. The individual configurations of the fuse program circuit 4, the switch circuit 5, and the voltage control circuit 6 are the same as those used in the first embodiment. In the arrangement shown in FIG. 12, memory power supply line MVDL is arranged in parallel with the word line in memory cell array 1. For memory cell array 1, a word line selection circuit 2 and a bit line load 3 are provided as in the first embodiment.

  Therefore, in the arrangement shown in FIG. 12, memory power supply line MVDL is arranged in the row direction in memory cell array 1, and the detection holding circuit in voltage control circuit 6 and the switch in switch circuit 5 correspond to each row. A gate is provided. The memory cell has a vertically long cell structure shown in FIG.

  FIG. 13 schematically shows a structure of a main part of the semiconductor memory device shown in FIG. FIG. 13 schematically shows a configuration of a portion corresponding to memory cells SMC arranged in 2 rows and 2 columns, similarly to the configuration shown in FIG. BL load circuit 13a is provided for bit lines BLa and ZBLa, and BL load circuit 13b is provided for bit lines BLb and ZBLb. The word line WLa extending in the row direction is driven by the word driver WDRa, and the word line WLb is driven by the word driver WDRb.

  A memory ground line MVSLa extends in the column direction parallel to the bit lines BLa and ZBLa, and a memory ground line MVSLb extends in the column direction for the bit lines BLb and ZBLb. The

  On the other hand, a memory power supply line MVCLa is provided extending in the row direction corresponding to the word line WLa, and a memory power supply line MVCLb is provided extending in the row direction parallel to the word line WLb.

  Therefore, the configuration of this memory array is the same as that of the first embodiment shown in FIG. 5 except for the extending direction of memory power supply line MVCL.

  A detection holding circuit 46a, a switch gate 45a and a program circuit 44a are provided for the memory power supply line MVCLa, and a detection holding circuit 46b, a switch gate 45b and a program circuit 44b are provided for the memory power supply line MVCLb. The configurations of program circuits 44a and 44b, switch gates 45a and 45b, and detection and holding circuits 46a and 46b are the same as those shown in FIGS. Since memory power supply lines MVCLa and MVCLb are arranged extending in the row direction, standby current failure is detected in units of rows. In program circuits 44a and 44b, therefore, program circuits 44a and 44b are programmed according to the defective memory cell row.

  In the configuration of the semiconductor memory device shown in FIGS. 12 and 13, the memory power supply lines MVCLa and MVCLb are arranged in parallel with the word lines WLa and WLb in the row direction, respectively, as shown in FIGS. It is the same as the structure shown. Therefore, the test operation of the standby current defective memory cell is the same as the test method in the first embodiment. That is, switch gates 45a and 45b are turned off in accordance with test mode instruction signal TEST1, and memory power supply lines MVCLa and MVCLb are separated from the power supply node. Subsequently, the detection holding circuits 46a and 46b are activated according to the test mode instruction signal TEST2, respectively, to detect the voltage level drop of the corresponding memory power supply lines MVCLa and MVCLb, and the voltage level of the memory power supply line at the lowered voltage level is detected. Drive to ground voltage level.

  The layout of memory cell SMC in the second embodiment shown in FIGS. 12 and 13 is the same as the layout of the memory cell shown in FIG. Therefore, in the memory cell layout shown in FIG. 52, the memory cell is a so-called vertically long cell, the distance between the bit line and the ground line is short, and there is a high possibility that a short circuit will occur due to a resistance component such as a foreign substance. Even in such a case, the standby current defective memory cell can be detected and replaced with a redundant cell exactly as in the first embodiment.

  FIG. 14 is a flowchart showing a method for testing a semiconductor memory device in the second embodiment of the present invention. In the test method shown in FIG. 14, the operation up to step S7 for specifying a defective memory cell is the same as the test method in the first embodiment shown in FIG. When a defective memory cell is specified in step S7, since this memory power supply line MVCL is arranged extending in the row direction, a defective row address is specified, and this defective row address is programmed in the defective address program circuit. The At this time, fusing of the link element of program circuit 44 (44a, 44b) arranged corresponding to memory power supply line MVCL arranged corresponding to the defective row is performed. As a result, the memory power supply line MVCL arranged corresponding to the standby current defective row is separated from the power supply node, and an abnormal standby current is prevented from flowing.

  In the second embodiment as well, the memory power supply line MVCL arranged corresponding to the malfunctioning memory cell row may be disconnected from the power supply node regardless of whether the standby current is abnormal or normal.

  Also in the second embodiment, the memory power supply line MVCL is individually divided corresponding to each row, and switch gates 45a and 45b are provided respectively. However, the switch gates 45a and 45b may be provided for each of a plurality of rows.

  In the configuration shown in FIG. 13 as well, the current drive capability of MOS transistor (22c) included in switch gates 45a and 45b ensures that a sufficient operating current is stably supplied to the memory cells arranged in the corresponding row. It is made to have the drive capability which can be. In this case, redundant replacement is performed in units of a plurality of rows.

  As described above, according to the second embodiment of the present invention, even in a memory power supply line arranged extending in the row direction, the memory power supply line is separated from the power supply node in the test mode, and an abnormal standby is performed. The voltage level is lowered by the leakage current, and the lowered memory power line is driven to the ground voltage level. Therefore, as in the first embodiment, the standby current failure / normal operation memory cell can be reliably set to the operation failure state, and the standby current failure memory cell can be detected and replaced with the redundant memory cell. Accordingly, the standby current failure can be remedied, and the product yield can be improved.

[Embodiment 3]
FIG. 15 shows a structure of a main portion of the semiconductor memory device according to the third embodiment of the present invention. In FIG. 15, P channel MOS transistors 50a-50c are provided in parallel to MOS transistors 22ca-22cc in the switch gate provided for each of memory power supply lines MVDLa-MVDLc (MVCLa-MVCLc). NOR circuits 22aa-22ac and inverters 22ba-22bc are arranged corresponding to these MOS transistors 22ca-22cc, and these MOS transistors 22ca-22cc correspond respectively to NOR circuits 22aa-22ac and inverters 22ba-22bc. Conduction / non-conduction is controlled according to the set of output signals.

  That is, MOS transistor 22ca is set to a conductive / non-conductive state according to test mode instruction signal TEST1 and fuse program signal PFa, and MOS transistor 22cb is set to a conductive / nonconductive state according to test mode instruction signal TEST1 and fuse program signal PFb. Is set, and conduction / non-conduction of MOS transistor 22cc is controlled according to test mode instruction signal TEST1 and fuse program signal PFc.

  These fuse program signals PFa-PFc are generated from program circuits included in fuse program circuit 4 of the first or second embodiment, respectively.

The conduction / non-conduction of MOS transistors 50a-50c is controlled according to the voltage generated by reference voltage generation circuit 52. Reference voltage generating circuit 52 sets N-channel MOS transistor 53b driving node 53c to the ground voltage level in accordance with test mode instruction signal TEST1, and sets the voltage level of node 53c according to the amount of current discharged by MOS transistor 53b. P channel MOS transistor 53a. MOS transistor 53a has its gate and drain coupled to node 53c, and functions as a current / voltage conversion element. A control voltage for MOS transistors 50a-50c is generated from node 53c.

  When test mode instruction signal TEST1 is at L level, MOS transistor 53b is non-conductive in reference voltage generating circuit 52, and node 53c is held at the power supply voltage level. Therefore, in this state, MOS transistors 50a-50c are non-conductive, and do not affect the state of MOS transistors 22ca-22cc.

  On the other hand, when test mode instruction signal TEST1 attains H level, MOS transistor 53b is rendered conductive in reference voltage generating circuit 52, and the voltage level of node 53c is set according to the amount of drive current of MOS transistor 53a. The voltage generated by MOS transistor 53a at node 53c is a voltage level between power supply voltage VDD and the ground voltage level. Although the MOS transistors 50a-50c are turned on by the control voltage output from the reference voltage generating circuit 52, the resistance value thereof is, for example, several MΩ, and is in a high resistance conductive state. These MOS transistors 50a-50c in the high resistance conductive state function as pull-up resistors.

  In the test mode, when the MOS transistors 22ca-22cc are in a non-conductive state and the memory power supply lines MVDCLa-MVDLc (MVCLa-MVCLc) are disconnected from the power supply node for a long time, normal standby leakage current As a result, the voltage level of these memory power supply lines MVDLa-MVDLc (MVCLa-MVCLc) may be lowered, and it may be determined as a defective state. By setting the MOS transistors 50a-50c to a high resistance conductive state, a normal standby leakage current (about 1 nA) is supplied by these MOS transistors 50a-50c, so that a normal standby current flows. However, the voltage level of the memory power supply line MVDL does not decrease.

  When only MOS transistors 22ca-22cc are used, it is necessary that the voltage level of the memory power supply line does not decrease due to normal standby leakage current. In order to reduce the voltage level of the memory power supply line in the test mode, MOS transistor 22ca There is a restriction on the period during which −22 cc is in a non-conductive state. However, as shown in FIG. 15, since the MOS transistors 50a-50c are kept in the high resistance conduction state in this test mode, the voltage drop of the memory power supply line at the normal standby current does not occur. The margin for setting the signal TEST1 to the H level is increased, and the standby current defective memory cell can be accurately detected.

  In this reference voltage generating circuit 52, the voltage level of node 53c is set to a voltage level that balances the current supplied from MOS transistor 53a with the current discharged from MOS transistor 53b. The level of the reference voltage generated when the reference voltage generating circuit 52 is activated may be a voltage level at which the MOS transistors 50a-50c are in a high resistance conductive state of about several MΩ.

Further, the MOS transistor 53a and the MOS transistors 50a-50c may constitute a current mirror circuit, and the drive current of these MOS transistors 50a-50c may be adjusted by the mirror ratio.

  As described above, according to the third embodiment of the present invention, an element that is in a high-resistance conduction state in the test mode is provided in parallel with the switching transistor for disconnecting the memory power supply line in the test mode from the power supply node. The voltage drop of the memory power line through which the normal standby current flows can be suppressed, and the standby current defective memory cell can be accurately detected. In addition, a sufficient margin can be secured for the activation period of test mode instruction signal TEST1, and an accurate test can be performed.

[Embodiment 4]
FIG. 16 schematically shows a structure of a main portion of the semiconductor memory device according to the fourth embodiment of the present invention. In the arrangement shown in FIG. 16, bit lines, memory power supply lines, and memory ground lines are arranged extending in parallel in the column direction.

  The power supply voltage is supplied to the BL load circuits 13a and 13b via the bit line load power supply lines BVDLa and BVDLb, respectively. These bit line load power supply lines BVDLa and BVDLb are arranged corresponding to memory power supply lines MVDLa and MVDLb, respectively. That is, a set of the memory power supply line MVDL and the load power supply line is arranged for each column, and supplies the power supply voltage to the memory cell and the BL load circuit in the corresponding column, respectively.

  These bit line load power supply lines BVDLa and BVDLb are activated when test mode instruction signal TEST2 is activated, and the voltage levels of bit line load power supply lines BVDLa and BVDLb are detected, and corresponding memory power supply lines are detected according to the detection results. Load detection circuits 66a and 66b for setting voltage levels of MVDLa and MVDLb are provided.

  Bit line load power supply lines BVDLa and BVDLb are coupled to power supply nodes via switch gate circuits 65a and 65b, respectively. Switch gate circuits 65a and 65b include switching transistors provided for bit line load power supply lines BVDLa and BVDLb, and switching transistors provided corresponding to memory power supply lines MVDLa and MVDLb, respectively.

  In the configuration shown in FIG. 16, when standby current failure is detected, bit line load power supply lines BVDLa and BVDLb are also separated from the power supply node in the same way as memory power supply lines MMVLa and MVDLb, and bit line load power supply line BVDLa is separated. When an abnormal standby current flows through BVDLb and its voltage level drops, the voltage levels of corresponding memory power supply lines MVDLa and MVDLb are driven to the ground voltage level. As a result, a short-circuit failure related to the bit line, that is, a short-circuit related to the power supply node, a short-circuit between the power supply node and the bit line, a short circuit between the bit line and the word line, and a short circuit between the bit line and the memory ground line. In addition to defects, further detection is possible.

  That is, when an abnormal standby current flows through the bit line, the voltage level of the corresponding memory power supply line is driven to the ground voltage level, and the memory cell is forcibly set to a malfunctioning state. Thereby, a memory cell in a malfunctioning state can be detected by a normal test.

  FIG. 17 shows an example of a configuration related to one bit line pair having the configuration shown in FIG. In FIG. 17, switch gate circuit 65 (65a, 65b) includes NOR circuit 22a that receives fuse program signal PF and test mode instruction signal TEST1, inverter 22b that receives the output signal of NOR circuit 22a, and the output signal of inverter 22b. Conductive when L level, and when conducting, P channel MOS transistor 22c that electrically couples the power supply node to memory power supply line MVDL, and when the output signal of inverter 22b is at L level, conducts when the power supply node is conductive. P channel MOS transistor 65a electrically connected to bit line load power supply line BVDL.

  In the configuration of switch gate circuit 65, in addition to the configuration of the switch gate circuit in the first embodiment, a P channel MOS transistor 65a is further provided for bit line load power supply line BVDL. Therefore, when test mode instruction signal TEST1 attains H level, MOS transistors 65a and 22c are rendered non-conductive, and both bit line load power supply line BVDL and memory power supply line MVDL are disconnected from the power supply node. When a standby current failure associated with the bit line exists, the voltage level of the bit line load power supply line BVDL decreases, and by detecting this voltage drop, a standby current failure associated with the bit line can be detected. it can.

  Load detection circuit 66 includes an inverter 67a that receives the potential of bit line load power supply line BVDL, an N channel MOS transistor 67b that selectively conducts in accordance with the output signal of inverter 67a and transmits the ground voltage when conducting, and a test mode instruction It includes an N-channel MOS transistor 67c that conducts when signal TEST2 is at H level and electrically couples the drain of MOS transistor 67b to memory power supply line MVDL when conducting.

  Inverter 67a functions as a level detection circuit that detects the voltage level of bit line load power supply line BVDL. When the voltage level of bit line load power supply line BVDL falls below the input logic threshold value of inverter 67a, the output signal of inverter 67a becomes high level, and MOS transistor 67b at the next stage is turned on to transmit the ground voltage. When test mode instruction signal TEST2 is at H level, memory power supply line MVDL is driven to the ground voltage level by MOS transistors 67b and 67c. Therefore, the MOS transistor 67b functions as an amplification transistor that amplifies the output signal of the inverter 67a.

  The detection holding circuit 16 is different in configuration from the detection holding circuit 16 shown in the first embodiment. That is, the detection holding circuit 16 is electrically connected to the inverter 24d receiving the potential of the memory power supply line MVDL, the N-channel MOS transistor 24e transmitting the ground voltage when the output signal of the inverter 24d is at a high level, and the test mode. N channel MOS transistor 24c is rendered conductive when instruction signal TEST2 is activated (at the H level) and electrically couples the drain node of MOS transistor 24e to memory power supply line MVDL.

  In the configuration of the detection holding circuit 16 shown in FIG. 17, when the voltage level of the memory power supply line MVDL is lowered, the inverter 24d detects the voltage level drop of the memory power supply line MVDL, and the output signal becomes high level. MOS transistor 24e conducts and transmits the ground voltage. Therefore, when memory power supply line MVDL is lowered, memory power supply line MVDL is driven to the ground voltage level by MOS transistors 24e and 24c.

  When bit line load power supply line BVDL is normal and no voltage drop occurs, the output signal of inverter 67a is at L level, and MOS transistor 67b maintains a non-conductive state. On the other hand, in this state, if the memory power supply line MVDL is defective and a voltage drop occurs, MOS transistor 24e is turned on according to the output signal of inverter 24d, and memory power supply line MVDL is driven to the ground voltage level. The When the memory power supply line MVDL is driven to the ground voltage level, even if the MOS transistor 67c conducts in accordance with the test mode instruction signal TEST2, the MOS transistor 67b maintains the non-conducting state. There is no influence on the driving of the power supply line MVDL to the ground voltage level. Therefore, even when bit line load power supply line BVDL is normal and memory power supply line MBDL is defective, memory power supply line MVDL can be reliably driven to the ground voltage level.

  When the memory power supply line MVDL is normal and the bit line load power supply line BVDL is abnormal, the inverter 67a detects a voltage drop of the bit line load power supply line BVDL, and the memory power supply line MVDL is connected to the MOS transistor. 67b and 67c can be driven to the ground voltage level. In driving the memory power supply line MVDL to the ground voltage level, in the initial stage, the output signal of the inverter 24d is at the L level, and the MOS transistor 24e maintains the non-conducting state. The voltage level of the memory power line MVDL can be lowered. When the voltage level of the memory power line MVDL falls below the input logic threshold value of the inverter 24d, the output signal of the inverter 24d becomes high level, the MOS transistor 24e becomes conductive, and the memory power line MVDL is grounded at high speed. Driven to voltage level.

  When memory power supply line MVDL and bit line load power supply line BVDL are both normal, the output signals of inverters 24d and 67a are at L level, and MOS transistors 67b and 24e are both non-conductive. MVDL and bit line load power supply line BVDL maintain the power supply voltage level without causing any voltage drop even when MOS transistors 67c and 24c are turned on.

  The load detection circuit 66 and the detection holding circuit 16 are configured by an inverter for potential detection and a MOS transistor that is selectively turned on in accordance with an output signal of the inverter, whereby the bit line load power supply line BVDL and the memory power supply line Even when the voltage level of MVDL is different, memory power supply line MVDL can be reliably driven to the ground voltage level when a failure occurs.

  Bit line load power supply line BVDL is electrically coupled to bit lines BL and ZBL via P channel MOS transistors 26a and 26b included in BL load circuit 13, respectively. In this BL load circuit 13, the gates of MOS transistors 26a and 26b are coupled to the ground node, indicating that these MOS transistors 26a and 26b are always in a conductive state. However, this is only shown so that the gates of these MOS transistors 26a and 26b are connected to the ground node in order to emphasize the operation of the BL load circuit 13 in the standby state. A control signal such as another control signal (for example, a write enable signal indicating data writing) is applied to the BL load circuit 13. As in the first embodiment, therefore, the specific configuration of the BL load circuit 13 is arbitrary as long as it has a function of holding the bit lines BL and ZBL at the power supply voltage on the bit line load power supply line BVDL in the standby state. is there.

  As described above, the load detection circuit 66 detects a voltage drop in the bit line load power supply line BVDL. When the voltage drop of bit line load power supply line BVDL occurs, the voltage level of corresponding memory power supply line MVDL is driven to the ground voltage level. Thus, when a standby current abnormality occurs due to a defect related to the bit line such as a short circuit between the word line and the bit line, the memory power supply line MVDL is driven to the ground voltage level and connected to the corresponding bit lines BL and ZBL. The memory cell to be operated is set to a malfunctioning state. Therefore, bit lines BL and ZBL can be reliably set to the defective column state.

[Example of change]
FIG. 18 shows a configuration of a modification of the fourth embodiment of the present invention. The configuration shown in FIG. 18 differs from the configuration shown in FIG. 17 in the following points. In other words, in load detection circuit 66, two stages of cascaded inverters 67d and 67e are connected between inverter 67a and N channel MOS transistor 67b. Also in detection holding circuit 16, two stages of cascaded inverters 24f and 24g are connected between inverter 24d and N-channel MOS transistor 24e. The other configuration shown in FIG. 18 is the same as the configuration shown in FIG. 17, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 18, the output signal of inverter 67a is waveform-shaped by two cascaded inverters 67d and 67e, and a binary signal at the power supply voltage or ground voltage level is reliably generated. Similarly, also in the detection holding circuit 16, the output signal of the inverter 24d is waveform-shaped by the inverters 24f and 24g connected in cascade in two stages to generate a binary signal. Therefore, even if the voltage drop amount of bit line load power supply line BVDL and memory power supply line MVDL is small and the output signal of inverter 67a and / or inverter 24d is at an intermediate voltage level, In accordance with 67e and / or 24f and 24g, memory power supply line MVDL can be reliably driven to the ground voltage level, and a memory cell with standby current abnormality / normal operation normal can be reliably set to a normal operation defective state. it can.

  The semiconductor memory device testing method in the fourth embodiment is the same as that in the first embodiment, and the test is executed according to the flowchart shown in FIG.

  Bit line load power supply line BVDL and memory power supply line MVDL are divided corresponding to each column, and a standby current failure is detected for each bit line pair unit. However, the switch gate circuit 65 may be arranged for each of the plurality of columns so that the standby current abnormality is detected in units of the plurality of columns. The same applies to the following embodiments.

  P channel MOS transistor 65a in switch gate circuit 65 has a current drive capability capable of supplying precharge current in standby state and column current in data reading to corresponding bit lines BL and ZBL. Its size is adjusted.

  As described above, according to the fourth embodiment of the present invention, during the test, the load power supply line is also disconnected from the power supply node to detect the voltage drop, and when a voltage drop occurs, the corresponding memory power supply line is connected. By driving to the ground potential level, the memory cells in the corresponding column are set in a malfunctioning state. Therefore, it is possible to reliably set a memory cell with standby current failure / normal operation to an operation failure state and detect a memory cell with abnormal standby current. Further, a standby current abnormality based on an abnormality related to the bit line can be detected, and the standby current abnormality can be detected more reliably and repaired by replacement of the redundant memory cell.

[Embodiment 5]
FIG. 19 shows a structure of a main portion of the semiconductor memory device according to the fifth embodiment of the present invention. FIG. 19 shows a configuration for one memory power supply line MVDL and one bit line load power supply line BVDL, similarly to the configuration shown in FIG. In the configuration shown in FIG. 19, P channel MOS transistors 65b and 50i are connected in parallel to MOS transistors 65a and 22c in switch gate circuit 65, respectively. A reference voltage (control voltage) from reference voltage generating circuit 52 is applied to the gates of MOS transistors 65b and 50i. Similarly to the configuration shown in FIG. 15, reference voltage generating circuit 52 includes an N channel MOS transistor 53b responding to test mode instruction signal TEST1, and a P channel MOS transistor generating a voltage at node 53c when MOS transistor 53b is conductive. 53a is included.

  In the configuration shown in FIG. 19, the other configurations are the same as those shown in FIG. 18, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 18, in the test mode, a reference voltage at an intermediate voltage level is generated from reference voltage generating circuit 52, MOS transistors 65b and 50i are turned on in a high resistance state, and bit line load power supply line BVDL Further, the memory power supply line MVDL is prevented from lowering its voltage level due to the normal standby leak current. When a normal standby current flows, these bit line load power supply line BVDL and memory power supply line MVDL are held at the power supply voltage level by MOS transistors 65b and 50i in a high resistance conductive state.

Therefore, when a standby current abnormality occurs, even if one of the voltage levels decreases due to the standby normal current and the other voltage decreases due to the standby current or more, the power line through which such standby normal current flows it is possible to identify the power supply line or a standby current flows. Therefore, even when the voltage drop speeds of the bit line load power supply line BVDL and the memory power supply line MVDL are different from each other, the bit line load power supply line BVDL and the memory power supply line MVDL are accurately detected using the test mode instruction signal TEST2. It is possible to detect a standby current abnormality by detecting a voltage drop.

  As described above, according to the fifth embodiment of the present invention, the switching transistor that is in the high resistance conduction state in the test mode is provided in parallel with the switching transistor that disconnects the load power supply line and the memory power supply line in the test mode. A power supply line that causes a voltage drop due to an abnormal standby current can be identified from a memory power supply line and a load power supply line that generate a normal standby leakage current, and a memory cell having an abnormal standby current can be reliably set to a malfunctioning state. .

[Embodiment 6]
FIG. 20 schematically shows a structure of a main portion of the semiconductor memory device according to the sixth embodiment of the present invention. The semiconductor memory device shown in FIG. 20 differs from the semiconductor memory device shown in FIG. 5 in the following points.

  That is, voltage control circuit 6 latches the potentials of corresponding memory power supply lines MVDCLa and MVDLb when test mode instruction signal TEST2 is activated, corresponding to memory power supply lines MVDCLa and MVDLb, and switch gates according to the latch results. Latch circuits 200a and 200b are provided for setting the states of 215a and 215b, respectively. The latch circuits 200a and 200b are supplied with a power supply voltage input detection signal POR that is driven to an H level when the power is turned on. The latch circuits 200a and 200b receive a latch signal when the power is turned on by the power supply detection signal POR. Is initialized.

  Switch gates 215a and 215b selectively correspond to memory power supply lines corresponding to output program information of corresponding program circuits 14a and 14b, latch signals (voltages) of corresponding latch circuits 200a and 200b, and test mode instruction signal TEST1, respectively. Power supply voltage is transmitted to MVDLa and MVDLb. Other configurations shown in FIG. 20 are the same as those shown in FIG. 5, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 21 shows an example of the configuration of latch circuits 200a and 200b and the configuration of switch gates 215a and 215b shown in FIG. In FIG. 21, since latch circuits 200a and 200b have the same configuration, latch circuit 200 is representatively shown in FIG. 21, and switch gates 215a and 215b also have the same configuration. Therefore, in FIG. Is representatively shown. These switch gate 215 and latch circuit 200 are provided corresponding to memory power supply line MVDL. The memory power supply line MVDL supplies the power supply voltage VDD to the memory cells connected to the bit lines BL and ZBL. Bit lines BL and ZBL are coupled to a power supply node supplying power supply voltage VDD via BL load circuit 13. FIG. 21 also shows the state of the load transistor in the standby state for the BL load circuit 13.

  In FIG. 21, a latch circuit 200 includes a transfer gate 202 that electrically couples the memory power supply line MVDL to the node 203 in response to a test mode instruction signal TEST2, and a latch gate 201 that latches the voltage of the node 203 when activated. Including. Transfer gate 202 is formed of an N channel MOS transistor.

  Latch gate 201 includes a NOR gate 201 a that receives power-on detection signal POR and a signal (voltage) on node 203, and an inverter 201 b that inverts the output signal of NOR gate 201 a and transmits the inverted signal to node 203.

  The power-on detection signal POR is at the H level during the period from when the power is turned on until the power supply voltage VDD reaches a predetermined voltage level or stabilizes. This power-on detection signal POR maintains the L level in the normal operation mode. Therefore, when the power is turned on, the output signal of NOR gate 201a is initialized to the L level in accordance with power-on detection signal POR. In the normal operation mode, the NOR gate 201a operates as an inverter, and an inverter latch is formed by the inverter 201b and the NOR gate 201a.

  The switch gate 215 receives the fuse program information PF from the corresponding program circuit, the output signal of the NOR gate 201a included in the latch gate 201, and the output signal of the NOR gate 216 that receives the test mode instruction signal TEST1. Inverting inverter 217 includes a P-channel MOS transistor 218 that conducts in response to an output signal of inverter 217 and transmits power supply voltage VDD to memory power supply line MVDL when conducting.

  The detection holding circuit 16 has the configuration shown in FIG. 8, FIG. 17, or FIG. The driving power of the detection holding circuit 16 when driving the memory power supply line MVDL is sufficiently larger than the driving power of the inverter 201b of the latch gate 201. Thereby, the latch gate 201 latches the voltage level of the memory power supply line MVDL without adversely affecting the detection holding operation of the detection holding circuit 16.

  FIG. 22 is a timing diagram representing a test operation of the semiconductor memory device according to the sixth embodiment of the present invention. The operation of the semiconductor memory device shown in FIGS. 20 and 21 will be described below with reference to FIG.

  First, before the test operation, the power is turned on, the power-on detection signal POR is set to H level, and the latch gate 201 is reset. The fuse program information PF is at the L level because it is before the fuse blow. When this initial setting is completed, the voltage level of the power supply voltage VDD supplied to the memory power supply line MVDL is raised as compared with that in the normal operation mode. Thereby, contribution of resistance components, such as a short circuit, is enlarged.

In this state, test mode instruction signal TEST1 is set to H level. Accordingly, the output signal of NOR gate 216 becomes L level , MOS transistor 218 is turned off, and memory power supply line MVDL is isolated from the power supply node. Test mode instruction signal TEST2 is still at the L level, and transfer gate 202 maintains the non-conduction state. Detection holding circuit 16 is in an inactive state, and the detection holding operation for the voltage of memory power supply line MVDL is not performed.

  Test mode instructing signal TEST1 is set at an H level for 20 μs, for example, and therefore, when there is a leakage path through which standby abnormal current flows in memory power supply line MVDL, its voltage level drops.

  Next, in a state where the test mode instruction signal TEST1 is maintained at the H level, the test mode instruction signal TEST2 is set to an H level active state for 150 ns, for example. Accordingly, detection holding circuit 16 is activated, and the voltage level of memory power supply line MVDL is set according to the detection result. At this time, transfer gate 202 is rendered conductive, and node 203 is coupled to memory power supply line MVDL. In response, the voltage level of the memory power supply line MVDL set by the detection holding circuit 16 is transferred to the node 203 and latched by the latch gate 201.

  By this test mode, the column of the standby current abnormality can be completely set to a defective state.

  When this test mode is completed, both test mode instruction signals TEST1 and TEST2 are set to L level. The latch gate 201 stores information as to whether or not the corresponding column is a column in which the standby current abnormality has occurred. When memory power supply line MVDL is driven to the ground voltage level in this test mode, the output signal of latch gate 201 is at H level, and in switch gate 215, the output signal of NOR gate 216 is at L level. In response, the output signal of inverter 217 becomes H level, and MOS transistor 218 maintains a non-conductive state.

  In this state, a function test of the memory cell is performed using various test patterns. Consider a state where a short circuit RZa exists between the word line WLa and the memory power supply line MVDLa as shown in FIG. When the test is performed using various test patterns, the bit lines BLa and ZBLa have the memory power line MVDLa at the ground voltage level, and the memory cells connected to the bit lines BLa and ZBLa are normal. Therefore, the bit lines BLa and ZBLa are detected as defective columns.

  Further, when the word line WLa is in a non-selected state, even if the word line WLa is connected to the memory power supply line MVDCLa by the short circuit RZa, the memory power supply line MVDCa is at the ground voltage level. A rise to the voltage level is prevented. Therefore, in the memory block including the defective word line WLa, word line multiple selection in which a plurality of word lines are simultaneously driven to the selected state is prevented, and a block defect in which the entire memory block including the word line WLa is determined to be defective occurs. Absent.

  A memory power supply line MVDLa is connected to the word line WLa via a short circuit RZa. The load is larger than that of a normal word line, and the voltage level of the word line WLa rises slower than that of the normal word line. In particular, in the case of a horizontally long memory cell structure, when a word line is short-circuited, it is connected to the memory power supply line MVDL via a low-resistance metal wiring, so that the capacity of the memory power supply line MVDL with respect to this defective word line WLa. Is connected. This slows down the voltage change rate of the defective word line.

  Therefore, data cannot be accurately stored in the memory cell connected to the word line WLa, and it is determined that the memory cell connected to the word line WLa is defective. As a result, it is possible to accurately detect a cross defect composed of defective columns and defective rows with respect to the short circuit RZa. Thereafter, by programming the defective column and defective row address using the redundant column and redundant row, bit lines BLa and ZBLa and word line WLa are replaced with redundant bit line pairs and redundant word lines. Further, by blowing the fuse in the program circuit 14a shown in FIG. 20, the memory power supply line MVDL is separated from the power supply node, the current consumption is reduced, and the standby current abnormality is relieved.

  As described above, according to the sixth embodiment of the present invention, the voltage level of the memory power supply line corresponding to the defective column is forcibly set to the ground voltage level in the test mode, and the voltage level is set in the latch circuit. By latching, it is possible to detect both the defective column and the defective row, accurately detect the cross defect composed of the defective row and the defective column, and repair the defective row and the defective column by replacement.

  In particular, in a horizontally long memory cell as shown in FIG. 2, the word line and the memory power supply line MVDL or the word line and the bit line are often short-circuited by a low-resistance first layer metal wiring. In this case, the capacitor of the short-circuited memory power supply line or bit line is connected to the word line, the operation of the defective word line is slowed down, and the data write / read of the memory cell is accurately performed. Reading cannot be performed. Thereby, a defective word line can be reliably detected.

[Embodiment 7]
FIG. 23 schematically shows a structure of a main portion of the semiconductor memory device according to the seventh embodiment of the present invention. In the configuration shown in FIG. 23, each of bit line load power supply lines BVDLa and BVDLb is activated according to test mode instruction signal TEST2, and when activated, memory power supply according to the voltage levels of bit line load power supply lines BVDLa and BVDLb Load detection circuits 66a and 66b for setting the voltage levels of lines MVDLa and MVDLb, and latch circuits 200a and 200b for latching the voltage levels of memory power supply lines MVDLa and MVDLb when test mode instruction signal TEST2 is activated, are provided.

  Output signals (voltages) of latch circuits 200a and 200b are transmitted to switch gate circuits 265a and 265b arranged corresponding to bit line load power supply lines BVDLa and BVDLb, respectively. These switch gate circuits 265a and 265b are connected to memory power supply lines MVDLa and MVDLb and bit line load power supply lines BVDLa and BVDLb in accordance with test mode instruction signal TEST1, output signals of corresponding latch circuits 200a and 200b, and power-on detection signal POR. Controls connection with the power supply node. Bit line load power supply line BVDLa is coupled to bit lines BLa and ZBLa via BL load circuit 13a, and bit line load power supply line BVDLb is coupled to bit lines BLb and ZBLb via BL load circuit 13b.

  Memory ground line MVSLa is arranged in parallel with bit lines BLa and ZBLa, and memory ground line MVSLb is arranged in parallel with bit lines BLb and ZBLb. Memory power supply line MVDLa supplies a power supply voltage to memory cells SMC connected to bit lines BLa and ZBLa, and memory power supply line MVDLb supplies a power supply voltage to memory cells SMC connected to bit lines BLb and ZBLb.

  FIG. 24 shows a specific example of the configuration of latch circuits 200a and 200b and switch gate circuits 265a and 265b shown in FIG. Since latch circuits 200a and 200b have the same configuration, and switch gate circuits 265a and 265b have the same configuration, latch circuit 200 and switch gate circuit 265 arranged for bit lines BL and ZBL in FIG. The structure of is representatively shown.

  In FIG. 24, latch circuit 200 is selectively turned on in response to test mode instruction signal TEST2, and when turned on, transfer gate 202 for electrically coupling memory power supply line MVDL to internal node 203, and internal node 203 A latch gate 201 for latching the voltage is included. Latch gate 201 includes a two-input NOR gate 201 a that receives the voltage of internal node 203 and power-on detection signal POR, and an inverter 201 b that inverts the output signal of NOR gate 201 a and transmits the inverted signal to internal node 203.

  The latch gate 201a has its output signal reset to L level in response to the power-on detection signal POR activated when the power is turned on.

  Instead of power-on detection signal POR, latch gate 201a may be supplied with a signal that is at an H level in an operation mode other than the test mode (this configuration will be described later).

  Switch gate circuit 265 receives three-input NOR gate 266 that receives fuse program information PF from the corresponding program circuit, test mode instruction signal TEST1, and an output signal of NOR gate 201a included in latch gate 201, and an output of NOR gate 266. Inverter 267 for inverting the signal, conductive when output signal of inverter 267 is at L level, and when conductive, P channel MOS transistor 268 transmitting power supply voltage VDD to memory power supply line MVDL, and output signal of inverter 267 is at L level P channel MOS transistor 269 which conducts at the time of and transmits power supply voltage VDD to bit line load power supply line BVDL at the time of conduction is included.

  The load detection circuit 66 has the same configuration as the load detection circuit 66 shown in FIG. However, the load detection circuit 66 may have a configuration similar to that of the detection holding circuit 16 shown in FIG.

Bit line load circuit 13 has a configuration similar to that shown in the previous embodiment.
In the configuration shown in FIG. 24, test mode instruction signals TEST1 and TEST2 are activated according to the operation sequence shown in FIG. 22 in the test mode.

  FIG. 25 is a flowchart showing a test operation of the semiconductor memory device according to the seventh embodiment of the present invention. A test method for the semiconductor memory device shown in FIGS. 23 and 24 will be described below with reference to FIG.

Consider a state where a short circuit RZb exists between the word line WL and the bit line BLa as shown in FIG. First, the power supply voltage is turned on, the power-on detection signal POR is activated, and the latch gate 201 of the latch circuit 200 is initialized. The voltage at node 203 is set to the power supply voltage level (step S20).

Next, the power supply voltage VDD is set to a higher state than the normal operation, and the influence of the short circuit RZb is made obvious (step S21).

  Next, test mode instruction signal TEST1 is set to H level. Test mode instruction signal TEST2 is at the L level. By setting test mode instruction signal TEST1 to the H level, MOS transistors 268 and 269 are both rendered non-conductive in switch gate 265, and the power supply node, bit line load power supply line BVDL and memory power supply line MVDL are separated. (Step S22).

When the short circuit RZb exists between the word line WL and the bit line BLa, the voltage of the bit line load power supply line BVDLa is discharged through the short circuit RZb because the word line WL is in a non-selected state. The level drops. For example, by setting test mode instruction signal TEST1 to H level for a period of about 10 μs, the voltage level of bit line load power supply line BVDLa sufficiently drops.

Next, both test mode instruction signals TEST2 and TEST1 are set to the H level (step S23). Responsively, load detection circuit 66 (66a, 66b) is activated to detect the voltage levels of bit line load power supply lines BVDLa and BVDLb, and set the voltage levels of memory power supply lines MVDLa and MVDLb according to the detection result. The voltage level of bit line load power supply line BVDLa drops due to short circuit RZb , and therefore, the voltage level of memory power supply line MVDLa is driven to the ground voltage level by load detection circuit 66a. At this time, transfer gate 202 is rendered conductive in accordance with test mode instruction signal TEST 2, and the voltage level of memory power supply line MVDL is latched by latch gate 201.

  Next, test mode instruction signals TEST1 and TEST2 are set to L level (step S24). Accordingly, load detection circuit 66 is deactivated, and transfer gate 202 is rendered non-conductive. Corresponding latch circuit 200a stores information indicating that bit lines BLa and ZBLa are defective columns, and switch gate 265a provides memory power supply line MVDLa and bit line load power supply according to the latch information of latch circuit 200a. Line BVDLa is isolated from the power supply node.

  In this state, data writing and reading are executed using various data patterns (step S25). Since no power supply voltage is supplied to memory power supply line MVDCLa, accurate data is not stored in the memory cells connected to bit lines BLa and ZBLa, and therefore bit lines BLa and ZBLa are defective columns. It is determined.

The word line WL is connected to the bit line BLa via the short circuit RZb . In a horizontally long memory cell, the short circuit between the word line WL and the bit line is often formed by a low-resistance first-layer metal wiring. Therefore, the bit line BLa is connected to the word line WL as a load capacitor, and the voltage change of the word line becomes slow, and the memory cell connected to the word line WL performs accurate data writing / reading. I can't.

  Further, the supply of the power supply voltage VDD is cut off to the bit line load power supply line BVDLa, the voltage level thereof is low level, and the voltage levels of the bit lines BLa and ZBLa are also low level. Therefore, even when the word line WL is in a non-selected state, its voltage level is low level and does not rise to the intermediate voltage level, and multiple selection of word lines is prevented. Therefore, an erroneous determination that the memory cell block included in the word line WL is defective is prevented. As a result, the word line WL can be accurately determined as a defective word line, and a cross defect can be identified (step S26).

  Next, the address of this row and defective column is programmed, and fuse blow of program circuit 14a is performed, so that memory power supply line MVDLa and bit line load power supply line BVDLa are fixedly separated from the power supply node (step S27).

  Therefore, the load power supply line for supplying the column current to the bit line is separated from the power supply node in the test mode, and the voltage level of the memory power supply line is set and latched according to the voltage level to accurately detect the cross defect. be able to.

  In the configuration shown in FIGS. 23 and 24, the voltage level of the memory power supply line in the corresponding column is set according to the voltage level of bit line load power supply line BVDLa. Even when bit line load power supply line BVDL is arranged corresponding to a defective column, its voltage level is not forcibly set to the ground voltage level. However, when the test operation mode instruction signals TEST1 and TEST2 are both set to the L level during the test operation, it is sufficient if the bit line load power supply line BVDL is separated from the power supply node for an appropriate time. The bit line load power supply line BVDL can be driven to the ground voltage level.

  Further, since the power supply voltage of the memory cell is once driven to the ground voltage level by the load detection circuit 66, even if the memory power supply line MVDL is in a floating state at the time of the test, the voltage level is sufficiently low. When memory cells are selected, bit lines BL and ZBL are both driven to the ground voltage level in accordance with complementary data of the selected memory cells. Therefore, in the data writing / reading in the test operation mode, the bit lines The voltage level of load power supply line BVDL can be set to the low level of the ground voltage level.

[Embodiment 8]
FIG. 26 schematically shows a structure of a main portion of the semiconductor memory device according to the eighth embodiment of the present invention. In the configuration shown in FIG. 26, it is activated when test mode instruction signal TEST2 is activated, and detects the voltage levels of bit line load power supply lines BVDLa and BVDLb, and the voltage levels of memory power supply lines MVDCLa and MVDLb according to the detection result. Is activated when the test mode instruction signal TEST2 is activated, and when activated, the voltage levels of the memory power supply lines MVDLa and MVDLb are detected, and the memory power supply line MVDLa is detected according to the detection result. And detection holding circuits 16a and 16b for setting the voltage level of MVDLb.

  Latch circuits 200a and 200b are further provided for memory power supply lines MVDLa and MVDLb, respectively. These latch circuits 200a and 200b latch the voltages of the corresponding memory power supply lines MVDLa and MVDLb in the test operation mode, and control the operation of the switch gate circuits 265a and 265b according to the latch voltage. Further, the power-on detection signal POR is applied to these latch circuits 200a and b200b as in the sixth and seventh embodiments.

  The configuration of switch gate circuits 265a and 265b is the same as the configuration of switch gate circuit 265 shown in FIG. 24, and the configuration of latch circuits 200a and 200b is the same as the configuration of latch circuit 200 shown in FIG.

  The configuration shown in FIG. 26 is equivalent to the combination of the sixth and seventh embodiments. Therefore, when a short circuit between the word line and the bit line and a short circuit between the word line and the memory power supply line occur, a cross failure with the short circuit portion as an intersection can be detected exactly as in the sixth and seventh embodiments. And defective rows and defective columns can be remedied by redundant replacement.

[Embodiment 9]
FIG. 27 shows a structure of a main portion of the semiconductor memory device according to the ninth embodiment of the present invention. 27 shows a switch gate circuit 265, a latch circuit 200, a load detection circuit 66, and a detection holding circuit 16 provided for one bit line BL and ZBL. The configurations of the switch gate circuit 265 and the latch circuit 200 are the same as those shown in FIGS. 21 and 24. Corresponding components are assigned the same reference numerals, and detailed descriptions thereof are omitted.

  In the configuration shown in FIG. 27, test mode instruction signal TEST3 is applied to latch gate 201 in place of power-on detector signal POR. Test mode instruction signal TEST3 is set to H level in a mode other than the test operation mode, and is set to L level when performing the test mode.

  The configurations of the load detection circuit 66 and the detection holding circuit 16 are the same as those shown in FIG. 17 or FIG. 18. In FIG. 27, the detection holding circuit 16 and the load detection circuit 66 are shown in order to simplify the drawing. Shown in blocks.

  FIG. 28 is a timing chart representing an operation of the semiconductor memory device shown in FIG. The operation of the semiconductor memory device shown in FIG. 27 will be briefly described below with reference to FIG.

  In the standby state before entering the test operation mode, test mode instruction signals TEST1 and TEST2 are set to L level, and test mode instruction signal TEST3 is set to H level. Since the fuse blow in the program circuit has not yet been performed, the fuse program information PF is at the L level. Latch gate 201 is reset to an initial state in accordance with test mode instruction signal TEST3, and the output signal of latch gate 201 is at L level. Therefore, in switch gate circuit 265, the output signal of NOR gate 266 is at the H level, and accordingly the output signal of inverter 267 is at the L level, and MOS transistors 268 and 269 are turned on. Therefore, memory power supply line MVDL and bit line load power supply line BVDL are coupled to the power supply node and receive power supply voltage VDD.

  On the other hand, in the test mode for detecting the standby current abnormality, first, the test mode instruction signal TEST3 is set to the L level, and the latch gate 201 is released from the reset state. Next, test mode instruction signal TEST1 is set to the H level for a predetermined period (for example, 20 μs), the output signal of inverter 267 is set to the H level at switch gate 265, and power supply lines MVDL and BVDL are disconnected from the power supply node. The voltage level of the line MVDL is set according to the presence or absence of a short circuit failure.

  Next, test mode instruction signal TEST2 is set to H level, load detection circuit 66 and detection holding circuit 16 are activated, and the voltage level of memory power supply line MVDL is set to the voltage of bit line load power supply line BVDL and memory power supply line MVDL. Set according to the level. The voltage level of the memory power supply line MVDL is latched by the latch gate 201.

  When setting and latching of the voltage level of the memory power supply line are completed, test mode instruction signals TEST1 and TEST2 are both set to the L level, and test mode instruction signal TEST3 is maintained at the L level. Therefore, the latch gate 201 maintains the latched state, and the switch 265 selectively separates the bit line load power supply line BVDL and the memory power supply line MVDL from the power supply node according to the presence or absence of a short circuit failure.

  In this state, a cross defect can be detected by writing / reading data using various data patterns and detecting a defective memory cell.

  Test mode instruction signal TEST3 is set to H level in a mode other than the test operation mode, and latch gate 201 is maintained in the reset state. This prevents the latch circuit 200 from being set in an incorrect state even if alpha rays and neutrons are incident from a noise source before the test mode is performed after the power is turned on. In addition, the cross failure can be detected by latching the voltage level of the memory power supply line MVDL.

  In the configuration shown in FIG. 27, the voltage levels of both the bit line load power supply line BVDL and the memory power supply line MVDL are detected, and the voltage level of the memory power supply line MVDL is set. However, the configuration using test mode instruction signal TEST3 instead of power-on detection signal POR is also applicable to the previous sixth and seventh embodiments.

[Embodiment 10]
FIG. 29 schematically shows a structure of a main portion of the semiconductor memory device according to the tenth embodiment of the present invention. 29, this semiconductor memory device includes eight memory blocks BLK0 to BLK7, a global row decoder 100 that is provided in common to these memory blocks BLK0 to BLK7, and selects a row according to an address signal (not shown). Global column decoder 102 for selecting a column in BLK0-BLK7, write / read circuit 104 for writing / reading data to / from a memory cell in the column selected by global column decoder 102, and these memory blocks BLK0-BLK7 A switch circuit 106 for detecting a voltage level of a load power supply line and a memory power supply line that are arranged in common in a test, and setting a voltage level of the bit line load power supply line and the memory power supply line according to the detection result, and a defective column Memory power line provided for The Tsu DOO line load power supply line includes a fuse program circuit 108 for driving the ground voltage level. The fuse program circuit 108 also keeps the corresponding column selection signal of the global column decoder 102 in a non-selected state in order to always bring a defective column into a non-selected state.

  Since each of memory blocks BLK0 to BLK7 has the same configuration, FIG. 29 schematically shows the configuration of memory block BLK0. Memory block BLK0 includes a memory subarray MSR0 having memory cells arranged in a matrix, a local row decoder LDC0 that selects a row in memory subarray MSR0 according to a global row decode signal from the global row decoder and a local row selection signal (not shown). And local bit line peripheral circuit BPH0 provided for the bit line of memory sub-array MSR0.

  Local bit line peripheral circuit BPH0 is used to connect a local sense amplifier for reading data of a selected memory cell, a bit line load circuit, and a bit line pair corresponding to a selected column of a memory subarray to a global data line. Includes column selection gate.

  In the configuration of the semiconductor memory device shown in FIG. 29, the layout of the memory cells provided in memory sub-array MSR0 has a horizontally long memory cell layout as shown in FIGS. In the horizontally long memory cell, the length in the column direction is longer than that in the vertical direction (bit line direction). Therefore, in the memory subarray, bit lines are arranged extending in the column direction, and word lines are arranged extending in the row direction. This bit line is connected to the bit line lead line extending in the row direction and connected to the local bit line peripheral circuit BPH0. In this case, the memory power supply line and the bit line load power supply line are also provided in common in the memory blocks BLK0 to BLK7 in the row direction. Therefore, even in the horizontally long cell structure, in the so-called “T-type bit line configuration”, the standby current failure of the bit line load power supply line and the memory power supply line can be remedied by specifying the defective column address.

  30 schematically shows a structure of a memory sub-array of the semiconductor memory device shown in FIG. Memory subarrays MSR0-MSR7 are each divided into M unit memory blocks MB. The unit memory block MB has SRAM cells having a horizontally long structure arranged in 8 rows and M columns. Global word line GWL is arranged in common in the rows of memory sub-arrays MSR0-MSR7. A global word line selection signal from global row decoder 100 shown in FIG. 29 is transmitted onto global word line GWL.

  In each unit memory block MB, a word line WL is arranged corresponding to a row of memory cells. In each of memory sub-arrays MSR0 to MSR7, a bit line pair BLP is provided in common to the corresponding M unit memory blocks. Therefore, M bit line pairs BLP are arranged in each of memory sub arrays MSR0 to MSR7.

  A memory sub-array is selected using a memory block selection signal. Selection of a memory cell row is commonly performed in unit memory blocks (memory row blocks) aligned in the row direction by a global word line. In the case of SRAM, row and column addresses are simultaneously applied, and the main word line selection signal and global column selection signal of the global row decoder and global column decoder are combined with this memory block selection signal to the memory cells in the selected unit memory block. to access.

  FIG. 31 schematically shows a structure of sub memory block SMB related to one unit memory block MB in memory blocks BLK0 to BLK7. The sub memory block SMB includes a unit memory block MB and its peripheral circuits.

  In FIG. 31, in the unit memory block MB included in the sub memory block SMB, the memory cells SMC are arranged in 8 rows and M columns. A word line WL is provided corresponding to each memory cell row. Therefore, eight word lines WL are arranged in the unit memory block MB of the sub memory block SMB.

  Local row decode circuit 110 included in local row decoder LDC drives one of these eight word lines to a selected state in accordance with a signal on global word line GWL and a word line selection signal (not shown). (When the corresponding global word line is selected). In this case, the local row decoding circuit 110 may be selectively activated by a memory block selection signal. That is, in a unit memory block (memory row block) aligned in the row direction, a row (word line) may be driven to a selected state in one sub memory block.

  Bit lines BL and ZBL are arranged extending in the column direction, and memory power supply line MVDL is also arranged extending in the column direction in parallel with these bit lines BL and ZBL.

  In parallel with global word line GWL, bit line bit line load power supply line BVDL is arranged in common in sub memory blocks SMB arranged in alignment in the row direction. Bit lines BL and ZBL are coupled to local peripheral circuit 112 through bit line lead lines BLL and ZBLL extending in the row direction, respectively. Local peripheral circuit 112 electrically couples bit line lead lines BLL and ZBLL to corresponding global data lines GIO and ZGIO in accordance with global column selection signal GYL from the global column decoder and a memory block selection signal (not shown). .

  Main memory power supply line MVDCLM is arranged extending in the row direction in common to sub memory blocks SMB arranged in alignment in the row direction. The main memory power supply line MVDLM is electrically connected to the memory power supply line MVDL in each sub memory block. As will be described in detail later, in the memory sub-array MSR, the connection between the bit line pairs (columns) and the bit line lead line pairs of the M unit memory blocks is uniquely determined. Two bit line lead line pairs are arranged and coupled to corresponding local peripheral circuits. Therefore, the memory power line MVDL to which the main memory power line MVDCLM is coupled is also uniquely determined according to the position of the sub memory block in each memory sub array.

  Global data lines GIO and ZGIO are arranged extending in the row direction in common to the sub memory blocks of the row block, and are coupled to write / read circuit 104 shown in FIG. These global data line pairs GIO and ZGIO are arranged corresponding to each memory row block, and a total of M pairs of global data lines GIO and ZGIO are arranged.

  FIG. 32 schematically shows an example of a configuration of local row decode circuit 110 shown in FIG. In FIG. 32, row decode circuit 110 includes a word line drive circuit 110i provided for word line WLi. Word line drive circuit 110i drives word line WL to a selected state in accordance with a word line selection signal φi from a word line selection signal generator (not shown) and a signal on a corresponding global word line GWL. Eight word lines WL0 to WL7 are arranged for one global word line GWL. Word line selection signal φi is generated from, for example, a 3-bit row address signal.

  In this case, a 3-bit column address signal is decoded to generate a memory block selection signal for specifying a memory block, and a word line drive signal is generated by a logical product of the word line selection signal and the memory block selection signal. Also good. That is, the memory cell row may be selected only in the selected memory block.

  In FIG. 32, the word line drive signal is generated from an AND circuit, and global word line GWL and word line selection signal φi are set to the H level when selected. However, these may be negative logic signals that become L level when selected. When this negative logic signal is used, a NOR circuit is used as the word line drive circuit.

  FIG. 33 schematically shows an arrangement of bit lines in one memory block BLK. In memory block BLK, bit line pairs BLP0-BLPn extend in the column direction and correspond to memory cell columns in common to M sub-memory blocks SMB0-SMBn (n = M-1) included therein. Arranged.

  Bit line lead line pairs BLLP0 to BLLPn are arranged in sub memory blocks SMB0 to SMBn, respectively. That is, each bit line lead line pair BLLP0 to BLLPn is uniquely determined in advance according to the position of the sub memory block SMB. That is, the bit line lead line pair BLLPi arranged for the sub memory block SMBi is connected to the bit line pair BLPi.

  In this memory block, spare bit line pairs BLPs for redundant replacement are arranged and connected to corresponding spare local peripheral circuits 112-s through spare bit line pair lead-out line pairs BLLPs. Spare local peripheral circuit 112-s selects spare bit line pair BLPs in accordance with the memory block selection signal and spare global column selection signal GYLs. Spare local peripheral circuit 112-s is arranged in a spare sub memory block. Spare word lines for repairing defective rows by replacement are arranged in the spare sub memory block. Therefore, although not shown in the figure, a spare global word line is also arranged for global word line GWL, and a spare global data line is also arranged for global data lines GIO and ZGIO.

  Local peripheral circuits 112-0 to 122-n are provided corresponding to these bit line lead line pairs BLLP0 to BLLPn, and corresponding bit line lead lines according to global column selection signals GYL0 to GYLn and memory block selection signal BSi. Pair BLLP is connected to corresponding global data lines GIO and ZGIO. Spare peripheral circuit 112-s couples the corresponding spare bit line lead line pair to the spare global data line in accordance with spare global column selection signal GYLs and memory block selection signal φi. Here, the number of spare bit line pairs and spare word lines is appropriately determined in consideration of storage capacity and relief efficiency.

  FIG. 34 schematically shows a wiring layout of the unit memory block MB. As shown in FIG. 34, in one unit memory block MB, as an example, memory cells SMC are arranged in 8 rows and 4 columns. A pair of bit lines BL and ZBL is arranged corresponding to each column of memory cells SMC.

  A memory ground line MVSL is arranged outside the paired bit lines, and a memory power line MVDL is arranged between the paired bit lines. That is, the memory ground line MVSL, the bit line BL, the memory power supply line MVDL, and the bit line ZBL are alternately arranged in the first metal wiring layer. These memory ground lines MVSL, bit lines BL and ZBL, and memory power supply line MVDL are arranged extending in the column direction in common to unit memory blocks MB included in one memory block BLK.

  Extending in the row direction and corresponding to each memory cell row by the second layer metal wiring, global word line GWL, bit line load power supply line BVDL, global data line GIO, bit line lead lines BLL and ZBLL, global Data line ZGIO, main memory power supply line MVDCLM, and global column selection line GYL are arranged. These wirings are arranged corresponding to each row of memory cells, and these second layer metal wirings can be arranged with a sufficient margin and with the pitch of the memory cell rows.

  Bit line lead lines BLL and ZBLL are connected to predetermined bit lines BL and ZBL via via holes VIB. In unit memory block MB, bit lines BL and ZBL to which bit line lead lines BLL and ZBLL are connected are uniquely determined (see FIG. 33).

  Similarly, main memory power supply line MVDCLM is also electrically connected to memory power supply line MVDL provided for bit lines BLL and ZBLL connected to bit line lead lines BLL and ZBLL via via hole VIA. Is done. Main memory power supply line MVDCLM is connected to sub memory arrays aligned in the row direction, that is, memory power supply line MVDL arranged for bit lines in the same column in the memory row block.

  Therefore, when the bit lines BL and ZBL provided with the via hole VIB are defective, the memory cells in the same column of the unit memory blocks aligned in the row direction are all replaced with redundant cells. When a standby current failure has occurred, the main memory power supply line MVDCLM is disconnected from the power supply node, so that the memory cell having the standby current failure can be relieved and the memory cell having the standby current failure can be disconnected from the power supply node. The standby current abnormality can be surely remedied.

  In the arrangement shown in FIG. 34, in the second layer metal wiring, the signal amplitude of bit line lead lines BLL and ZBLL and global data lines GIO and ZGIO is small during data reading, and global word line GWL and global column The signal amplitude of the selection line GYL is large. However, bit line load power supply line BVDL is arranged adjacent to these global word lines GWL, and main memory power supply line MVDCLM is arranged adjacent to global column selection line GYL. These power supply lines Since BVDL and MVDCLM function as a shield layer, it is possible to prevent capacitive coupling noise from being transmitted to these small amplitude signal lines GIO, BLL, ZBLL, and ZGIO, and to accurately read data. be able to.

  FIG. 35 shows a structure of local peripheral circuit 112 shown in FIG. 35, local peripheral circuit 112 includes bit line load circuit 120 for pulling up the voltage levels of bit line lead lines BLL and ZBLL to power supply voltage VDD level, memory block selection signal BSi, and sense amplifier activation signal. Sense amplifier 122 that is activated in accordance with SE and global column selection signal GYL and drives global data lines GIO and ZGIO in accordance with signal potentials on bit line lead lines BLL and ZBLL, memory block selection signal BSi, and write activation signal A write column select gate 124 which selectively conducts according to WE and couples bit line lead lines BLL and ZBLL to global data lines GIO and ZGIO, respectively.

  Bit line load circuit 120 includes a P channel MOS transistor 125a connected between bit line load power supply line BVDL and bit line lead line BLL and having its gate connected to bit line lead line ZBLL, and bit line load power supply line BVDL. Is connected between bit line lead line ZBLL and its gate is connected to bit line lead line BLL, and is connected in parallel to P channel MOS transistor 125a and its gate is bit line lead line BLL. P channel MOS transistor 125c connected to, and P channel MOS transistor 125d connected in parallel to P channel MOS transistor 125b and having its gate connected to bit line lead line ZBLL.

  In the bit line load circuit 120, in the standby state, the MOS transistors 125c and 125d cause the voltage level on the bit line load power supply line BVDL to correspond to the corresponding bit lines BL and ZBL via the bit line lead lines BLL and ZBLL. Is precharged. At the time of data reading, the potential difference between bit lines BLL and ZBLL is detected by MOS transistors 125a and 125b, high potential bit line lead line BLL or ZBLL is maintained at power supply voltage VDD level, and bit line lead lines BLL and Latch the potential difference of ZBLL. At the time of data writing, MOS transistors 125a and 125b latch write data in accordance with write data applied via global data lines GIO and ZGIO.

  MOS transistors 125c and 125d pull up data line lead lines BLL and ZBLL to the power supply voltage level on bit line load power supply line BVDL, respectively, and release the latched state of MOS transistors 125a and 125b at the transition to the standby state. To be provided.

  Sense amplifier 122 includes N channel MOS transistors 126a and 126b for detecting a potential difference between bit line lead lines BLL and ZBLL, and a sense amplifier activating MOS transistor 126c for activating sense amplifier 122. An output signal of AND circuit GA1 receiving memory block selection signal BSi and sense amplifier activation signal SE is applied to the gate of MOS transistor 126c. The output signal of the NAND circuit receiving global column selection signal GYL and sense amplifier activation signal SE is applied to the source of MOS transistor 126c.

  Note that global column selection signal GYL, memory block selection signal BSi, and sense amplifier activation signal SE are all at H level, the corresponding memory block is designated, and a row block (a block constituted by subarrays aligned in the row direction) When designated, the sense amplifier 122 is activated. Therefore, the sense amplifier 122 is activated in one sub memory block SMB. When sense amplifier 122 is activated, global data lines ZGIO and GIO are driven by MOS transistors 126a and 126b in accordance with the potential difference between bit lines BLL and ZBLL. For example, when the potential of the bit line lead line BLL is higher than the potential of the bit line lead line ZBLL, the conductance of the MOS transistor 126a becomes larger than the conductance of the MOS transistor 126b, and the potential level of the global data line ZGIO is lowered. Let Thereby, a read signal having a small amplitude can be transmitted from bit line lead lines BLL and ZBLL to global data lines GIO and ZGIO. These global data lines GIO and ZGIO are provided with load circuits, and these global data lines GIO and ZGIO are precharged to the H level in the standby state.

  Write column select gate 124 is turned on when both memory block select signal BSi and write activation signal WE are active, and connects bit line lead lines BLL and ZBLL to global data lines GIO and ZGIO, respectively. N channel MOS transistors 128a and 128b. At the time of data writing, write data from a write driver (not shown) is transmitted to bit line lead lines BLL and ZBLL via global data lines GIO and ZGIO.

  Here, the output signal of AND circuit GA3 receiving memory block selection signal BSi and write activation signal WE is applied to MOS transistors 128a and 128b of write column selection gate 124. Therefore, in each sub memory block in the memory block, the bit line lead line is connected to the corresponding global data line. In a memory sub-block in which the global word line is not selected, the word line is not selected. Even if the bit line lead line is connected to the global data line, the global data line is set to the power supply voltage level by the load circuit. In particular, the column selection gate is provided in the final stage write / read circuit, and the write data is not transmitted to the non-selected memory sub-block, and no particular problem occurs.

  By activating the sense amplifier 122 only in the sub memory block including the selected memory cell, the current consumption during the sensing operation is reduced.

  FIG. 36 schematically shows a configuration of write / read circuit 104 shown in FIG. 36, write / read circuit 104 is provided corresponding to each of global data lines GIO0, ZGIO0-GIOn, ZGIOn, and corresponding global data lines GIO0, ZGIIO0-GIOn, ZGIOn according to global column select lines GIL0-GIILn. Are connected to main data lines MIO, ZMIO, load circuits GLD0-GLDn provided corresponding to global data lines GIO0, ZGIO0, GIOn, ZGIOn, respectively, and activated when data is read. Preamplifier 130 for amplifying data on data lines MIO and ZMIO, output buffer 132 for outputting data amplified by preamplifier 130 to the outside, and input for generating internal write data in accordance with write data DI from the outside Includes a Ffa 136 is the data write activation, from the input buffer 136 amplifies the internal write data, the write driver 134 for transmitting main data line MIO, the ZMIO.

  Write / read circuit 104 is further provided for spare global data lines GIOs and ZGIOs. When a defective column is accessed, global spare data lines GIOs and ZGIOs are connected to main data line MIO and global spare column selection signal GYLs. Spare column selection gates CSGs connected to ZMIO are included. Load circuit GLDs is arranged for spare global data lines GIOs and ZGIOs.

  Each of load circuits GLD0 to GLDn and GLDs has a configuration similar to that of bit line load circuit 120 shown in FIG. Column selection gates CSG0 to CSGn couple corresponding global data lines to main data lines MIO and ZMIO when global column selection signals GYL0 to GYLn are selected.

  FIG. 37 schematically shows an arrangement of wirings related to sub memory blocks (memory row blocks) aligned in the row direction. Unit memory blocks MB are aligned in the row direction. A memory row block is constituted by the unit memory blocks MB arranged in alignment in the row direction. A global word line GWLj is provided in common to the memory row blocks, and a bit line load power supply line BVDLj is provided in parallel with the global word line GWLj. A global data line pair GIOPj is provided in common to the unit memory blocks MB of the memory row block, and a main memory power supply line MVDLj is provided in parallel with the global data line pair GIOPj.

  In unit memory block MB, for example, eight word lines WL are arranged in the row direction. A bit line pair BLP is arranged in the column direction of the unit memory block MB in common with the sub memory blocks of the memory block. In unit memory block MB in the memory row block, bit line pair BLPj is coupled to global data line GIOPj through bit line lead line pair BLLPj.

  At the time of data reading / writing, bit line lead line pair BLPj provided for one unit memory block MB in this memory row block is selected according to memory block selection signal BSi and coupled to global data line pair GIOPj. The A memory power supply line MVDLj is arranged in parallel with the bit line pair BLPj, and the memory power supply line MVDLj is connected to the main memory power supply line MVDCLMj. Global data line pair GIOPj is coupled to main data line pair MIOP via column select gate CSGj.

  Therefore, bit line load power supply line BVDLj and main memory power supply line MVDCLMj arranged for the memory row block supply the power supply voltage, column current, and memory cell power supply voltage to bit line pair BLPj, respectively. Therefore, when a standby current failure occurs, for the column of the standby current failure, the bit line pair that causes the standby current failure is separated by disconnecting the main memory power supply line and the bit line load power supply line BVDLj from the power supply node. It can be disconnected from the power supply node, and standby current abnormality can be relieved.

  In this case, at the time of replacement of the bit line pair that causes the standby current abnormality, the corresponding column is replaced with the redundant column in each of the unit memory blocks MB in the memory row block. This is because, in a memory row block constituted by memory blocks, a bit line pair to which a global data line is connected is uniquely determined, and this memory row block is equivalently designated by a global column selection signal GYL. Therefore, at the time of defective address programming of global column selection signal GYL, it is necessary to perform redundant replacement in the entire memory row block.

  FIG. 38 shows a structure of a portion provided corresponding to one memory row block of global column decoder 102, switch circuit 106 and fuse program circuit 108 shown in FIG. 38, global column decoder 102 includes a global column decoding circuit 102j that generates global column selection signal GYLj. Bit line pairs in the same column in the unit memory block included in the memory row block are designated in accordance with global column selection signal GYLj from global column decode circuit 102j.

  The fuse program circuit 108 includes a fuse program circuit 108j that generates a fuse program signal PFj. The configuration of the fuse program circuit 108j is the same as the configuration of the fuse program circuit 14 shown in FIG.

  Switch circuit 106 includes a voltage control circuit 106j for controlling the voltage levels of bit line load power supply line BVDLj and main memory power supply line MFDLMj in accordance with fuse program signal PFj and test mode instruction signals TEST1 and TEST2 from fuse program circuit 108j. .

  Voltage control circuit 106j conducts when NOR circuit 140g receives test mode instruction signal TEST1 and fuse program signal PFj, inverter 140h receives the output signal of NOR circuit 140g, and when the output signal of inverter 140h is at the L level. P channel MOS transistor 140j that couples the node to bit line load power supply line BVDLj and P channel MOS transistor 140i that conducts when the output signal of inverter 140h is at L level and couples the power supply node to main memory power supply line MVDCLMj are included.

  In the test mode, test mode instruction signal TEST1 becomes H level, the output signal of NOR circuit 140j becomes L level, and the output signal of inverter 140h becomes H level accordingly. In this state, MOS transistors 140j and 140i are both rendered non-conductive, and the power supply node, bit line load power supply line DVDLj and main memory power supply line MVDLMj are disconnected.

  As for fuse program signal PFj from fuse program circuit 108j, if defective column BLPj exists in the corresponding memory row block, fuse program signal PFj becomes H level due to fusing of the link element included therein. . MOS transistors 140j and 140i are always non-conductive, and bit line load power supply line BVDLj and memory power supply line MVDCLMj are both disconnected from the power supply node. This prevents a standby current abnormality caused by a defective memory cell during normal use.

  Voltage control circuit 106j further includes an inverter 140a that receives a signal (voltage) on main memory power supply line MVDCLMj, two-stage cascaded inverters 140b and 140c that receive the output signal of inverter 140a, and the output of inverter 140c. N-channel MOS transistor 140m that conducts when the signal is at H level and transmits the ground voltage when conducting, and conducts when test mode instruction signal TEST2 is at H level, and electrically connects the drain node of MOS transistor 140m to main memory power supply line MVDLMj. N-channel MOS transistor 140n, an inverter 140d receiving a signal (voltage) on bit line load power supply line BVDLj, an inverter 140e receiving an output signal of inverter 140d, and an output signal of inverter 140d Received two-stage cascaded inverters 140e and 140f, conductive when output signal of inverter 140f is at H level, N channel MOS transistor 140p transmitting ground voltage when conductive, and test mode instruction signal TEST2 are at H level N channel MOS transistor 140q which is conductive at the time and electrically couples the drain node of MOS transistor 140p to main memory power supply line MVDLMj.

  Inverters 140a and 140d function as a potential detector, inverters 140b and 140c function as a waveform shaping circuit to convert the output signal of inverter 140a into a binary signal, and inverters 140e and 140f waveform the output signal of inverter 140d. A binary signal is generated by shaping.

  In the test mode, when test mode instruction signal TEST1 attains H level, bit line load power supply line BVDLj and main memory power supply line MVDCLMj are disconnected from the power supply node. In the corresponding memory row block, when a memory cell having a defective standby current is connected to the bit line pair BLPj, the voltage level of these bit line load power supply line BVDLj or main memory power supply line MVDCLMj decreases. The potential drop of power supply lines MVDCLMj and BVDLj is detected by inverter 140a or 140d, the output signal of inverter 140c or 140f becomes H level, and MOS transistor 140p or 140m is turned on.

  Thereafter, test mode instruction signal TEST2 is set to H level, and MOS transistors 140n and 140q are turned on. Output signals of inverters 140d and 140e are transmitted to main memory power supply line MVDLMj. If MOS transistor 140m or 140p is conductive, main memory power supply line MVDCLMj is driven to the ground voltage level, and supply of power supply voltage to the memory cell having an abnormal standby current is stopped.

  Therefore, when a voltage drop occurs due to a standby current abnormality in main memory power supply line MVDCLMj or bit line load power supply line VBDLj, main memory power supply line MVDCLMj is driven to the ground voltage level. As a result, as in the first to ninth embodiments, the memory cell having an abnormal standby current can be set in a malfunctioning state. Thereafter, by reading the memory cell data, it is possible to detect a memory cell having a standby current failure / normal operation.

  A defective column address is detected according to the detection result, and the link element is blown in the fuse program circuit 108j corresponding to the defective column address (global column selection line GYLj). As a result, the memory cell having the standby current failure can be disconnected from the power supply node, and the standby current abnormality can be remedied. In this case, redundant column replacement is performed in each memory block BLK.

  Further, global column decode circuit 102j is maintained in an inactive state in accordance with fuse program signal PFj from fuse program circuit 108j, and global select line GYLj is always fixed in a non-selected state. The global column selection line GYLj may be a positive logic signal or a negative logic signal.

  As shown in FIGS. 29 to 38, in a semiconductor memory device having a T-type bit line structure having a bit line to which a memory cell is connected and a bit line lead line for connecting the bit line to a peripheral circuit, a standby current is provided. It is possible to relieve the standby current abnormality by relieving the defective column that causes the abnormality.

  The test sequence of the semiconductor memory device shown in FIGS. 29 to 38 is the same as the test operation flow shown in FIG.

  As described above, according to the tenth embodiment of the present invention, the bit line load power supply line and the main memory power supply line are disconnected from the power supply node and maintained in the standby state in memory row block units in the T-type bit line configuration. The presence or absence of a voltage drop in these power supply lines is detected, and the voltage level of the main memory power supply line is set according to the detection result. Therefore, even in such a T-type bit line configuration, it is possible to detect the presence of a memory cell with a standby current failure / normal operation, and replacement of redundant memory cells, that is, using a spare global data line and a spare bit line pair. The standby current defective column can be relieved.

  At the time of replacement of the redundant column, the spare bit line load power supply line and the spare main memory power supply line arranged corresponding to the spare global data line are used only when the redundant column (spare bit line pair) is used. May be configured to be coupled.

  Also, in the T-type bit line configuration, the power supply lines and the bit line lead lines are alternately arranged in the second layer metal wiring, and these power supply lines are used as a shield layer, and coupling noise between the wirings Can be reduced, and data can be read stably.

[Embodiment 11]
FIG. 39 shows a structure of a main portion of the semiconductor memory device according to the eleventh embodiment of the present invention. The configuration shown in FIG. 39 is different from the configuration shown in FIG. 38 in the following points. That is, in the voltage control circuit 106j, a P-channel MOS transistor 140u is provided in parallel with the MOS transistor 140i, and a P-channel MOS transistor 140t is provided in parallel with the MOS transistor 140j. The output voltage of reference voltage generating circuit 150 is applied to the gates of MOS transistors 140t and 140u. Other configurations shown in FIG. 39 are the same as those shown in FIG. 38, and corresponding portions bear the same reference numerals and will not be described in detail.

  Reference voltage generation circuit 150 is connected between a power supply node and node 153c and has a gate connected to node 153c, a P channel MOS transistor 152a connected between node 153 and a ground node, and a gate connected to a test mode. N channel MOS transistor 152b receiving instruction signal TEST1 is included.

  When test mode instruction signal TEST1 is at L level, reference voltage generation circuit 150 outputs a voltage at power supply voltage VDD level from node 153, and sets MOS transistors 140t and 140u to a non-conductive state. On the other hand, when test mode instruction signal TEST1 becomes H level, reference voltage generation circuit 150 generates a voltage corresponding to the current flowing through MOS transistor 152b at node 153 by MOS transistor 152a. In this state, MOS transistors 140t and 140u are in a conductive state having a high resistance of about several MΩ, for example, and function as pull-up resistors for main memory power supply line MVDCLMj and bit line load power supply line BVDLj. These MOS transistors 140t and 140u have a resistance value of several MΩ in a high resistance conductive state, and when a normal standby current flows as a leakage current, these main memory power supply line MVBLj and bit line load power supply line BVDLj Voltage drop can be suppressed, and a memory cell having a defective standby current can be reliably identified.

  Note that the reference voltage generation circuit 150 is provided in common to the voltage control circuit included in the switch circuit 106.

  As described above, according to the eleventh embodiment of the present invention, in the T-type bit line configuration, these are connected via the high resistance resistance elements during the voltage drop test of the bit line load power supply line and the main memory power supply line. The bit line couples the power supply line and the main memory power supply line to the power supply node, so that normal standby current leakage and abnormal standby current leakage can be reliably identified, and memory cells with standby current failure are accurately identified can do.

[Embodiment 12]
FIG. 40 shows a structure of a main portion of the semiconductor memory device according to the twelfth embodiment of the present invention. The semiconductor memory device shown in FIG. 40 differs from the configuration of voltage control circuit 106j shown in FIG. 38 in the following points. 40, voltage control circuit 106j is turned on in accordance with test mode instruction signal TEST2, and when turned on, N channel MOS transistor 282 connecting main memory power supply line MVDCLMj and node 283, and signal (voltage) on node 283 are turned on. ) And a test mode instruction signal TEST3, and an inverter 281 that receives an output signal of NRO gate 280 and transmits the signal to node 283.

  The output signal of NOR gate 280 is applied to 3-input NOR gate 285 receiving test mode instruction signal TEST1 and fuse program information PFj. That is, a three-input NOR gate 285 is arranged instead of the two-input NOR gate 140g shown in FIG. The other configuration of voltage control circuit 106j shown in FIG. 40 is the same as that shown in FIG. 38, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 40, the activation / inactivation sequence of test mode instruction signals TEST1-TEST3 is the same as the activation / inactivation sequence shown in FIG.

  First, in a standby state before the test operation mode, test operation mode instruction signal TEST3 is set to L level, and node 283 is initially set to H level. In this initial setting operation, test operation mode instruction signals TEST1 and TEST2 are at L level, and NOR gate 285 receives an L level signal at three inputs and outputs an H level signal, and accordingly, inverter 140h Outputs an L level signal, MOS transistors 140i and 140j are both in a conductive state, and a power supply voltage is supplied to power supply lines BVDLj and MVDCLMj.

  When test mode instruction signal TEST1 is set to H level, MOS transistors 140i and 140j are rendered non-conductive by NOR gate 285 and inverter 140h, and main memory power supply line MVDCLMj and bit line load power supply line BVDLj are separated from the power supply node. Is done. In this state, if there is a defect that causes an abnormal standby current, the voltage level of bit line load power supply line BVDLj and / or memory power supply line MVDCLMj decreases.

  Next, test mode instruction signal TEST2 is set to H level, MOS transistors 140n and 140q are rendered conductive, and memory power supply line MVDCLMj is driven to the ground voltage level by MOS transistors 140m and / or 140p. At this time, MOS transistor 282 is in a conductive state, and NOR gate 280 and inverter 281 latch the L level voltage of memory power supply line MVDCLMj at node 283.

  When test mode instruction signals TEST1 and TEST2 are both set to L level with test mode instruction signal TEST3 set to L level, MOS transistors 140n, 140q and 282 are rendered non-conductive. In this state, a voltage of L level is latched at node 283, and the output signal of NOR gate 280 becomes H level. Accordingly, the output signals of NOR gate 285 and inverter 140h maintain H level. Therefore, the memory power supply line MVDCLMj and the bit line load power supply line BVDLj corresponding to the memory cell in which the short circuit in which the standby current abnormality has occurred is maintained at the L level. Although bit line load power supply line BVDLj is in a floating state, it is coupled to the word line via a short circuit, and this voltage level is set substantially to the ground voltage level.

  A cross defect can be detected by performing data access to the memory cell using various test patterns in a state where the test mode instruction signal TEST3 is set to the L level.

  As described above, according to the twelfth embodiment of the present invention, the number of columns arranged corresponding to bit line load power supply line BVDL and memory power supply line MVDLMj can be increased even in the T-type bit line configuration. In addition, the number of latch circuits that latch the voltage level of the memory power supply line MVDCLMj can be reduced, and a cross failure can be accurately detected without increasing the circuit occupation area.

  In the twelfth embodiment, the test operation sequence is the same as in the ninth embodiment.

  In the tenth to twelfth embodiments, the cascaded inverters for waveform shaping are not used, and MOS transistors 140m and 140p may be driven in accordance with the output signals of potential detection inverters 140a and 140d.

  In the twelfth embodiment, power-on detection signal POR may be used instead of test mode instruction signal TEST3.

[Embodiment 13]
FIG. 41 schematically shows a structure of a main portion of the semiconductor memory device according to the thirteenth embodiment of the present invention. The configuration shown in FIG. 41 is different from the configuration shown in FIG. 26 in the following points. That is, test mode instruction signal TEST3 is applied to load detection circuits 366a and 366b provided for bit line load power supply lines BVDLa and BVDLb, and detection holding circuit 316a provided for memory power supply lines MVDLa and MVDLb. And 316b are also supplied with test mode instruction signal TEST3.

  In load detection circuits 366a and 366b, when bit line load power supply lines BVDLa and BVDLb are driven to an intermediate voltage level due to a short circuit failure such as a micro short circuit, a through current flows in load detection circuits 366a and 366b. It has a function to prevent this.

  Since detection holding circuits 316a and 316b drive memory power supply lines MVDLa and MVDLb to the ground voltage level when bit line load power supply lines BVDLa and BVDLb attain an intermediate voltage, there is a possibility that through current flows. Few. However, these detection holding circuits 316a and 316b also reliably block the path through which this through current flows in accordance with test mode instruction signal TEST3.

  In load detection circuits 366a and 366b, by causing the through current prevention mechanism to function in accordance with test mode instruction signal TEST3, current is consumed by the through current in load detection circuits 366a and 366b when measuring the standby current of the semiconductor memory device. The standby current can be accurately detected.

  The other configuration shown in FIG. 41 is the same as the configuration shown in FIG. 26, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 42 shows an example of the configuration of load detection circuits 366a and 366b and detection holding circuits 316a and 316b shown in FIG. FIG. 42 representatively shows a configuration of load detection circuit 366 and detection holding circuit 316 provided for bit line load power supply line BVDL and memory power supply line MVDL arranged for bit lines BL and ZBL.

  42, the detection holding circuit 316 is connected at its input stage to a NOR circuit 316a that receives the test mode instruction signal TEST3 and the voltage on the memory power supply line MVDL, and a two-stage cascade connection that receives the output signal of the NOR circuit 316a. Inverters 24f and 24g, selectively turned on in accordance with the output signal of inverter 24g, and turned on in response to activation of test mode instruction signal TEST2, and N channel MOS transistor 24e transmitting ground voltage when turned on, MOS transistor MOS transistor 24c electrically coupling 24e to memory power supply line MVDL is included.

  The load detection circuit 366 (with a leak prevention function) includes a NOR circuit 367a that receives the test mode instruction signal TEST3 and the voltage on the load power supply line BVDL, and a two-stage cascaded inverter 67d that receives the output signal of the NOR circuit 367a. And 67e are selectively turned on in accordance with the output signal of inverter 67e. When turned on, they are turned on in response to activation of test mode instruction signal TEST2 and N channel MOS transistor 67d for transmitting the ground voltage. N channel MOS transistor 67c is provided for electrically coupling transistor 37d to memory power supply line MVDL.

  The configuration of the detection and holding circuit 316 and the load detection circuit 366 shown in FIG. 42 includes a NOR circuit 316a and 367a instead of the detection and holding circuit 16 and the load detection circuit 66 shown in FIG. Different points. Other configurations of these circuits 16 and 66 are the same as those shown in FIG. 19, and the configurations of switch gate circuit 265 and BL load circuit 13 are the same as those shown in FIG. Are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 43 is a signal waveform diagram representing an operation during the test of the semiconductor memory device shown in FIG. Hereinafter, with reference to FIG. 43, an operation at the time of testing of the semiconductor memory device shown in FIG. 42 will be described. In the standby state, test mode instruction signals TEST1 and TEST2 are held at the L level, and test mode instruction signal TEST3 is held at the H level. In this state, load detection circuit 366 and detection holding circuit 316 are in an inactive state, and no detection operation is performed. The latch circuit 201 is maintained in the initial state because the transfer gate 202 is in a non-conducting state. In this test mode, fuse program information PF is at the L level because the fuse program is not performed again.

  In latch circuit 201, test mode instruction signal TEST3 is at H level, and its output signal is initialized to L level. The switch gate 265 is in the conductive state because the output signal of the input first stage NOR circuit 22a is H level, and the power supply voltage is supplied to the load power supply line BVDL and the memory power supply line MVDL.

  At the time of transition to the test mode, first, test mode instruction signal TEST3 is set to L level, NOR circuits 316a, 367a and 201a are enabled, and operate as an inverter. Thereby, it is possible to set an operation mode for detecting a standby abnormality. In order to detect a standby abnormal / normal operation memory cell, test mode instruction signal TEST1 is set to H level, and after a predetermined time has elapsed, test mode instruction signal TEST2 is set to H level for a predetermined period (eg, 100 ns). . As a result, the memory power supply line MVDL associated with the memory cell in which the short circuit failure has occurred is driven to the ground voltage level by the load detection circuit 366 or the detection holding circuit 316. When a short circuit failure due to a micro short or the like occurs in bit line BL or ZBL, bit line load power supply line BVDL is held at an intermediate voltage level.

  In this state, a function test such as writing / reading of data to / from the memory cell is performed, and the memory power supply line and bit line load power supply line BVDL related to the defective memory cell are detected. After the test is completed, by programming the fuse program circuit arranged corresponding to the switch gate circuit 265, the switch gate circuit 265 arranged corresponding to the defective memory cell becomes non-conductive, and the bit line load power supply line BVDL and memory power supply line MVDL are isolated from the power supply node.

  During the test, the test mode instruction signals TEST1 to TEST3 are set to the L level to further detect the standby current. In the latch circuit 201, the voltage level of the memory power supply line MVDL is held. Therefore, when the memory power supply line MVDL is set to L level, the latch circuit 201 outputs an H level signal, the switch gate circuit 265 is non-conductive, and the power supply node and the bit line load power supply line BVDL and Memory power line MVDL is isolated. In this state, the standby current is measured. The bit line load power supply line BVDL is separated from the power supply node by the switch gate circuit 265 when it corresponds to a defective memory cell, and the current consumption in the standby state can be accurately measured.

  In this state, when test mode instruction signal TEST3 is set to H level, NOR circuits 316a and 367a are both disabled and their output signals are fixed to L level. On the other hand, the output signal of the latch circuit 201 becomes L level, and the switch gate circuit 265 becomes conductive. Therefore, when bit line load power supply line BVDL is coupled to the power supply node by switch gate 265 and a short circuit failure such as a micro short-circuit occurs in this state, the voltage level is lowered to the intermediate voltage level. The output signals of NOR circuits 316a and 367a are fixed at the L level, and it is possible to prevent a through current from flowing through these detection circuits 316 and 366. As a result, the standby current can be accurately measured.

  When the fuse program circuit is programmed after the test is completed, switch gate circuit 265 arranged corresponding to the defective memory cell becomes non-conductive, and test mode instruction signal TEST3 is set to H level during standby. Even if the bit line load power supply line BVDL is driven to an intermediate voltage level, the through current in the load detection circuit 366 can be reliably prevented, and the standby current can be reliably reduced.

  In this state, even if the voltage level of the memory power supply line MVDL is driven to an intermediate voltage level due to a short circuit to the intermediate voltage level, it is possible to reliably prevent a through current from occurring in the detection holding circuit 316. Can do.

[Example of change]
FIG. 44 shows a structure of a modification of the thirteenth embodiment of the present invention. The switch circuit 106 shown in FIG. 44 is different in configuration from the switch circuit 106 shown in FIG. 40 in the following points. In switch circuit 106, instead of inverter 140a, NOR circuit 340a receiving test mode instruction signal TEST3 and the voltage on main memory power supply line MVDCLMj is arranged, and instead of inverter 140b, on bit line load power supply line BVDLj NOR circuit 340b receiving voltage and test mode instruction signal TEST3 is arranged. The other configuration shown in FIG. 44 is the same as the other configuration shown in FIG. 40, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in the configuration of switch circuit 106 shown in FIG. 44, when test mode instruction signal TEST3 is set to H level, the output signals of NOR circuits 340a and 340b are fixed to L level. In this state, even if the voltage on the bit line load power supply line BVDLj is lowered to the intermediate voltage level during the test for detecting a short circuit failure, no through current is generated in the NOR circuit 340b. Therefore, even when a micro short circuit exists, the bit circuit load power line BVDLj and the main memory power line MVDCLMj are separated from the power supply node by the latch circuit in the switch circuit 106, and the leakage current of the micro short circuit is reduced. Since the flowing path is cut off, it is possible to accurately measure the standby current while eliminating the influence of such a micro short circuit.

  After the fuse program of the fuse program circuit 108j, even if the MOS transistors 140j and 140i are set in the OFF state in the switch circuit 106, even in the standby state, these bit line load power supply lines BVDLj and / or Even when the main memory power supply line MVDCLMj is driven to an intermediate voltage level, no through current is generated, and the standby current can be reduced.

  42 and 44, NOR circuits 316a and 340a may be replaced with inverters in the configuration for detecting the voltage level of memory power supply line MVDL or MVDCLMj. This is because when the power supply voltage of these memory power supply lines MVDL or MVDCLMj drops to an intermediate voltage level, the memory power supply line MVDL or MVDCLMj is driven to the ground voltage level by the voltage level detection operation. However, during this detection operation, if the time during which the memory power supply line MVDL or MVDCLMj is maintained at the intermediate voltage level is long, a through current flows. Therefore, by using the NOR circuit 316a or 340a, Generation of a through current can be prevented.

  Further, by setting the test mode instruction signal TEST3 to H level in a state where both the test mode instruction signals TEST1 and TEST2 are set to L level, the memory power supply line MVDLMj or MVDL is set for some reason before the fuse program. Even when driven to the intermediate voltage level, it is possible to reliably prevent a through current from occurring in NOR circuits 316a and 340a.

  As described above, according to the thirteenth embodiment of the present invention, in load detection circuit 366 or switch circuit 106, the gate circuit coupled to bit line load power supply line BVDL (or BVDLj) is selected by test mode instruction signal TEST3. In the standby state, the output signal of the NOR gate can be fixed to the L level, and even when the bit line load power supply line is driven to the intermediate voltage level, It is possible to reliably prevent a through current from occurring in the load detection circuit. As a result, the standby current can be accurately measured.

[Embodiment 14]
FIG. 45 shows a structure of a main portion of the semiconductor memory device according to the fourteenth embodiment of the present invention. 45, the configuration of load detection circuit 366 that drives memory power supply line MVDL in accordance with the voltage on bit line load power supply line BVDL is different from the configuration of load detection circuit 66 shown in FIG. That is, load detection circuit 366 shown in FIG. 45 is turned on in response to the output signal of inverter 67e. When turned on, it responds to activation of N channel MOS transistor 367c transmitting the ground voltage and test mode instruction signal TEST2. An N channel MOS transistor 367b is provided which is turned on and couples MOS transistor 367c to bit line load power supply line BVDL when turned on. The other configuration of the load detection circuit 366 is the same as the configuration of the load detection circuit 66 shown in FIG. 18, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The configuration of the switch gate circuit 265 and the latch circuit 201 is the same as that of the corresponding circuit shown in FIG. The configurations of the detection holding circuit 16 and the BL load circuit 13 are the same as those shown in FIG. 18, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 46 shows waveforms of test mode instruction signals in the test operation mode of the semiconductor memory device according to the fourteenth embodiment of the present invention. Hereinafter, the test operation of the configuration shown in FIG. 45 will be described with reference to FIG.

  The test operation sequence with the signal waveforms shown in FIG. 46 is substantially the same as the test operation sequence shown in FIG.

  In the normal operation before the test operation, the test mode instruction signals TEST1 and TEST2 are both at the L level, the test mode instruction signal TEST3 is at the H level, the output signal of the latch gate 201 is at the L level, and the switch gate circuit 265 is in a conductive state before the test.

  In the configuration of load detection circuit 366 shown in FIG. 45, when test mode instruction signal TEST2 is at L level, bit line load power supply line BVDL is isolated from the ground node because MOS transistor 367b is non-conductive. On the other hand, when test mode instruction signal TEST2 attains H level, MOS transistor 367b is rendered conductive.

  The test operation mode is entered, and the test operation mode instruction signal TEST1 becomes H level, and the switch gate circuit 265 is turned off. When the voltage level of the bit line load power supply line BVDL is lowered to an intermediate voltage level due to a micro short circuit or the like, and the output signal of the inverter circuit 67a as this level detection circuit is lowered to the extent of outputting H level, the MOS Transistor 367c is turned on together with MOS transistor 367d. In this state, when test operation mode instruction signal TEST2 becomes H level, bit line load power supply line BVDL is driven to the ground voltage level by MOS transistors 367b and 367c. Therefore, in this case, both memory power supply line MVDL and bit line load power supply line BVDL are held at the L level.

  Thereafter, even if test mode instruction signals TEST1 and TEST2 are set to the L level, in latch circuit 201, since test operation mode instruction signal TEST3 is at the L level, it responds to the H level of test operation mode instruction signal TEST2. Thus, the L level voltage of the memory power supply line MVDL is latched, the switch gate circuit 265 is non-conductive, and the bit line load power supply line BVDL and the memory power supply line MVDL are separated from the power supply node. maintain.

  In this state, even if all the test mode instruction signals TEST1-TEST3 are set to the L level, the bit line load power supply line BVDL has a leak source that lowers the voltage level of the bit line load power supply line BVDL. Bit line load power supply line BVDL maintains the ground voltage level. Therefore, all of these test mode instruction signals TEST1-TEST3 are set to L level, and the standby current of this semiconductor memory device is measured. The input signal of the inverter circuit 67a functioning as a voltage detection circuit is at the ground voltage level, and no through current is generated in the inverter 67a. Therefore, the standby current of the semiconductor memory device can be accurately measured without considering the current consumption in the load detection circuit 366. At this time, the memory power supply line MVDL is already driven to the ground voltage level, and no through current is generated in the inverter circuit 24d in the standby current measurement.

  As described above, by detecting the voltage level of the bit line load power supply line BVDL and setting the voltage level of the bit line load power supply line BVDL according to the detection result, a memory cell that operates normally / abnormally in the test mode. In addition, the standby current of the semiconductor memory device can be continuously measured without being affected by the through current of the detection circuit.

[Example of change]
FIG. 47 shows a structure of a modification of the fourteenth embodiment of the present invention. The switch circuit 106 shown in FIG. 47 is different from the switch circuit shown in FIG. 40 in the following points. More specifically, N channel MOS transistor 340d that conducts in response to the output signal of inverter circuit 140f and transmits ground voltage when conducting, and conducts when test mode instruction signal TEST2 is activated, and MOS transistor 340d when conducting, connect bit transistor to bit line. An N channel MOS transistor 340c electrically connected to load power supply line BVDLj is further provided. The other configuration of this switch circuit 106 is the same as the configuration of the switch circuit shown in FIG.

  Also in the configuration of switch circuit 106 shown in FIG. 47, when test mode instruction signal TEST2 is activated, when the voltage level of bit line load power supply line BVDLj drops to the intermediate voltage level, MOS transistors 340d and 340c Thus, bit line load power supply line BVDLj is driven to the ground voltage level. At the same time, the main memory power line MVDCLMj is also driven to the ground voltage level. Therefore, even if these test mode instruction signals TEST1-TEST3 are all set to L level, memory power supply line MVDCLMj and bit line load power supply line BVDLj are at the ground voltage level, and no through current occurs in inverters 140d and 140a. , Can accurately detect the standby current.

  When MOS transistors 140j and 140i are turned off after the fuse program, if the voltage level of bit line load power supply line BVDLj becomes an intermediate voltage level for some reason, a through current may flow in inverter 140d. . However, the leak source existing in the bit line load power supply line BVDLj is a leak source that lowers the voltage level of the bit line load power supply line BVDLj. Therefore, if this leak source is a leak source to the ground voltage source, bit line load power supply line BVDLj is held at the ground voltage level, and no through current is generated in inverter 140d.

  As described above, according to the fourteenth embodiment of the present invention, when the voltage of the bit line load power supply line drops, the voltage level of this bit line load power supply line is detected, and the bit line load power supply line is grounded according to the detection result. Even when there is a leak source that is driven to a voltage level and the bit line load power supply line is reduced to an intermediate voltage level due to a short circuit failure, the bit line load power supply line is reliably driven to the ground voltage level, It is possible to prevent a through current from occurring in a circuit that detects the voltage of the bit line load power supply line, and to accurately detect a standby current. Therefore, a standby current measurement test can be performed in accordance with a test mode performed after detection of a memory cell malfunction / standby abnormality memory cell.

[Embodiment 15]
FIG. 48 shows a structure of a main portion of the semiconductor memory device according to the fifteenth embodiment of the present invention. The load detection circuit 366 shown in FIG. 48 is different in configuration from the load detection circuit 360 shown in FIG. 45 in the following points. That is, instead of inverter 67a at the first input stage, NOR circuit 340e receiving voltage on bit line load power supply line BVDL and test mode instruction signal TEST3 is arranged. In detection holding circuit 316, a NOR circuit receiving test mode instruction signal TEST3 and the voltage on memory power supply line MVDL is arranged instead of inverter 24d. Other configurations are the same as those of circuits 366 and 316 shown in FIG. 45, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The configuration of the switch gate circuit 265, the latch circuit 201, and the BL load circuit 13 is also the same as the configuration shown in FIG. 45, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  In the configuration of load detection circuit 366 shown in FIG. 48, when test mode instruction signal TEST3 is at the H level, the output signal of NOR circuit 340b is fixed at the L level. Therefore, even when bit line load power supply line BVDL falls to the intermediate voltage level in the standby state in which test mode instruction signal TEST3 is set to H level, NOR circuit 340b has its output signal at L level. It is fixed and no through current is generated.

  Further, after the test operation for detecting the short-circuit failure, all the test mode instruction signals TEST1 to TEST3 are set to the L level. As shown in FIG. 49, when there is a leak source for bit line load power supply line BVDL, both MOS transistors 67c and 367b are non-conductive in the load detection circuit, and latch circuit 201 Output signal becomes H level, and bit line load power supply line BVDL is isolated from the ground node. In this bit line load power supply line BVDL, there is a leak source that lowers its voltage level, and this bit line load power supply line BVDL is maintained at the ground voltage level. Therefore, in this load detection circuit 366, no through current is generated, and the standby current can be accurately detected.

  Also in the detection holding circuit 316, even when the memory power supply line MVDL is separated from the power supply node according to the output signal of the latch circuit 201, the detection holding circuit 316 holds the ground voltage level accurately. The test mode instruction signals TEST1-TEST3 can be set to L level to detect the standby current.

  Further, even when the fuse program is performed and the switch gate circuit 265 corresponding to the defective column becomes non-conductive and the bit line load power supply line BVDL is separated from the power supply node, in the standby state (the test mode instruction signal TEST3 is at the H level) When the NOR circuit 340b and the output signal are fixed at the L level, no through current is generated, and the standby current can be reduced (the bit line load power supply line BVDL operates in this normal operation due to the leak source). Even if the voltage is held at the intermediate voltage level in the mode, the standby current does not flow).

  Similarly, for memory power supply line MVDL, similarly to bit line load power supply line BVDL, even when the voltage level is driven to an intermediate voltage level by a micro short circuit or the like, if test mode instruction signal TEST3 is at H level, No through current is generated, and the standby current can be reduced.

  By using the configuration shown in FIG. 48, even when bit line load power supply line BVDL is held at the intermediate voltage level, no through current is generated in load detection circuit 366, and the standby current is accurately detected. Can do. Even when the bit line load power supply line BVDL is separated from the power supply node that supplies the power supply voltage by the fuse program corresponding to the defective column, it is arranged corresponding to the defective column due to the leak source of the defective column. Even if the bit line load power supply line BVDL to be set becomes an intermediate voltage level, the test mode instruction signal TEST3 is set at the H level (in the normal operation mode), and a through current in the load detection circuit 366 is generated. Can be prevented, and the standby current can be reduced.

  The prevention of through current generation in the load detection circuit 366 is similarly established in the detection holding circuit 316, whereby the standby current is reduced, the standby current can be reliably measured, and the standby current is reduced. It is possible to realize a semiconductor memory device that can be used.

[Example of change]
FIG. 50 shows a structure of a modification of the fifteenth embodiment of the present invention. The configuration of the switch circuit 106 shown in FIG. 50 is different from the switch circuit shown in FIG. 47 in the following points. That is, instead of inverter 140a that detects the voltage of memory power supply line MVDCLMj, a NOR circuit 340a that receives test mode instruction signal TEST3 and the voltage of main memory power supply line MVDCLMj is arranged. Similarly, NOR circuit 340b receiving test mode instruction signal TEST3 and the voltage on bit line load power supply line BVDLj is arranged instead of inverter 140d for detecting the voltage level of bit line load power supply line BVDLj. The other configuration of the switch circuit 106 shown in FIG. 50 is the same as the configuration of the switch circuit shown in FIG. 47, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Also in the configuration of switch circuit 106 shown in FIG. 50, if test mode instruction signal TEST is at H level, the output signals of NOR circuits 340a and 340b are fixed at L level, and bit line load power supply line BVDLj and memory Even if the voltage level on the power supply line MVDCLMj is an intermediate voltage level, no through current is generated in the switch circuit 106.

  Even if all test mode instruction signals TEST1-TEST3 are set to L level, if bit line load power supply lines BVDLj and MVDLj are related to a defective column, they are maintained at the ground voltage level, and no through current is generated. , Can accurately measure the standby current. In the normal operation mode, test mode instruction signal TEST3 is at the H level, and the standby current can be reduced.

  In the configuration shown in FIGS. 48 and 50, NOR circuits 340b and 340a coupled to memory power supply line MVDL or MVDLMj may be replaced with inverters. That is, a configuration in which a NOR circuit is arranged only for bit line load power supply line BVDL or BVDLj may be used.

[Other embodiments]
In the above description, a static random access memory is shown as a semiconductor memory device. However, for example, in a dynamic random access memory (DRAM), the present invention can also be applied to a sense power supply line of a sense amplifier circuit that latches each voltage of a memory cell column as differential amplification.

  The present invention is also applicable to a bit line precharge voltage transmission line for precharging and equalizing a bit line to a predetermined voltage level in a DRAM, for example. In this case, when the bit line is precharged and equalized to the intermediate voltage level (VDD / 2) level, the input logic threshold value of the inverter for detecting the voltage level of the precharge voltage transmission line is preselected. By setting the voltage level lower than the charge voltage level, the bit line precharge voltage transmission line through which this abnormal standby current flows can be driven to the ground voltage level. When reading the memory cell data, the bit lines where the standby current abnormality has occurred are both at the ground voltage level, and the corresponding sense amplifier circuit does not receive complementary data. Therefore, normal sense operation cannot be performed, and the read data By comparing the write test data, the bit line in which the standby current abnormality has occurred can be identified.

  As described above, according to the present invention, the voltage transmission line is disconnected from the reference potential node in the test mode, the voltage level of the voltage transmission line is detected, and the voltage transmission line is set to the voltage level according to the detection result. Therefore, it can be easily identified whether or not an abnormal standby current flows through this voltage transmission line. Further, the memory cell in which the standby current failure has occurred can be identified by reading data, and the memory cell with the standby current failure can be relieved by redundant replacement, and the standby current failure can be relieved accordingly. .

  By driving the voltage transmission line to the ground potential level when the voltage is lower than a predetermined voltage, the corresponding memory cell can be surely set to the operation failure state, and the address of the memory cell having the standby current failure is detected. Can do.

  In addition, by switching the switch circuit to a non-conductive state when replacing the redundant memory cell, even if there is a memory cell with a standby current failure, the leakage current path can be cut off and the standby current failure Can be surely remedied.

  In addition, by setting the switch circuit in the non-conductive state during the test mode in the specific operation mode, the voltage level of the voltage transmission line can be reliably detected in this test operation mode, and the standby current abnormality is detected accordingly. Can be done.

  In addition, when this switch circuit is non-conductive, the voltage transmission line is connected to the power supply node through a high-resistance element, so that the normal leakage current and the abnormal leakage current are distinguished, and the abnormal leakage current is accurately detected. Can be detected.

  Further, by setting the auxiliary switch circuit in a high resistance conduction state in the test operation mode, the current consumption of the circuit driving the auxiliary switch circuit can be reduced during the normal operation.

  By arranging this voltage transmission line corresponding to a predetermined number of memory cells, it is possible to detect standby current abnormalities / normality in units of a predetermined number of memory cells and to repair standby current failure.

  Further, when this voltage transmission line is a memory power supply line that supplies a power supply voltage to the latch type memory cell, it is possible to easily identify a leakage current abnormality due to a short circuit related to the memory power supply line.

  Also, by detecting the voltage level of the load power supply line that supplies the voltage to the bit line load circuit, and setting the voltage level of the voltage transmission line according to this detection result, the leakage abnormality caused by the short circuit related to the bit line is eliminated. By detecting, the memory cell can be set to a malfunctioning state. Thereby, it is possible to detect a standby current failure caused by a short circuit related to the bit line.

  In addition, by configuring the bit line with a bit line to which a memory cell is connected and a bit line voltage transmission line that couples the bit line to a peripheral circuit, coupling noise during data reading between signal lines is suppressed. However, standby current abnormality in a semiconductor memory device that operates accurately can be detected and redundant replacement can be performed to relieve standby current failure.

  In addition, the voltage control circuit is configured to determine the voltage transmission line potential in binary, so that the voltage level of the voltage transmission line is detected according to the detection result by detecting the abnormality / normality of the voltage of the voltage transmission line with a simple circuit configuration. Can be set to either an abnormal state or a normal state to identify the presence or absence of a leakage current in the voltage transmission line.

  In addition, by connecting a high-resistance resistance element in parallel with the auxiliary switch circuit, it is possible to distinguish between the standby current abnormality of the bit line and the normal standby current, and the standby current related to the bit line short circuit accurately. Defects can be detected.

  The voltage control circuit is selectively turned on in accordance with a binary detection circuit that generates a binary signal according to the voltage of the first voltage selection line, and an output signal of the binary detection circuit. And a latch transistor that couples the voltage transmission transistor to the first voltage transmission line in accordance with the specific operation mode instruction signal, so that the first voltage transmission line can be accurately obtained with a simple circuit configuration. The first voltage level can be set according to the detection result.

  Similarly, the voltage control circuit includes a first voltage detection circuit that generates a binary signal, a first detection transistor that drives an internal node to a predetermined voltage level in accordance with an output signal of the first voltage detection circuit, The first internal node is formed of a first latch transistor electrically coupled to the first voltage transmission line in accordance with the specific operation mode instruction signal, and the load voltage detection circuit is set to the voltage level of the second voltage transmission line. According to the second detection circuit for generating a binary signal, a second detection transistor for transmitting a predetermined voltage to the second internal node according to the output signal of the second voltage detection circuit, and the specific operation mode instruction signal By configuring the second internal node and the second latch transistor electrically coupled to the first voltage transmission line, the voltage levels of the first and second voltage transmission lines are different. In case, it is possible to accurately set the voltage level of the first voltage transmission line according to the voltage level of the detection results of the first and second voltage transmission line.

  By configuring each of the first and second voltage detection circuits with an odd number of inverters, a binary signal can be reliably generated according to the voltage levels of the first and second voltage transmission lines, and high speed Thus, the first voltage level can be set to the corresponding voltage level accurately according to the detection result.

  Corresponding to the switch circuit, a control signal generating circuit for selectively setting the switch circuit to a non-conductive state, and latching the voltage of the first voltage transmission line set by the voltage control circuit, the latch signal And a latch circuit for setting the logic level of the control signal generated by the control signal generation circuit according to the voltage level of the first voltage transmission line according to the voltage level of the latch circuit. Can be maintained. As a result, in addition to the defective column, it is possible to suppress the occurrence of multiple selection for the defective row, and to accurately identify the defective row, and to accurately detect the cross defect caused by the short circuit. Thus, it is possible to surely repair defective rows and defective columns.

  Further, by detecting the voltage level of the second voltage transmission line that transmits a voltage to each bit line pair, and setting the voltage level of the first voltage transmission line that transmits the voltage to the memory cell according to the detection result. If a short circuit failure related to the bit line occurs reliably, the memory cell can be set to a defective state, and the short circuit failure can be detected reliably.

  In addition, as a load voltage detection circuit for detecting the voltage of the second voltage transmission line, a gate circuit receiving the specific operation mode instruction signal and the voltage level of the second voltage transmission line, and a first circuit according to the output signal of the gate circuit By forming a circuit that drives the voltage level of the voltage transmission line, even when the second voltage transmission line is lowered to the intermediate voltage level, generation of a through current in the gate circuit can be suppressed. The current during standby can be reduced.

  Instead of this, the load voltage detection circuit is configured to detect the voltage level of the second voltage transmission line, and to drive the first and second voltage transmission lines according to the output signal of the gate circuit. By configuring with the first and second drive circuits, even when a leak path exists in the second voltage transmission line, the second voltage transmission line can be held at a predetermined voltage level. Can be prevented from being maintained at the intermediate voltage level, and the through current of the gate circuit can be suppressed. In this state, the standby current can be accurately detected, and both the memory cell abnormality and the standby current abnormality can be detected.

  A gate circuit receiving the first operation mode instruction signal and the voltage level of the second voltage transmission line, and first and second driving the first and second voltage transmission lines according to the output signal of the gate circuit, respectively. By configuring a load voltage detection circuit that detects the voltage of the second voltage transmission line with the two drive circuits, even when a defect related to the bit line occurs, the memory cell is accurately set to a defective state. Thus, a defective memory cell can be detected. Further, even when the bit line load power supply line (second voltage transmission line) is held at an intermediate voltage level, generation of a through current of the gate circuit can be suppressed, and the standby current can be accurately measured. . Further, even in the normal operation mode, even when the second voltage transmission line becomes an intermediate voltage level due to a leak source, generation of a through current of the gate circuit in this detection circuit can be suppressed, and a standby current can be reduced. Can do.

  In the specific operation mode, the second voltage transmission line is driven to the same voltage level as that of the first voltage transmission line according to the voltage level of the second voltage transmission line. Even when a defect associated with the transmission line occurs, it is possible to reliably set the memory cell to an abnormal state and suppress the standby current or through current, and accurately match the standby current in this memory cell abnormality detection mode. Abnormalities can also be detected.

  In addition, after data is written in the memory cell, the standby state is maintained, and then the transmission line and the power supply node are separated, the potential of the voltage transmission line is detected, and the voltage level of the voltage transmission line is set according to the detection result. Later, by reading the data of the memory cell, it is possible to easily set the standby current failure / normal operation memory cell to the operation failure state, and to identify the address of the standby current abnormality memory cell, By replacing the redundant memory cell, the standby current abnormality can be remedied.

  In addition, the bit line load power supply line is disconnected from the power supply node, its voltage level is detected, and the potential of the corresponding memory power supply line is set according to the detection result, so that the standby current caused by the short circuit related to the bit line Defects can be detected.

  The voltage level of the first voltage transmission line is set to a voltage level corresponding to the voltage level of the first or second voltage transmission line, and the voltage of the first voltage transmission line is stored to store the first and / or Alternatively, by setting the connection state between the second voltage transmission line and the power supply node, it is possible to detect the defective column by executing the data writing / reading with the memory cell having the defective standby current as a defective state. it can. Further, the non-selected defective word line can be maintained in the non-selected state due to the short circuit, and the word line multiple selection does not occur, and the defective line can be detected accurately and the cross defect can be relieved.

  According to the present invention, a semiconductor memory device with low current consumption can be realized, and a system with low current consumption is constructed by applying to a semiconductor memory device used in a system that requires low power consumption. Can do.

1 schematically shows an entire configuration of a semiconductor memory device according to a first embodiment of the invention. FIG. It is a figure which shows the electrical equivalent circuit of the memory cell in Embodiment 1 of this invention. FIG. 2 schematically shows a planar layout of the memory cell shown in FIG. 1. FIG. 4 schematically shows a layout of an upper layer wiring of the memory cell shown in FIG. 3. 1 schematically shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the invention. FIG. FIG. 6 is a diagram illustrating an example of a configuration of a program circuit illustrated in FIG. 5. It is a figure which shows an example of a structure of the switch gate shown in FIG. It is a figure which shows the structure of the detection holding circuit shown in FIG. It is a figure which shows the structure at the time of the standby state of BL load circuit shown in FIG. FIG. 7 is a signal waveform diagram representing an operation during a test of the semiconductor memory device according to the first embodiment of the present invention. 1 is a flowchart showing a test method for a semiconductor memory device according to a first embodiment of the present invention. It is a figure which shows roughly the whole structure of the semiconductor memory device according to Embodiment 2 of this invention. FIG. 11 schematically shows a structure of a main portion of a semiconductor memory device according to the second embodiment of the present invention. It is a flowchart which shows the test operation of the semiconductor memory device according to Embodiment 2 of this invention. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 3 of this invention. FIG. 14 schematically shows a structure of a main portion of a semiconductor memory device according to the fourth embodiment of the invention. It is a figure which shows an example of a structure of the switch gate circuit shown in FIG. 16, a load detection circuit, and a detection holding circuit. It is a figure which shows the example of a change of the load detection circuit and detection holding circuit which are shown in FIG. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 5 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 6 of this invention. FIG. 21 is a diagram showing a configuration of a bit line peripheral circuit shown in FIG. 20. FIG. 22 is a timing diagram illustrating an operation of the configuration illustrated in FIGS. 20 and 21. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 7 of this invention. FIG. 24 shows a configuration of a bit line peripheral circuit shown in FIG. 23. It is a flowchart which shows the test operation | movement of the semiconductor memory device according to Embodiment 7 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 8 of this invention. FIG. 27 is a diagram showing a configuration of a bit line peripheral circuit shown in FIG. 26. FIG. 38 is a timing diagram representing an operation of a semiconductor memory device according to the ninth embodiment of the present invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 10 of this invention. FIG. 30 schematically shows a structure of a memory block of the semiconductor memory device shown in FIG. 29. FIG. 30 schematically shows a configuration of a sub memory block of the memory block shown in FIG. 29. FIG. 30 is a diagram showing an example of a configuration of a local row decoder shown in FIG. 29. FIG. 30 schematically shows a configuration of a memory block shown in FIG. 29. It is a figure which shows roughly the wiring layout in one unit memory block. FIG. 32 is a diagram showing an example of a configuration of a local peripheral circuit shown in FIG. 31. FIG. 30 schematically shows a configuration of a write / read circuit shown in FIG. 29. FIG. 30 schematically shows an arrangement of wirings in one row block of the semiconductor memory device shown in FIG. 29. FIG. 30 is a diagram illustrating an example of a configuration of a switch circuit illustrated in FIG. 29. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 11 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 12 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 13 of this invention. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 13 of this invention. It is a figure which shows the test mode instruction | indication signal waveform at the time of the test operation mode in Embodiment 13 of this invention. It is a figure which shows the example of a change of Embodiment 13 of this invention. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 14 of this invention. It is a figure which shows the signal waveform at the time of the test mode in Embodiment 14 of this invention. It is a figure which shows the example of a change of Embodiment 14 of this invention. FIG. 41 schematically shows a structure of a main portion of a semiconductor memory device according to the fifteenth embodiment of the present invention. It is a signal waveform diagram which shows the operation | movement at the time of the test mode in Embodiment 15 of this invention. It is a figure which shows the structure of the principal part of the semiconductor memory device according to Embodiment 15 of this invention. It is a figure which shows the structure of the conventional SRAM cell. FIG. 52 schematically shows a layout of the SRAM cell shown in FIG. 51. It is a figure which shows an example of the leakage current path | route of the conventional SRAM cell.

Explanation of symbols

  1 memory cell array, 2 word line selection circuit, 3 bit line load, 4 fuse program circuit, 5 switch circuit, 6 voltage control circuit, 7 test control circuit, MVDL, MVLLa, MVDLb memory power supply line, MVSL, MVSLa, MVSLb memory ground Line, BL, ZBL, BLa, ZBLa, BLb, ZBLb bit line, WLa, WLb, WL word line, 13a, 13b BL load circuit, 16a, 16b detection holding circuit, 15a, 15b switch gate, 14a, 14b program circuit, SMC memory cell (SRAM cell), 44a, 44b program circuit, 45a, 45b switch gate, 46a, 46b detection holding circuit, MVCLa, MVCL memory power line, 22c, 22ca, 22cb, 22cc MOS transistor 52 reference voltage generation circuit, 50a, 50b, 50c MOS transistor, 65a, 65b switch gate circuit, 66a, 66b load detection circuit, BVDL bit line load power supply line, 100 global row decoder, 102 global column decoder, 104 write / read Circuit, 106 switch circuit, 108 fuse program circuit, BLK0-BLK7 memory block, MSR0 memory subarray, LDC0 local row decoder, BPH0 local bit line peripheral circuit, 110 local row decoding circuit, 112 local peripheral circuit, GWL global word line, GIO , ZGIO global data line, BLL, ZBLL bit line lead line, BVDLj bit line load power line, MVDCLM main memory power line, GIL global column select line 112-0-112-n local peripheral circuit, 112-n spare local peripheral circuit, BLPs spare bit line pair, BLP0-BLPn bit line pair, 120 bit line load circuit, 122 sense amplifier, 124 write column select gate, CSG0-CSGn column selection gate, CSGs spare column selection gate, 106j voltage control circuit, 108j fuse program circuit, 102j global column decoding circuit, 140i, 140j, 140n, 140i, 140j, 140n, 140m MOS transistor, 150 reference voltage generation circuit 200a, 200b, 200 latch circuit, 215a, 215b, 215 switch gate, 201a, 216 NOR gate, 201b, 217 inverter, 202 transfer gate, 265a, 265b, 26 Switch gate circuit, 266 NOR gate, 267 inverter, 268, 269 P-channel MOS transistor, 280 NOR gate, 281 inverter, 282 transfer gate, 366, 366a, 366b load detection circuit, 316a, 316b detection hold circuit, 316a, 367a NOR Circuit, 340a, 340b NOR circuit, 367b, 367c MOS transistor.

Claims (6)

A plurality of memory cells arranged in a matrix,
A plurality of memory power lines arranged corresponding to each column of the plurality of memory cells, each connected to a plurality of memory cells in a corresponding column;
A plurality of bit line pairs arranged corresponding to each column of the plurality of memory cells, each connected to a plurality of memory cells in a corresponding column;
A plurality of word lines arranged corresponding to each row of the plurality of memory cells, each connected to a plurality of memory cells in a corresponding row;
Are arranged corresponding to said plurality of memory power supply line, each of which power voltage is supplied to the memory power supply line corresponding to the active time, a plurality of inactivated in response to the first specific operation instruction signal during a particular operation A power supply potential control unit;
A plurality of bit lines arranged corresponding to the plurality of bit line pairs, each charging a bit line in a corresponding column when activated, and being deactivated according to the first specific operation instruction signal during the specific operation A bit line potential control unit;
Wherein are arranged corresponding to the plurality of memory power supply line, each said activated in response to the second specific operation instruction signal during a particular operation, it detects the voltage drop of the corresponding memory power supply line, according to the detection result A plurality of first potential control circuits for setting the potential of the corresponding memory power supply line to a potential corresponding to the detection result;
Said plurality of arranged corresponding to the bit line pairs, each said activated in response to the at specific operation second specific operation instruction signal, the corresponding bit line pair through said bit line potential control unit A plurality of second potential control circuits configured to detect a voltage drop and set a potential of a memory power supply line connected to a memory cell in the same column as the bit line to a potential corresponding to the detection result according to the detection result; A semiconductor memory device comprising: The memory cell is a static random access memory cell;
Each of the memory power supply line and the bit line pair is formed to extend in the column direction on the same metal wiring layer above the layer in which the transistors constituting the memory cells in the same column are formed,
The semiconductor memory device according to claim 1, wherein the memory power supply line is disposed between the bit line pair. It is arranged corresponding to the memory cell for each column or the memory cells for a plurality of columns, and for each column or a plurality of columns depending on the detection result of the first potential control circuit or the detection result of the second potential control circuit. The semiconductor memory device according to claim 1 , further comprising a redundant memory cell group replaced with a memory cell. In response to the detection result of the first potential control circuit or the detection result of the second potential control circuit, a control signal for inactivating the power supply potential control unit and the bit line potential control unit is output for each column. The semiconductor memory device according to claim 3, further comprising a program circuit . 5. The semiconductor memory device according to claim 1, further comprising a specific operation control circuit that generates the first specific operation instruction signal and the second specific operation instruction signal during the specific operation. 6. The specific operation, said a test operation for testing the semiconductor memory device, the semiconductor memory device according to any one of claims 1-5.

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