JP4604492B2 - SOI semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  In particular, the present invention relates to an SOI semiconductor integrated circuit device including a logic cell formed on an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.

  The SOI (Silicon On Insulator) technique is known as a technique for forming an integrated circuit device such as a MOSFET on a silicon single crystal formed on a buried insulating film. The SOI MOSFET has an advantage that the source / drain junction capacitance can be suppressed smaller than that of a normal bulk MOSFET. Since an SOI MOSFET operates at high speed even with a low voltage power supply, application to a low power consumption LSI is being studied.

When considering a logic cell layout using CMOS transistors in SOI, a P-channel MOSFET and an N-channel MOSFET are arranged at a predetermined distance. Such a configuration is the same as the technology of a normal bulk MOSFET (see, for example, Patent Document 1). A contact formation region is formed in a separation region between the two transistors.
JP 7-161944 (3rd page, FIG. 1)

  If the arrangement distance between the P-channel MOSFET and the N-channel MOSFET is increased, the layout area is increased by that distance. Further, it is possible to consider a horizontal arrangement in which the drains are adjacent to each other. However, when a contact for body potential is formed, the cell area is remarkably increased.

  The present invention has been made in consideration of the above-mentioned circumstances. In order to minimize the increase in the cell area, a contact for body potential can be simply provided in a horizontal configuration in which drains of different conductivity types are adjacent to each other. It is an object of the present invention to provide a layoutable SOI semiconductor integrated circuit device and a manufacturing method thereof.

  An SOI semiconductor integrated circuit device according to the present invention includes a first conductivity type silicon single crystal substrate on an insulating layer, and a second conductivity type silicon adjacent to the first conductivity type silicon single crystal substrate on the insulation layer. A single crystal base, a second conductive type first region and a second conductive type second region provided on the first conductive type silicon single crystal base, and between the first region and the second region The first conductivity type provided in the first conductivity type high concentration region adjacent to the first region and at least the first conductivity type high concentration region adjacent to the first conductivity type silicon single crystal substrate, and the second conductivity type silicon single crystal substrate A first conductivity type fourth region adjacent to the third region and the second region, and the second conductivity type silicon single crystal substrate between the third region and the fourth region, and at least the first region A second conductivity type high concentration region adjacent to the three regions; From the first conductivity type silicon single crystal substrate between both the first region and the second region, to the first conductivity type silicon single crystal substrate adjacent to the first conductivity type high concentration region, and From the second conductivity type silicon single crystal substrate between both the third region and the fourth region, to the second conductivity type silicon single crystal substrate adjacent to the second conductivity type high concentration region, And a gate electrode provided through a gate insulating film.

  According to the SOI semiconductor integrated circuit device of the present invention, the first conductivity type and the second conductivity type silicon single crystal bases are adjacent to each other, and the first conductivity type, the first region, the second region, and the first conductivity type, respectively. The third and fourth regions are provided. With such a configuration, the second region and the fourth region are adjacent to each other as a combination of devices having different conductivity types, which is suitable for common drain connection. The first conductivity type high concentration region connected to the silicon single crystal substrate of each body is adjacent to the first region, and the second conductivity type high concentration region is adjacent to the third region, which is suitable for the source / tie structure of the body. This greatly reduces the distance between devices of different conductivity types and minimizes the increase in cell area even if a contact for body potential is provided.

  An SOI semiconductor integrated circuit device as a more preferred embodiment according to the present invention includes a first conductivity type silicon single crystal substrate on an insulating layer, and adjacent to the first conductivity type silicon single crystal substrate on the insulating layer. A second conductivity type silicon single crystal substrate, a second conductivity type first region and a second conductivity type second region provided on the first conductivity type silicon single crystal substrate, the first region, The first conductivity type silicon single crystal substrate between both the second regions is connected to the first conductivity type high concentration region adjacent to the first region, and the second conductivity type silicon single crystal substrate is provided. A third region of the first conductivity type and a fourth region of the first conductivity type adjacent to the second region; and the second conductivity type silicon single crystal substrate between the third region and the fourth region; Connected, adjacent to the third region, the second conductivity type high concentration A region, an isolation region between the first conductivity type high concentration region and the second conductivity type high concentration region, and the first conductivity type silicon single crystal substrate between both the first region and the second region, From the first conductivity type silicon single crystal substrate adjacent to the first conductivity type high concentration region and from the second conductivity type silicon single crystal substrate between both the third region and the fourth region. A gate electrode provided on the second conductivity type silicon single crystal substrate adjacent to the second conductivity type high concentration region via a gate insulating film, a sidewall of the gate electrode, and at least the sidewall Except for the total region of the first region and the first conductivity type high concentration region, the total region of the second region and the fourth region, the total region of the third region and the second conductivity type high concentration region, And the upper surface of each of the gate electrodes Including a silicide product provided, a.

  According to the SOI semiconductor integrated circuit device of the present invention, the first conductivity type and the second conductivity type silicon single crystal bases are adjacent to each other, and the first conductivity type, the first region, the second region, and the first conductivity type, respectively. The third and fourth regions are provided. With such a configuration, the second region and the fourth region are adjacent to each other as a combination of devices having different conductivity types, which is suitable for common drain connection. The first conductivity type high concentration region connected to the silicon single crystal substrate of each body is adjacent to the first region, and the second conductivity type high concentration region is adjacent to the third region, which is suitable for the source / tie structure of the body. The first conductivity type high concentration region and the second conductivity type high concentration region are separated by a separation region. The isolation region is a component in the form of a self-aligned silicide together with the sidewall of the gate electrode. As a result, the distance between devices of different conductivity types is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

In the SOI semiconductor integrated circuit device according to the present invention, the gate electrode is a shared electrode extending from the first conductivity type silicon single crystal substrate to the second conductivity type silicon single crystal substrate.
In the SOI semiconductor integrated circuit device according to the present invention, the gate electrode extends on the isolation region and extends from the first conductivity type silicon single crystal substrate to the second conductivity type silicon single crystal substrate. It is a shared electrode that straddles.

  A method for manufacturing an SOI semiconductor integrated circuit device according to the present invention includes a first conductivity type silicon single crystal substrate including regions adjacent to each other on an insulating layer and regions adjacent to each other by an insulating isolation region, and Forming a second conductive type silicon single crystal substrate; forming a gate insulating film on the first conductive type and second conductive type silicon single crystal substrates; and The first conductivity type passing through the gate extension region on the one conductivity type silicon single crystal substrate and the gate extension region on the second conductivity type silicon single crystal substrate and connecting the ends of both of the gate extension regions and A step of forming a common gate electrode on the second conductivity type silicon single crystal substrate; and a predetermined region on the first conductivity type silicon single crystal substrate using the predetermined region of the gate electrode as a mask. Introducing a second conductivity type impurity into the first conductivity type impurity, a step of introducing a first conductivity type impurity into a predetermined region on the second conductivity type silicon single crystal substrate using the predetermined region of the gate electrode as a mask, Forming a sidewall of the gate electrode; and introducing a second conductivity type impurity into the first conductivity type silicon single crystal substrate side using the gate extension region portion of the gate electrode and the sidewall region as a mask. Forming a second conductive type first region and a second conductive type second region across the gate electrode, and extending the gate electrode to the second conductive type silicon single crystal substrate side. The first conductivity type third region and the second region are separated from the gate electrode by introducing a first conductivity type impurity using the region portion and the sidewall region as a mask. Forming a fourth region of adjacent first conductivity type, and connecting to the first conductivity type silicon single crystal substrate between both the first region and the second region, and adjacent to at least the first region; A step of forming one conductivity type high concentration region, and a second conductivity type high concentration adjacent to at least the third region, connected to the second conductivity type silicon single crystal substrate between the third region and the fourth region. Forming a concentration region, excluding at least the sidewall, a total region of the first region and the first conductivity type high concentration region, a total region of the second region and the fourth region, the third region, Siliciding the total area of the second conductivity type high concentration area and the upper surface of each of the gate electrodes.

  According to the method for manufacturing an SOI semiconductor integrated circuit device of the present invention, the shapes of the first conductivity type silicon single crystal substrate and the second conductivity type silicon single crystal substrate for forming devices of different conductivity types are: An adjacent region and an adjacent region separated by an insulating isolation region are included. The gate electrode has a portion formed on the insulating isolation region, and serves as a gate electrode shared between both devices. Further, as a combination of devices having different conductivity types, the second region and the fourth region are adjacent to each other, and are suitable for common drain connection. In addition, the first conductivity type high concentration region and the second conductivity type high concentration region, which are connected to the silicon single crystal substrate of each body, are adjacent to the first region, respectively, and are suitable for the source / tie structure of the body. The isolation region is important for realizing a self-aligned silicide configuration together with the sidewall of the gate electrode. As a result, the distance between devices of different conductivity types is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

  In the method for manufacturing an SOI semiconductor integrated circuit device according to the present invention, the step of forming the first conductivity type high concentration region is the same as at least a part of the step of forming the third region and the fourth region. The step of forming the second conductivity type high concentration region is achieved in the same step as at least a part of the step of forming the first region and the second region.

Further, an SOI semiconductor integrated circuit device as a more preferred embodiment according to the present invention includes a first conductivity type silicon single crystal substrate on an insulating layer, and the first conductivity type silicon single crystal substrate on the insulating layer. The adjacent second conductive type silicon single crystal substrate, the second conductive type first region and the second conductive type second region provided on the first conductive type silicon single crystal substrate, the first conductive type A first conductivity type high-concentration region adjacent to the first region, and a second conductivity type silicon single crystal substrate between the first region and the second region; The first conductivity type third region and the first conductivity type fourth region adjacent to the second region,
A second conductivity type high concentration region adjacent to the third region, connected to the second conductivity type silicon single crystal substrate between both the third region and the fourth region; and the first conductivity type high concentration region; The isolation region of the second conductivity type high concentration region and the first conductivity type silicon single crystal substrate between both the first region and the second region are adjacent to the first conductivity type high concentration region. Adjacent to the second conductivity type high-concentration region on the first conductivity type silicon single crystal substrate and on the second conductivity type silicon single crystal substrate between the third region and the fourth region. A gate electrode provided on the second conductivity type silicon single crystal substrate through a gate insulating film, a sidewall of the gate electrode, at least the sidewall, the second region, and the first conductivity type high The predetermined area including the boundary of the density area and its The first region and the first conductivity type high concentration except for the gate electrode portion in the vicinity and the predetermined region including the boundary between the fourth region and the second conductivity type high concentration region and the gate electrode portion in the vicinity thereof. Silicide provided on the upper surface of the total region of the region, the total region of the second region and the fourth region, the total region of the third region and the second conductivity type high concentration region, and the predetermined region of the gate electrode Including.

  According to the SOI semiconductor integrated circuit device of the present invention, the first conductivity type and the second conductivity type silicon single crystal bases are adjacent to each other, and the first conductivity type, the first region, the second region, and the first conductivity type, respectively. The third and fourth regions are provided. With such a configuration, the second region and the fourth region are adjacent to each other as a combination of devices having different conductivity types, which is suitable for common drain connection. The first conductivity type high concentration region connected to the silicon single crystal substrate of each body is adjacent to the first region, and the second conductivity type high concentration region is adjacent to the third region, which is suitable for the source / tie structure of the body. The first conductivity type high concentration region and the second conductivity type high concentration region are separated by a separation region. The isolation region is a component in the form of a self-aligned silicide together with the sidewall of the gate electrode. In addition, there is a portion that needs to be prevented from being short-circuited by silicidation, a predetermined region including a boundary between the second region and the first conductivity type high concentration region, a gate electrode portion in the vicinity thereof, and a fourth region and the second conductivity type high region. The predetermined region including the boundary of the concentration region and the gate electrode portion in the vicinity thereof are not provided with silicide. As a result, the distance between devices of different conductivity types is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

In the SOI semiconductor integrated circuit device according to the present invention, the gate electrode is a shared electrode extending from the first conductivity type silicon single crystal substrate to the second conductivity type silicon single crystal substrate.
Further, in the SOI semiconductor integrated circuit device according to the present invention, the gate electrode has the second conductivity type from above the first conductivity type silicon single crystal substrate connecting each end on the side opposite to the isolation region. It is a shared electrode straddling on a silicon single crystal substrate.

  A method for manufacturing an SOI semiconductor integrated circuit device according to the present invention includes a first conductivity type silicon single crystal substrate including regions adjacent to each other on an insulating layer and regions adjacent to each other by an insulating isolation region, and Forming a second conductive type silicon single crystal substrate; forming a gate insulating film on the first conductive type and second conductive type silicon single crystal substrates; and The first conductivity type passing through the gate extension region on the one conductivity type silicon single crystal substrate and the gate extension region on the second conductivity type silicon single crystal substrate and connecting the ends of both of the gate extension regions and A step of forming a common gate electrode on the second conductivity type silicon single crystal substrate; and a predetermined region on the first conductivity type silicon single crystal substrate using the predetermined region of the gate electrode as a mask. Introducing a second conductivity type impurity into the first conductivity type impurity, a step of introducing a first conductivity type impurity into a predetermined region on the second conductivity type silicon single crystal substrate using the predetermined region of the gate electrode as a mask, Forming a sidewall of the gate electrode; and introducing a second conductivity type impurity into the first conductivity type silicon single crystal substrate side using the gate extension region portion of the gate electrode and the sidewall region as a mask. Forming a second conductive type first region and a second conductive type second region across the gate electrode, and extending the gate electrode to the second conductive type silicon single crystal substrate side. The first conductivity type third region and the second region are separated from the gate electrode by introducing a first conductivity type impurity using the region portion and the sidewall region as a mask. Forming a fourth region of adjacent first conductivity type, and connecting to the first conductivity type silicon single crystal substrate between both the first region and the second region, and adjacent to at least the first region; A step of forming one conductivity type high concentration region, and a second conductivity type high concentration adjacent to at least the third region, connected to the second conductivity type silicon single crystal substrate between the third region and the fourth region. A step of forming a concentration region, a predetermined region including at least a boundary between the second region and the first conductivity type high concentration region, the gate electrode portion in the vicinity thereof, and the fourth region and the second conductivity type high concentration. A step of forming a protective layer covering a predetermined region including a boundary of the region and the gate electrode portion in the vicinity thereof, and at least the sidewall and the protective layer except for the first region and the first conductivity type high concentration region. General area, Silicidizing the upper surface of each of the second region and the fourth region, the third region and the second conductivity type high concentration region, and the predetermined region of the gate electrode.

  According to the method for manufacturing an SOI semiconductor integrated circuit device of the present invention, the shapes of the first conductivity type silicon single crystal substrate and the second conductivity type silicon single crystal substrate for forming devices of different conductivity types are: An adjacent region and an adjacent region separated by an insulating isolation region are included. The gate electrode has a portion formed on the insulating isolation region, and serves as a gate electrode shared between both devices. Further, as a combination of devices having different conductivity types, the second region and the fourth region are adjacent to each other, and are suitable for common drain connection. In addition, the first conductivity type high concentration region and the second conductivity type high concentration region, which are connected to the silicon single crystal substrate of each body, are adjacent to the first region, respectively, and are suitable for the source / tie structure of the body. The isolation region and the protective layer are important for realizing a self-aligned silicide configuration together with the sidewall of the gate electrode. As a result, the distance between devices of different conductivity types is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

  In the method for manufacturing an SOI semiconductor integrated circuit device according to the present invention, the step of forming the first conductivity type high concentration region is the same as at least a part of the step of forming the third region and the fourth region. The step of forming the second conductivity type high concentration region is achieved in the same step as at least a part of the step of forming the first region and the second region.

BEST MODE FOR CARRYING OUT THE INVENTION

1 to 4 are each a diagram showing a main configuration of the SOI semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 1 is a plan view, and FIG. 3 is a cross-sectional view taken along line F3-F3 shown in FIG. 1, and FIG. 4 is a cross-sectional view taken along line F4-F4 shown in FIG.
The SOI substrate 11 has a single crystal substrate disposed on a buried insulating layer 10 provided on a base substrate (not shown). The single crystal substrate 13 in the element region surrounded by the element isolation region 12 includes an N-type well region (N ⁻ well) 131 and a P-type well region (P ⁻ well) 132. The N ⁻ well region 131 and the P ⁻ well region 132 have a region adjacent to each other and a region adjacent to each other at the portion 12 a of the element isolation region 12. In the case of showing the relationship between the regions, “adjacent” means that both regions are in contact with each other, and “adjacent” means that both regions are in a non-contact positional relationship.

In the N ⁻ well region 131, a P-type source region S1 and a drain region D1 are formed. The source region S1 and the drain region D1 are each composed of a relatively low concentration impurity region (N ⁻ extension region) and a relatively high concentration impurity region (N ⁺ region). The N ⁺ region BC1 is a body contact region having a higher concentration than the N ⁻ well region 131. The N ⁺ region BC1 is connected to the N ⁻ well region 131 between the source region S1 and the drain region D1, and is formed adjacent to the source region S1.

On the other hand, an N-type source region S2 and drain region D2 are formed in the P ^- well region 132. The source region S2 and the drain region D2 are each composed of a relatively low concentration impurity region (P ⁻ extension region) and a relatively high concentration impurity region (P ⁺ region). Further, the P ⁺ region BC2 is a body contact region having a higher concentration than the P ⁻ well region 132. The P ⁺ region BC2 is connected to the P ⁻ well region 132 between the source region S2 and the drain region D2, and is formed adjacent to the source region S2.

The gate electrode 15, the source region S1, N between the drain region D1 ^- over well region 131, N between the ^{N +} region BC1 and the drain region D1 ^- on well region 131 and source region S2, the drain region D2 over well region 132, P between ^{P +} region BC2 and the drain region D2 ^{- -} P between the upper well region 132, it is provided via a gate insulating film 14. The gate electrode 15 extends on the portion 12 a of the element isolation region 12, and serves as a common electrode extending from the N ⁻ well region 131 to the P ⁻ well region 132. Side walls 16 are formed on the gate electrode 15.

From the above configuration, the P-channel MOSFET Qp includes the N ⁺ region BC1 formed in the N ⁻ well region 131, the source region S1, the drain region D1, the gate insulating film 14 and the gate electrode 15 therebetween. The N-channel MOSFET Qn includes a P ⁺ region BC2 formed in the P ^- well region 132, a source region S2, a drain region D2, a gate insulating film 14 therebetween, and a gate electrode 15.

In addition, the silicide layer 17, except for the sidewall 16, includes a total region of the source region S 1 and the N ⁺ region BC 1, a total region of the drain regions D 1 and D 2, a total region of the source region S 2 and the P ⁺ region BC 2, and the gate electrode 15. It is provided on each upper surface. Thereby, each region is further reduced in resistance.

According to the configuration of the above embodiment, the N-type well region (N ^- well) 131 and the P-type well region (P ^- well) 132 are adjacent to each other as the silicon single crystal substrate, and the source / drain regions are provided in the respective substrates. I did it. As a combination of such a horizontally placed P-channel MOSFET Qp and N-channel MOSFET Qn, the drain regions D1 and D2 are adjacent to each other and are suitable for common drain connection. In addition, the N ⁺ region BC1 of each body contact is adjacent to the source region S1 and the P ⁺ region BC2 is adjacent to the source region S2, which is suitable for the source tie structure of the body. Further, the N ⁺ region BC1 and the P ⁺ region BC2 are separated by the element isolation region 12 under the gate electrode 15. The element isolation region 12 under the gate electrode 15 is a component in a self-aligned silicide form together with the sidewall 16. With such a configuration, the distance between devices of different conductivity types can be greatly reduced, and even if a contact for body potential is provided, an increase in cell area can be minimized.

5 to 7 are plan views showing the main part of the manufacturing method of the SOI semiconductor integrated circuit device according to the second embodiment of the present invention in the order of steps. This is an example method for realizing the configuration shown in FIG. 1, and the same parts as those in FIG.
As shown in FIG. 5, in the SOI substrate 11 on the buried insulating film 10, an element isolation region 12 is formed using a trench element isolation method or the like. The element isolation region portion 12a becomes a body contact ion-implanted resist together with a gate electrode to be formed later, and becomes a silicide block. Next, in the single crystal substrate 13, after forming a sacrificial oxide film (not shown), an N-type well region (N ^- well) 131 and a P-type well region (P ^- well) that are adjacent to each other using an ion implantation method. 132 is formed. Although not shown, impurity ion implantation for adjusting the threshold value of each channel is also performed.

Next, as shown in FIG. 6, after the sacrificial oxide film is removed by wet etching or the like, a gate insulating film (for example, 14 in FIG. 2) (not shown) is formed by using a wet oxidation method or the like. To deposit a polysilicon layer. Next, after ion implantation for obtaining predetermined conductivity, patterning is performed as a polysilicon electrode. Thereby, the gate electrode 15 is formed. Here, the pattern of the gate electrode 15 passes through the gate extension region on the N ⁻ well region 131, the gate extension region on the P ⁻ well region 132, and the element isolation region portion 12 a, and ends of both of the gate extension regions. A common electrode pattern is used for the N ^- well region 131 and the P ^- well region 132 that connect each other.

Next, although not shown, P channel impurity ion implantation under a predetermined condition is performed on a predetermined region of the N ⁻ well region 131 using the region of the gate electrode 15 as a mask. Similarly, N channel impurity ion implantation under a predetermined condition is performed on the predetermined region of the P ^- well region 132 using the region of the gate electrode 15 as a mask. As these ion implantations, extension regions represented by an LDD structure or the like, pocket ion implantation (halo), or the like can be considered.

Next, an insulating film is deposited so as to cover the gate electrode 15 by CVD, and anisotropic dry etching is performed. Thereby, the sidewall 16 is formed. Next, in a predetermined region of the N ⁻ well region 131, a P ⁺ region is formed by performing impurity ion implantation under a predetermined condition using the region of the gate electrode 15 and the sidewall 16 as a mask. Thereby, the source region S1 and the drain region D1 are formed. Also, P ^- in a predetermined area of the well area 132, so that adjacent to the source region S2 to be formed later, P ^- forming a ^{P +} region BC2 connect with well region 132. The P ⁺ region and the P ⁺ region BC2 of the source region S1 and the drain region D1 may be formed in the same process by sharing an ion implantation mask (not shown). It is also conceivable that a separate ion implantation mask is used and formed in a separate process.

Next, as shown in FIG. 7, an N ⁺ region is formed in a predetermined region of the P ⁻ well region 131 by performing impurity ion implantation under a predetermined condition using the region of the gate electrode 15 and the sidewall 16 as a mask. To do. Thereby, the source region S2 and the drain region D2 are formed. Further, an N ⁺ region BC1 connected to the N ⁻ well region 131 is formed so as to be adjacent to the source region S1. The N ⁺ region and the N ⁺ region BC1 of the source region S2 and the drain region D2 may be formed in the same process by sharing an ion implantation mask (not shown). It is also conceivable that a separate ion implantation mask is used and formed in a separate process.

  Further, a salicide process is performed on the configuration of FIG. That is, in the element region, except for the sidewall 16, the surfaces of the gate electrode 15 and the source / drain regions S1, D1, S2, and D2 are silicided in a self-aligning manner. Thereby, the silicide layer 17 is formed (see FIG. 1).

According to the method of the above embodiment, the N ^- well region 131 and the P ^- well region 132 have different shapes from each other in order to form devices (MOSFETs Qp, Qn) having different conductivity types. The area | region adjacently separated by 12a is contained. The gate electrode 15 has a portion formed on the element isolation region portion 12a, and serves as a gate electrode shared between both devices (Qp, Qn). Further, as a combination of devices (Qp, Qn) having different conductivity types, the drains D1, D2 are adjacent to each other and are suitable for common drain connection. The N ⁺ region BC1 connected to the N ⁻ well region 131 is adjacent to the source region S1 and the P ⁺ region BC2 connected to the P ⁻ well region 132 is adjacent to the source region S2 and is suitable for the source / tie structure of the body. The element isolation region portion 12 a is important for realizing a self-aligned silicide form together with the sidewall 16. As a result, the distance between the MOSFETs Qp and Qn is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

8 to 11 are each a diagram showing a configuration of a main part of an SOI semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 8 is a plan view, and FIG. 9 is F9− shown in FIG. FIG. 10 is a sectional view taken along line F9, FIG. 10 is a sectional view taken along line F10-F10 shown in FIG. 8, and FIG. 11 is a sectional view taken along line F11-F11 shown in FIG.
The SOI substrate 21 has a single crystal substrate disposed on a buried insulating layer 20 provided on a base substrate (not shown). The single crystal substrate 23 in the element region surrounded by the element isolation region 22 includes an N-type well region (N ⁻ well) 231 and a P-type well region (P ⁻ well) 232. The N ⁻ well region 231 and the P ⁻ well region 232 have regions adjacent to each other and separated from each other by the portion 22 a of the element isolation region 22.

In the N ⁻ well region 231, a P-type source region S1 and a drain region D1 are formed. The source region S1 and the drain region D1 are each composed of a relatively low concentration impurity region (N ⁻ extension region) and a relatively high concentration impurity region (N ⁺ region). The N ⁺ region BC1 is a body contact region having a higher concentration than the N ⁻ well region 231. The N ⁺ region BC1 is connected to the N ⁻ well region 231 between the source region S1 and the drain region D1, and is formed adjacent to the source region S1.

On the other hand, an N-type source region S2 and drain region D2 are formed in the P ^- well region 232. The source region S2 and the drain region D2 are each composed of a relatively low concentration impurity region (P ⁻ extension region) and a relatively high concentration impurity region (P ⁺ region). Further, the P ⁺ region BC2 is a body contact region having a higher concentration than the P ⁻ well region 232. The P ⁺ region BC2 is connected to the P ⁻ well region 232 between the source region S2 and the drain region D2, and is formed adjacent to the source region S2.

The gate electrode 25, the source regions S1, N between the drain region D1 ^- over well region 231, N between the ^{N +} region BC1 and the drain region D1 ^- on well region 231 and source region S2, the drain region D2 over well region 232, P between ^{P +} region BC2 and the drain region D2 ^{- -} P between the upper well region 232, it is provided via a gate insulating film 24. The gate electrode 25 extends on the part 22 b of the element isolation region 22 opposite to the part 22 a of the element isolation region 22, and serves as a shared electrode extending from the N ⁻ well region 231 to the P ⁻ well region 232. . A sidewall 26 is formed on the gate electrode 25.

From the above configuration, the P-channel MOSFET Qp includes the N ⁺ region BC1 formed in the N ⁻ well region 231, the source region S1, the drain region D1, the gate insulating film 24 and the gate electrode 25 therebetween. The N-channel MOSFET Qn includes a P ⁺ region BC2 formed in the P ^- well region 232, a source region S2, a drain region D2, a gate insulating film 24 and a gate electrode 25 therebetween.

The silicide layer 27 includes the sidewall 26, the predetermined region 31 including the boundary between the drain region D1 and the N ⁺ region BC1, the portion 251 of the gate electrode 25 in the vicinity thereof, and the boundary between the drain region D2 and the P ⁺ region BC2. Except for the predetermined region 32 and the gate electrode 25 portion 252 in the vicinity thereof, the total region of the source region S1 and the N ⁺ region BC1, the total region of the drain regions D1 and D2, the total region of the source region S2 and the P ⁺ region BC2, and the gate The electrode 25 is provided on the upper surface of each predetermined region. Thereby, each region has a lower resistance, and S1 and BC1, and S2 and BC2 are electrically connected to each other.

According to the configuration of the above embodiment, the N-type well region (N ^- well) 231 and the P-type well region (P ^- well) 232 are adjacent to each other as the silicon single crystal substrate, and the source / drain regions are provided in the respective substrates. I did it. A combination of such a horizontally placed P-channel MOSFET Qp and N-channel MOSFET Qn is suitable for common connection of the drain regions D1 and D2. In addition, the N ⁺ region BC1 of each body contact is adjacent to the source region S1 and the P ⁺ region BC2 is adjacent to the source region S2, respectively, which is suitable for the source tie structure of the body.

Further, the N ⁺ region BC1 and the P ⁺ region BC2 are separated by the element isolation region 22 below the gate electrode 25. The element isolation region 22 under the gate electrode 25 is a component in the form of a self-aligned silicide together with the sidewall 26. In addition, there is a portion where a short circuit due to silicidation should be prevented. That is, the predetermined region 31 including the boundary between the drain region D1 and the N ⁺ region BC1 and the portion 251 of the gate electrode 25 in the vicinity thereof, and the predetermined region 32 including the boundary between the drain region D2 and the P ⁺ region BC2 and the gate electrode in the vicinity thereof. The 25 portion 252 is not provided with silicide. With such a configuration, the distance between devices of different conductivity types can be greatly reduced, and even if a contact for body potential is provided, an increase in cell area can be minimized.

12 to 15 are plan views showing the main part of the method for manufacturing an SOI semiconductor integrated circuit device according to the fourth embodiment of the present invention in the order of steps. This is an example method for realizing the configuration of FIG. 8, and the same parts as those in FIG.
As shown in FIG. 12, in the SOI substrate 21 on the buried insulating film 20, an element isolation region 22 is formed using a trench element isolation method or the like. Next, in the single crystal substrate 23, after forming a sacrificial oxide film (not shown), an N-type well region (N ^- well) 231 and a P-type well region (P ^- well) that are adjacent to each other using an ion implantation method. 232 is formed. Although not shown, impurity ion implantation for adjusting the threshold value of each channel is also performed.

Next, as shown in FIG. 13, after removing the sacrificial oxide film by wet etching or the like, a gate insulating film (for example, 24 in FIG. 9) (not shown) is formed by using a wet oxidation method or the like. To deposit a polysilicon layer. Next, after ion implantation for obtaining predetermined conductivity, patterning is performed as a polysilicon electrode. Thereby, the gate electrode 25 is formed. Here, the pattern of the gate electrode 25 passes through the gate extension region on the N ⁻ well region 231, the gate extension region on the P ⁻ well region 232, and the element isolation region portion 22 b, and ends of both the gate extension regions. A common electrode pattern is used for the N ^- well region 231 and the P ^- well region 232 that connect each other.

Next, although not shown, P channel impurity ion implantation under a predetermined condition is performed on the predetermined region of the N ⁻ well region 231 using the region of the gate electrode 25 as a mask. Similarly, N channel impurity ion implantation under a predetermined condition is performed on a predetermined region of the P ⁻ well region 232 using the region of the gate electrode 25 as a mask. As these ion implantations, extension regions represented by an LDD structure or the like, pocket ion implantation (halo), or the like can be considered.

Next, an insulating film is deposited by CVD to cover the gate electrode 25, and anisotropic dry etching is performed. Thereby, the sidewall 26 is formed. Next, in a predetermined region of the N ⁻ well region 231, a P ⁺ region is formed by performing impurity ion implantation under a predetermined condition using the region of the gate electrode 25 and the sidewall 26 as a mask. Thereby, the source region S1 and the drain region D1 are formed. In addition, a P ⁺ region BC2 connected to the P ⁻ well region 232 is formed in a predetermined region of the P ⁻ well region 232 so as to be connected to the source region S2 to be formed later. The P ⁺ region and the P ⁺ region BC2 of the source region S1 and the drain region D1 may be formed in the same process by sharing an ion implantation mask (not shown). It is also conceivable that a separate ion implantation mask is used and formed in a separate process.

Next, as shown in FIG. 14, an N ⁺ region is formed in a predetermined region of the P ⁻ well region 231 by performing impurity ion implantation under a predetermined condition using the region of the gate electrode 25 and the side wall 26 as a mask. To do. Thereby, the source region S2 and the drain region D2 are formed. Further, an N ⁺ region BC1 connected to the N ⁻ well region 231 is formed so as to be connected to the source region S1. The N ⁺ region and the N ⁺ region BC1 of the source region S2 and the drain region D2 may be formed in the same process by sharing an ion implantation mask (not shown). It is also conceivable that a separate ion implantation mask is used and formed in a separate process.

Next, as shown in FIG. 15, a protective layer PRT for the silicide block is formed. The protective layer PRT includes the predetermined region 31 including the boundary between the drain region D1 and the N ⁺ region BC1 and the portion 251 of the gate electrode 25 in the vicinity thereof, and the predetermined region 32 including the boundary between the drain region D2 and the P ⁺ region BC2 and the vicinity thereof. Patterning is performed so as to cover the portion 252 of the gate electrode 25. The protective layer PRT uses, for example, an oxide film, and may have a rectangular shape that crosses over the element isolation region portion 22a as shown in the figure. The protective layer PRT slightly covers the boundary side between the source region S1 and the N ⁺ region BC1 and the boundary side between the source region S2 and the P ⁺ region BC2 in order to secure a positioning margin. Next, the salicide process is performed. That is, in the element region, the surfaces of the gate electrode 25 and the source / drain regions S1, D1, S2, and D2 are silicided in a self-aligned manner except for the sidewall 26 and the protective layer PRT. Thereby, the silicide layer 27 is formed (see FIG. 8).

According to the method of the above-described embodiment, the N ^- well region 231 and the P ^- well region 232 have different shapes from each other in order to form devices (MOSFETs Qp, Qn) having different conductivity types. The area | region which is spaced apart and adjacent by 22a is included. The gate electrode 25 has a portion formed on the element isolation region portion 22b, and serves as a common gate electrode between both devices (Qp, Qn). Moreover, it is suitable for the common connection of the drains D1, D2 as a combination of devices (Qp, Qn) having different conductivity types. The N ⁺ region BC1 connected to the N ⁻ well region 231 is adjacent to the source region S1 and the P ⁺ region BC2 connected to the P ⁻ well region 232 is adjacent to the source region S2 and is suitable for the source / tie structure of the body. The element isolation region portion 22a and the protective layer PRT are important for realizing a self-aligned silicide form together with the sidewall 26. As a result, the distance between the MOSFETs Qp and Qn is greatly reduced, and even if a contact for body potential is provided, the silicidation configuration is compact and the increase in cell area is minimized.

In each of the embodiments or methods described above, FIG. 1 shows that the drain regions D1 and D2, the source S1 and the N ⁺ region BC1, and the source S2 and the P ⁺ region BC2 are not in contact with each other and are adjacent to each other. The injection region (dashed line) is shown. Also in FIG. 2, the drain regions D1 and D2 are shown adjacent to each other without contact. On the other hand, FIG. 8 shows ion implantation regions (broken lines) in which the drain regions D1 and D2, the source S1 and the N ⁺ region BC1, and the source S2 and the P ⁺ region BC2 are adjacent (contacted). Also in FIG. 9, the drain regions D1 and D2 are shown to be adjacent (contact). Such a difference in illustration is not clear in practice and depends on ion implantation accuracy and other process margins, and either form may be used.

As described above, according to the configuration and method of each embodiment, a horizontally placed logic cell of a compact P-channel MOSFET Qp and N-channel MOSFET Qn can be obtained. That is, the N ^- well region and the P ^- well region of the silicon single crystal substrate having opposite conductivity types are formed adjacent to each other. After that, reverse conductivity type impurities are introduced into the N ^- well region side and the P ^- well region side using the gate electrode and sidewall regions as masks, respectively. Each body contact region is separated from each other by an element isolation region and a protective layer. Further, it is easy to use a salicide process in which the surfaces of the gate electrode, each source / drain region and the body contact region are silicided in a self-aligning manner. As a result, a compact logic cell that contributes to low resistance and high-speed operation of the device is configured. As a result, an SOI semiconductor integrated circuit device which can be laid out so as to easily provide a body potential contact in a horizontal configuration in which drains of different conductivity types are adjacent to each other and minimize an increase in cell area, and a method for manufacturing the same. can do.

FIG. 2 is a plan view showing the main configuration of the SOI semiconductor integrated circuit device according to the first embodiment. F2-F2 sectional view taken on the line of FIG. F3-F3 sectional view taken on the line of FIG. F4-F4 sectional view taken on the line of FIG. The 1st top view showing the principal part process of the manufacturing method of the SOI semiconductor integrated circuit device concerning a 2nd embodiment. FIG. 6 is a second plan view following FIG. 5. The 3rd top view following FIG. The top view which shows the principal part structure of the SOI semiconductor integrated circuit device which concerns on 3rd Embodiment. F9-F9 sectional view taken on the line of FIG. F10-F10 sectional view taken on the line of FIG. F11-F11 sectional view taken on the line of FIG. The 1st top view showing the principal part process of the manufacturing method of the SOI semiconductor integrated circuit device concerning a 4th embodiment. FIG. 13 is a second plan view following FIG. 12. FIG. 14 is a third plan view following FIG. 13. The 3rd top view following FIG.

Explanation of symbols

10, 20 ... buried insulating film, 11, 21 ... SOI substrate, 12, 22 ... element isolation region, 13, 23 ... single crystal substrate, 131, 231 ... N-type well region (N ^- well), 132, 232 ... P Type well region (P ^- well), 14, 24 ... gate insulating film, 15, 25 ... gate electrode, 16, 26 ... sidewall, 17, 27 ... silicide layer, Qp ... P channel MOSFET, Qn ... N channel MOSFET, S1, S2 ... source region, D1, D2 ... drain region, BC1 ... N ⁺ region (body contact region), BC2 ... P ⁺ region (body contact region), PRT ... protective layer.

Claims (5)

A first conductivity type silicon single crystal substrate on an insulating layer;
A second conductivity type silicon single crystal substrate in contact with the first conductivity type silicon single crystal substrate on the insulating layer;
A first region of a second conductivity type and a second region of a second conductivity type provided on the first conductivity type silicon single crystal substrate;
A first conductivity type high concentration region adjacent to the first region, connected to the first conductivity type silicon single crystal substrate between the first region and the second region;
A first conductivity type third region provided on the second conductivity type silicon single crystal substrate and a first conductivity type fourth region adjacent to the second region;
A second conductivity type high-concentration region connected to the second conductivity type silicon single crystal substrate between both the third region and the fourth region, and adjacent to the third region;
A separation region of the first conductivity type high concentration region and the second conductivity type high concentration region;
From the first conductivity type silicon single crystal substrate between both the first region and the second region, to the first conductivity type silicon single crystal substrate adjacent to the first conductivity type high concentration region, and From the second conductivity type silicon single crystal substrate between both the third region and the fourth region, to the second conductivity type silicon single crystal substrate adjacent to the second conductivity type high concentration region, A gate electrode provided via a gate insulating film;
A sidewall of the gate electrode;
A predetermined region including at least the sidewall, a boundary between the second region and the first conductivity type high concentration region, the gate electrode portion in the vicinity thereof, and a boundary between the fourth region and the second conductivity type high concentration region; Excluding the predetermined region including the gate electrode portion in the vicinity thereof, the total region of the first region and the first conductivity type high concentration region, the total region of the second region and the fourth region, the third region and the A silicide formed on the upper surface of each of the total region of the second conductivity type high concentration region and the predetermined region of the gate electrode;
SOI semiconductor integrated circuit device. Wherein the gate electrode, SOI semiconductor integrated circuit device of claim 1, wherein a first conductivity type silicon single crystal substrate on which a common electrode extending over the second conductivity type silicon single crystal substrate. The gate electrode may claim a common electrode and the isolation region spanning from the first conductivity type silicon single crystal substrate connecting the end opposite to the second conductivity type silicon single crystal substrate 1 The SOI semiconductor integrated circuit device described. Forming a first conductivity type silicon single crystal substrate and a second conductivity type silicon single crystal substrate including a region in contact with each other on the insulating layer and a region adjacent to each other by an insulating isolation region; ,
Forming a gate insulating film on the first conductivity type and second conductivity type silicon single crystal substrates;
On the gate insulating film, it passes through a gate extension region on the first conductivity type silicon single crystal substrate and a gate extension region on the second conductivity type silicon single crystal substrate, and ends of both gate extension regions. Forming a common gate electrode on the silicon single crystal substrates of the first conductivity type and the second conductivity type that connect each other;
Introducing a second conductivity type impurity into a predetermined region using the predetermined region of the gate electrode as a mask on the first conductivity type silicon single crystal substrate;
Introducing a first conductivity type impurity into a predetermined region using the predetermined region of the gate electrode as a mask on the second conductivity type silicon single crystal substrate;
Forming a sidewall of the gate electrode;
By introducing a second conductivity type impurity into the first conductivity type silicon single crystal substrate side using the gate extension region portion of the gate electrode and the sidewall region as a mask, the second conductivity type is separated from the gate electrode. Forming a first region of a mold and a second region of a second conductivity type;
By introducing a first conductivity type impurity into the second conductivity type silicon single crystal substrate side using the gate extension region portion of the gate electrode and the sidewall region as a mask, the first conductivity type is separated from the gate electrode. Forming a third region of the mold and a fourth region of the first conductivity type adjacent to the second region;
Forming a first conductivity type high concentration region adjacent to at least the first region connected to the first conductivity type silicon single crystal substrate between both the first region and the second region;
Forming a second conductivity type high concentration region adjacent to at least the third region, connected to the second conductivity type silicon single crystal substrate between both the third region and the fourth region;
A predetermined region including at least a boundary between the second region and the first conductivity type high concentration region, the gate electrode portion in the vicinity thereof, and a predetermined region including a boundary between the fourth region and the second conductivity type high concentration region; Forming a protective layer covering the gate electrode portion in the vicinity thereof;
Except at least the sidewall and the protective layer, the first region and the first conductivity type high concentration region, the second region and the fourth region, the third region and the second conductivity Silicidizing the upper surface of each of the integrated region of the high concentration region of the mold and the predetermined region of the gate electrode;
Of manufacturing an SOI semiconductor integrated circuit device. The step of forming the first conductivity type high concentration region is achieved by the same step as the step of forming the third region and the fourth region, and the step of forming the second conductivity type high concentration region. 5. The method for manufacturing an SOI semiconductor integrated circuit device according to claim 4 , wherein the method is achieved in the same step as at least a part of the step of forming the first region and the second region.

Images