JP4602364B2 - Liquid crystal drive device and liquid crystal display system - Google Patents

Description

  The present invention relates to a technique that is useful when applied to a semiconductor integrated circuit having a differential circuit such as a small amplitude differential signal interface, and is particularly useful when applied to a semiconductor integrated circuit that receives two power supplies such as a liquid crystal driver. Technology.

  For example, as a liquid crystal driver for driving a data line of a TFT (thin film transistors) liquid crystal panel used as a display in a notebook computer or the like, for example, 6-bit digital display data per pixel is inputted at high speed, and these digital data are Some of them generate 384 liquid crystal driving output voltages with 64 gradations.

In recent years, LVDS (Low Voltage Differential Signaling) or a small-amplitude differential signal interface derived therefrom is used as an interface for transmitting and receiving digital data at high speed in such a liquid crystal driver. By using such a small-amplitude differential signal interface, it is possible to reduce power consumption and electromagnetic interference (EMI) of input / output signals compared to the case where a CMOS level interface or the like is applied. I can do it.
Japanese Patent Laid-Open No. 5-284004

FIG. 5 shows a MOSFET circuit diagram of an example of a small amplitude differential signal interface studied by the present inventors before the present invention.
For example, as shown in FIG. 5, the small-amplitude differential signal interface amplifies a differential voltage of an input differential signal, and an output voltage from the differential amplification stage 61 is raised by a level shift circuit 62a. And a drive stage 62 that generates a signal on the output side based on the output voltage, and an output stage 63 that drives a load connected to the output side and outputs a signal having a predetermined amplitude. is there. The differential amplifier stage 61 is provided with a constant current MOSFET Q61 that is connected to a common source of the pair of differential input MOSFETs Q62 and Q63 and supplies a constant current. The constant current MOSFET Q61 provides a differential amplifier stage. The direct current flowing through 61 is controlled.

  By the way, in a small-amplitude differential signal interface and a semiconductor chip equipped with the interface, a request for widening the fluctuation tolerance of the center voltage of the input differential signal and a power supply voltage for logic supplied to the semiconductor chip are set. There is a demand to lower the power consumption by lowering.

  However, in the above-described small amplitude differential signal interface, the logic power supply voltage VCC supplied to the drive stage 62 and the output stage 63 is supplied to the source of the constant current MOSFET Q61 provided in the differential amplifier stage 61. Since the power supply voltage VCC is lowered, the gate-source voltage Vgs of the constant current MOSFET Q61 is also reduced because of the common supply configuration.

The following equation (1) shows the drain current equation in the saturation region of the MOSFET.
I = β (W / L) (Vgs−Vth) ² (1)
Here, β is a constant, W is a gate width, L is a gate length, and Vth is a threshold voltage.
As can be seen from this equation (1), when the gate-source voltage Vgs decreases, the influence of this variation on the current value I when the threshold voltage Vth deviates from the reference value due to MOSFET process variation. There arises a problem that the gate width needs to be increased in order to allow the same current to flow.

  Further, when the power supply voltage VCC is lowered, the potential of the common source of the differential input MOSFETs Q62 and Q63 is also lowered, so that the current flowing through the differential amplifier stage 61 due to the fluctuation of the center voltage of the input differential signals YP and YN is relatively high. Since the current consumption and circuit characteristics are changed greatly, there arises a problem that the fluctuation tolerance of the center voltage of the input differential signals YP and YN cannot be widened.

  Further, when the potential of the common source of the differential input MOSFETs Q62 and Q63 is lowered, the output voltage from the differential amplifier stage is lowered, and there is a problem that it is necessary to provide a level shift circuit 62a in the subsequent drive stage 62. there were. However, since the level shift circuit 62a needs to pass a direct current, the current consumption increases accordingly, so that the direct current passed through the level shift circuit 62a is generally designed to be small. However, such a design causes a problem that the rise of the signal in the level shift circuit 62a is delayed and the signal delay time is increased.

  From the above, in the semiconductor integrated circuit having the input circuit as shown in FIG. 5, the power supply voltage VCC for logic cannot be set very low, and as a result, the power consumption of the semiconductor chip cannot be reduced. I found out.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit and a liquid crystal driving device provided with a differential circuit capable of widening the fluctuation tolerance of the center voltage of an input differential signal and reducing power consumption.

  Another object of the present invention is to provide a semiconductor integrated circuit and a liquid crystal driving device capable of widening the allowable fluctuation range of the center voltage of the input differential signal and reducing the power consumption by reducing the logic power supply voltage. There is.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a differential input signal having a pair of differential MOS transistors whose sources are connected in common and a constant current MOS transistor connected between the common source of the differential MOS transistor pair and the power supply voltage terminal. In a semiconductor integrated circuit comprising a differential circuit provided with a differential amplifier stage to be amplified and an output stage for generating an output signal based on a voltage output from one output terminal of the differential amplifier stage, The power supply voltage terminal of the differential amplification stage is configured to be supplied with a second power supply voltage having a voltage value higher than the first power supply voltage supplied to the output stage.

  According to such a means, the gate-source voltage Vgs of the constant current MOS transistor can be increased by the second power supply voltage that is higher than the first power supply voltage. As described above, the influence of variations in the threshold voltage Vth of the transistor on the current can be reduced, and further, the size of the transistor required to flow the same current can be reduced.

  Further, since the voltage on the drain side of the constant current MOS transistor can be increased, fluctuations in current due to changes in the center voltage of the input differential signal can also be suppressed. Accordingly, it is possible to realize a circuit having a wide fluctuation tolerance of the center voltage in which the consumption current and the circuit characteristics are not changed by the fluctuation of the center voltage of the input differential signals YP and YN.

  Further, since the voltage on the drain side of the constant current MOS transistor can be increased, the output voltage from the differential amplification stage can be increased, and there is no need to provide a level shift circuit in the subsequent stage. Therefore, the direct current flowing through the level shift circuit can be eliminated and the power consumption can be reduced, and since the level shift circuit is unnecessary, the rise of the signal can be accelerated and the signal delay time can be shortened.

  In addition, a semiconductor integrated circuit according to the present invention includes an input circuit that receives a pair of differential signals input from the outside and supplies a signal corresponding to a voltage difference between the differential signals to an internal circuit, and An internal logic circuit that receives a signal and performs a logic operation; and an output circuit that outputs a signal having a larger amplitude than the signal of the internal logic circuit to the outside. In a semiconductor integrated circuit in which a second power supply voltage having a voltage value higher than the first power supply voltage is supplied to the output circuit, the input circuit includes a pair of differential MOS transistors whose sources are connected in common and the differential circuit. A differential amplifier stage having a constant current transistor connected between a common source of a MOS transistor pair and a power supply voltage terminal and amplifying a differential input signal, and output from one output terminal of the differential amplifier stage To voltage And an output stage for generating Hazuki output signal, to said power supply voltage terminal of the differential amplifier stage are those constructed as the second power supply voltage is supplied.

  According to such a means, since the second power supply voltage is supplied to the differential amplifier stage, it is possible to widen the center voltage fluctuation allowable range of the differential signal input to the input circuit, and for the logic It is possible to reduce the power consumption by setting the first power supply voltage low. Also, as the second power supply voltage having a voltage value higher than that of the first power supply voltage, a power supply used for outputting a high voltage signal in the output circuit is used, so a new power supply voltage is prepared for the differential amplification stage. There is no need to do. Even when a constant direct current is passed, the transistor size of the differential amplification stage can be reduced, so that the chip area is not increased.

  Specifically, digital data for each pixel consisting of differential signals is input to the input circuit, and a driving voltage for driving a liquid crystal panel is generated based on the digital data and output from the output circuit. In the semiconductor integrated circuit, a liquid crystal driving power source for driving the liquid crystal panel may be used as the second power source voltage.

  More specifically, the constant current transistor is a P-channel MOS transistor in which a bias voltage is applied to the gate and a constant current flows.

  The differential amplifier stage has two differential input P-channel MOS transistors each having a source connected in common and receiving a pair of differential signals at the gates. The two differential input P-channel MOS transistors The common source is connected to the drain of the constant-current P-channel MOS transistor.

  The liquid crystal drive device according to the present invention is provided with standby means for cutting off an operating current flowing in the differential amplification stage in a differential input circuit for inputting display data. According to such means, it is possible to cut off the current that flows unnecessarily to the differential amplifier stage and further reduce the power consumption.

  Desirably, based on an external signal indicating the timing at which a plurality of display data is continuously transferred, the operating current is interrupted by the standby means, and on the basis of detection of completion of input of the continuously transferred display data. It is preferable that the operation current cut off by the standby means is started.

  According to such a configuration, it is not necessary to input a new signal from the outside for controlling the standby means, and the current of the differential amplification stage can be controlled with the conventional input / output signal system exchanged with the outside. Become.

  Preferably, when two input signals are serially input to the input circuit for each external clock, the positive phase side and the negative phase side of the differential external clock are reversed from each other. It is preferable to provide two clock input circuits that are input in relation to each other, and to provide the input timing of the two input signals based on the two clock signals input through the two clock input circuits.

  According to such a configuration, even if conditions such as semiconductor manufacturing variations, differential external clock center voltage, power supply voltage, and temperature change to some extent, it will affect clock signal variations that give input signal capture timing. Since it is difficult, the display data capture timing can be easily adjusted.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, in a differential circuit such as a small-amplitude differential signal interface, there is an effect that the fluctuation tolerance of the center voltage of the input differential signal can be widened and the power consumption can be reduced.

  In addition, in a semiconductor integrated circuit having a small amplitude differential signal interface, there is an effect that the fluctuation tolerance of the input differential signal can be widened and the power supply voltage for logic can be lowered to reduce power consumption.

  In addition, since the standby function cuts off the operating current flowing through the differential amplification stage of the small amplitude differential interface during the blank period when display data is not transferred, the power consumption of the liquid crystal driving circuit and the power consumption of the liquid crystal system are further reduced. I can do it.

  In addition, the standby function is automatically canceled based on a horizontal clock or an enable signal that informs the continuous transfer of display data, and the standby function is automatically started by detecting the end of a series of display data that are continuously transferred. By adopting the function, there is no need to provide a new external signal for the standby function, and the conventional system can be applied as it is.

  In an input interface that inputs data twice with one clock using both edges of the differential clock signal, the clock is output with two differential amplifiers in which the positive phase and negative phase input terminals are inverted. By inputting a signal and capturing data using these clock signals, the clock skew can be reduced and the data can be stably captured. As a result, it becomes possible to relax the conditions of the waveform of the differential clock signal and the data signal, and to perform higher-speed data transfer.

Preferred embodiments of the present invention will be described below with reference to the drawings.
<First embodiment>
FIG. 1 is a circuit diagram showing in detail an embodiment of a small amplitude differential signal interface suitable for application of the present invention. In the figure, a suitable numerical example of the ratio “W / L” between the gate width W (μm) and the gate length L (μm) is shown beside the MOSFET.

  The low-amplitude differential signal interface (differential input circuit) of this embodiment is, for example, an LVDS (Low Voltage Differential Signaling) interface defined by IEEE (Institute of Electrical and Electronics Engineers) or a small-amplitude of its derivative technology. This is a differential signal interface. For example, a small-amplitude differential signal (for example, an amplitude of 200 mV to 500 mV) input from the outside such as an external clock or a data signal is input, and the voltage difference between the pair of small-amplitude differential signals is determined. Thus, a high level or low level signal is output to the internal circuit.

  As shown in FIG. 1, the small-amplitude differential signal interface includes a pair of differential input MOSFETs Q2 and Q3 and a constant current MOSFET Q1 connected to a common source of the differential input MOSFETs Q2 and Q3, and a difference between the differential input MOSFETs Q2 and Q3. The differential amplification stage 1 composed of active load MOSFETs Q4 and Q5 connected to the drains of the dynamic input MOSFETs Q2 and Q3, and the amplified output from the differential amplification stage 1 are received and set to a high level according to the output voltage. The driving stage 2 and the output stage 3 are configured to output a low level signal.

  In the circuit of this embodiment, the power supply voltage VCC (for example, 2.7 V to 3.6 V) is supplied to the drive stage 2 and the buffer stage 3. On the other hand, the differential amplification stage 1 is supplied with a power supply voltage VLCD (for example, 6V to 10V) for driving a liquid crystal that is higher than the power supply voltage VCC for logic. Further, the current control voltage SVGP (for example, 1.6 V to 1.8 V) generated by the constant voltage circuit and the bias circuit is applied to the gate of the constant current MOSFET Q1, and the difference depends on the operation of the saturation region of the MOSFET. A bias current is supplied to the common source side of the dynamic input MOSFETs Q2 and Q3.

At this time, the gate-source voltage Vgs of the constant current MOSFET Q1 becomes larger than the circuit form of FIG. 5 due to the power supply voltage VLCD for driving the liquid crystal. Therefore, as can be seen from the current equation I = β (W / L) (Vgs−Vth) ^{2 in} the saturation state of the MOSFET, the threshold voltage Vth slightly deviates from the reference value due to the process variation of the MOSFET. However, the drain current value is not greatly affected. Further, since the gate-source voltage Vgs is relatively large, a desired current value can be obtained without increasing the gate width W of the MOSFET.

  Further, since the voltage at the node n1 to which the source terminals of the differential input MOSFETs Q2 and Q3 are connected also increases, the current flowing through the differential amplifier stage 1 even if the center voltage of the input differential signals YP and YN varies somewhat. Does not change so much, and the current consumption and circuit characteristics are constant. Therefore, it is possible to widen the fluctuation allowable range of the center voltage of the input differential signals YP and YN.

  Further, since the common source voltage of the differential input MOSFETs Q2 and Q3 becomes high, the high level voltage output to the output node n2 of the differential amplifier stage 1 sufficiently turns on the P-channel MOSFET Q6 of the drive stage 2 For example, the level shift circuit 62a provided in the conventional small amplitude differential signal interface shown in FIG. 5 can be eliminated. Therefore, since there is no level shift circuit, power consumption can be reduced and signal delay can be reduced.

  Since a high power supply voltage VLCD is supplied to the differential amplifier stage 1, the MOSFET constituting the differential amplifier stage 1 and the drive stage 2 that receives the output of the differential amplifier stage 1 at its gate has a high breakdown voltage (for example, 7V). It is desirable that it be composed of a MOSFET having a withstand voltage.

Next, the characteristics of the small amplitude differential signal interface will be described quantitatively.
3 and 4 are graphs showing the characteristics of the small-amplitude differential interface of FIG. 1. FIG. 3 shows that the threshold voltage Vth of the MOSFET is high in both the P-channel type and the N-channel type due to process variations. FIG. 4 shows a case where both are formed low.

  In these graphs, the horizontal axis represents the voltage value of the power supply voltage VLCD supplied to the source of the constant current MOSFET Q1, and the vertical axis represents the direct current value flowing through the differential amplifier stage 1. Each graph line shows the case where the center voltage Vref of the input differential signal is 0.5 V, 1.2 V, and 2.4 V, and the case where the chip temperature is −30 ° C., 25 ° C., and 75 ° C., respectively. Yes.

Hereinafter, characteristic changes due to process variations, characteristic changes due to the center voltage Vref of the input differential signal, and characteristic changes due to the power supply voltage VLCD will be described in order.
The amount of change in current value due to process variations is less than 10%. For example, under the conditions of a chip temperature of 25 ° C., a liquid crystal drive voltage VLCD = 8 V, and a center voltage of the input differential signal = 1.2 V, a current value of 67 μA is obtained when the threshold voltage Vth of FIG. On the other hand, when the threshold voltage Vth of FIG. 4 is formed low, a current value of 73 μA is obtained, and the difference between them is less than 10%. It can also be seen from the graph that the amount of change in the current value due to this process variation is the same regardless of the chip temperature, the liquid crystal drive voltage VLCD, and the center voltage of the input differential signal.

  The change in the center voltage Vref of the input differential signal is indicated by a solid line, a dotted line, and a two-dot chain line in the graphs of FIGS. From the graph, it can be seen that if the characteristics of the chip temperature and the threshold voltage Vth are the same, there is almost no deviation in the current value due to the difference in the center voltage Vref of the input differential signal.

  Further, when the change in the current value due to the power supply voltage VLCD is large (when the threshold voltage Vth in FIG. 3 is formed high and the chip temperature is −30 ° C.), it is 26 μA / 5V, and the standard case (chip temperature 30 ° C.). ) 20 μA to 17 μ / 5 V, and the amount of change is small. As a result, even if it is designed to operate with a current minimum, the current max does not become extremely large, and low current consumption is possible.

  6 to 8 show characteristic graphs of the conventional small amplitude differential interface shown in FIG. FIG. 6 shows a case where the threshold voltage Vth of the MOSFET is formed low together with the P channel and the N channel, and the power supply voltage VCC is a maximum value of 3.6 V. FIG. In the case of the value, FIG. 8 shows the case where both the threshold voltages Vth are formed high and the power supply voltage VCC is the minimum value 2.7V.

  In these graphs, the horizontal axis represents the gate width W of the constant current MOSFET Q1, and the vertical axis represents the direct current value flowing through the differential amplifier stage 1. Each graph line shows a case where the center voltage Vref of the input differential signal is 0.5 V, 1.2 V, and VCC-1.2 V, respectively.

  In the conventional small amplitude differential signal interface, when the gate width W of the constant current MOSFET Q1 is 100 μm and the center voltage Vref of the input differential signal changes from 0.5 to VCC-1.2 V, FIG. In some cases, the current value is 563 μA to 326 μA, which is a change amount of 40% or more. Similarly, in the case of FIG. 7, it can be seen that the amount of change is 330 μA to 190 μA, which is 40% or more, and in the case of FIG. 8, the amount of change is 173 μA to 101 μA, which is 40% or more.

  Further, when the center voltage of the input differential signal is constant (Vref = 1.2 V) and other conditions change to the maximum, that is, the threshold voltage Vth of the MOSFET is min, the power supply voltage VCC is max3. 6V, chip temperature changed from −30 ° C. (point A in FIG. 6), MOSFET threshold voltage Vth changed to max, power supply voltage VCC changed to min 2.7V, and chip temperature changed to 75 ° C. (point C in FIG. 6). Sometimes the current value drops by 74% from 484 μA to 123 μA. When designing to ensure operation under the minimum current condition, the current max becomes extremely large and low current consumption cannot be achieved.

  Considering the characteristics of the small-amplitude differential signal interface of FIG. 1 of this embodiment under substantially the same conditions, the condition that the threshold voltage Vth of the MOSFET is minimum and the chip temperature is −30 ° C. (point A ′ in FIG. 4). Therefore, even when the threshold voltage Vth of the MOSFET is maximum and the chip temperature is changed to 75 ° C. (point C ′ in FIG. 3), the current value can be suppressed to a decrease of 43% from 96 μA to 54 μA. I understand.

  As described above, according to the small amplitude differential signal interface of the above embodiment, the liquid crystal drive voltage VLCD higher than the logic power supply voltage VCC is supplied to the differential amplification stage 1, so that the process variation Even if the threshold voltage Vth of the MOSFET, the center voltage Vref of the input differential signal, and the power supply voltage VLCD slightly change, the value of the current flowing through the differential amplification stage 1 does not vary so much. Characteristics (for example, rise / fall time, output voltage, etc.) can be kept normal. Therefore, it is possible to widen the fluctuation tolerance of the center voltage of the input differential signal.

Hereinafter, an example in which the above-described small-amplitude differential signal interface is applied to a semiconductor integrated circuit that receives two power supply voltages will be described.
FIG. 2 is a block diagram showing an overall configuration of a liquid crystal driving driver provided with the small amplitude differential signal interface in a signal input unit.
A liquid crystal driver 100 as a liquid crystal driving device of this embodiment drives a data line of a TFT liquid crystal panel used as a display of a notebook computer, for example. It is formed on a single semiconductor chip.

  The liquid crystal driver 100 according to this embodiment inputs, for example, 6-bit digital display data DATA00P, DATA00N to DATA22P, DATA22N and external clocks CLP, CLN inputted at a high speed per pixel in the form of a small amplitude differential signal. As the interface 101, the above-described small amplitude differential interfaces 101 and 12 are provided. The data register 104 that temporarily holds input digital data, the data latch circuit 122 that holds data for one line by sequentially shifting the data held in the data register 104 to a predetermined bit, and the data register A shift register 121 for transferring 104 data to a predetermined bit of the data latch circuit 122, and D / D for converting digital data for one line held in the data latch circuit 121 into an analog signal indicating the gradation for each pixel. An output buffer 124 for generating and outputting drive voltages Y1 to Y384 of data lines of the TFT liquid crystal panel based on analog signals from the A converter 123 and the D / A converter 123 is provided.

  The liquid crystal driver 100 includes a power supply voltage VCC used as an operating power supply for internal logic circuits such as the driving stage 2 and the buffer stage 3 of the small amplitude differential interface 101, the data register 104, the shift register 121, the data latch circuit 122, and the like. A liquid crystal driving power supply voltage VLCD used to generate the liquid crystal driving voltages Y1 to Y384 is supplied from the outside of the chip. The liquid crystal driving power supply voltage VLCD is divided into a plurality of stages of voltages V1 to V10 for gradation display by a resistor dividing circuit (not shown) or the like and supplied to the D / A converter 123 and the output buffer 124. The liquid crystal driving power supply voltage VLCD is also supplied to the differential amplification stage 1 of the small amplitude differential signal interface 101.

  According to such a liquid crystal driver 100, it is possible to widen the fluctuation tolerance of the center voltage of the digital display data DATA00P, DATA00N to DATA22P, DATA22N and the external clocks CLP, CLN inputted from the outside, and the power supply voltage for logic Since VCC does not affect the characteristics of the small amplitude differential signal interface 101, the power supply voltage VCC can be set low. Thereby, it is possible to realize a semiconductor chip capable of operating at higher speed and having lower power consumption.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, the specific circuit configuration of the small-amplitude differential interface has been illustrated, but the differential amplification stage has various known modifications, and the circuit configuration subsequent to the differential amplification stage can be variously modified. is there. Moreover, it is not restricted to MOSFET, but can also be comprised with a bipolar transistor. In addition, the values specifically shown in the embodiment such as the power supply voltage VCC for logic, the liquid crystal drive voltage VLCD, and the size of the MOSFET can be appropriately changed.

  Next, a configuration example in which a voltage other than the power supply voltage VLCD for driving the liquid crystal can be applied as the power supply voltage supplied to the differential amplification stage 1 in FIG. 1 will be described. In FIG. 1, the power supply voltage VLCD for driving liquid crystal is connected to the source terminal of the constant current MOSFET Q1 (FIG. 1). Hereinafter, the case where the second power supply voltage VDD2 is connected to the source terminal will be described. To do.

FIG. 9 is a diagram illustrating an example of a selection circuit that can select the second power supply voltage VDD2 supplied to the small amplitude differential interface from a plurality of voltages.
In this embodiment, the second power supply voltage VDD2 supplied to the differential amplification stage 1 of the small amplitude differential interface 101 is supplied from the outside for the power supply voltage VLCD for driving the liquid crystal and the gradation driving of the liquid crystal. One of the gradation power supplies V0 to V10 can be selected from appropriate ones (for example, four from the higher voltage).

  An effect can be obtained if the power supply voltage VDD2 of the differential amplifier stage 1 is somewhat higher than the power supply voltage VCC for logic. On the other hand, if the power supply voltage VDD2 is too large, the device withstand voltage needs to be raised excessively. It can be considered. Therefore, in this embodiment, the gradation power supplies V0, V1,... Having a lower potential than the power supply voltage VLCD for driving the liquid crystal can be selected as the power supply voltage VDD2 of the differential amplification stage. The gradation power sources V0, V1,... Are applied.

  The gradation power supplies V0 to V10 are resistance-divided at a predetermined ratio inside the liquid crystal driver, thereby generating, for example, 64 × 2 gradation drive voltages. Since different values are required for the drive voltage depending on the characteristics of the liquid crystal panel, the grayscale power supplies V0 to V10 are used as external inputs, and the values of the drive voltage generated internally are made variable by dividing them with resistors.

  Therefore, since the values of the gradation voltages V0 to V10 vary depending on the system to be applied, when applying to the power supply voltage VDD2, one of several gradation voltages V0, V1,... Can be selected. This is convenient.

  In the selection circuit of FIG. 9, the power supply line Lvdd2 of the power supply voltage VDD2 of the differential amplification stage 1 supplied to the small amplitude differential interface 101, the power supply voltage VLCD for driving the liquid crystal, and the gradation voltages V0 to V3 are respectively applied. High-voltage switch MOSFETs MS1 to MS5 are respectively provided between the power supply lines L00 and L0 to L3, and are connected via their source terminals and drain terminals. A selection signal is supplied to the gate terminals of these switch MOSFETs MS1 to MS5.

  For example, the selection signal is supplied from the outside through a dedicated input terminal provided in the liquid crystal driver. Alternatively, a control register may be provided in the liquid crystal driver and supplied from the control register based on a value set in the control register.

  As described above, even when any one of the gradation power supplies V0 to V3 is applied as the power supply voltage VDD2 of the differential amplifier stage 1, the fluctuation tolerance of the center voltage of the differential input signal is increased, or the power supply voltage for logic is used. It is possible to obtain an effect that the internal circuit speed can be increased and the power consumption can be reduced by reducing VCC.

  Furthermore, in the liquid crystal driver of this embodiment, when the power supply voltage VLCD for driving the liquid crystal is very high, an appropriate one is selected from the lower gradation voltages V0 to V3 and the power supply for the differential amplifier stage 1 is selected. Since the voltage VDD2 can be set, it is not necessary to excessively increase the element withstand voltage of the differential amplifier stage 1, thereby suppressing an increase in power consumption.

  Note that the configuration that allows the liquid crystal drive power supply voltage VLCD and the gradation power supplies V0 to V3 to be selected as the power supply voltage VDD2 is not limited to the configuration using the above-described switch MOSFET, and various configurations are applicable.

10 and 11 show a configuration example in which the power supply voltage can be selected by the wiring on the wiring film in the case of the COF package.
This example employs a COF (Chip on Film) package in which a semiconductor chip 52 as a liquid crystal driving device is mounted on a wiring film 51 as a mounting structure of the liquid crystal driver 100. In this example, the connection pad G0 of the second power supply voltage VDD2 is provided on the semiconductor chip 52 in which the circuit of the liquid crystal driver 100 is integrated, and the power supply voltage VDD2 is set to the power supply voltage for driving the liquid crystal by appropriately selecting the wiring of the wiring film 51. It is possible to select from VLCD or gradation power sources V0, V1,.

  For example, as shown in FIG. 10 and FIG. 11, the connection pad G0 of the power supply voltage VDD2 and the input pad J00 of the liquid crystal driving power supply voltage VLCD or the gradation by the wirings H1 and H2 indicated by the dotted lines formed on the wiring film 51 By connecting to any of the connection pads J0, J1,... Of the power supplies V0, V1,..., It is possible to select either the liquid crystal driving power supply voltage VLCD or the gradation power supplies V0, V1.

FIGS. 12 and 13 show an example in which the second power supply voltage VDD2 can be selected by a master slice type wiring pattern.
In this example, in the process of manufacturing the semiconductor chip 52, the power supply voltage VDD2 is selected according to the wiring pattern. As shown in FIGS. 12 and 13, as the wiring pattern, for example, the power supply line Lvdd2 of the second power supply voltage VDD2, the input pad J00 of the liquid crystal driving power supply voltage VLCD, or the input pads J0 to J3 of the gradation power supplies V0, V1,. By appropriately selecting the wiring pattern to which any of the above is connected, it is possible to select either the liquid crystal driving power supply voltage VLCD or the gradation power supplies V0, V1,... As the second power supply voltage VDD2.

FIG. 14 shows a configuration example in which the second power supply voltage can be selected by cutting the fuse element provided in the semiconductor chip 52.
In this example, for example, a fuse element FS is provided between the power supply line Lvdd2 of the power supply voltage VDD2 and the input pads of the liquid crystal driving power supply voltage VLCD and the gradation power supplies V0, V1,. By cutting unnecessary fuse elements FS at the package stage, it is possible to select either the liquid crystal driving power supply voltage VLCD or the gradation power supplies V0, V1,... As the second power supply voltage VDD2. The fuse element FS is cut by, for example, cutting using a laser or passing a predetermined current using a probe.

FIG. 15 shows an example of a circuit that generates the second power supply voltage supplied to the small amplitude differential interface 101.
In the above-described embodiment, the liquid crystal driving power supply voltage VLCD and the gradation power supplies V0, V1,... Are directly used as the second power supply voltage VDD2 supplied to the differential amplifier stage 1. A voltage lower than that is generated using the power supply voltage VLCD for driving the liquid crystal and supplied as the second power supply voltage VDD2.

  Various known techniques can be applied to the voltage generating circuit. For example, as shown in FIG. 15, the power source voltage VLCD for driving the liquid crystal is divided by resistors R1 and R2, and the potential obtained by dividing the voltage. Can be output via the voltage follower 40.

  In FIG. 15, the second power supply voltage VDD2 is generated using the power supply voltage VLCD. However, the grayscale power supplies V0, V1,... May be used instead of the power supply voltage VLCD, and further, a voltage generated therefrom is used. May be.

<Second embodiment>
In the second embodiment, the operation current of the differential amplification stage 1 of the small-amplitude differential interface 101 in which the differential display data DATAP and DATAN are input to the liquid crystal driver 100 described in the first embodiment is unnecessary. A standby function that cuts off sometimes is added. That is, the power supply voltage (VLCD, VDD2) of the differential amplification stage 1 of the small amplitude differential interface 101 described in the first embodiment is set higher than the power supply voltage (VCC) of the internal circuit. The power consumption becomes a value that cannot be ignored. Further, in the liquid crystal system, for example, eight liquid crystal drivers 100 of the first embodiment are used, so that the power consumption of the system is considered to increase. Therefore, in this embodiment, a liquid crystal driver 100 is described in which a standby function is added to the differential amplifier stage 1 of the first embodiment, and the power consumption can be reduced as much as possible.

FIG. 16 shows an example of a circuit diagram of the small amplitude differential interface of the second embodiment to which a standby function is added.
In this small amplitude differential interface, as a main change from the small amplitude differential interface 101 of FIG. 1, a bias voltage applied to the gate terminal of the constant current MOSFET Q1 is used to supply a constant operating current. Switching between the current control voltage SVGPD0 and the second power supply voltage VDD2 is enabled. Along with this, there is provided a switch MOSFET Q21 for forcibly holding the potential of the output node n4 of the differential amplification stage 1 at a low level when the differential amplification stage 1 is deactivated.

  The configuration for switching the bias voltage of the constant current MOSFET Q1 includes a level shift circuit 5 that converts a logic standby signal STB to a high voltage to drive a high voltage MOSFET, a power supply voltage VDD2, and a gate terminal of the constant current MOSFET Q1. High withstand voltage P-channel switch MOSFET Q15 for connecting / disconnecting, and high withstand voltage P-channel switch MOSFET Q16 for connecting / disconnecting current control voltage SVGPD0 and the gate terminal of constant current MOSFET Q1; The inverter is composed of an inverter INV20 for inversion. If the difference between the power supply voltage VCC and VDD2 is not so great, the level shift circuit 5 may be omitted.

  According to the above configuration, when the standby signal STB is at the low level, the switch MOSFET Q16 that connects the current control voltage SVGPD0 is turned on, and the switch MOSFET Q15 that connects the power supply voltage VDD2 is turned off. As a result, the current control voltage SVGPD0 is applied to the gate of the constant current MOSFET Q1, and the operating current is supplied to the differential amplifier stage 1.

  Further, at this time, the switch MOSFET Q21 connected to the output node n4 is turned off and has no effect. Since this switch MOSFET Q21 is of the N channel type, the switch MOSFET Q21 can be turned off without level conversion of the signal input to its gate by the level shift circuit 5.

  On the other hand, when the standby signal STB is set to the high level, the switch MOSFET Q15 that connects the power supply voltage VDD2 is turned on, and the switch MOSFET Q16 that connects the current control voltage SVGPD0 is turned off. As a result, the power supply voltage VDD2 is applied to the gate of the constant current MOSFET Q2, and the operating current of the differential amplifier stage 1 is cut off.

  Further, at this time, the switch MOSFET Q21 of the output node n4 is turned on, and the potential of the output node n4 is forcibly lowered to the ground GND. As a result, the states of the drive stage 2 and the buffer stage 3 are stabilized and the through current is cut off.

  Although the illustration of the standby signal STB is omitted, in the liquid crystal driver having the above-described small amplitude differential interface, for example, timing control for generating an internal timing signal based on a clock signal or timing pulse input from the outside Supplied from a circuit or the like.

  FIG. 17 is a configuration diagram showing an example of a liquid crystal display system configured using a liquid crystal driver to which the standby function is added. Hereinafter, for easy understanding, the external clock CLK1 input to the data latch circuit 122 in FIG. 2 is transferred to the horizontal clock CL1 and the external clocks CLP and CLN input to the differential amplifier 12 are transferred. The name of the clock CL2 is changed.

  In this figure, 33 is a liquid crystal panel in which a TFT (thin film transistor) array and three primary color filters enabling color display are arranged on a panel filled with liquid crystal, and 32 is a horizontal scanning clock for the gate lines of the TFT array. A scanning driver (gate line driver) that sequentially drives in synchronization with CL3, 34 a liquid crystal drive power supply circuit that generates various power supply voltages necessary for liquid crystal drive, and 35 a standby function that drives the source lines of the TFT array. A liquid crystal driver (source line driver) 31 as a liquid crystal drive device is a controller as a control device that supplies display data to the liquid crystal driver 35 and gives control signals and operation timings to the liquid crystal driver 35 and the scan driver 32. Note that a terminal and a wiring for supplying the power supply voltage VCC and the ground potential GND as reference potentials to the circuits 31, 32, 34, and 35 are also provided in the liquid crystal display system.

  The liquid crystal drive power supply circuit 34 includes a counter electrode voltage VCOM to the liquid crystal panel 33, gate array drive voltages VGON and VGOFF to the scan driver 32, and a liquid crystal drive power supply voltage VLCD to the liquid crystal driver 35. And gradation power supplies V0 to V9 are generated. The supply lines LVS for the voltages VLCD and V0 to V9 output from the power supply circuit 34 are lines for supplying the voltages VLCD and V0 to V9 to the respective liquid crystal drivers 35, and are also provided in the liquid crystal system of the present invention. It has been. Therefore, the liquid crystal driver (100, 35) of the present invention can be used for the liquid crystal system without changing the wiring LVS of the liquid crystal system.

  In the liquid crystal display system of this embodiment, a plurality of (for example, eight) liquid crystal drivers 35 are arranged in accordance with the number of source lines of the liquid crystal panel 33. The plurality of liquid crystal drivers 35 respectively drive the corresponding 384 (128 pixels × 3 primary colors) source lines, while the gate lines are sequentially driven by the scanning driver 32, so that the liquid crystal panel 33 The display operation is performed in all areas. Note that the liquid crystal driver 35 of FIG. 17 can be configured as a liquid crystal system even if it is the drive driver 100 of the first embodiment.

  FIG. 18 is a time chart for explaining the operation of the liquid crystal display system. In this figure, the upper two steps and the lower three steps are shown with different time scales. FRM is a frame signal representing a frame period.

  In the liquid crystal display system of FIG. 17, in addition to the display data DATA, a horizontal clock CL1 representing one horizontal period, a transfer clock CL2 for giving display data DATA transfer timing, and the like are output from the controller 31 to each liquid crystal driver 35. Is done. The display data DATA is continuously transferred in one horizontal period using data of three primary colors × 1 line (1024 pixels) as a transfer unit. Differential signals are used for the display data DATA and the transfer clock CL2.

  Further, among the plurality of liquid crystal drivers 35, the display data DATA of 3 primary colors × 128 pixels carried by each driver out of the display data DATA for one line transferred continuously is fetched. Each liquid crystal driver 35 is input with an enable signal EIO that informs the input timing of the display data DATA so that only the display data DATA for the assigned charge is input.

  The enable signal EIO is first output from the controller 31 to the first liquid crystal driver 35, and based on this, the first liquid crystal driver 35 starts to input display data. Thereafter, the transfer proceeds, and the enable signal EIO is transferred from the liquid crystal driver 35 to the second liquid crystal driver 35 immediately before the data input corresponding to the first liquid crystal driver 35 is completed. The second liquid crystal driver 35 similarly starts display data input based on the enable signal EIO, and transfers the enable signal EIO to the next-stage liquid crystal driver 35 immediately before the data input for the assigned charge is completed. Such processing is executed over the liquid crystal driver 35 from the first stage to the last stage so that all display data for one line is divided and inputted to the plurality of liquid crystal drivers 35. It has become.

  In FIG. 18, the enable signals EIO output from the controller 31 and the liquid crystal drivers 35 are collectively shown in one stage, EIO0 is output from the controller 31, and EIO1 is output from the first liquid crystal driver 35. The output, EIO8, is output from the last liquid crystal driver 35. There is no output destination of the enable signal EIO8 generated by the last liquid crystal driver 35.

  The timing at which each liquid crystal driver 35 transfers the enable signal EIO to the next stage is measured, for example, by counting the transfer clock CL2 after the input of the enable signal EIO in the timing control circuit built in each liquid crystal driver 35.

  As shown in FIGS. 17 and 18, the display data DATA is transferred to the liquid crystal driver 35 at both the rising and falling timings of the clock signal CL2P. The transfer rate is 18 bits in which gradation data of 6 bits per pixel is included for three primary colors per clock, and 9 bits, which is half that of one edge per clock.

  As for the display data DATA, data for three primary colors × one line is transferred in one horizontal period, but a blank period in which display data is not transferred occurs before the transfer to the next line is transferred. In addition, each liquid crystal driver 35 inputs only display data DATA for the portion in charge during transfer of one line of display data DATA, and does not perform input processing while the other portions are being transferred.

  Therefore, in the liquid crystal driver 35 of this embodiment, during the period when the display data DATA is not input, the small-amplitude differential interface 101 is set to the standby mode to reduce power consumption.

FIG. 19 shows an example of a timing chart of the operation timing of standby processing performed in each liquid crystal driver.
The standby process is executed by a timing control circuit built in the liquid crystal driver 35 using signals necessary for display control of the liquid crystal display system.

  FIG. 19 shows an example in which the horizontal clock CL1 is used as a signal for returning from the standby mode. That is, when the horizontal clock CL1 from the controller 31 is input to the timing control circuit of each liquid crystal driver 35 and its rising edge is detected, the standby signal STB output from the timing control circuit is set to the low level, and the standby mode is set. Canceled.

  On the other hand, the standby mode is started by detecting that the timing control circuit of each liquid crystal driver 35 has completed the input of display data DATA for each charge. The timing control circuit of each liquid crystal driver 35 starts to input the display data DATA based on the enable signal EIO input after the horizontal clock CL1, and takes in the display data DATA while counting the transfer clock CL2 with a counter. Then, the timing at which the last data of the display data DATA for the assigned charge (3 primary colors × 128 pixels) is latched by the latch circuit such as the data latch circuit 122 or the data register 104 in the subsequent stage through the small amplitude differential interface 101 Is detected from the count value of the counter. Based on this detection, the standby signal STB output to the small amplitude differential interface 101 is set to the high level to shift to the standby mode.

FIG. 20 shows another example of the operation timing of standby processing.
In this example, the enable signal EIO is used as a signal for returning from the standby mode. That is, when the rising edge of the enable signal EIO is detected by the timing control circuit built in each liquid crystal driver 35, the standby signal STB supplied to the small amplitude differential interface 101 is set to the low level, and the standby mode is released. The The start of the standby mode is the same as in the example of FIG.

  As described above, according to the liquid crystal driver 35 and the liquid crystal display system of the second embodiment, the operating current of the differential amplifier stage 1 of the small amplitude differential interface 101 is transmitted during the period when the display data DATA is not transferred in each liquid crystal driver. Therefore, even if the power supply voltage (VDD2) of the differential amplifier stage 1 is set higher than the power supply voltage (VCC) of the internal circuit, the power consumption can be further reduced.

  In the examples of FIGS. 19 and 20, the latter can generate the stamper mode more efficiently, so that the power consumption can be further reduced. However, the period from the input of the enable signal EIO to the start of the input of the display data DATA Is short, there is a possibility that the standby release of the small amplitude differential interface 101 may not be in time. In such a case, the example of FIG. 19 may be applied.

<Third embodiment>
FIG. 21 is a circuit diagram showing an input unit for display data and a transfer clock in the liquid crystal driver of the third embodiment.
The third embodiment is an improvement of the input circuit of the transfer clock CL2 that gives the transfer timing of the display data DATA in the liquid crystal driver shown in the first and second embodiments.

  When the differential transfer clock CL2 (the positive phase side is indicated as CL2P and the negative phase side is indicated as CL2N) is taken in by the differential amplifier, the rise time of the transfer clock CL2 passing through the differential amplification stage is determined by the characteristics of the differential amplifier. It is difficult to make the fall time the same, and there is a difference in these times depending on conditions such as the center voltage, power supply voltage, or temperature of the differential signal. Therefore, in the transfer clock CL2 passing through the differential amplifier, the delay time of the rising signal (hereinafter referred to as the rising delay) is shifted from the delay time of the falling signal (hereinafter referred to as the falling delay).

  Therefore, the transfer clock CL2 is inputted by one differential amplifier, and the differential display data DATA (its positive phase side is DATAT and the negative phase side is DATAN) twice by one clock using both edges of this input clock. When the center voltage of the transfer clocks CL2P and CL2N input from the outside is greatly shifted, for example, the clock skew of the transfer clock CL2 increases and the display data DATA is captured. There is a fear that it will not be possible to perform correctly. In order to avoid such a problem, in the case of the configuration as described above, the signal waveform conditions of the externally input transfer clock CL2 and display data DATA must be strictly defined.

  Therefore, the liquid crystal driver of the third embodiment is provided with two differential amplifiers 12 and 13 to which the transfer clock CL2 is input, as shown in FIG. The display data DATA is latched by the latch circuits 15 and 16 based on the two input clock signals CC3 and CC4.

  The display data DATA is input via the differential amplifier 11 of the small amplitude differential interface 101 and the delay circuit 14 for timing adjustment. The latch circuits 15 and 16 constitute a data register 104 (FIG. 2) provided at the subsequent stage of the small amplitude differential interface 101.

  One of the two differential amplifiers 12 and 13 is configured such that the positive phase transfer clock CL2P is input to the positive phase input terminal and the negative phase transfer clock CL2N is input to the negative phase input terminal. It is connected to the. The other differential amplifier 13 is connected such that a negative phase transfer clock CL2N is input to its positive phase input terminal and a positive phase transfer clock CL2P is input to its negative phase input terminal.

  One latch circuit 15 captures display data DATA at the rising edge of the clock signal CC4 from the differential amplifier 12, and the other latch circuit 16 captures display data DATA at the rising edge of the clock signal CC3 from the differential amplifier 13. It is configured.

FIG. 22 is a waveform diagram showing the display data and the delay amount of the transfer clock in the circuit of FIG.
According to the configuration as described above, as shown in FIG. 22A, there is a difference between the rising delay and the falling delay in the differential amplifiers 12 and 13, but the positive phase input of the differential amplifiers 12 and 13. Since the terminal and the negative phase input terminal are connected in reverse to each other, the rising timing T3 of the signal CC3 after passing through the differential amplifier 13 and the rising timing T4 of the signal CC4 after passing through the differential amplifier 14 are transferred. The timing is obtained by adding the rising delays DF and DR of the differential amplifiers 12 and 13 from the falling timing T1 and the rising timing T2 of the clock CL2P (= signal CC1).

  Therefore, according to the transfer clock CL2 input method of the third embodiment, the generation interval between the rising edge of the signal CC4 giving the latch timing to the latch circuit 15 and the rising edge of the signal CC3 giving the latch timing to the latch circuit 16 is set. As a result, the display data DATA fetch error is less likely to occur. Therefore, conditions such as the differential transfer clock CL2 and the center voltage of the differential display data DATA can be relaxed, and the display data DATA can be transferred at higher speed.

  The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first to third embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the third embodiment, the horizontal clock CL1 and the enable signal EIO are used to cancel the standby mode, but other signals that indicate the start of continuous display data transfer are used in the system. In such a case, the standby mode may be canceled using such a signal. The standby mode is also configured to start the standby mode using such a signal when the system uses a signal that indicates the end of continuous display data transfer. Also good. In addition, the standby signal itself may be input from outside the chip, and the standby signal may be supplied to each liquid crystal driver by a controller or the like that controls the timing of each block in the liquid crystal display system.

  Further, as a configuration for cutting off the operating current of the differential amplification stage of the small amplitude differential interface 101 in the standby mode, the third embodiment has shown the configuration for switching the bias voltage of the current MOSFET Q1, but in addition, the power supply voltage VDD2 There can be various methods such as a configuration for shutting off the supply of.

  In the second embodiment, the standby mode is described as being generated every horizontal period. For example, when there is a horizontal period in which display data is not transferred at the beginning or end of the frame period, these horizontal modes are displayed. Control may be made so that the entire period is set to the standby mode. Further, even when the standby mode is generated only at the beginning or end of the frame period and the standby mode is canceled during the horizontal period in which display data is transferred, the power consumption can be reduced as compared with the conventional case.

  Further, in the input circuit for the transfer clock CL2 of the third embodiment, the two differential amplifiers that input the transfer clock CL2 do not have to have exactly the same circuit configuration, and if the rising delay or falling delay is equal, the circuit The configuration is arbitrary.

  In the first embodiment, in order to stably capture the differential display data DATA, the operation voltage of the differential amplification stage 1 is changed to the operation voltage of the drive stage 2 and the buffer stage 3 in the subsequent stage in the small amplitude differential interface 101. However, instead of increasing the operating voltage, a low-threshold voltage MOSFET is used as a constituent element of the differential amplifier stage 1, and the drive stage 2 and buffer stage 3 of the subsequent stage are used. Even if the small-amplitude differential interface 101 is configured by using a MOSFET having a high threshold voltage as a constituent element, the display data DATA can be stably captured by the same action as when the operation power supply is changed. Is possible.

  In the above description, the liquid crystal driver, which is the field of use behind the invention made by the present inventor, has been described. However, the present invention is not limited to this, for example, a one-chip microcomputer or a DSP (Digital Signal Processor). ) And the like, and can be widely used in semiconductor integrated circuits that are supplied with two power supply voltages, one for an internal logic circuit and one for an interface.

FIG. 1 is a circuit diagram showing an embodiment of a small amplitude differential signal interface suitable for application of the present invention. FIG. 2 is a block diagram showing the overall configuration of a liquid crystal driver having a small amplitude differential signal interface according to the present invention. FIG. 3 is a characteristic graph of the small amplitude differential interface of FIG. 1 when the threshold voltage Vth of the MOSFET is formed high with the P channel and the N channel. FIG. 4 is a characteristic graph of the small amplitude differential interface of FIG. 1 when the threshold voltage Vth of the MOSFET is formed low together with the P channel and the N channel. FIG. 5 is a circuit diagram showing an example of a small amplitude differential signal interface investigated by the present inventors. FIG. 6 is a characteristic graph of the small amplitude differential interface of FIG. 5 when the threshold voltage Vth of the MOSFET is formed to be low together with the P channel and the N channel. FIG. 7 is a characteristic graph of the small amplitude differential interface of FIG. 5 when the threshold voltage Vth of the MOSFET is formed at the reference value together with the P channel and the N channel. FIG. 8 is a characteristic graph of the small amplitude differential interface of FIG. 5 when the threshold voltage Vth of the MOSFET is formed to be high together with the P channel and the N channel. FIG. 9 is a diagram illustrating a configuration example in which the second power supply voltage supplied to the small-amplitude differential interface can be selected from a plurality. FIG. 10 is a plan view of a COF package showing a configuration example in which the second power supply voltage can be selected by wiring on the COF, in a state where the liquid crystal driving voltage VLCD is selected as the second power supply voltage. FIG. 11 is a diagram illustrating a state in which a gradation driving voltage is selected as the second power supply voltage in the COF package of FIG. FIG. 12 is a schematic diagram of a semiconductor chip showing a configuration example that enables selection of the second power supply voltage in the master slice of the aluminum wiring, in a state where the liquid crystal driving voltage VLCD is selected as the second power supply voltage. . FIG. 13 is a diagram illustrating a state in which a gradation driving voltage is selected as the second power supply voltage in the semiconductor chip of FIG. FIG. 14 is a schematic diagram of a semiconductor chip showing a configuration example in which a fuse is provided in the semiconductor chip and the second power supply voltage can be selected. FIG. 15 is a circuit diagram showing an example of a second power supply voltage generation circuit supplied to the small amplitude differential interface. FIG. 16 is a circuit diagram showing a small amplitude differential interface of the third embodiment to which a standby function is added. FIG. 17 is a configuration diagram illustrating an example of a liquid crystal display system configured using a liquid crystal driver to which a standby function is added. FIG. 18 is a time chart for explaining the operation of the liquid crystal display system of FIG. FIG. 19 is a timing chart showing an example of operation timing of standby processing performed in each liquid crystal driver. FIG. 20 is a timing chart showing another example of the operation timing of standby processing performed by each liquid crystal driver. FIG. 21 is a circuit diagram illustrating an input unit for display data and a transfer clock in the liquid crystal driver of the embodiment. FIG. 22 is a waveform diagram showing the relationship between display data and a transfer clock in the circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Differential amplification stage 2 Drive stage 3 Output stage 51 Wiring film 52 Semiconductor chip (liquid crystal drive device)
100 LCD driver

Claims (9)

A liquid crystal panel having a plurality of source lines and a plurality of gate lines;
A source line driver coupled to the plurality of source lines and generating a drive signal for selectively driving the source lines based on display data to be displayed on the liquid crystal panel;
A gate line driver coupled to the plurality of gate lines and sequentially scanning the gate lines;
A power supply circuit coupled to the liquid crystal panel, the source line driver and the gate line driver, and supplying a driving power supply potential to be supplied to the liquid crystal panel, the source line driver and the gate line driver;
A controller coupled to the source line driver and the gate line driver to supply the display data to the source line driver and to supply a timing control signal to the source line driver and the gate line driver;
A terminal for supplying a reference potential supplied to the source line driver and the gate line driver,
The controller supplies the display data in a differential format to the source line driver,
The source line driver includes a differential input circuit for receiving the display data in the differential format, a data latch circuit for latching an output of the differential input circuit, and an output circuit for generating the drive signal. Have
As the power supply potential of the differential input circuit of the source line driver, a power supply potential selected from the drive power supply potential is used.
As the power supply potential of the data latch circuit of the source line driver, the reference potential supplied from the terminal is used.
A liquid crystal display system, wherein a power supply potential of the differential input circuit is larger than a power supply potential of the data latch circuit. The differential input circuit is
A pair of differential MOS transistors each having a gate for receiving each of the differential display data and a common source;
2. The liquid crystal display according to claim 1, further comprising a current source MOS transistor having a drain coupled to the common source, a source to which a power source potential selected from the driving power source potential is supplied, and a gate to which a bias potential is supplied. system. The source line driver further includes a standby control circuit,
3. The liquid crystal display system according to claim 2, wherein the bias potential is selectively supplied to the gate of the current source MOS transistor according to the control of the standby control circuit. The standby control circuit supplies the bias potential to the gate of the current source MOS transistor based on activation of a signal representing one horizontal period of the liquid crystal panel among the timing control signals supplied from the controller. The liquid crystal display system according to claim 3. A liquid crystal panel having a plurality of source lines and a plurality of gate lines;
A plurality of source line drivers coupled to the plurality of source lines and generating drive signals for selectively driving the source lines based on display data to be displayed on the liquid crystal panel;
A gate line driver coupled to the plurality of gate lines and sequentially scanning the gate lines;
A power supply circuit coupled to the liquid crystal panel, the plurality of source line drivers and the gate line driver, and supplying a driving power supply potential to be supplied to the liquid crystal panel, the plurality of source line drivers and the gate line driver;
A controller coupled to the plurality of source line drivers and the gate line driver, for supplying the display data to the plurality of source line drivers and for supplying a timing control signal to the plurality of source line drivers and the gate line driver; ,
A terminal for supplying a reference potential to be supplied to the plurality of source line drivers and the gate line driver;
The controller supplies the display data in a differential format to the plurality of source line drivers,
Each of the plurality of source line drivers includes a differential input circuit for receiving the display data in the differential format, a data latch circuit for latching an output of the differential input circuit, and a drive signal for generating the drive signal. An output circuit,
As the power supply potential of the differential input circuit of each of the plurality of source line drivers, a power supply potential selected from the drive power supply potential is used.
The reference potential supplied from the terminal is used as the power supply potential of the data latch circuit of each of the plurality of source line drivers.
A liquid crystal display system, wherein a power supply potential of the differential input circuit is larger than a power supply potential of the data latch circuit. The differential input circuit is
A pair of differential MOS transistors each having a gate for receiving the differential display data and a common source;
6. The liquid crystal display according to claim 5, further comprising a current source MOS transistor having a drain coupled to the common source, a source to which a power source potential selected from the driving power source potential is supplied, and a gate to which a bias potential is supplied. system. Each of the plurality of source line drivers further includes a standby control circuit,
The liquid crystal display system according to claim 6, wherein the bias potential is selectively supplied to the gate of the current source MOS transistor under the control of the standby control circuit. The standby control circuit is
In response to activation of a signal representing one horizontal period of the liquid crystal panel among the timing control signals supplied from the controller, the bias potential is supplied to the gate of the current source MOS transistor,
8. The liquid crystal display system according to claim 7, wherein the bias potential to the gate of the current source MOS transistor is cut off in response to activation of an enable signal among the timing control signals supplied from the controller. The standby control circuit is
In response to the activation of the corresponding enable signal among the timing control signals supplied from the controller, the bias potential is supplied to the gate of the current source MOS transistor,
8. The bias potential to the gate of the current source MOS transistor is cut off in response to activation of an enable signal related to a source line driver at the next stage among the timing control signals supplied from the controller. The liquid crystal display system described.

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