JP4696510B2 - Manufacturing method of SOI wafer - Google Patents

Description

  The present invention relates to a method for manufacturing an SOI wafer.

JP-A-9-64319

  In manufacturing a semiconductor device such as a CMOS-IC or a high voltage IC, a silicon oxide film is formed on a silicon single crystal substrate (hereinafter also referred to as a base wafer), and another silicon single crystal layer is formed on the SOI ( A so-called SOI wafer formed by stacking as a silicon on insulator) layer is used. As a method for manufacturing an SOI wafer, a bonding method, a SIMOX method, and the like are known. In the bonding method, a base wafer made of silicon single crystal and a bond wafer are bonded together by heat treatment through a silicon oxide film, and then the bond wafer is polished, etched, or peeled off using an ion implantation layer (so-called smart cut). This is a method for forming an SOI layer by reducing the thickness by the (registered trademark) method. On the other hand, the SIMOX method is a method in which a buried oxide film is formed by performing an internal oxidation heat treatment after implanting high-concentration oxygen ions into a silicon single crystal substrate.

  Conventionally, an SOI wafer has a drawback that warpage of the substrate is likely to occur because the base wafer and SOI layer made of silicon single crystal and the silicon oxide film have different thermal expansion coefficients. When the warpage of the SOI wafer becomes large, it may be difficult to focus on the photolithography process, thereby making it difficult to form an element. This defect becomes more prominent as the integration rate of the integrated circuit increases.

  Conventionally, the warpage of the SOI wafer as described above has been mainly focused on the heat treatment in the bonding method and the internal oxidation heat treatment in the SIMOX method, and various countermeasures have been taken. For example, in Patent Document 1, a defect-free layer having a zero oxygen precipitate formation density is formed in a region in contact with a silicon oxide film of a base wafer, and the remaining wafer region has a higher oxygen precipitate density than the defect-free layer. An SOI wafer structure having an oxygen precipitate layer is disclosed, which can prevent warpage of the wafer due to the above-described difference in thermal expansion coefficient.

  However, as a result of investigations by the present inventors, it has been found that the cause of warping of the SOI wafer is not necessarily caused only by the difference in linear expansion coefficient between the silicon oxide film and the base wafer or silicon forming the SOI layer. . For example, the present inventors have found that a warp of an SOI wafer, in which warpage was not so remarkable in a state before being subjected to device processing, becomes apparent during heat treatment in device processing, and cannot be understood by the above warp generation mechanism. Often faced. This phenomenon is more likely to occur when the thickness of the SOI layer or silicon oxide film is reduced (for example, 2 μm or less, respectively) when the wafer diameter is large (e.g. This is particularly noticeable in the case of 200 mm or more, for example.

  An object of the present invention is to provide a method for manufacturing an SOI wafer that has a relatively thin silicon oxide film and an SOI layer and is less likely to warp during heat treatment performed in a device process.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the present invention has a structure in which an SOI layer made of a semiconductor single crystal is bonded to a first main surface of a base wafer made of a silicon single crystal via a silicon oxide film, and the SOI A method for manufacturing an SOI wafer in which heat treatment is performed by infrared irradiation with a peak wavelength λ of 0.7 μm or more and 2 μm or less on the layer side, the first main surface of a base wafer made of silicon single crystal, and a bond made of semiconductor single crystal A laminated body having a bonding process in which the first main surface of the wafer is bonded to each other through a silicon oxide film formed on at least one of the main surfaces, and a base wafer and a bond wafer are heated to 400 to 600 ° C. to delamination heat treatment Te comprises a release step of peeling the bond wafer, the thickness decrease of SOI layer and forming by subtracting the thickness of the bond wafer And extent, warmed to 1000 ° C. or higher 1250 ° C. or less at a Atsushi Nobori rate bonding heat treatment the temperature of the separation heat treatment of 10 to 40 ° C. / min for increasing the binding to the base wafer of the SOI layer through the silicon oxide film A silicon oxide film thickness t1 and an SOI layer thickness t2 is a refractive index in the infrared wavelength region of SiO ₂ forming a silicon oxide film, and a semiconductor forming an SOI layer. And the optical thickness t _OP in the infrared wavelength region between the silicon oxide film and the SOI layer is t _OP = n1 × t1 + n2 × t2, and 0.1λ <t _OP <2λ is satisfied. In addition, (t1 × n1) / (t2 × n2) is set within a range of 0.2 or more and 3 or less, and further, a precipitation erasing heat treatment for reducing the formation density of oxygen precipitates in the base wafer after the bonding heat treatment. Do The formation density of the oxygen precipitates in the base wafer was adjusted to less than 1 × 10 9 ^/ cm ^3, primary and Rukoto heat treatment by infrared irradiation is performed by an infrared light source disposed only on the first main surface side of the SOI layer Features. The SOI layer in the present invention is not only a typical SOI layer made of silicon single crystal, but also a SiGe layer or Ge layer represented by Si _X Ge _1-X (0 ≦ X <1), or other semiconductor thin films. It means a broadly defined SOI (Semiconductor On Insulator) layer.

In the present invention, the formation density of oxygen precipitates in the base wafer is determined by using an OPP (Optical Precipitate Profiler: High) which is a device using a well-known infrared interferometry with the second main surface of the base wafer as a mirror-polished surface. This refers to the number per 1 cm ³ of microprecipitates (Bulk Micro-Defect: BMD) having a size diameter of 50 nm or more detected by Yield Technology). Hereinafter, when simply referred to as “oxygen precipitate” in the present invention, it means BMD. In bonding, a silicon oxide film may be formed only on one of the base wafer and the bond wafer, or both the oxide films may be integrated by bonding to both. In the latter case, the thickness of the silicon oxide film after the bonding corresponds to the total thickness of the silicon oxide films formed on both sides.

As a result of detailed examination of the relationship between the heat treatment conditions when forming an SOI wafer into a device and the warpage of the generated wafer, the present inventor has come to grasp the following facts.
(1) The warpage of the SOI wafer, in which the warpage was not so remarkable in the state before being subjected to the device processing, may become apparent during the heat treatment in the device processing. Specifically, this is a case where heat treatment heating is performed by infrared irradiation from the SOI layer side.
(2) The occurrence of warpage is remarkable when the wavelength of infrared rays to be irradiated (hereinafter represented by the peak wavelength λ) and the optical thickness t _OP in the infrared wavelength region between the silicon oxide film and the SOI layer are constant. In particular, the occurrence of warping is significant when the relationship close to t _OP = 0.5λ is satisfied.
(3) The SOI wafer in which warpage has occurred has a high level of 1 × 10 ⁹ or more in the formation density of oxygen precipitates on the base wafer.

As a result of further intensive studies, when the formation density of oxygen precipitates in the entire base wafer is adjusted to less than 1 × 10 ⁹ / cm ³ , it is possible to make a device even under the above conditions (1) and (2). It has been found that the occurrence of warpage of the SOI wafer during the heat treatment can be effectively suppressed, and the present invention has been completed.

  The reason why warp was particularly likely to occur when the condition (2) was satisfied during heat treatment with infrared irradiation is considered as follows. First, a resistance heating lamp such as a halogen lamp is often used as an infrared source used for heat treatment. As shown in FIG. 11, the peak wavelength λ differs depending on the light source temperature, but most of them fall within the range of 0.7 μm to 2 μm. The optical spectrum is generally broad, but the main component in the infrared region contributing to heating is within the wavelength range of 0.5 μm to 3 μm.

In relation to the above peak wavelength λ, the optical thickness t _OP (= n1 × t1 + n2 × t2) in the infrared wavelength region between the silicon oxide film and the SOI layer satisfies 0.1λ <t _OP <2λ. In addition, the situation where (t1 × n1) / (t2 × n2) is 0.2 or more and 3 or less means that both the silicon oxide film and the SOI layer are formed with a small thickness of less than 4 μm (preferably The thickness t1 of the silicon oxide film is, for example, not less than 10 nm and not more than 500 nm, and the thickness t2 of the SOI layer is, for example, not less than 10 nm and not more than 500 nm). If the thickness of the base wafer is the same as that of a normal SOI wafer (for example, a diameter of 200 mm and not less than 600 μm and not more than 800 μm), with this thickness of silicon oxide film, the degree of warpage based on the difference in linear expansion coefficient from Si is For example, it is considered to be much smaller than the configuration described in Patent Document 1 and the like. However, in a state where the formation density of oxygen precipitates on the base wafer is as high as 1 × 10 ⁹ / cm ³ or more, if heat treatment is performed by infrared irradiation from the SOI layer side, the amount of warpage is unexpectedly large, for example, a diameter of 200 mm In such an SOI wafer, warping as large as 200 μm to 300 μm may occur. Therefore, it is clear that the main factor of the warpage is not a difference in linear expansion coefficient between layers that has been assumed in the past. The inventor believes that the cause of this warpage is a decrease in strength of the base wafer due to the formation of oxygen precipitates and non-uniform heating due to infrared reflection on the SOI layer side. This will be described in more detail below.

  The infrared reflection on the surface of the SOI layer may be total reflection derived from the difference in refractive index between the ambient atmosphere (for example, air) and the SOI layer. This is when the incident angle of infrared rays is larger than a certain critical angle. In the case where infrared rays can be uniformly irradiated on the entire surface of the wafer with a wide light source in the plane, the problem is not so much. However, when a silicon oxide film and an SOI layer having different refractive indexes are combined, depending on the relationship between the thickness of the layer and the wavelength of incident infrared rays, the incident direction of infrared rays is close to the surface normal direction. Even so, very strong reflections may occur.

  For example, in the layer thickness direction of a laminate in which the refractive index changes periodically, such as a structure in which silicon oxide films and silicon layers are alternately laminated, electrons in the crystal against photoquantized electromagnetic wave energy It is known that a band structure similar to energy is formed, and electromagnetic waves having a specific wavelength corresponding to the period of change in refractive index are prevented from entering the laminate structure. Such a structure is referred to as a photonic band structure, and in the case of a multilayer film, the refractive index change is formed only in the layer thickness direction, so in a narrow sense it is also referred to as a one-dimensional photonic band gap structure.

In such a photonic band gap structure, as the number of stacking periods increases, the wavelength range in which incidence is prohibited (that is, the wavelength range in which the reflectivity increases: hereinafter referred to as the photonic band gap region) tends to become wider. Even if the number of stacking periods is 1, the photonic band gap region is only relatively narrowed, and very large reflection is generated near the gap center wavelength. A typical SOI wafer structure, that is, a structure in which a silicon oxide film and an SOI layer are formed on a base wafer one by one corresponds to this, and the conditions for generating a one-dimensional photonic band gap structure are silicon oxide. This is a case where the optical thickness t _OP = n1 × t1 + n2 × t2 in the infrared wavelength region between the film and the SOI layer satisfies ½ (that is, 0.5λ) of the wavelength λ of the incident infrared rays. Actually, the reflectance shows a maximum value in the vicinity of t _OP = 0.5λ, but the reflectance is still large even in a wavelength region slightly deviated from this condition, and the peak wavelength of the incident infrared spectrum is λ. Actually, as shown in FIG. 11, since the wavelength of the incident line is distributed over a wide range including λ, the wavelength region where relatively strong reflection occurs in consideration of these influences is also 0.1λ <t. It is expanded to about _OP <2λ. The ratio of the optical thicknesses of both layers (t1 × n1) / (t2 × n2) is likely to cause relatively strong reflection when the ratio is 0.2 or more and 3 or less, particularly when the ratio is around 1. When the optical thicknesses of the two layers are equal to each other, the wavelength range where strong reflection occurs is the widest and the reflectance is high. The refractive index n1 in the infrared wavelength region of the silicon oxide film is 1.5, the refractive index n2 of the SOI layer is 3.5 in the case of silicon single crystal, and 4.0 in the case of Ge (germanium). In the case of Si _x Ge _1-x , Si is 3.5, Ge is 4.0, and a refractive index linearly interpolated by the value of the mixed crystal ratio x is used.

FIG. 12 shows the relationship between the wavelength of the incident line and the reflectance in the combination of the SOI layer and the silicon oxide film having various thicknesses, and the total optical thickness t _{OP of} each layer and the corresponding relationship. The center wavelength λ _PBG (≡2t _OP ) of the photonic band gap is also shown (incident angle is 5 °). Under any condition, it is clear that the reflectance is maximized in the vicinity of λ _PBG , but the wavelength region where reflection of 50% or more occurs is in a wide range from at least 700 nm to 1.6 μm. I understand that. The present invention, SOI wafer structure thus reflectance for the incident wavelength is maximized in the vicinity of lambda _PBG, and having a reflectivity of 50% or more in a wide wavelength region (at least 500nm or more regions) containing lambda _PBG It is extremely effective against. The mirror-polished wafer (PW) does not have a maximum reflectance and shows a low reflectance in the entire wavelength region.

If the center wavelength of the photonic band gap formed by the silicon oxide film and the SOI layer is close to the wavelength λ of the incident infrared light, even if the surface of the SOI layer is evenly irradiated with infrared light, the influence of reflection causes the wafer The heating distribution in the layer thickness direction becomes non-uniform (this non-uniformity does not necessarily occur so that the SOI layer side where reflection occurs is at a low temperature, as will be described in detail later). When temperature non-uniformity occurs in the layer thickness direction of the base wafer, the in-plane thermal stress of the base wafer is also distributed in the layer thickness direction and acts as warp generation stress. On the other hand, when oxygen precipitates are formed in the base wafer, in the silicon single crystal bulk region constituting the wafer around the oxygen precipitates, a number of crystal defects such as dislocations are introduced and the strength is lowered. It has become. If oxygen precipitates are formed at a high density inside the base wafer, the rigidity of the base wafer cannot resist the warp stress in the layer thickness direction derived from the heating non-uniformity, and a significant warp occurs. It is considered a thing. Therefore, if the formation density of oxygen precipitates in the entire base wafer is suppressed to less than 1 × 10 ⁹ / cm ³ , strong warpage occurs in the SOI wafer after heat treatment even if heating nonuniformity occurs due to the photonic band gap effect. This can be effectively suppressed. The formation density of oxygen precipitates in the base wafer is desirably less than 5 × 10 ⁸ / cm ³ , more desirably less than 5 × 10 ⁷ / cm ³ .

  In particular, when the heat treatment of the SOI wafer is performed using a so-called single-sided heat treatment apparatus that is performed by an infrared light source disposed only on the first main surface side of the SOI layer, the effect of the present invention is particularly remarkable. Is done. In such a heat treatment apparatus, the temperature of the base wafer is usually set while the temperature of the base wafer is measured by a temperature sensor (for example, a radiation thermometer) disposed on the second main surface side of the base wafer. Heating is performed by controlling the heat generation output of the infrared light source so that the temperature is raised and maintained at the heat treatment temperature. At this time, if the SOI layer forms a photonic band gap structure together with the silicon oxide film, the following situation occurs.

That is, in the initial stage, the temperature of the base wafer detected by the temperature sensor is lower than the set temperature, so the power of the infrared light source is controlled in the increasing direction and the temperature rise starts. However, since most of the incoming infrared rays are reflected on the SOI layer side, the temperature detected on the second main surface side of the base wafer does not rise easily. As a result, the control unit of the light source increases the infrared power more and more to bring the detected temperature closer to the target value. That is, the power of the infrared light source is controlled in a state shifted to the over side as compared with a case where reflection is not so much (for example, when heat-treating a mirror-polished wafer or the like not forming an SOI layer). On the other hand, heat transfer from the SOI layer surface to the base wafer side involves not only radiant heat transfer by direct incidence of infrared rays but also heat conduction from the ambient atmosphere. If the power of the infrared light source is shifted to the over side, the temperature of the ambient atmosphere that is not affected by the reflection is abnormally increased, and the temperature on the SOI layer side that is in contact with the temperature is excessively increased. The temperature difference is also very large. As a result, the warpage of the SOI wafer is more likely to occur. However, as in the present invention, if the formation density of oxygen precipitates in the entire base wafer is suppressed to less than 1 × 10 ⁹ / cm ³ , the SOI wafer can be obtained even when heat treatment is performed using such a heating method. Can be sufficiently suppressed.

  This effect is particularly remarkable when the heat treatment set temperature in the device process is as high as 1000 ° C. or more and 1200 ° C. or less, and the rate of temperature rise to the set temperature is as large as 50 ° C./sec or more and 100 ° C./sec or less. It is. In other words, when the heating rate is set to be large, the power of the infrared light source is increased before the heat conduction in the thickness direction of the wafer is sufficiently advanced, and the temperature is measured on the second main surface of the base wafer. The temperature rise is increasingly delayed with respect to the temperature on the SOI layer side. As a result, the power of the infrared light source is more likely to overshoot and warpage is likely to occur.

  Oxygen precipitates in the base wafer are particularly likely to occur when the base wafer is composed of a silicon single crystal having a relatively high oxygen content. Specifically, the Czochralski method (CZ method) using a quartz crucible When the wafer is manufactured by the above-described method, a large amount of oxygen precipitates that cause warpage are likely to be generated due to various thermal histories applied during the manufacturing process of the SOI wafer. Therefore, in the manufacturing process of the SOI wafer, it is desirable to appropriately perform heat treatment for reducing oxygen precipitates from the viewpoint of reducing the final density of oxygen precipitates formed on the SOI wafer.

  A silicon single crystal wafer having a relatively high oxygen concentration, such as a CZ wafer (the oxygen concentration of a bulk silicon single crystal is, for example, 12 ppma or more and 25 ppma or less) is oxygenated by cooling after crystal pulling or by high-temperature heat treatment at 1000 ° C. or more. At the time of cooling after the solid solution is formed, fine oxygen precipitates pass through a temperature range around 500 ° C., specifically, 480 ° C. slightly higher than 450 ° C. at which the thermal donor is formed. It is known that (BMD) precipitation nuclei (embryo: size is usually 1 nm or less), and the longer the holding time near the center temperature, the higher the density of precipitation nuclei formed. And when this precipitation nucleus is more than the said nucleation temperature and is hold | maintained below the critical temperature which concerns on the re-solid solution to Si single crystal bulk, a nucleus will grow into BMD. In the manufacturing process of SOI wafers, it is necessary to pay attention to the bonding heat treatment for increasing the bonding strength between the SOI layer and the base wafer. The temperature is set to 1200 ° C. or lower and is performed in a batch for a plurality of SOI wafers. In this bonding heat treatment, the processing temperature is the temperature range where the nuclei disappear, but since the heat treatment is a batch heat treatment with a relatively large processing capacity, the temperature rising rate to the set processing temperature is as low as 10 to 40 ° C./min. The precipitation nuclei will grow into BMD when the temperature is raised. In this specification, the unit of oxygen concentration is shown using the standard of JEIDA (abbreviation of Japan Electronic Industry Promotion Association. Currently renamed JEITA (Japan Electronics and Information Technology Industries Association)). .

Therefore, after the bonding heat treatment step, the precipitation elimination heat treatment is performed at a higher temperature than the bonding heat treatment step, so that the oxygen precipitates in the base wafer are formed into a solution. As a result, in the SOI wafer subjected to the device process, the formation density of BMD in the base wafer is reduced to less than 1 × 10 ⁹ / cm ³ . The decrease in the BMD formation density also appears significantly in the change in dissolved oxygen concentration before and after the precipitation erasing heat treatment.

  The precipitation elimination heat treatment is preferably performed at a holding temperature of 1275 ° C. or higher and 1350 ° C. or lower. At a low holding temperature, it is difficult for the solution formation of BMD to proceed effectively. On the other hand, if the holding temperature is too high, the occurrence of slip dislocation may become significant. Preferably, it is performed at 1280 ° C or higher and 1300 ° C or lower. In addition, the time for holding the SOI wafer in such a temperature range is preferably 1 hour or more and 5 hours or less in consideration of the progress of solutionization of BMD and the economy. In addition, as the precipitation erasure heat treatment performed under such conditions, it is preferable to adopt a batch processing method using a batch heat treatment furnace.

  As an atmosphere for the precipitation elimination heat treatment, an atmosphere containing an inert gas (for example, a rare gas such as argon) and a small amount of oxygen can be employed. If the atmosphere contains a trace amount of oxygen, introduction of atomic vacancies (which mediate diffusion during oxygen precipitation) into the silicon single crystal is suppressed, which is effective in reducing BMD. Conversely, high-temperature heat treatment (for example, around 1200 ° C.) in a hydrogen or argon atmosphere promotes the introduction of atomic vacancies into the silicon single crystal and may hinder the reduction in BMD density.

  As described above, a CZ wafer is often used for manufacturing an SOI wafer. Although the CZ silicon single crystal rod as a whole has a close initial oxygen concentration, it still has a distribution in the axial and radial directions. In general, when the BMD density is controlled, it is considered that strict examination of the initial oxygen concentration is necessary. However, the method of the present invention hardly requires such examination, and not only when using CZ wafers cut from the same CZ silicon single crystal rod, but also when manufacturing SOI wafers using CZ wafers with different production lots, As long as the conditions for the precipitation erasing heat treatment are adjusted, it is possible to stably manufacture an SOI wafer that is unlikely to warp even if RTA (Rapid Thermal Annealing) is performed in the device process.

  Next, the thickness reducing step includes a peeling ion implantation layer forming step for forming a peeling ion implantation layer by implanting ions from the ion implantation surface on the first main surface side of the bond wafer prior to the bonding step. Then, after the bonding step, the silicon single crystal thin layer to be the SOI layer can be implemented as including a peeling step of peeling from the bond wafer in the peeling ion implantation layer (so-called smart cut (registered trademark)). Law).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 illustrates a basic embodiment of a method for manufacturing an SOI wafer according to the present invention. First, as shown in the step (a), for example, a base wafer 7 made of a silicon single crystal and a bond wafer 1 made of a silicon single crystal substrate shown in the step (b) are prepared. These silicon single crystals are manufactured by a well-known Czochralski method using a quartz crucible, and those having a relatively high initial oxygen content of, for example, 12 ppma to 25 ppma are used. As the bond wafer 1, an epitaxial wafer obtained by epitaxially growing a semiconductor single crystal such as Si, SiGe, Ge on a silicon single crystal wafer can also be used.

  Next, as shown in step (c), a silicon oxide film 2 is formed as an insulating film on at least the first main surface J side of the bond wafer 1. The silicon oxide film 2 can be formed by, for example, thermal oxidation such as wet oxidation or dry oxidation, but a method such as CVD (Chemical Vapor Deposition) can also be employed. The thickness of the silicon oxide film is set to a value of 10 nm to 500 nm, for example. Then, as shown in step (d), ions are implanted by irradiating, for example, a hydrogen ion beam with the first main surface J side of the bond wafer 1, in this embodiment, the surface of the silicon oxide film 2 as the ion implantation surface. Then, the ion implantation layer 4 for peeling is formed. The ions for forming the peeling ion implantation layer 4 can be at least one selected from an ion group consisting of hydrogen ions and rare gas (He, Ne, Ar, Kr, Xe) ions. Although hydrogen ions are used in this embodiment, the ion implantation layer 4 for peeling may be formed by implanting rare gas ions such as helium ions, neon ions, or argon ions instead of hydrogen ions.

  The bond wafer 1 and the base wafer 7 on which the ion implantation layer 4 for peeling is formed are cleaned with a cleaning solution, and further, as shown in the step (e), both wafers 1 and 7 are formed on the side where the ion implantation layer 4 is formed ( That is, bonding is performed on the first main surface J, K side). And as shown to a process (f), by carrying out peeling heat processing of the laminated body at the low temperature of 400-600 degreeC, the bond wafer 1 peels in the density | concentration peak position of the above-mentioned ion implantation layer 4 for peeling, The portion remaining on the base wafer 7 side becomes the SOI layer 15 (peeling process). In some cases, the heat treatment for stripping can be omitted by increasing the amount of ion implantation when forming the ion implantation layer 4 for stripping or by activating the surface by previously performing plasma treatment on the surface to be overlapped. . Further, the remaining bond wafer portion 3 after peeling can be reused again as a bond wafer or a base wafer after re-polishing the peeled surface.

The thickness of the SOI layer 15 is 10 nm or more and 500 nm or less, and can be adjusted by the formation depth of the ion implantation layer 4 for peeling. As shown in FIG. 9, the thickness t1 of the silicon oxide film 2 after bonding and the thickness t2 of the SOI layer 15 are such that the refractive index n1 in the infrared wavelength region of SiO ₂ forming the silicon oxide film 2 is 1. 5. The refractive index n2 of Si forming the SOI layer 15 is 3.5, and the optical thickness t _OP in the infrared wavelength region between the silicon oxide film 2 and the SOI layer 15 is t _OP = n1 × t1 + n2 × t2. 0.1λ <t _OP <2λ is satisfied, and (t1 × n1) / (t2 × n2) is set in the range of 0.2 to 3.

  Then, after the peeling step, a bonding heat treatment for firmly bonding the base wafer 7 and the SOI layer 15 through the silicon oxide film 2 is performed. As shown in FIG. 3, this bonding heat treatment is performed at a temperature of 1000 ° C. or more and 1250 ° C. or less in a batch-type heat treatment furnace BF on a plurality of wafers 50 ′ (only one is shown in the figure). . Because of the batch heat treatment having a relatively large processing capacity, the rate of temperature rise to the set processing temperature is as low as 10 to 40 ° C./min. At the time of temperature rise, the precipitation nuclei N in the base wafer 7 are oxygen precipitates (BMD). ) Grow to P. In the silicon single crystal bulk region constituting the wafer around the oxygen precipitate P, a large number of crystal defects D such as slip dislocations are introduced and the strength is lowered.

  Therefore, a precipitation erasing heat treatment is performed on the SOI wafer 50 ′ after the bonding heat treatment to reduce the BMD formation density. First, prior to the precipitation erasing heat treatment, after removing the oxide film on the surface of the SOI wafer, a step of removing the damaged layer and surface roughness of the SOI layer 15 is performed. When an SOI wafer is manufactured by an ion implantation separation method, it is known that a damaged layer and surface roughness at the time of ion implantation remain on the surface of the SOI layer. Therefore, the damage layer and the surface roughness formed on the SOI layer are removed after the end of the bonding heat treatment. For this removal step, a method of heat treatment in an inert gas such as Ar or hydrogen gas, or a mixed gas atmosphere thereof can be employed. For example, heat treatment is performed in an Ar atmosphere at 1150 to 1250 ° C. for 1 to 5 hours. However, the damaged layer removal step by heat treatment is not essential.

  Next, a precipitation erasing heat treatment for reducing BMD is performed. Specifically, as shown in the upper diagram of FIG. 4, a plurality of SOI wafers 50 b after the damaged layer removal process by heat treatment are accommodated in a wafer boat 62, and the whole wafer boat 62 is introduced into a batch-type heat treatment furnace 60. To do. The heater 61 is controlled so that the temperature in the heat treatment furnace 60 is higher than the bonding heat treatment described in FIG. 3, that is, 1275 ° C. or higher and 1350 ° C. or lower. By performing the heat treatment at such a temperature, the BMD formed on the base wafer 7 of the SOI wafer 50b is in solution, and the dissolved oxygen increases instead. The heat treatment time varies depending on the holding temperature to be set and the diameter of the wafer to be used (200 mm, 300 mm, or more), but it is set to 1 hour or more and 5 hours or less in consideration of the progress of solutionization of BMD and economics. It is good. The pressure is normal pressure.

  Further, the inside of the heat treatment furnace 60 is an atmosphere substantially containing only argon and a trace amount of oxygen. Other noble gases may be used instead of argon. When heat treatment is performed in an atmosphere containing a small amount of oxygen, introduction of vacancies into the silicon single crystal is suppressed, which is desirable from the viewpoint of reducing BMD. The oxygen concentration in the atmosphere may be, for example, 0.3 volume% or more and 5 volume% or less. In this way, as shown in the lower part of FIG. 4, it is possible to obtain an SOI wafer 500 in which the formation density of BMD (P) is extremely small.

  The obtained SOI wafer 500 can improve the surface roughness of the SOI layer 15 by performing touch polishing. Touch polishing is mirror polishing with an extremely small polishing allowance, and is generally performed by a chemical mechanical polishing method. The damage layer can be removed and the surface roughness can be improved by performing touch polishing instead of the treatment for removing the damage layer by the heat treatment described above or after the heat treatment.

When the surface roughness is improved by touch polishing, the thickness of the SOI layer 15 also changes. Therefore, when all of these processes are completed, the thickness t1 of the silicon oxide film 2 and the thickness t2 of the SOI layer 15 However, the refractive index n1 of the infrared wavelength region of SiO ₂ forming the silicon oxide film 2 is 1.5, the refractive index n2 of Si forming the SOI layer 15 is 3.5, and the silicon oxide film 2 and the SOI layer 15 are Where the optical thickness t _OP in the infrared wavelength region is t _OP = n1 × t1 + n2 × t2, 0.1λ <t _OP <2λ is satisfied, and (t1 × n1) / (t2 × n2) is 0 It is even better if it falls within the range of 2 to 3.

  FIG. 5 is a graph showing the results of measuring the BMD density of a base wafer by a known LST (Light Scattering Tomography) method for an SOI wafer that has been subjected to precipitation elimination heat treatment under several conditions. All samples were prepared in the same lot using a CZ wafer (φ200 mm) whose initial oxygen concentration was adjusted in the range of 13.8 ppma to 14.4 ppma, and until the damaged layer removal process by heat treatment. It can be considered that the influence of the error between them and the difference in the initial oxygen concentration is extremely small.

First, the data at the left end is a measurement result of the SOI wafer 50b that has not been subjected to the precipitation erasing heat treatment, and shows a high BMD density. In contrast, the SOI wafer 500 subjected to the precipitation erasing heat treatment at 1275 ° C. for 1 hour has a BMD density reduced to a level lower than 1.0 × 10 ⁹ / cm ³ . For an SOI wafer 500 that has been subjected to precipitation erasure heat treatment at 1288 ° C. for 1 hour, 1300 ° C. for 1 hour, and 1350 ° C. for 4 hours, the BMD density is the detection limit of the LST device (approximately 1.0 × 10 ⁶ / cm ³ ). The BMD density was reduced to a level lower than. Incidentally, the data at the right end is data indicating the BMD density of SIMOX measured as a reference example. However, according to the present invention, it was found that the BMD density can be reduced to a level that is not different from SIMOX.

  Moreover, the reduction of the BMD density by the precipitation erasing heat treatment is obvious from the measurement result of the dissolved oxygen concentration. FIG. 6 is a graph showing the results of measuring the dissolved oxygen concentration in the base wafer 7 by the FT-IR method for the same sample as FIG. The dissolved oxygen concentration was measured at three points: wafer center, R / 2 (R: radius) from the wafer center, and 10 mm from the outer periphery of the wafer, but there was no significant difference.

  First, the data showing the lowest dissolved oxygen concentration is the data of the SOI wafer 50b not subjected to the precipitation erasing heat treatment, and shows about 8 ppma. As explained above, since a CZ wafer having an initial oxygen concentration of 13.8 ppma or more and 14.4 ppma or less is used, it is considered that the difference is precipitated as BMD. On the other hand, the SOI wafer 500 subjected to the precipitation erasure heat treatment shows a value from about 13 ppma to about 16 ppma. In particular, the dissolved oxygen concentration of the SOI wafer 500 obtained by performing precipitation erasure heat treatment at 1350 ° C. for 4 hours exceeded the initial value. This fact indicates that oxygen contained in the atmosphere of the precipitation elimination heat treatment has been taken into the base wafer 7. When the interstitial oxygen concentration is high, there is an advantage that the function of suppressing the movement of dislocations generated by thermal stress is enhanced. These facts also support that the precipitation elimination heat treatment is preferably performed in an atmosphere containing argon and a trace amount of oxygen.

  Now, the SOI wafer 500 in which the BMD density is reduced as described above is subjected to various heat treatments when it is made into a device. For example, when the doping region is patterned by ion implantation, since the dopant immediately after ion implantation is not activated as a carrier source, heat treatment for activating this is performed. For example, in the case of B dope, the temperature of the active heat treatment is, for example, 1100 ° C. or more and 1200 ° C. or less. This heat treatment is performed using an RTP (Rapid Thermal Processing) apparatus 100 shown in FIG.

  FIG. 2 shows an example of a single-sided heating type RTP apparatus 100, in which a container 21 in which an accommodation space 14 for accommodating only one SOI wafer 500 as an object to be processed is formed, and an SOI wafer 500 in the accommodation space 14. And a heating lamp 46 composed of a tungsten-halogen lamp or the like. The heating lamp 46 is disposed to face the first main surface (upper surface side in the drawing) of the SOI wafer 500 with the heating gap 25 interposed therebetween. On the back side of the SOI wafer 500, the reflection plate 28 is disposed so as to face the SOI wafer 500, and a reflection gap 35 is formed. The reflecting plate 28 is exposed at the end of a glass fiber 30 (connected to a radiation thermometer not shown) for measuring the temperature of the back side of the SOI wafer 500 (that is, the second main surface side of the base wafer 7). is doing. And the heat ray taken out from the reflective space | gap 35 via the glass fiber 30 is separately detected with the known radiation thermometer which makes a temperature detection part, and is converted into a temperature signal. The plurality of heating lamps 46 arranged corresponding to the respective temperature measuring positions by the glass fiber 30 can be independently controlled in output. The heating rate up to the heat treatment temperature is rapid heating set to 50 ° C./second or more and 100 ° C./second or less (for example, 75 ° C./second). The SOI wafer 500 is disposed so that the SOI layer 15 faces the heating lamp 46 side. The infrared rays emitted from the heating lamp 46 are near infrared rays having a continuous spectrum as shown in FIG. 11 and a peak wavelength λ of 0.7 μm or more and 2 μm or less.

  FIG. 8 shows an example of the temperature rise profile and the power control profile of the heating lamp 46 (measurement of a plurality of points in the wafer surface) in comparison with an SOI wafer and a reference mirror-polished wafer (silicon single crystal wafer). It is a graph. With a mirror polished wafer, a temperature control profile of 75 ° C./second is realized, but the power control profile is within about 70% of full power except for an instantaneous value. There is no rising sign. However, in the case of the SOI wafer, it can be seen that a remarkable overshoot exceeding 80% of the full power occurs during the temperature rising. The reason is considered as follows.

In the structure in which the silicon oxide film 2 and the SOI layer 15 are formed on the base wafer 7 one by one, as described above, the thickness t1 of the silicon oxide film 2 and the thickness t2 of the SOI layer 15 are the silicon oxide film. The refractive index n1 of the infrared wavelength region of SiO ₂ forming 1.5 is 1.5, the refractive index n2 of Si forming the SOI layer 15 is 3.5, and these are used for heat treatment of the silicon oxide film 2 and the SOI layer 15 When the optical thickness t _OP in the infrared wavelength range is t _OP = n1 × t1 + n2 × t2, the peak wavelength of the infrared to be used is λ (see FIG. 11), and 0.1λ <t _OP <2λ is satisfied. When the layer thicknesses t1 and t2 are selected so that (t1 × n1) / (t2 × n2) is 0.2 or more and 3 or less, the above-described one-dimensional as shown in FIG. By formation of photonic band gap structure Strong reflection of infrared IR in the SOI layer 15 side occurs. In the single-sided heating type RTP apparatus 100 as shown in FIG. 2, as shown in FIG. 10, since most of the incoming infrared rays are reflected on the SOI layer 15 side, it is detected on the second main surface side of the base wafer 7. The temperature does not rise easily. As a result, the control unit of the heating lamp 46 increases the power more and more so as to bring the detected temperature closer to the target value, and the above-described overshoot occurs. The heat transfer from the surface of the SOI layer 15 to the base wafer 7 side involves not only radiant heat transfer by direct incidence of infrared rays but also heat conduction from the surrounding atmosphere. When the power of the heating lamp 46 is shifted to the over side, the temperature of the surrounding atmosphere that is not affected by the reflection is abnormally increased, and the temperature on the SOI layer 15 side in contact with the temperature is excessively increased. The temperature difference between the front and back is also very large.

  At this time, as shown in FIG. 3, when the formation density of the oxygen precipitates P on the base wafer 7 is high, the SOI wafer whose strength is reduced by introducing crystal defects around the oxygen precipitates P is shown in FIG. As shown in FIG. 3, the thermal expansion in the in-plane direction on the SOI layer side, which is the high temperature side, increases, and a strong warp is generated so as to protrude upward. For example, as shown in FIG. 7, a first conductivity type ion implantation region (for example, a p-type region in the case of B) is formed by patterning by a photolithography process, and then rapid thermal processing is performed to activate the ion implantation region. Then warping occurs. If the second conductivity type ion implantation region (for example, an n-type region in the case of P) is to be formed by patterning in a state where the warp has occurred, the mask is relatively moved relative to the SOI layer due to the in-plane displacement due to the warp. There is a problem that the position of the ion-implanted region of the second conductivity type is easily shifted.

However, as shown in FIG. 4, if the formation density of the oxygen precipitates P in the entire base wafer 7 is suppressed to less than 1 × 10 ⁹ / cm ³ , the heat treatment at the time of device fabrication is performed using such a heating method. Even in this case, warping of the SOI wafer 500 can be sufficiently suppressed, and as a result, the occurrence of defective pattern deviation as shown in FIG. 7 can be effectively suppressed.

Explanatory drawing which shows an example of the manufacturing process of an SOI wafer. The cross-sectional perspective view which shows an example of an RTP apparatus. The schematic diagram explaining the relationship between bond heat processing and oxygen precipitate production | generation. The schematic diagram which shows the reduction effect of BMD by precipitation elimination heat processing. The graph which shows the measurement result of the BMD density in a base wafer. The graph which shows the measurement result of the dissolved oxygen concentration in a base wafer. 10A and 10B illustrate a problem caused by warping of an SOI substrate due to heat treatment during device fabrication. The graph which shows the relationship between the temperature rising profile by a single-sided heating type RTP apparatus, and the control profile of heating power by comparing with an SOI wafer and a mirror-polished wafer. The figure which shows typically the mode of the infrared rays reflection in the SOI layer side by formation of a photonic band gap structure. The schematic diagram explaining the mechanism in which the curvature generate | occur | produces in a SOI wafer in a single-sided heating type RTP apparatus. The figure which illustrates some spectrums of the infrared light source used for a RTP apparatus. The graph which shows the relationship between the wavelength of the incident infrared rays of the SOI layer / silicon oxide film which satisfy | fills various layer thickness relationships, and a reflectance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bond wafer 2 Silicon oxide film 7 Base wafer 15 SOI layer 500 SOI wafer

Claims (6)

The first main surface of a base wafer made of silicon single crystal has a structure in which an SOI layer made of a semiconductor single crystal is bonded via a silicon oxide film, and the peak wavelength λ is 0. A method for manufacturing an SOI wafer which performs a heat treatment by infrared irradiation of 7 μm or more and 2 μm or less,
Affixing the first main surface of a base wafer made of silicon single crystal and the first main surface of a bond wafer made of semiconductor single crystal through a silicon oxide film formed on at least one of these main surfaces An SOI layer with a reduced thickness of the bond wafer, including a bonding step, and a peeling step of peeling the bond wafer by peeling heat treatment of the laminate including the base wafer and the bond wafer at 400 to 600 ° C. A thickness reduction step to be performed and a bonding heat treatment for increasing the bonding of the SOI layer to the base wafer via the silicon oxide film at a rate of 10 to 40 ° C./min from the temperature of the peeling heat treatment at 1000 ° C. or more A bonding heat treatment step performed by raising the temperature to 1250 ° C. or lower ,
The thickness t1 of the silicon oxide film and the thickness t2 of the SOI layer are defined such that the refractive index in the infrared wavelength region of SiO ₂ forming the silicon oxide film is n1, and the refractive index of the semiconductor forming the SOI layer is n2. The optical thickness t _OP of the silicon oxide film and the SOI layer in the infrared wavelength region is t _OP = n1 × t1 + n2 × t2, and 0.1λ <t _OP <2λ is satisfied, and (t1 × n1) / (t2 × n2) is set within the range of 0.2 to 3,
Further, after the bonding heat treatment, a precipitation erasing heat treatment is performed to reduce the formation density of oxygen precipitates in the base wafer, and the formation density of oxygen precipitates in the base wafer is adjusted to less than 1 × 10 ⁹ / cm ^3. ,
Method for manufacturing an SOI wafer heat treatment according to the infrared radiation is characterized by Rukoto performed by the first main surface side infrared light source disposed only on the SOI layer.   2. The method of manufacturing an SOI wafer according to claim 1, wherein the SOI layer is made of a silicon single crystal.   3. The method for manufacturing an SOI wafer according to claim 1, wherein a wafer manufactured by a Czochralski method using a quartz crucible is used as the base wafer.   4. The precipitation erasing heat treatment is performed under a condition that a holding temperature is 1275 ° C. or higher and 1350 ° C. or lower and a holding time is 1 hour or longer and 5 hours or shorter. Manufacturing method of SOI wafer.   5. The method for manufacturing an SOI wafer according to claim 1, wherein the precipitation erasing heat treatment is performed in an atmosphere containing an inert gas and a small amount of oxygen.   Prior to the bonding step, the thickness reducing step is a peeling ion implantation layer forming step for forming a peeling ion implantation layer by implanting ions from the ion implantation surface on the first main surface side of the bond wafer. And a peeling step of peeling the semiconductor single crystal thin layer to be the SOI layer from the bond wafer in the peeling ion implantation layer after the bonding step. 6. The method for producing an SOI wafer according to any one of items 5.

Images