JP4687366B2 - Semiconductor chip storage tray and semiconductor chip transfer method - Google Patents

Description

  The present invention relates to a semiconductor chip storage tray and a semiconductor chip transport method. In particular, the present invention relates to a semiconductor chip storage tray and a method for transporting semiconductor chips, which can reduce the cost of transporting semiconductor chips as compared with the prior art.

  FIG. 6 is a perspective view for explaining the configuration and usage of the conventional semiconductor chip storage tray 100. The semiconductor chip storage tray 100 is reversible and is used by being stacked. FIG. 7 is a cross-sectional view of the semiconductor chip storage tray 100 when in use.

  The semiconductor chip storage tray 100 has a lattice-like upper surface rib 102 on the upper surface, and has a lattice-like lower surface rib 103 on the lower surface. When the semiconductor chip storage tray 100 is stacked, the end surfaces of the upper surface rib 102 of the lower semiconductor chip storage tray 100 and the lower surface rib 103 of the upper semiconductor chip storage tray 100 face each other. Then, the area 101 a that accommodates the semiconductor chip 110 is separated from each other by the upper surface rib 102 and the lower surface rib 103. The semiconductor chip 110 is accommodated in the area 101a with the active surface facing upward.

  When the semiconductor chip 110 is taken out from the semiconductor chip storage tray 100 with the back surface facing up, it is necessary to invert the stacked semiconductor chip storage tray 100. In this case, it is necessary to prevent the semiconductor chip 110 from moving up and down in the area 101a during conveyance and reversal. Conventionally, the paper 120 is sandwiched between the stacked semiconductor chip storage trays 100.

  In the prior art described above, it is necessary to sandwich paper between the stacked semiconductor chip storage trays. For this reason, when the semiconductor chip is stored in the semiconductor chip storage tray, the cost of the paper itself and the operation cost for sandwiching the paper are required. Moreover, when taking out a semiconductor chip from a semiconductor chip storage tray, the operation | work cost for removing paper was required. Therefore, the cost for transporting the semiconductor chip is high.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor chip storage tray and a semiconductor chip transport method that can reduce the cost of transporting semiconductor chips as compared with the prior art. There is.

In order to solve the above problems, a semiconductor chip storage tray according to the present invention is a semiconductor chip storage tray that is used by stacking a plurality of stacks,
A base plate,
An upper surface rib provided on the upper surface of the base plate and partially provided along a boundary of the area to divide the space on the base plate into a plurality of areas;
A lower surface rib that is provided on the lower surface of the base plate, divides the space under the base plate, and fits into the upper surface rib when a plurality of the semiconductor chip storage trays are stacked.

According to this semiconductor chip storage tray, when a plurality of the semiconductor chip storage trays are stacked, the lower surface rib fits into the upper surface rib, so the distance between the upper base plate and the lower base plate is Smaller than that. For this reason, it is possible to suppress the semiconductor chip from moving up and down within the area without interposing paper. Therefore, the cost for transporting the semiconductor chip can be reduced.
In addition, it is preferable that the lower surface rib is disposed at a position not overlapping the upper surface rib in a planar positional relationship, and the height of the lower surface rib is substantially the same as the height of the upper surface rib.

  When the planar shape of the area is substantially rectangular, it is preferable that each of the upper surface rib and the lower surface rib is provided along each of the four sides of the area. If it does in this way, when the semiconductor chip is accommodated in the area and when the semiconductor chip accommodation tray is turned upside down and taken out from the area, it is possible to suppress the rotation of the semiconductor chip.

  One of the upper surface rib and the lower surface rib is, for example, an L-shaped, T-shaped, or cross-shaped rib provided at each of the four corners of the area, and the other of the upper surface rib and the lower surface rib is, for example, It is a linear rib provided at substantially the center of each of the four sides of the area.

Another semiconductor chip storage tray according to the present invention is a semiconductor chip storage tray used by stacking a plurality of,
A base plate,
A plurality of upper surface pin members provided along the boundary of the area, in order to divide the space on the base plate into a plurality of areas, provided on the upper surface of the base plate;
A plurality of lower surface pin members which are provided on the lower surface of the base plate, divide a space under the base plate, and which do not overlap the upper surface pin member when a plurality of the semiconductor chip receiving trays are stacked; .

Preferably, the height of the upper surface pin member is substantially the same as the height of the lower surface pin member.
When the planar shape of the area is substantially rectangular, the upper surface pin member and the lower surface pin member are preferably disposed on each of the four sides of the area. In this case, one of the upper surface pin member and the lower surface pin member is provided, for example, in the vicinity of each of the four corners of the area, and the other of the upper surface pin member and the lower surface pin member is, for example, four sides of the area. It is provided in each central part.

A method for transporting a semiconductor chip according to the present invention includes:
A base plate,
An upper surface rib provided on the upper surface of the base plate and partially provided along a boundary of the area to divide the space on the base plate into a plurality of areas;
A lower surface rib that is provided on the lower surface of the base plate, divides the space under the base plate, and fits into the upper surface rib when a plurality of the semiconductor chip storage trays are stacked;
Preparing a plurality of semiconductor chip storage trays,
In each of the plurality of areas of each of the plurality of semiconductor chip storage trays, a semiconductor chip is stored with the upper surface facing upward,
Stacking the plurality of semiconductor chip storage trays containing the semiconductor chips, transporting the plurality of semiconductor chip storage trays in a stacked state,
After reversing the top and bottom of the plurality of semiconductor chip storage trays in a stacked state, the plurality of semiconductor chips are placed with the bottom surface facing upward while removing each of the plurality of semiconductor chip storage trays. It is taken out from each storage tray.

Another method for transporting semiconductor chips according to the present invention is as follows.
A base plate,
A plurality of upper surface pin members provided along the boundary of the area, in order to divide the space on the base plate into a plurality of areas, provided on the upper surface of the base plate;
A plurality of lower surface pin members which are provided on the lower surface of the base plate, divide the space under the base plate, and are not overlapped with the upper surface pin member when a plurality of the semiconductor chip accommodation trays are stacked;
Preparing a plurality of semiconductor chip storage trays,
In each of the plurality of semiconductor chip storage trays, a plurality of semiconductor chips are stored in a state where the upper surface faces upward,
Stacking the plurality of semiconductor chip storage trays, transporting the plurality of semiconductor chip storage trays together with the plurality of semiconductor chips in a stacked state;
After reversing the top and bottom of the plurality of semiconductor chip storage trays in a stacked state, the plurality of semiconductor chips are placed with the bottom surface facing upward while removing each of the plurality of semiconductor chip storage trays. It is taken out from each storage tray.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a view of the semiconductor chip storage tray 1 according to the first embodiment of the present invention as viewed obliquely from above, and FIG. 2 is a view of the semiconductor chip storage tray 1 as viewed from diagonally below. The semiconductor chip storage tray 1 is provided with an upper surface rib 2 on the upper surface of a substantially square base plate 1a and a lower surface rib 3 on the lower surface of the base plate 1a. On the upper surface of the semiconductor chip storage tray 1, a plurality of areas 1b for storing semiconductor chips are provided in a matrix. The planar shape of the area 1b is substantially rectangular, but the upper surface rib 2 and the lower surface rib 3 are partially provided along the boundary between the areas 1b so as not to overlap each other.
The semiconductor chip storage tray 1 is made of, for example, a plastic resin such as polystyrene, and is manufactured by injection molding using a mold.

  In the present embodiment, the upper surface rib 2 is linear and is disposed at substantially the center of each of the four sides of the area 1b. The lower surface rib 3 has a cross shape, an L shape, or a T shape, and is disposed at each of the four corners of the area 1b.

  A plurality of semiconductor chip storage trays 1 are stacked after storing semiconductor chips in each of the plurality of areas 1b. Since the upper surface rib 2 is disposed on each of the four sides of the area 1b, the semiconductor chip is prevented from rotating in the area 1b. Thereafter, a plurality of semiconductor chip storage trays 1 are conveyed in a stacked state.

  In a state where a plurality of semiconductor chip storage trays 1 are stacked, the upper surface rib 2 of the lower semiconductor chip storage tray 1 fits into the gap between the lower surface ribs 3 of the upper semiconductor chip storage tray 1. Further, the lower rib 3 on the upper stage side fits into the gap between the upper surface rib 2 on the lower stage side. In this manner, the upper-side rib 2 on the lower stage side and the lower-surface rib 2 on the upper stage side mesh with each other, and surround the boundary between the areas 1b with almost no gap. Thereby, the semiconductor chip accommodated in the area 1b is prevented from moving to the adjacent area 1b during transportation.

  The plurality of semiconductor chip storage trays 1 are turned upside down while being stacked at the transport destination. Thereby, a semiconductor chip can be taken out from the semiconductor chip storage tray 1 with the back surface facing upward. Since the lower surface ribs 3 are arranged on each of the four sides of the area 1b, the semiconductor chip is prevented from rotating in the area 1b when taken out.

  FIG. 3 is a cross-sectional view for explaining a state in use of the semiconductor chip storage tray 1. As described above, a plurality of semiconductor chip storage trays 1 are stacked during use. The heights of the upper surface rib 2 and the lower surface rib 3 are substantially the same, and the upper surface rib 2 and the lower surface rib 3 are arranged so as not to overlap each other in a planar arrangement. For this reason, the distance between the upper base plate 1a and the lower base plate 1a is equal to the height of the upper surface rib 2 and is smaller (for example, half) than in the prior art. Therefore, it is possible to suppress the semiconductor chip 10 from moving up and down in the area 1b during conveyance and reversal without using paper.

  As described above, according to the first embodiment of the present invention, the upper surface rib 2 provided on the upper surface of the semiconductor chip storage tray 1 and the lower surface rib 3 provided on the lower surface are respectively arranged along the boundary between the areas 1b. They are arranged so as not to overlap each other. For this reason, when a plurality of semiconductor chip storage trays 1 are stacked, the distance between the upper base plate 1a and the lower base plate 1a is equal to the height of the upper surface rib 2 and is smaller than the conventional one.

  Therefore, it is possible to suppress the semiconductor chip 10 from moving up and down in the area 1b during conveyance and reversal without using paper. For this reason, the conveyance cost of a semiconductor chip can be lowered.

  FIG. 4 is a view of the semiconductor chip storage tray 1 according to the second embodiment of the present invention as viewed obliquely from above, and FIG. 5 is a view of the semiconductor chip storage tray 1 shown in FIG. 4 as viewed from obliquely below. It is. The semiconductor chip storage tray 1 according to this embodiment is the first except that it has an upper surface pin 2a instead of the upper surface rib 2 and a lower surface rib 3a instead of the lower surface rib 3. This is the same configuration as the semiconductor chip storage tray 1 according to the embodiment. The method for using the semiconductor chip storage tray 1 according to the present embodiment is also the same as the method for using the semiconductor chip storage tray 1 according to the first embodiment. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

Each of the upper surface pin 2a and the lower surface pin 3a is disposed on each of the four sides of the area 1b so as not to overlap each other. A plurality of (for example, two) upper surface pins 2a are arranged at substantially the center of each of the four sides of the area 1b. The lower surface pins 3a are arranged in the vicinity of the four corners of the area 1b so as to sandwich the corners.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in 1st Embodiment, you may change arrangement | positioning of the upper surface rib 2 and the lower surface rib 3 in the range which does not mutually overlap. In this case, it is preferable that the upper surface rib 2 and the lower surface rib 3 are positioned on each of the four sides of the area 1b. In the second embodiment, the arrangement of the upper surface pins 2a and the lower surface pins 3a may be changed within a range that does not overlap each other.

The figure which looked at the semiconductor chip accommodation tray 1 which concerns on 1st Embodiment from diagonally upward. The figure which looked at the semiconductor chip accommodation tray 1 from diagonally downward. Sectional drawing for demonstrating the state at the time of use of the semiconductor chip accommodation tray. The figure which looked at the semiconductor chip accommodation tray 1 which concerns on 2nd Embodiment from diagonally upward. The figure which looked at the semiconductor chip accommodation tray 1 shown in FIG. 4 from diagonally downward. The perspective view explaining the structure and usage method of the conventional semiconductor chip storage tray 100. FIG. Sectional drawing at the time of use of the semiconductor chip accommodation tray 100. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,100 ... Semiconductor chip accommodation tray, 1a, 101a ... Base board, 1b ... Area, 2,102 ... Upper surface rib, 2a ... Upper surface pin, 3,103 ... Lower surface rib, 3a ... Lower surface pin, 10, 110 ... Semiconductor chip 120 ... paper

Claims (4)

A semiconductor chip storage tray used by stacking a plurality of stacks,
A base plate,
A plurality of upper surface pin members provided along the boundary of the area, in order to divide the space on the base plate into a plurality of areas, provided on the upper surface of the base plate;
A plurality of lower surface pin members which are provided on the lower surface of the base plate, divide the space under the base plate, and are not overlapped with the upper surface pin member when a plurality of the semiconductor chip accommodation trays are stacked;
A semiconductor chip storage tray. The semiconductor chip storage tray according to claim 1 , wherein a height of the upper surface pin member is the same as a height of the lower surface pin member. The planar shape of the area is a rectangle ,
The semiconductor chip storage tray according to claim 1 , wherein each of the upper surface pin member and the lower surface pin member is disposed on each of four sides of the area. A base plate,
A plurality of upper surface pin members provided along the boundary of the area, in order to divide the space on the base plate into a plurality of areas, provided on the upper surface of the base plate;
A plurality of lower surface pin members which are provided on the lower surface of the base plate, divide the space under the base plate, and are not overlapped with the upper surface pin member when a plurality of the semiconductor chip accommodation trays are stacked;
Preparing a plurality of semiconductor chip storage trays,
In each of the plurality of semiconductor chip storage trays, a plurality of semiconductor chips are stored in a state where the upper surface faces upward,
Stacking the plurality of semiconductor chip storage trays, transporting the plurality of semiconductor chip storage trays together with the plurality of semiconductor chips in a stacked state;
After reversing the top and bottom of the plurality of semiconductor chip storage trays in a stacked state, the plurality of semiconductor chips are placed with the bottom surface facing upward while removing each of the plurality of semiconductor chip storage trays. A method of transporting semiconductor chips, which is taken out from each storage tray.

Images