JP4678100B2 - Three-phase AC-DC power converter - Google Patents

Description

ここで、max （Ｉrs、Ｉst、Ｉtr）はＩrs、Ｉst、Ｉtrの内の最大を示し、min （Ｉrs、Ｉst、Ｉtr）はＩrs、Ｉst、Ｉtrの内の最小を示す。
【００７１】
補正用の第１、第２及び第３の減算器７５、７６、７７は、第１、第２及び第３の乗算器４３、４４、４５と第１、第２及び第３の除算器４７、４８、４９との間に接続され、第１、第２及び第３の電流指令値Ｉrs、Ｉst、Ｉtrから補正値演算器７４で求めた補正値ΔＩを次式に示すように減算して補正電流指令値Ｉrs′、Ｉst′、Ｉtr′を出力する。
Ｉrs′＝Ｉrs−ΔＩ
Ｉst′＝Ｉst−ΔＩ
Ｉtr′＝Ｉtr−ΔＩ ・・・ （８）
なお、補正値演算器７４から負の極性の補正値−ΔＩが出力される場合には、第１、第２及び第３の減算器７５、７６、７７を加算器に置き換えることができる。
【００７２】
図１６は図１４の各部の状態を示す。第１、第２及び第３の乗算器４３、４４、４５から得られた図１６（Ｂ）の第１、第２及び第３の電流指令値Ｉrs、Ｉst、Ｉtrは、図１６（Ｃ）の補正値ΔＩで補正され、第１、第２及び第３の減算器７５、７６、７７から図１６（Ｄ）に示す補正電流値Ｉrs′、Ｉst′、Ｉtr′が得られる。
絶対値回路５０、５１、５２からは図１６（Ｄ）の補正電流指令値Ｉrs′、Ｉst′、Ｉtr′の絶対値に相当する第１、第２及び第３の通電率指令信号Ｄrs、Ｄst、Ｄtrが図１６（Ｅ）に示すように得られる。タイミング信号演算器５３は、前述した式（２）によって第１の実施形態と同様に第１〜第６のタイミング信号Ｇa1〜Ｇｃ２ を求める。第１〜第６のタイミング信号Ｇa１〜Ｇc２ は第１の実施形態と同一の制御信号形成回路５５で鋸波Ｖｔと比較され、第１の実施形態と同一の方法で第１、第２及び第３の制御信号Ｖga、Ｖgb、Ｖgcが形成される。
【００７３】
ΔＩの補正を加えることによって第１、第２及び第３の導通率指令信号Ｄrs、Ｄst、Ｄtrを図１６（Ｅ）のように形成すると、図１６（Ｅ）の第１の通電率指令値ＤrsがＲ相電圧を基準にして０〜６０度及び１８０〜２４０度の区間で零になると、第１の制御信号Ｖgaが零に保たれ、第１及び第２のスイッチＳ1、Ｓ2がオフに保たれる。
第３の通電率指令値Ｄtrが６０〜１２０度及び２４０〜３００度の区間で零になると、第３の制御信号Ｖgｃが零に保たれ、第５及び第６のスイッチＳ5、Ｓ6がオフに保たれる。
第２の通電率指令値Ｄstが１２０〜１８０度及び３００〜３６０度で零になると、第２の制御信号Ｖgｂが零に保たれ、第３及び第４のスイッチＳ3、Ｓ4がオフに保たれる。
制御信号が零に保たれている区間では第１〜第６のスイッチＳ1〜Ｓ6のオン・オフ動作が中断するので、第１〜第６のスイッチＳ1〜Ｓ6 の単位時間当りのスイッチング回数が低減し、スイッチング損失が少なくなり、効率が向上する。
【００７４】
【第７の実施形態】
図１７は第７の実施形態の制御回路５ｆを示す。図１７の制御回路５ｆは図３の制御回路５に補正用演算器７４′と補正用の第１、第２及び第３の減算器７５′、７６′、７７′とを付加し、この他は図３と同様に構成したものである。補正用演算器７４′は図１５の補正用演算器７４と同一の目的のものであって、ライン６ａ、７ａ、８ａの線間電圧Ｖrs、Ｖst、Ｖtrに基づいて補正信号を形成する。第１、第２及び第３の減算器７５′、７６′、７７′はライン６ａ、７ａ、８ａと乗算器４３、４４、４５との間に接続され、第１、第２及び第３の線間電圧Ｖrs、Ｖst、Ｖtrから補正用演算器７４′の補正値を減算する。減算器７５′、７６′、７７′による補正は、図１７の電流指令値Ｉrs、Ｉst、Ｉtrが図１６（Ｄ）の補正電流指令値Ｉrs′、Ｉst′、Ｉtr′と同一になるように行う。これにより、第７の実施形態によっても第６の実施形態と同一の効果を得ることができる。
【００７５】
【第８の実施形態】
次に第８の実施形態を図１８を参照して説明する。
トランス２には、第１及び第２のスイッチS1、Ｓ2 のオン期間に電圧Ｖrs、第３及び第４のスイッチＳ3、Ｓ4 のオン期間にＶst、第５及び第６のスイッチＳ5、Ｓ6のオン期間にＶtrが印加され、第１〜第６のスイッチＳ1〜Ｓ6のいずれもオフの時には０の端子電圧が印加される。鋸波Ｖt の一周期内にトランス２にかかる端子電圧の平均は次式になる。
トランスの端子電圧の平均＝Ｖrs×Ｄrs＋Ｖst×Ｄst＋Ｖtr×Ｄtr・・・ （９）
【００７６】
（９）式を零と置き、（１）式及び（２）式を用いて補正値ΔＩについて解くと、補正値ΔＩは次の（１０）式のようになる。
Ｉrs×Ｉst×Ｉtr≧０又はＶrs×Ｖst×Ｖtr≧０の時、

Ｉrs×Ｉst×Ｉtr＜０又はＶrs×Ｖst×Ｖtr＜０の時、

【００７７】
図１８は（１０）式に従う動作を図１６と同様に示す。図１８（Ｃ）の補正値ΔＩに基づいて補正電流指令値Ｉrs′、Ｉst′、Ｉtr′が図１８（Ｄ）に示すように変化すると、第１、第２及び第３の通電率指令値Ｄrs、Ｄst、Ｄtrは図１８（Ｅ）に示すように変化する。第１〜第６のタイミング信号Ｇa1〜Ｇc2は（２）式によって決定される。
【００７８】
第８の実施形態によれば、上述から明らかなようにトランスの平均端子電圧を零にすることができる。従って、トランスの励磁電流の増加が防止され、トランス２が飽和しにくくなる。
なお、第６、第７及び第８の実施形態と同一の補正を第２〜第７の実施形態にも適用することができる．
【００７９】
【第９の実施形態】
図１９は第９の実施形態の直流−交流変換装置は、図１の電流検出器１０を省き、この代りに第１、第２及び第３相の変換回路の入力ライン１４、１６、１８に直列に第１、第２及び第３の電流検出器９７ａ、９７ｂ、９７ｃを接続し、この検出値Ｉa 、Ｉb 、Ｉc を制御回路５ｇに送るように構成し、この他は図１と同一に構成したものである。
【００８０】
制御回路５ｇは、図２０に示すように図３の制御回路５の除算器４７、４８、４９を減算器４７′、４８′、４９′に変え、図１９の第１、第２及び第３の電流検出器９７ａ、９７ｂ、９７ｃの検出電流Ｉa 、Ｉb 、Ｉc をフィルタ９８ａ、９８ｂ、９８ｃを介して減算器４７′、４８′、４９′に入力させ、この他は図３と同一に構成したものである。
第１、第２及び第３の減算器４７′、４８′、４９′からは、第１、第２及び第３の電流指令値Ｉrs、Ｉst、Ｉtrと第１、第２及び第３の検出電流値Ｉa 、Ｉb 、Ｉc との差ΔＩrs、ΔＩst、ΔＩtrが得られ、これに基づいて増幅器５０、５１，５２は第１、第２及び第３の通電率指令値Ｄrs、Ｄst、Ｄtrを形成する。
【００８１】
第９の実施形態によれば、第１の実施形態と同一の効果を得ることができる他に、各線間電流Ｉa 、Ｉb 、Ｉc を検出してフィードバックしているので、制御応答の改善効果が得られる。
【００８２】
【第１０の実施形態】
第１〜第９の実施形態の第１、第２及び第３の双方向スイッチＱa 、Ｑb 、Ｑc を図２１に示すように構成することができる。
図２１の双方向スイッチＱa 、Ｑb 又はＱc は、ＦＥＴから成る第１、第２、第３及び第４のスイッチＱ1 、Ｑ2 、Ｑ3 、Ｑ4 と第１、第２、第３及び第４のダイオードＤ1 、Ｄ2 、Ｄ3 、Ｄ4 と、コンデンサＣとから成り、ライン１４、１６又は１８に直列に接続されている。第１及び第２のスイッチＱ1 、Ｑ2 は互いに逆の方向性を有して端子Ｐ1 と端子Ｐ2 との間に接続されている。第３及び第４のスイッチＱ3 、Ｑ4 は互いに逆の方向性を有して端子Ｐ1 と端子Ｐ2 との間に接続されている。第３及び第４のスイッチＱ3 、Ｑ4 は第１及び第２のスイッチＱ1 、Ｑ2 に対して逆の方向性を有している。第１、第２、第３及び第４のダイオードＤ1 、Ｄ2 、Ｄ3 、Ｄ4 は第１、第２、第３及び第４のスイッチＱ1 、Ｑ2 、Ｑ3 、Ｑ4 に逆方向並列に接続されている。コンデンサＣは第１及び第２のスイッチＱ1 、Ｑ2 の相互接続点Ｐ3 と第３及び第４のスイッチＱ3 、Ｑ4 の相互接続点Ｐ4 との間に接続されている。第２の端子Ｐ2 は１次巻線Ｎ1a、Ｎ1b又はＮ1cに接続される。
【００８３】
図２１の双方向スイッチＱa 、Ｑb 又はＱc に図で上から下に向かう第１の方向（正方向）の電流を流す時には、第１及び第４のスイッチＱ1 、Ｑ4 にオン制御信号を与え、第２及び第３のスイッチＱ2 、Ｑ3 はオフに保ち、第２の方向（負方向）の電流を流す時には第２及び第３のスイッチＱ2 、Ｑ3 にオン制御信号を与え、第１及び第４のスイッチＱ1 ，Ｑ4 はオフに保つ。第１の方向の電流は、第１のスイッチＱ1 と第２のダイオードＤ2 の経路と、第３のダイオードＤ3 と第４のスイッチＱ4 の経路との両方に流れる。第２の方向の電流は第２のスイッチＱ2 と第１のダイオードＤ1 の経路と、第４のダイオードＤ4 と第３のスイッチＱ3の経路との両方に流れる。
【００８４】
第１の方向の電流が流れている状態で第１及び第４のスイッチＱ1 、Ｑ4 をターンオフ制御した時には、コンデンサＣが第３のダイオードＤ3 を介して第１のスイッチＱ1 に並列に接続され、且つ第２のダイオードＤ2 を介して第４のスイッチＱ4 に並列に接続され、スナバコンデンサとして作用し、第１及び第４のスイッチＱ1 、Ｑ4 を過電圧から防止する。
また、第２の方向の電流が流れている状態で第２及び第３のスイッチＱ2 、Ｑ3 をターンオフ制御した時には、コンデンサＣが第４のダイオードＤ4 を介して第２のスイッチＱ2 に並列に接続され、且つ第１のダイオードＤ1 を介して第３のスイッチＱ3 に並列に接続され、スナバコンデンサとして作用し、第２及び第３のスイッチＱ2 、Ｑ3 を過電圧から防止する。コンデンサＣの電荷は双方向スイッチの導通時にトランス２を介して零まで放電する。
【００８５】
図２１の双方向スイッチＱa ，Ｑb 、Ｑc を使用すると、１つのコンデンサＣで４つのスイッチＱ1 〜Ｑ4 のスナバ効果を得ることができる。なお、第３及び第４のスイッチＱ3 、Ｑ4 と第３及び第４のダイオードＤ3 、Ｄ4 が追加されているが、主電流の通路として使用され、主電流は分割されて流れるので、図２に比べて第１〜第４のスイッチＱ1 〜Ｑ4 の電流容量を低減することができ、スイッチＱ3 、Ｑ4 が無駄にならない。
【００８６】
【第１１の実施形態】
図1及び図1９の第１、第2及び第３の双方向スイッチＱa、Ｑb、Ｑcを正方向スイッチ手段と逆方向スイッチ手段との巻線の一方の側と他方の側とに分けて配置して構成することができる。図１の第１の双方向スイッチＱaの変形を示す図２２では、図１と同一の第１の１次巻線Ｎ1aの一方の側に第1のスイッチ手段Ｑa1が接続され、他方の側に第2のスイッチ手段Ｑa2が接続され、第1及び第2のスイッチ手段Ｑa1、Ｑa2の組み合わせによって図1の第1の双方向スイッチＱaと同一のスイッチングを達成している。
【００８７】
第１のスイッチ手段Ｑａ1は制御可能な半導体スイッチ（例えばFET又はトタンジスタ又はIGBT）から成る第１のスイッチＳ1とこの第１のスイッチＳ1に逆方向並列に接続された第１のダイオードＤ1とから成る。第１のスイッチＳ1の第１の主端子（ソース又はエミッタ）はＲ相ライン１４に接続されている。第１のスイッチＳ1の第２の主端子（ドレイン又はコレクタ）は交流負荷としての第１の１次巻線Ｎ1ａの一端に接続されている。第１のダイオードＤ1は第１の１次巻線Ｎ1ａにＲ相ライン１４側からＳ相ライン１５に向う第１の方向の電流を流すことができる方向性を有して第１のスイッチＳ1に並列に接続されている。この第１のダイオードＤ1は個別ダイオードであってもよいし、ＦＥＴ、トランジスタ、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）等から成る第１のスイッチＳ1のボディダイオード又は寄生ダイオードと呼ばれる内蔵ダイオードであってもよい。第１のスイッチＳ1をオン・オフ制御するための第１の駆動回路３１はＲ相ライン１４即ち第１のスイッチＳ1の第１の主端子と第１のスイッチＳ1の制御端子との間に接続されている。第１の駆動回路３１はライン２５の第１の制御信号Ｖｇａに応答して第１のスイッチＳ1をオン・オフ制御する。
【００８８】
第２のスイッチ手段Ｑａ2は制御可能な半導体スイッチから成る第２のスイッチＳ2とこの第２のスイッチＳ2に逆方向並列に接続された第２のダイオードＤ2とから成る。第２のスイッチＳ2の第１の主端子（ソース又はエミッタ）はＳ相ライン１５に接続されている。第２のスイッチＳ2の第２の主端子（ドレイン又はコレクタ）は第１の１次巻線Ｎ1ａの他端に接続されている。第２のダイオードＤ2は第１の１次巻線Ｎ1ａにＳ相ライン１５側からＲ相ライン１４に向う第２の方向の電流を流すことができる方向性を有して第２のスイッチＳ2に並列に接続されている。この第２のダイオードＤ2は個別ダイオードであってもよいし、ＦＥＴ、トランジスタ、ＩＧＢＴ等から成る第２のスイッチＳ2のボディダイオード又は寄生ダイオードと呼ばれる内蔵ダイオードであってもよい。第２のスイッチＳ2をオン・オフ制御するための第２の駆動回路３２はＳ相ライン１５即ち第２のスイッチＳ2の第１の主端子と第２のスイッチS2の制御端子との間に接続されている。第２の駆動回路３２はライン２５の第１の制御信号Ｖｇａに応答して第２のスイッチＳ2をオン・オフ制御する。
【００８９】
図1の第2及び第3の双方向スイッチＱb、Ｑcに相当するものは図２２に示されていないが、図２２の第1及び第2のスイッチ手段Ｑa1、Ｑa2と同様に形成される。
【００９０】
図２２においては、第1及び第2のスイッチＳ1、Ｓ2の第1の主端子としてのソースが電源ライン１４、１５に接続されているので、ソースの電位が電源ライン１４、１５の電位になり、1次巻線Ｎa1の電圧が急変してもソース・ゲート間電圧の変化がさほど発生せず、第1及び第2のスイッチＳ1、Ｓ2を安定的に制御することができる。
なお、図2２の第１１の実施形態において、双方向スイッチ以外は図1と同一であるので、第1の実施形態と同一の効果も得ることができる。
【００９１】
【第１２の実施形態】
図２３に示す第1２の実施形態の電力変換装置は、図1の過電圧防止回路１００を変形した過電圧防止回路１００ａを設け、この他は図１と同一に構成したものである。従って、図２３において図１と実質的に同一の部分には同一の符号を付してその説明を省略する。図２３の過電圧検出回路１００ａは、図１の過電圧検出回路１００に第１及び第２のダイオードＤ11、Ｄ12を付加し、この他は図１と同様に形成したものである。第１のダイオードＤ11は２次巻線Ｎ2の一端と過電圧抑制用スイッチＱ0のドレインとの間に接続され、第２のダイオードＤ12は２次巻線Ｎ2の他端と過電圧抑制用スイッチＱ0のドレインとの間に接続されている。従って、過電圧抑制用スイッチＱは第１及び第２のダイオードＤ11、Ｄ12を介して２次巻線Ｎ2の第１及び第２の部分Ｎ2a、Ｎ2bに並列に接続されている。第１のダイオードＤ11は２次巻線Ｎ2に第１の方向の電圧が発生したときに導通する方向性を有し、第２のダイオードＤ2は２次巻線Ｎ2に第１の方向と反対の第２の方向の電圧が発生した時に導通する方向性を有している。第１および第２のダイオードＤ11、Ｄ12は過電圧抑制用スイッチＱ0に対しては図１の第１および第２の整流素子２１、２２と同様に機能するので、図２３の第１２の実施形態によっても第１の実施形態と同一の効果を得ることができる。
【００９２】
【第１３の実施形態】
図２４に示す第１３の実施形態では、図２３のトランス２に３次巻線Ｎ3が設けられ、ここに図２３と同一の過電圧防止回路１００ａが接続されている。即ち、図２４では、過電圧防止回路１００ａが２次巻線Ｎ2に接続されないで、３次巻線Ｎ3 に接続されている。３次巻線Ｎ3は１次巻線Ｎ1a、Ｎ1b、Ｎ1c及び２次巻線Ｎ2に電磁結合されているので、３次巻線Ｎ3の第１及び第２の部分Ｎ3a、Ｎ3bに第１及び第２のダイオードＤ11、Ｄ12を介して過電圧抑制用スイッチＱ0を接続し、このスイッチＱ0をオン制御すれば、図１及び図２３と同様に過電圧を防止することができる。
【００９３】
【第１４の実施形態】
第１４の実施形態の電力変換装置は、図２５に示す変形された過電圧防止回路１００ｂを設けた他は図１と同一に形成したものである。図２５の過電圧防止回路１００ｂは、図１の過電圧防止回路１００における過電圧判定回路１０１を過電圧判定回路１０１ａに変形し、この他は図１と同一に形成したものである。図２５の過電圧判定回路１０１ａは、第１及び第２の整流素子２１、２２のカソードとセンタタップ２０との間に接続されたツエナーダイオードから成る定電圧ダイオードＺＤと抵抗Ｒ1との直列回路から成る。定電圧ダイオードＺＤと抵抗Ｒ1との相互接続点はスイッチＱ0のゲートに接続されている。従って、判定回路１０１ａの両端側の電圧が所定値よりも高くなると、定電圧ダイオードＺＤがオンになり、抵抗Ｒ1の電圧が高くなり、過電圧抑制用スイッチＱ0がオンになり、図１と同様に過電圧が抑制される。従って、図２５の第１４の実施形態によっても図１の第１の実施形態と同一の効果を得ることができる。
【００９４】
【第１５の実施形態】
第１５の実施形態の電力変換装置は、図２３の過電圧判定回路１０１を図２６に示すように変形した過電圧判定回路１０１ｂを設け、この他は図２３と同一に形成したものである。図２６の過電圧判定回路１０１ｂは、図２５と同様に定電圧ダイオードＺＤと抵抗Ｒ1との直列回路から成り、第１及び第２のダイオードＤ１1、Ｄ１2のカソードとセンタタップ２０との間に接続されている。定電圧ダイオードＺＤと抵抗Ｒ1との相互接続点はスイッチＱ0のゲートに接続されているので、過電圧時にスイッチＱ0がオンになる。従って、図２６の実施形態によっても図２２の第１２の実施形態と同一の効果を得ることができる。
【００９５】
【変形例】
本発明は上述の実施形態に限定されるものでなく、例えば次の変形が可能なものである。
（１） 図２の双方向スイッチＱa 、Ｑb 、Ｑc においては、第１のスイッチ３０ａ、３０ｂ、３０ｃと第２のスイッチ３１ａ、３１ｂ、３１ｃとの両方に同時に制御信号を供給しているが、交流電圧Ｖrs、Ｖst、Ｖtrの正の半波期間に第１のスイッチ３０ａ、３０ｂ、３０ｃに制御信号を供給し、負の半波期間に第２のスイッチ３１ａ、３１ｂ、３１ｃに制御信号を供給するように構成し、スイッチの制御損失を低減させることができる。また、図２２の第１のスイッチＳ1を交流の負の半波で制御し、第２のスイッチＳ2を正の半波で制御することができる。
（２） 双方向スイッチング素子Ｑa 、Ｑb 、Ｑc 及び図２２に示すスイッチＱａ1、Ｑａ2の構成を種々変形することができ、例えば、スイッチ３０ａ、３０ｂ、３０ｃ、３１ａ、３１ｂ、３１ｃ、Ｑ1 〜Ｑ4 、Ｓ1、Ｓ2をＩＧＢＴ、トランジスタ等の半導体スイッチング素子とすることができる。また、ダイオード３２ａ、３２ｂ、３２ｃ、３３ａ、３３ｂ、３３ｃ、Ｄ1 〜Ｄ4 をスイッチ３０ａ、３０ｂ、３０ｃ、３１ａ、３１ｂ、３１ｃ、Ｑ1 〜Ｑ4 、Ｓ1、Ｓ2の内蔵ダイオードとすることができる。
（３） 図２０の制御回路５ｇに第６〜第８の実施形態の機能を付加することができる。
（４） 第１〜第１５の実施形態において、それぞれの一部を他の実施形態に適用することができる。例えば、図２１の双方向スイッチＱa 、Ｑb 、Ｑc を第２〜第９の実施形態に適用することができる。また、図１９の過電圧防止回路１００を図２３、図２４、図２５、図２６の過電圧防止回路１００ａ、１００ｂ、１００ｃ等に変形することができる。
（５） 制御回路５〜５ｇの入力段にアナログ・ディジタル変換器（ＡＤＣ）を設け、制御回路をディジタル回路構成とすることができる。
（６）第4及び第5の実施形態では、
F＝１のときGａ≦Gｃ≦Gｂ、
F＝２のときGｂ≦Gａ≦Gｃ、
F＝３のときGｃ≦Gｂ≦Gａとしたが、その他は順番、例えば、
F＝１のときGｂ≦Gｃ≦Gａ、
F＝２のときGｃ≦Gａ≦Gｂ、
F＝３のときGａ≦Gｂ≦Gｃとしても同様な効果が得られる。
【図面の簡単な説明】
【図１】第１の実施形態の交流−直流電力変換装置を示す回路図である。
【図２】図１の第１、第２及び第３の双方向スイッチとトランスとを詳しく示す回路図である。
【図３】図１の制御回路を詳しく示す回路図である。
【図４】図３の制御信号形成回路を示す回路図である。
【図５】図３の各部の状態を示す波形図である。
【図６】第２の実施形態の制御回路を示す回路図である。
【図７】図６の制御信号形成回路を示す回路図である。
【図８】図６の各部の状態を示す波形図である。
【図９】第３の実施形態の制御回路を示す回路図である。
【図１０】図９の各部の状態を示す波形図である。
【図１１】第４の実施形態の制御回路を示す回路図である。
【図１２】図１１の制御信号形成回路を示す回路図である。
【図１３】第５の実施形態の制御回路を示す回路図である。
【図１４】図１３の各部の状態を示す波形図である。
【図１５】第６の実施形態の制御回路を示す回路図である。
【図１６】図１５の各部の状態を示す波形図である。
【図１７】第７の実施形態の制御回路を示す回路図である。
【図１８】第８の実施形態の制御回路の各部の状態を示す波形図である。
【図１９】第９の実施形態の交流−直流電力変換装置を示す回路図である。
【図２０】図１９の制御回路を詳しく示す回路図である。
【図２１】第１０の実施形態の交流−直流電力変換装置の双方向スイッチを示す回路図である。
【図２２】第１１の実施形態の電力変換装置の一部を示す回路図である。
【図２３】第１２の実施形態の電力変換装置を示す回路図である。
【図２４】第１３の実施形態の電力変換装置の一部を示す回路図である。
【図２５】第１４の実施形態の電力変換装置の一部を示す回路図である。
【図２６】第１５の実施形態の電力変換装置の一部を示す回路図である。
【符号の説明】
１ｒ、１ｓ、１ｔ ３相交流入力端子
２ トランス
３ 全波整流平滑回路
５〜５ｇ 制御回路
100、100ａ、100ｂ、100ｃ 過電圧防止回路
Ｑa 、Ｑb 、Ｑc 第１、第２及び第３の双方向スイッチ
Ｎ1a、Ｎ1b、Ｎ1c １次巻線
Ｎ2 ２次巻線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a three-phase AC-DC power converter that has a switching circuit and an insulating transformer and converts three-phase AC power into DC power.
[0002]
[Prior art]
When configuring an isolated rectifier for use in a battery-charger, etc., if an isolation transformer is provided on the commercial frequency side and a rectifier circuit and a PWM switching circuit for voltage adjustment are provided on the secondary side of the transformer, the transformer is large. Become. In order to solve this problem, a PWM rectifier, that is, an AC-DC converter is connected to a three-phase AC power source, a DC link capacitor is connected between the output terminals of this converter, and a transformer is connected to the output stage of the DC link capacitor. May be connected, and a rectifying / smoothing circuit may be provided at the output stage of the inverter. In this case, since the transformer is a high-frequency transformer with a small loss, the size can be reduced.
[0003]
[Problems to be solved by the invention]
However, converters, DC link capacitors, inverters, transformers, and rectifying / smoothing circuits are required, so parts other than the transformer become large, and losses occur in each circuit, making it difficult to increase overall efficiency. Become.
Moreover, in the power converter device which has a switching circuit, it is requested | required that the overvoltage which generate | occur | produces based on on / off of a switch should be suppressed.
[0004]
Therefore, a first object of the present invention is to reduce the size of a three-phase AC-DC power converter having an insulating transformer and a switching circuit. A second object of the present invention is to provide a three-phase AC-DC power converter that can be miniaturized and can suppress overvoltage.
[0005]
[Means for Solving the Problems]
In order to achieve the first object, the present invention provides first, second and third AC input terminals connected to a three-phase AC power source, the first AC input terminal and the second AC input. A first primary winding connected between the second AC input terminal, a second primary winding connected between the second AC input terminal and the third AC input terminal; A third primary winding connected between three AC input terminals and the first AC input terminal, and two electromagnetically coupled to the first, second and third primary windings, respectively. A current in a first direction is supplied to the next winding and the first primary winding by on / off control, and a current in a second direction opposite to the first direction is on / off controlled. A first bidirectional switch means for flowing, and a second direction opposite to the first direction while flowing the current in the first direction to the second primary winding by controlling on / off. Second bidirectional switch means for controlling the current in the direction to flow on / off, and flowing the current in the first direction in the third primary winding by controlling the on / off, and the first A third bidirectional switch means for flowing a current in a second direction opposite to the direction in an on / off control, a rectifying / smoothing circuit connected to the secondary winding, the first, second and First, second, and third control signals for on / off control of the third bidirectional switch means at a frequency higher than the frequency of the AC voltage of the three-phase AC power supply are formed to form the first, second, To the second and third bidirectional switch means, and the first, second and second second switch means have a period in which all of the first, second and third bidirectional switch means are simultaneously turned off. And a power converter comprising a control circuit for forming a third control signal. That.
[0006]
In order to achieve the second object, as described in claim 2, overvoltage determination means for determining whether the voltage of the secondary winding is an overvoltage or a risk of overvoltage. It is desirable to provide overvoltage suppression switch means for short-circuiting the secondary winding when an output indicating that there is an overvoltage or a possibility of overvoltage is obtained from the determination means.
Further, in order to achieve the second object, as shown in claim 3, a tertiary coupled electromagnetically to the first, second and third primary windings and the secondary winding is further provided. Windings,
An overvoltage determination means for determining that the secondary winding or the tertiary winding is overvoltage or likely to become an overvoltage, and that the overvoltage determination means indicates that there is an overvoltage or an overvoltage risk. When the output is obtained, an overvoltage suppressing switch means for short-circuiting the tertiary winding can be provided.
According to a fourth aspect of the present invention, the overvoltage determination means detects a period in which the first, second and third bidirectional switch means are simultaneously turned off as a period in which there is a possibility of overvoltage. Is desirable.
According to a fifth aspect of the present invention, the secondary winding has a center tap, and the rectifying and smoothing circuit includes a first rectifying element connected to one end of the secondary winding, and the 2 A second rectifying element connected to the other end of the next winding, and a smoothing circuit connected to an interconnection point of the output terminals of the first and second rectifying elements and the center tap. The suppression switch means is controllable connected between the interconnection point of the output terminals of the first and second rectifying elements and the center tap and configured to respond to the output of the overvoltage determination means A switch is desirable.
According to a sixth aspect of the present invention, the secondary winding has a center tap, and the rectifying and smoothing circuit includes a first rectifying element connected to one end of the secondary winding, and the 2 A second rectifying element connected to the other end of the next winding, and a smoothing circuit connected to an interconnection point of the output terminals of the first and second rectifying elements and the center tap. The suppression switch means includes a first overvoltage suppression diode connected to one end of the secondary winding, a second overvoltage suppression diode connected to the other end of the secondary winding, and the first And a controllable switch connected between the interconnection point of the output terminals of the second overvoltage suppression diode and the center tap and configured to respond to the output of the overvoltage determination means.
[0007]
【The invention's effect】
According to the invention of each claim, three-phase AC-DC conversion can be performed only by intermittently alternating voltage with a bidirectional switch on the primary side of the transformer and rectifying and smoothing the output of the secondary winding. The configuration of the three-phase AC-DC power converter is simplified as a whole and the efficiency is improved. In addition, since a period for turning off all of the first, second and third bidirectional switch means at the same time is provided, the on / off control of the first, second and third bidirectional switch means is repeated a predetermined number of times. It is possible to adjust the on-time width of the first, second and third switch means for adjusting the voltage or current while performing with frequency. That is, a period in which all of the first, second, and third switch means are simultaneously turned off can be used as an absorption period for fluctuations in on-time width.
According to the inventions of claims 2 to 6, it is possible to easily suppress overvoltage that may or may occur during the period when the first, second and third bidirectional switch means are simultaneously turned off. it can.
[0008]
Embodiment
Next, embodiments of the present invention will be described with reference to the drawings.
[0009]
[First Embodiment]
The three-phase AC-DC power converter according to the first embodiment shown in FIG. 1 includes first, second, and third AC input terminals 1r, 1s, 1t, and first, second, and third capacitors Ca. , Cb, Cc, the first, second, and third bidirectional switches Qa, Qb, Qc, and the first, second, and third primary windings N1a, N1b, N1c of the transformer 2, Secondary winding N2, common magnetic core 2a, rectifying and smoothing circuit 3, paired DC output terminals 4a and 4b, common control circuit 5, and first, second and third input voltage detection circuits 6, 7, 8, output voltage detection circuit 9, current detector 10, reactors 11, 12, 13 for removing high frequency components, and overvoltage prevention circuit 100.
[0010]
The first, second, and third AC input terminals 1r, 1s, and 1t are used to input a three-phase sinusoidal AC R-phase, S-phase, and T-phase voltage of commercial frequency (50 Hz or 60 Hz).
[0011]
First, second, and third capacitors Ca, Cb, and Cc are AC capacitors for removing high-frequency components. The first capacitor Ca is connected to the first and second AC input terminals 1r and 1s via the input lines 14 and 15 and the reactors 11 and 12, and both ends of the first capacitor Ca are connected between the R phase and the S phase. 1 line voltage Vrs is supplied.
The second capacitor Cb is connected to the second and third AC input terminals 1s and 1t via the input lines 16 and 17 and the reactors 12 and 13, and the second capacitor Cb is connected between the S phase and the T phase at both ends. A line voltage Vst of 2 is supplied.
The third capacitor Cc is connected to the first and third AC input terminals 1r and 1t via the input lines 18 and 19 and the reactors 11 and 13, respectively. 3 line voltage Vtr is supplied.
[0012]
A series circuit of the first bidirectional switch Qa and the first primary winding N1a is connected between the R-phase and S-phase input lines 14 and 15 in the same manner as the first capacitor Ca. A series circuit of the second bidirectional switch Qb and the second primary winding N1b is connected between the S-phase and T-phase input lines 16 and 17 in the same manner as the second capacitor Cb. The series circuit of the third bidirectional switch Qc and the third primary winding N1c is connected between the T-phase and R-phase input lines 18 and 19 in the same manner as the third capacitor Cc. The first, second and third windings N1a, N1b and N1c are set to the same or substantially the same number of turns.
[0013]
The secondary winding N2 of the transformer 2 is electromagnetically coupled to the first, second and third primary windings N1a, N1b and N1c via the magnetic core 2a. The secondary winding N2 is divided by the center tap 20 into first and second portions N2a and N2b having the same number of turns.
[0014]
The common rectifying / smoothing circuit 3 includes first and second rectifying elements 21 and 22 made of a diode, a smoothing reactor 23, and a smoothing capacitor 24. The first rectifying element 21 is connected through a reactor 23 between one end of the secondary winding N2 and one terminal of the capacitor 24. The second rectifying element 22 is connected via a reactor 23 between the other end of the secondary winding N2 and one terminal of the capacitor 24. The center tap 20 of the secondary winding N2 is connected to the other end of the capacitor 24. Therefore, the rectifying / smoothing circuit 3 is a double-wave rectifying circuit. The first and second DC output terminals 4 a and 4 b connected to the capacitor 24 supply DC power to the load 4.
[0015]
The first input voltage detection circuit 6 is connected to the R-phase and S-phase input lines 14 and 15, and sends a signal indicating the line voltage Vrs between the R-phase and the S-phase to the line 6a. The second input voltage detection circuit 7 is connected to the S-phase and T-phase input lines 16 and 17, and sends a signal indicating the line voltage Vst between the S-phase and the T-phase to the line 7a. The third input voltage detection circuit 8 is connected to the T-phase and R-phase input lines 18 and 19, and sends a signal indicating a line voltage Vtr between the T-phase and the R-phase to the line 8a.
The output voltage detection circuit 9 is connected to the first and second DC output terminals 4a and 4b, and sends a detection signal indicating the DC output voltage Vo between the output terminals 4a and 4b to the line 9a. In order to simplify the description, the input voltage and the output voltage of each voltage detection circuit 6, 7, 8, 9 are represented by the same symbols Vrs, Vst, Vtr, Vo.
[0016]
A current detector 10 comprising a current transformer for control for improving the power factor of the AC input is connected in series to the smoothing reactor 23 and sends a signal indicating the reactor current Io to the line 10a. Here, both the input and the output of the current detector 10 for simplicity of description are indicated by the same symbol Io.
[0017]
The control circuit 5 to which the lines 6a, 7a, 8a, 9a, and 10a are connected controls the first, second, and third bidirectional switches Qa, Qb, and Qc based on the detection signals supplied from them. First, second and third control signals Vga, Vgb and Vgc for the first, second and third bidirectional switches Qa, Qb and Qc are controlled by lines 25, 26 and 27, respectively. Send to terminal.
[0018]
FIG. 2 shows in detail the first, second and third bidirectional switches Qa, Qb, Qc and the transformer 2 of FIG. A first for controlling both the first direction of the first, second and third primary windings N1a, N1b, N1c, i.e. the positive direction current and the opposite second direction, i.e. the negative direction current. Since the first, second and third bidirectional switches Qa, Qb and Qc as the second and third bidirectional switch means have the same circuit configuration, the same reference numerals are assigned to the same circuit elements. The first, second and third bidirectional switches Qa, Qb and Qc are distinguished by the subscripts a, b and c. Further, the configuration of the first bidirectional switch Qa will be described in detail, and the detailed description of the second and third bidirectional switches Qb and Qc will be omitted.
The first bidirectional switch Qa includes first and second switches 30a and 31a made of a field effect transistor, and first and second diodes 32a and 33a. The first and second switches 30a and 31a have opposite directions and are connected in series with each other, and are connected in series via the first primary winding N1a between the R-phase and S-phase input lines 14 and 15. It is connected to the. The first and second diodes 32a and 33a are connected in reverse parallel to the first and second switches 30a and 31a. The second and third bidirectional switches Qb and Qc are configured in the same manner as the first bidirectional switch Qa. Accordingly, the first, second and third bidirectional switches Qa, Qb and Qc are AC switches capable of flowing a current in the first direction and a current in the second direction opposite thereto.
[0019]
The first, second and third primary windings N1a, N1b, N1c and the common secondary winding N2 of the high-frequency transformer 2 are wound around a common core 2a, and each primary winding N1a, N1b, N1c and secondary winding N2 are isolated from each other.
[0020]
FIG. 3 shows the control circuit 5 of FIG. 1 in detail. The control circuit 5
(1) A function for controlling the output voltage Vo to be constant,
(2) Power factor improvement function,
(3) A function for selectively controlling the first, second and third bidirectional switches Qa, Qb and Qc.
Have
[0021]
In order to execute the constant voltage control, a reference voltage generator 40, a voltage fluctuation detection subtracter 41, and a current amplitude command calculator 42 are provided. The subtracter 41 subtracts the DC output voltage Vo of the line 9a from the reference voltage Vo1 of the reference voltage generator 40. Based on the output of the subtractor 41, the current amplitude command calculator 42 generates a current amplitude command value Io1 for making the output voltage Vo constant. The current command calculator 42 includes a proportional integration circuit and an amplifier. The current amplitude command value Io1 can also be called an output voltage control command value. In this embodiment, since the DC output voltage is achieved by current control on the AC side, Io1 is called a current amplitude command value.
[0022]
First, second and third multipliers 43, 44 and 45 are provided for controlling the first, second and third bidirectional switches Qa, Qb and Qc by the common current amplitude command value Io1. ing. The first, second, and third multipliers 43, 44, and 45 are provided between the first, second, and third lines composed of the sine wave shown in FIG. 5A supplied from the lines 6a, 7a, and 8a. The voltages Vrs, Vst, Vtr are multiplied by the current amplitude command value Io1, and the first, second, and third current command values Irs, Ist, Itr shown in FIG. 5B are output. The current command values Irs, Ist, Itr are three-phase AC signals corresponding to the target current command value for setting the output voltage Vo to the target value.
[0023]
A coefficient multiplier 46 connected to the line 10a of the current detection signal Io multiplies the current Io by a coefficient N2 / n1 (turn ratio) in order to convert the current Io into a current on the primary side of the transformer. The output current Io 'is obtained. Note that n1 represents the number of turns of the primary windings N1a, N1b and N1c, and N2 represents the number of turns of the first and second portions N2a and N2b of the secondary winding N2.
[0024]
The first, second, and third dividers 47, 48, and 49 are first, second, and third current command values Irs obtained from the first, second, and third multipliers 43, 44, and 45, respectively. , Ist, Itr are divided by the output Io ′ of the coefficient multiplier 46 to obtain first, second, and third current ratio command signals Drs, Dst, Dtr, which can also be referred to as conduction ratio signals. Is.
Drs = Irs / Io ′ = Irs / (Io × n2 / n1)
Dst = Ist / Io '= Ist / (Io * n2 / n1)
Dtr = Itr / Io '= Itr / (Io * n2 / n1) (1)
[0025]
The first, second and third absolute value circuits 50, 51 and 52 connected to the first, second and third dividers 47, 48 and 49 are the first and second absolute values obtained by the above equation (1). The absolute values of the second and third energization rate command values Drs, Dst, and Dtr are output. Here, in order to simplify the description, the input and output of the absolute value circuits 50, 51 and 52 are indicated by the same symbol.
[0026]
The timing signal calculator 53 connected to the absolute value circuits 50, 51, 52 is based on the first, second, and third energization rate command signals Drs, Dst, Dtr. First, second, third, fourth, fifth and sixth timing signals Ga1, Ga2, Gb1, Gb2, Gc1, for determining the timing of the on / off operation of the direction switches Qa, Qb, Qc, This circuit calculates Gc2. This timing signal calculator 53 is connected to the first, second, third, fourth, fifth and sixth lines 53a, 53a ', 53b, 53b', 53c, 53c 'shown in FIG. Second, third, fourth, fifth and sixth timing signals Ga1, Ga2, Gb1, Gb2, Gc1, Gc2 are output. The first timing signal Ga1 is used to determine the ON timing of the first bidirectional switch Qa. In this embodiment, the first timing signal Ga1 has a zero level value shown in FIG. The second timing signal Ga2 is used to determine the OFF timing of the first bidirectional switch Qa. The third timing signal Gb1 is used to determine the ON timing of the second bidirectional switch Qb. The fourth timing signal Gb2 is used to determine the OFF timing of the second bidirectional switch Qb. The fifth timing signal Gc1 is used to determine the ON timing of the third bidirectional switch Qc. The sixth timing signal Gc2 is used to determine the off timing of the third bidirectional switch Qc.
[0027]
The relationship between the first to sixth timing signals Ga1 to Gc2 in FIG. 3 and the first, second and third continuity command values Drs, Dst and Dtr input to the timing signal calculator 53 is as follows (2). As shown in the equation.
Ga1 = 0
Ga2 = Drs
Gc1 = Ga2 = Drs
Gc2 = Gc1 + Dtr = Drs + Dtr
Gb1 = Gc2 = Drs + Dtr
Gb2 = Gb1 + Dst = Drs + Dtr + Dst (2)
[0028]
The sawtooth wave generator 54 as a comparison wave or carrier generator has a sawtooth wave Vt for forming a PWM pulse as high as multiple times the frequency of the input AC voltages Vr, Vs, Vt as shown in FIG. It occurs at a frequency (for example, 20 to 150 kHz). The minimum value of the sawtooth wave Vt is set to zero, and the maximum value is set larger than the first, second, third, fourth, fifth and sixth timing signals Ga1, Ga2, Gb1, Gb2, Gc1, and Gc2. Has been. Note that the sawtooth wave generator 54 may be a triangular wave generator. Further, the sawtooth wave Vt can be a falling inclined sawtooth wave.
[0029]
The control signal forming circuit 55 of FIG. 3 connected to the timing signal calculator 53 by lines 53a, 53a ′, 53b, 53b ′, 53c, 53c ′ and to the sawtooth generator 54 by line 54a is shown in FIG. As shown in the figure, it comprises first, second, third, fourth, fifth and sixth comparators 81, 82, 83, 84, 85, 86 and a logic circuit 87. The positive input terminal of the first comparator 81 is connected to the line 53a of the first timing signal Ga1, and the negative input terminals of the second to sixth comparators 82 to 86 are connected to the second to sixth timing signals Ga2 to. The negative input terminal of the first comparator 81 and the positive input terminals of the second to sixth comparators 82 to 86 are connected to the lines 53a ′ to 53c ′ of Gc2, respectively, to the output line 54a of the sawtooth generator 54. It is connected. The first comparator 81 generates a pulse when the sawtooth wave Vt becomes zero, and the second to sixth comparators 82 to 86 have a high level when the sawtooth wave Vt becomes higher than the respective timing signals Ga2 to Gc2. Generate output.
[0030]
The logic circuit 87 includes first to sixth trigger circuits 88 to 93 and first, second and third RS flip-flops 94, 95 and 96. The first RS flip-flop 94 is set in response to the output of the first comparator 81 changing to a high level and reset in response to the output of the second comparator 82 changing to a high level. Then, the first control signal Vga shown in FIG. 5 (E) is formed and sent to the first bidirectional switch Qa.
The second RS flip-flop 95 is set in response to the output of the third comparator 83 being switched to a high level, and reset in response to the output of the fourth comparator 84 being switched to a high level. Then, the second control signal Vgb shown in FIG. 5G is formed and sent to the second bidirectional switch Qb.
The third RS flip-flop 96 is set in response to the output of the fifth comparator 85 switching to a high level and reset in response to the output of the sixth comparator 86 switching to a high level. Then, the third control signal Vgc shown in FIG. 5F is formed and sent to the third bidirectional switch Qc.
[0031]
The first, second and third control signals Vga, Vgb and Vgc on the lines 25, 26 and 27 are sent to the control terminals of the first, second and third bidirectional switches Qa, Qb and Qc in FIG. It is done. The first, second and third bidirectional switches Qa, Qb and Qc are turned on when the first, second and third control signals Vga, Vgb and Vgc are logic 1 (high level).
[0032]
The first, second and third bidirectional switches Qa, Qb and Qc are turned on / off by the first, second and third control signals Vga, Vgb and Vgc shown in FIGS. When OFF control is performed, the line voltages Vrs, Vst and Vtr are applied to the first, second and third primary windings N1a, N1b and N1c during these ON periods, and the transformer secondary winding N2 is applied. In the positive half-wave period of alternating current, the first rectifier element 21 is turned on, and in the negative half-wave period, the second rectifier element 22 is turned on, and the secondary winding N2 is turned on. The voltage is smoothed by the reactor 23 and the capacitor 24 and supplied to the load 4.
The first, second, and third bidirectional switches Qa, Qb, Qc are turned on at a high frequency in both the positive half-wave period and the negative half-wave period of the AC line voltages Vrs, Vst, Vtr. Since the full-wave rectifying / smoothing circuit 3 is connected to the secondary side of the transformer, the ripple is small in the output stage of the first and second rectifying elements 21 and 22 like the three-phase full-wave rectified waveform. An output can be obtained, and the ripple of the output voltage Vo of the capacitor 24 is also reduced.
[0033]
When the DC output voltage Vo becomes higher than the target value Vo1, for example, the output of the output voltage control subtracter 41 decreases, the current amplitude command value Io1 decreases, and as a result, the timing signals Ga1 to Gc2 also decrease, and the PWM pulse , The power supplied to the secondary side during the ON period of the first, second and third bidirectional switches Qa, Qb and Qc decreases, and the voltage Vo at the DC output terminals 4a and 4b becomes the target. Returned to value. When the output voltage Vo becomes lower than the target value Vo1, the operation is the reverse of that when the output voltage Vo becomes higher.
[0034]
In this embodiment, the pulse widths of the control signals Vga, Vgb, and Vgc are controlled based on the detection of the output current Io of the secondary winding N2. Since the control by the output current Io is executed according to the equation (1), the pulse widths of the control signals Vga, Vgb and Vgc change in proportion to the output current Io. Accordingly, the pulse widths of the control signals Vga, Vgb, and Vgc can be changed to correspond to the output current Io.
[0035]
The first, second and third current command values Irs, Ist, Itr are sine waves created based on the first, second and third line voltages Vrs, Vst, Vtr, The sixth timing signals Ga1 to Gc2 also change with periodicity based on three-phase alternating current. Therefore, the power factor at the first, second and third AC input terminals Ir, Is and It is improved.
[0036]
The overvoltage prevention circuit 100 shown in FIG. 1 comprises an overvoltage suppression switch Q0 comprising an FET as an overvoltage suppression switch means and a determination circuit 101 as an overvoltage determination means. The overvoltage prevention switch Q0 is connected between the interconnection point of the output ends (cathodes) of the first and second rectifying elements 21 and 22 and the center tap 20 of the secondary winding N2. That is, the overvoltage suppression switch Q0 is connected in parallel to the first and second secondary windings N2a and N2b via the first and second rectifier elements 21 and 22, respectively.
[0037]
The overvoltage determination circuit 101 detects an overvoltage state of each winding of the transformer 2 or a state that may become an overvoltage, and controls the overvoltage suppression switch Q0 to be turned on. The overvoltage determination circuit 101 in the embodiment of FIG. 1 includes a drive power supply 102, a switch 103, and a NOR gate 104 as an overvoltage determination logic circuit. A series circuit of the drive power source 102 and the switch 103 is connected between the control terminal, that is, the gate, and one main terminal, that is, the source, of the overvoltage suppressing switch Q0 composed of an N-channel insulated gate field effect transistor. The overvoltage suppression switch Q0 is turned on when the switch 103 is turned on. The drive power source 102 and the switch 103 can be considered as a part of the overvoltage suppression switch means together with the overvoltage suppression switch Q0.
[0038]
A three-input NOR gate 104 for determining overvoltage is connected to the first, second and third control signal lines 25, 26 and 27, and the first, second and third of the three lines 25, 26 and 27 are connected. When all of the control signals Vga, Vgb, and Vgc are at logic 0 or low level, a logic 1 or high level output is generated and applied to the control terminal of the switch 103. The first, second, and third control signals Vga, Vgb, and Vgc are sequentially generated as shown in, for example, ta to te in FIGS. 5 (E), (G), and (F). That is, in FIG. 5, the first control signal Vga is generated in the period ta to tb, the third control signal Vgc is generated in the period tb to tc, the second control signal Vgb is generated in the period tc to td, and the second control signal Vgb is generated in the period td to te. None of the first, second and third control signals Vga, Vgb and Vgc are generated. The NOR gate 104 of FIG. 1 generates a logic 1 or high level output voltage during the period td to te. Since the period td to te is an overvoltage generation period or a period in which overvoltage may occur, the output of the NOR gate 104 indicates the possibility of overvoltage or overvoltage generation.
[0039]
The output terminal of the NOR gate 104 is connected to the control terminal of the switch 103. Accordingly, the switch 103 is turned on when the output of the NOR gate 104 is logic 1 or high level, and the drive signal is applied between the gate and the source of the overvoltage suppression switch Q0 from the drive power supply 102, and the switch Q0 is turned on. .
[0040]
When any of the first, second and third bidirectional switches Qa, Qb and Qc is on, the terminal voltages of the capacitors Ca, Cb and Cc with respect to the primary windings N1a, N1b and N1c in the respective states. Is applied. At this time, a voltage having a turn ratio (N2a / N1 and N2b / N1) is applied between the terminals of the secondary windings N2a and N2b. At this time, the current of the reactor 23 is supplied from the first secondary winding N2a via the rectifier 21 when the terminal voltage of the secondary winding N2 is positive, and the terminal voltage of the secondary winding N2 is negative. Is supplied from the second secondary winding N2b via the rectifying element 22.
When all of the first, second and third bidirectional switches Qa, Qb and Qc are simultaneously turned off as shown in the period td to te in FIG. 5 without the overvoltage prevention circuit 100 according to the present invention. The current of the reactor 23 flows in both the direction from the first secondary winding N2a to the rectifying element 21 and the direction from the second secondary winding N2b to the rectifying element 22. Since the former and the latter are magnetically coupled, when the exciting current is ignored, the currents of the first and second secondary windings N2a and N2b have the same magnitude. Actually, there is a transformer excitation current (not shown), which is the difference between the former and latter currents.
However, when all the bidirectional switches are off and the light load, that is, the current of the reactor 23 is smaller than the excitation current of the transformer (not shown), the energization path for the excitation current is lost. For this reason, an excessive surge voltage is generated by the excitation current.
In the converter of FIG. 1 according to the present invention, since the overvoltage prevention circuit 100 is provided, the exciting current is switched even when all the bidirectional switches Qa, Qb, Qc are in the off state and no load is applied. Qo can be passed, and surge voltage caused by the excitation current can be prevented.
[0041]
This embodiment has the following advantages.
(1) In the conventional insulation type three-phase AC-DC converter, a converter circuit and an inverter circuit must be provided on the primary side of the insulation separation transformer, which inevitably increases in size. On the other hand, the apparatus of this embodiment is configured to provide first, second and third bidirectional switches Qa, Qb and Qc on the primary side of the transformer 2 and to control on / off thereof. Therefore, the number of switching elements is reduced, and the size and cost can be significantly reduced as compared with the conventional device.
(2) Since the number of conversion stages on the primary side of the transformer 2 is one, the loss is reduced compared to the conventional two-stage configuration, and the conversion efficiency can be improved.
(3) In the circuit of FIG. 1, since the primary side of the transformer 2 is a single stage, there is no need for a DC link capacitor provided between a conventional converter and an inverter, and the size and cost are reduced. Can be achieved.
(4) Since the first, second and third bidirectional switches Qa, Qb and Qc are on-controlled at different times, the power capacity of the secondary circuit of the transformer 2 can be suppressed. In addition, an output voltage Vo with less ripple can be obtained.
(5) Since a period in which all of the first, second and third bidirectional switches Qa, Qb and Qc are simultaneously turned off is provided, the first, second and third switches Qa, Qb and Qc are turned on. The time width can be adjusted to easily achieve output voltage control and power factor improvement.
(6) Since the overvoltage prevention circuit 100 is provided, it is possible to achieve overvoltage suppression when the first, second, and third bidirectional switches Qa, Qb, Qc are all turned off.
(7) The overvoltage of the first, second and third primary windings N1a, N1b and N1c can be prevented by the common overvoltage prevention circuit 100 on the secondary side, and the circuit configuration can be simplified.
(8) The overvoltage can be determined by the NOR gate 104, and the overvoltage determination can be performed quickly and reliably.
[0042]
[Second Embodiment]
Next, the three-phase AC-DC converter according to the second embodiment will be described with reference to FIGS. 6, 7 and 8. However, in the three-phase AC-DC converter of the second embodiment, the control circuit 5 shown in FIG. 3 of the first embodiment is transformed into the control circuit 5a shown in FIG. In the second embodiment, reference is also made to FIG. 1, FIG. 2 and FIG. 5, and the description of the parts common to the first embodiment is omitted.
[0043]
The control circuit 5a of the second embodiment of FIG. 6 includes a timing signal calculator 530 and a control signal forming circuit 550 obtained by modifying the timing signal calculator 53 and the control signal 55 in the control circuit 5 of FIG. Others are the same as in FIG.
[0044]
The modified timing signal calculator 530 of FIG. 6 is substantially the same as the timing signal calculator 53 of FIG. 3 except for the number of output lines. That is, the timing signal calculator 530 is connected to the second, third, fourth, fifth, and sixth timing signals Ga2, Gb1, Gb2, FIG. 3 by the first, second, and third lines 53a, 53b, and 53c. , Gc1, and Gc2, the first, second, and third timing signals Ga, Gb, and Gc including the same information are output. The first timing signal Ga is used to determine the turn-off timing of the first and second switches S1, S2 and the turn-on timing of the third and fourth switches S3, S4. The second timing signal Gb is used to determine the OFF timing of the third and fourth switches S3 and S4 and to determine the ON timing of the fifth and sixth switches S5 and S6. The third timing signal Gc is used to determine the OFF timing of the fifth and sixth switches S5 and S6. The first to third timing signals Ga, Gb and Gc and the first to sixth timing signals Ga1 to Gc2 in FIG. 3 have the following relationship.
Ga = Ga2 = Gc1
Gc = Gc2 = Gb1
Gb = Gb2
[0045]
The relationship between the first to third timing signals Ga to Gc of FIG. 6 and the first, second and third continuity command values Drs, Dst and Dtr input to the timing signal calculator 530 is as follows: As shown in the equation.
Ga = Drs
Gc = Drs + Dtr
Gb = Drs + Dst + Dtr (3)
In FIG. 5D, the first timing signal Ga is indicated by a solid line, the second timing signal Gb is indicated by a chain line, and the third timing signal Gc is indicated by a dotted line.
[0046]
A control signal forming circuit 550 connected to the timing signal calculator 530 and the sawtooth generator 54 forms first, second and third control signals Vga, Vgb and Vgc composed of PWM pulses. As shown in FIG. 7, the first, second and third comparators 56, 57 and 58 and the first, second and third control signals Vga and Vgb based on their outputs CP1, CP2 and CP3. , Vgc, and a logic circuit 59. Negative input terminals of the first, second, and third comparators 56, 57, and 58 are lines 53a and 53b that output the first, second, and third timing signals Ga, Gb, and Gc of the timing signal calculator 530, respectively. , 53c, respectively. The positive input terminals of the first, second and third comparators 56, 57 and 58 are connected to the output line 54 a of the sawtooth generator 54, respectively. In the first, second, and third comparators 56, 57, and 58, as shown in FIGS. 5D and 8A, the sawtooth wave Vt and the first, second, and third timing signals Ga are used. , Gb and Gc are compared, and first, second and third comparison outputs CP1, CP2 and CP3 shown in FIGS. 8B, 8C and 8D are obtained. That is, comparison outputs CP1, CP2, and CP3 are obtained in which the sawtooth wave Vt is at a high level during a period higher than the first, second, and third timing signals Ga, Gb, and Gc and is at a low level during a low period.
The logic circuit 59 includes a first NOT circuit 60, an exclusive OR gate 61, an AND gate 62, and a second NOT circuit 58a. The first NOT circuit 60 is connected to the first comparator 56. The first NOT circuit 60 inverts the first comparison output CP1 shown in FIG. 8B, and the first NOT circuit 60 shown in FIG. 5E and FIG. The control signal Vga is sent to the line 25. The exclusive OR gate 61 is connected to the first and second comparators 56 and 57, and the first and second comparison outputs CP1 and CP2 shown in FIGS. 8B and 8C are at different levels. The second control signal Vgb shown in FIG. The 3-input AND gate 62 is connected to the first and second comparators 56 and 57 and to the third comparator 58 via the second NOT circuit 58a, and FIG. The third and second comparison outputs CP1 and CP2 shown in (C) and the third comparison output CP3 in FIG. 8D and the third comparison output CP3 are all at a high level during the period from t2 to t3. The control signal Vgc is sent to the line 27. Note that the logic circuit 59 for forming the first, second, and third control signals Vga, Vgb, and Vgc is not limited to the circuit shown in FIG. 7, and logic elements other than the logic elements shown in FIG. It can also be configured using.
[0047]
The control signal forming circuit 550 generates a signal based on the sawtooth wave Vt and the first, second and third timing signals Ga, Gb and Gc shown in FIGS. ) (F) and the conditions for forming the first, second and third control signals shown in FIGS. 8E, 8G, 8F are as follows.
Vga is logical 1 (high level) when 0 ≦ Vt <Ga, and 0 (low level) otherwise.
Vgc is logical 1 when Ga ≦ Vt <Gc, and 0 otherwise.
Vgb is logical 1 when Gc ≦ Vt <Gb, and 0 otherwise.
As apparent from FIGS. 5E, 5G, and 8E, 8G, 8F, the logic of the first, second, and third control signals Vga, Vgb, and Vgc is 1 (high). It does not occur at the same time during the level) period, but occurs sequentially at different times.
[0048]
The first, second and third control signals Vga, Vgb and Vgc on the lines 25, 26 and 27 are sent to the control terminals of the first to sixth switches S1 to S6 in FIG. The first to sixth switches S1 to S6 are turned on when the first, second and third control signals Vga, Vgb and Vgc are logic 1 (high level).
[0049]
The first to third timing signals Ga, Gb, Gc output from the timing signal calculator 530 of the second embodiment are substantially the same as the first to sixth timing signals Ga1-Gc2 shown in FIG. The first, second and third control signals Vga, Vgb and Vgc obtained from the control signal forming circuit 550 are also the same as those shown in FIGS. Therefore, the same effect as the first embodiment can be obtained also by the second embodiment.
[0050]
[Third Embodiment]
Next, a three-phase AC-DC converter according to a third embodiment will be described with reference to FIGS. 9 and 10. However, in the three-phase AC-DC converter according to the third embodiment, the control circuit 5 shown in FIG. 3 of the first embodiment is transformed into the control circuit 5b shown in FIG. 9, and the others are the first embodiment. Therefore, the third embodiment also refers to FIGS. 1 and 2 and omits the description of the parts common to the first embodiment. The control circuit 5b of the third embodiment of FIG. 9 is provided with a timing signal calculator 531 obtained by modifying the timing signal calculator 53 in the control circuit 5 of FIG. Since it is formed in the same way as in FIG. 3, the same parts as those in FIG.
[0051]
The flag forming circuit 70 is connected to the lines 6a, 7a and 8a of the first, second and third line voltages Vrs, Vst and Vtr, and compares the voltages Vrs, Vst and Vtr shown in FIG. To form flags F = 1, 2 and 3.
That is, the flag 1 in the sections of 30 ° to 90 ° and 210 ° to 270 ° with respect to the first phase voltage Vr,
Flag 2 in 90 ° -150 ° and 270 ° -330 ° sections
The flag 3 is generated in the interval of 150 ° to 210 ° and −30 ° to + 30 °.
[0052]
The modified timing signal calculator 531 of FIG. 9 is formed substantially the same as the timing signal calculator 53 of FIG. 3 except for the calculation contents.
The relationship between the first to sixth timing signals Ga1 to Gc2 of FIG. 9 and the first, second and third energization command values Drs, Dst and Dtr inputted to the timing signal calculator 531 and the flag F is as follows. (4) As shown in the equation.
When flag F = 1
Ga1 = 0
Ga2 = Drs
Gb1 = Ga2 = Drs
Gb2 = Gb1 + Dst = Drs + Dst
Gc1 = Gb2 = Drs + Dst
Gc2 = Gc1 + Dtr = Drs + Dst + Dtr
When flag F = 2
Ga1 = Gc2 = Dst + Dtr
Ga2 = Ga1 + Drs = Drs + Dst + Dtr
Gb1 = 0
Gb2 = Dst
Gc1 = Gb2 = Dst
Gc2 = Gc1 + Dtr = Dst + Dtr
When flag F = 3,
Ga1 = Gc2 = Dtr
Ga2 = Ga1 + Drs = Dtr + Drs
Gb1 = Ga2 = Dtr + Drs
Gb2 = Gb1 + Dst = Dst + Dtr + Drs
Gc1 = 0
Gc2 = Dtr (4)
[0053]
The control signal forming circuit 551 in FIG. 9 is formed in the same manner as in FIG. 4, and the first to sixth timing signals Ga1 to Gc2 and the sawtooth wave Vt are compared with each other in FIGS. First, second and third control signals Vga, Vgb and Vgc are formed and sent to the first to sixth switches S1 to S6.
[0054]
In FIG. 10, when the flag F = 1, the first phase switches S1 and S2, the second phase switches S3 and S4, and the third phase switches S5 and S6 are turned on in this order. When the flag F = 2, the second-phase, third-phase, and first-phase switches S3 and S4, S5 and S6, and S1 and S2 are turned on in this order. When the flag F = 3, the third-phase, first-phase and first-phase switches S5 and S6, S1 and S2, and S3 and S4 are turned on in this order. Therefore, according to the third embodiment, in addition to the same effects as those of the first embodiment, the first to sixth switches S1 to S6 are turned on in one cycle consisting of 360 degrees of the AC power supply voltage. The effect that the shift | offset | difference of a period can be prevented can also be acquired.
[0055]
[Fourth Embodiment]
Next, a three-phase AC-DC converter according to a fourth embodiment will be described with reference to FIGS. 11 and 12. However, in the three-phase AC-DC converter of the fourth embodiment, the control circuit 5 shown in FIG. 3 of the first embodiment is transformed into the control circuit 5c shown in FIG. 11, and the others are the first embodiment. Therefore, the fourth embodiment also refers to FIGS. 1 and 2 and omits the description of the parts common to the first embodiment. Further, the control circuit 5c of the fourth embodiment in FIG. 11 includes a timing signal calculator 532, a control signal forming circuit 552, and a modification of the timing signal calculator 531 and the control signal forming circuit 551 in the control circuit 5b of FIG. The other parts are the same as those shown in FIG. 9, and the same parts as those shown in FIGS. 3, 7 and 9 are designated by the same reference numerals and their description is omitted.
[0056]
The modified timing signal calculator 532 of FIG. 11 is formed substantially the same as the timing signal calculator 531 of FIG. 9 except for the number of output lines. That is, the timing signal calculator 532 is connected to the first, second, third, fourth, fifth and sixth timing signals Ga1, Ga2 of FIG. 9 by the first, second and third lines 53a, 53b, 53c. , Gb1, Gb2, Gc1, and Gc2, the first, second, and third timing signals Ga, Gb, and Gc including the same information are output.
[0057]
The timing signal calculator 532 is connected to the absolute value circuits 50, 51, 52 and the flag forming circuit 70, and is supplied from the first, second and third energization rate command signals Drs, Dst, Dtr and the line 71. Based on the flag F, the following equation is calculated to output first, second, and third timing signals Ga, Gb, Gc.
When flag F = 1
Ga = Drs
Gb = Drs + Dst
Gc = Drs + Dst + Dtr
When flag F = 2
Ga = Dtr + Drs + Dst
Gb = Dst
Gc = Dst + Dtr
When flag F = 3,
Ga = Drs + Dtr
Gb = Dst + Dtr + Drs
Gc = Dtr (5)
[0058]
As shown in FIG. 12, the control signal forming circuit 552 shown in FIG. 11 has an input side switching circuit 73 and an output side switching circuit 73a added to the control signal forming circuit 550 shown in FIG. Is. The input side switching circuit 73 is connected between the first, second and third lines 53a, 53b and 53c and the first, second and third comparators 56, 57 and 58 and is connected by the line 72 in FIG. Connected to the flag forming circuit 70, the connection relationship between the lines 53a, 53b, 53c and the comparators 56, 57, 58 is switched according to the change of the flag F. The connection form by the switching circuit 73 is as follows.
When flag F = 1,
Ga line 53a is connected to the first comparator 56;
The Gb line 53b is connected to the third comparator 57,
Gc line 53c is connected to the second comparator 58.
Connected. Accordingly, when the flag is 1, as apparent from FIG. 10, the first and second switches S1, S2 are set, the fifth and sixth switches are set, and the third and fourth switches are set in this order. These switches are turned on.
When flag F = 2,
Ga line 53a is connected to the second comparator 58,
Gb line 53b is connected to first comparator 56,
Gc line 53c is connected to the third comparator 57.
Connected. Therefore, when the flag is 2, as is apparent from FIG. 10, the set of the third and fourth switches S3 and S4, the set of the first and second switches S1 and S2, the fifth and sixth switches S5, These switches are turned on in the order of the set of S6.
When flag F = 3,
The Ga line 53a is connected to the third comparator 57,
Gb line 53b is connected to second comparator 58,
Gc line 53c is connected to the first comparator 56.
Connected. Therefore, when the flag is 3, the set of the fifth and sixth switches S5 and S6, the set of the third and fourth switches S3 and S4, and the first and second switches S1 and S2 are in this order. The switch is turned on.
The output side switching circuit 73a is connected between the NOT circuit 60, the exclusive OR gate 61, the AND gate 62 and the first, second and third control signal output lines 25, 26, 27. Control is performed as follows by the flag F of the line 72.
When flag F = 1,
The output terminal of the NOT circuit 60 is connected to the Vga line 25.
The output terminal of the exclusive OR gate 61 is connected to the Vgb line 26.
The output terminal of the AND gate 62 is connected to the Vgc line 27.
When flag F = 2,
The output terminal of the NOT circuit 60 is connected to the Vgb line 26.
The output terminal of the exclusive OR gate 61 is connected to the Vgc line 27.
The output terminal of the AND gate 62 is connected to the Vga line 25.
When flag F = 3,
The output terminal of the NOT circuit 60 is connected to the Vgc line 27.
The output terminal of the exclusive OR gate 61 is connected to the Vga line 25.
An output terminal of the AND gate 62 is connected to the Vgb line 26.
[0059]
According to the fourth embodiment, the same operational effects as those of the first embodiment can be obtained, and, in the same manner as in the third embodiment, the first to sixth first cycles in one cycle consisting of 360 degrees of the AC power supply voltage are obtained. It is also possible to obtain an effect that it is possible to prevent the shift of the ON period of the switches S1 to S6.
[0060]
[Fifth Embodiment]
Next, a three-phase AC-DC converter according to a fifth embodiment will be described with reference to FIGS. 13 and 14. However, in the three-phase AC-DC converter according to the fifth embodiment, the control circuit 5 shown in FIG. 3 of the first embodiment is transformed into the control circuit 5d shown in FIG. 13, and the others are the first embodiment. Therefore, the fifth embodiment also refers to FIGS. 1 and 2 and omits the description of the parts common to the first embodiment.
[0061]
The control circuit 5d of the fifth embodiment of FIG. 13 uses the timing signal calculator 53 and the control signal forming circuit 55 in the control circuit 5 of FIG. 3 in the waveforms of FIGS. 14 (D), (E), (F), and (G). The timing signal computing unit 533 and the control signal forming circuit 55 modified to obtain the above are provided, the flag forming circuit 70 is further provided, and the others are formed in the same manner as in FIG.
[0062]
Similarly to FIG. 9, the flag forming circuit 70 is connected to the lines 6a, 7a and 8a of the first, second and third line voltages Vrs, Vst and Vtr, and the voltages Vrs and Vst shown in FIG. , Vtr are compared by a comparator to form the same flags 1, 2 and 3 as in FIG.
[0063]
The timing signal calculator 533 is connected to the absolute value circuits 50, 51, 52 and the flag forming circuit 70, and is supplied from the first, second and third energization rate command signals Drs, Dst, Dtr and the line 71. Based on the flag F, the following equation (6) is calculated to output first, second, third, fourth, fifth and sixth timing signals Ga1, Ga2, Gb1, Gb2, Gc1, and Gc2. To do. In order to simplify the equation, in the following equation (6), 1− (Drs + Dst + Dtr) is represented by D, and the remainder when A is divided by B is represented by mod (A, B). A is (θ + 30) / 60, and B is 1. θ represents an angular position with reference to the first phase voltage Vr in FIG.
[0064]
When flag F = 1
Ga1 = D × mod {(θ + 30) / 60, 1} / 3
Ga2 = Ga1 + Drs
Gb1 = Ga2 + D / 3
Gb2 = Gb1 + Dst
Gc1 = Gb2 + D / 3
Gc2 = Gc1 + Dtr
When flag F = 2
Ga1 = Gc2 + D / 3
Ga2 = Ga1 + Drs
Gb1 = D × mod {(θ + 30) / 60, 1} / 3
Gb2 = Gb1 + Dst
Gc1 = Gb2 + D / 3
Gc2 = Gc1 + Dtr
When flag F = 3,
Ga1 = Gc2 + D / 3
Ga2 = Ga1 + Drs
Gb1 = Ga2 + D / 3
Gb2 = Gb1 + Dst
Gc1 = D × mod {(θ + 30) / 60, 1} / 3
Gc2 = Gc1 + Dtr (6)
[0065]
The first and second timing signals Ga1 and Ga2 form a first control signal Vga for turning on the first and second switches S1 and S2, as is apparent from FIGS. When the first timing signal Ga1 crosses the sawtooth wave Vt, a pulse is generated to turn on the first and second switches S1 and S2, and the second timing signal Ga2 crosses the sawtooth wave Vt. Then, the on-pulse of the first and second switches S1, S2 disappears.
The third and fourth timing signals Gb1 and Gb2 form a second control signal Vgb for turning on the third and fourth switches S3 and S4, as is apparent from FIGS. When the third timing signal Gb1 crosses the sawtooth wave Vt, a pulse is generated to turn on the third and fourth switches S3 and S4, and the fourth timing signal Gb2 crosses the sawtooth wave Vt. Then, the ON pulses of the third and fourth switches S3 and S4 disappear.
The fifth and sixth timing signals Gc1 and Gc2 form a third control signal Vgc for turning on the fifth and sixth switches S5 and S6, as is apparent from FIGS. When the fifth timing signal Gc1 crosses the sawtooth wave Vt, a pulse is generated to turn on the fifth and sixth switches S5 and S6, and the sixth timing signal Gc2 crosses the sawtooth wave Vt. Then, the on-pulses of the fifth and sixth switches S5 and S6 disappear.
[0066]
The control signal forming circuit 55 in FIG. 13 is formed in the same manner as in FIG. 4, and the first to sixth timing signals Ga1 to Gc2 and the sawtooth wave Vt are compared as shown in FIG. (E) First, second and third control signals Vga, Vgb and Vgc of (F) and (G) are output.
[0067]
In the fifth embodiment, as is clear from FIGS. 14E, 14F, and 14G, in the section where the flags F of 30 ° to 90 ° and 210 ° to 270 ° are 1, the first phase switch S1, These are on-controlled in the order of S2, third phase switches S5, S6, second phase switches S3, S4. When the flag F of 90 ° to 150 ° and 270 ° to 330 ° is 2, these are turned on in the order of the second phase switches S3 and S4, the first phase switches S1 and S2, and the third phase switches S5 and S6. Be controlled. In the section where the flag F of 150 ° to 210 ° and −30 ° to + 30 ° is 3, the third phase switches S5 and S6, the second phase switches S3 and S4, and the first phase switches S1 and S2 are arranged in this order. Etc. are on-controlled.
[0068]
According to the fifth embodiment, in addition to the same effects as those of the first embodiment, the first to sixth in the 360-degree section of the AC power supply voltage as in the third and fourth embodiments. It is also possible to obtain an effect that it is possible to prevent the shift of the ON period of the switches S1 to S6. In addition, since the idle periods are arranged between the ON periods of the first phase, second phase and third phase switches S1 and S2, S3 and S4, and S5 and S6, two or three even if switching is delayed. It is possible to prevent two phase switches from being turned on at the same time. If the switches of a plurality of phases are turned on at the same time, the direction of the terminal voltage of the transformer 2 becomes unstable, and the operation stability decreases. In this embodiment, the above problem does not occur.
[0069]
[Sixth Embodiment]
In the three-phase AC-DC converter of the sixth embodiment, the control circuit 5 of the embodiment shown in FIG. 1 is modified to the control circuit 5e of FIG. 15, and the other components are the same as those of the first embodiment. It is.
[0070]
The control circuit 5e shown in FIG. 15 is obtained by adding a correction value calculator 74 and three subtractors 75, 76, 77 to the control circuit 5 shown in FIG. is there. Therefore, in FIG. 15, the same parts as those in FIG.
The correction value calculator 74 is connected to the first, second, and third multipliers 43, 44, 45, and performs the following calculation based on the first, second, and third current command values Irs, Ist, Itr. To obtain the correction value ΔI.

Here, max (Irs, Ist, Itr) indicates the maximum of Irs, Ist, Itr, and min (Irs, Ist, Itr) indicates the minimum of Irs, Ist, Itr.
[0071]
The first, second, and third subtractors 75, 76, and 77 for correction are the first, second, and third multipliers 43, 44, and 45, and the first, second, and third dividers 47. , 48, 49, and subtracts the correction value ΔI obtained by the correction value calculator 74 from the first, second and third current command values Irs, Ist, Itr as shown in the following equation. Correction current command values Irs', Ist ', Itr' are output.
Irs ′ = Irs−ΔI
Ist ′ = Ist−ΔI
Itr ′ = Itr−ΔI (8)
If the correction value calculator 74 outputs a negative polarity correction value -ΔI, the first, second and third subtractors 75, 76 and 77 can be replaced with adders.
[0072]
FIG. 16 shows the state of each part of FIG. The first, second, and third current command values Irs, Ist, Itr in FIG. 16B obtained from the first, second, and third multipliers 43, 44, 45 are shown in FIG. The correction current values Irs ′, Ist ′, and Itr ′ shown in FIG. 16D are obtained from the first, second, and third subtractors 75, 76, and 77.
From the absolute value circuits 50, 51, 52, the first, second and third energization command signals Drs, Dst corresponding to the absolute values of the correction current command values Irs', Ist ', Itr' of FIG. , Dtr are obtained as shown in FIG. The timing signal calculator 53 obtains the first to sixth timing signals Ga1 to Gc2 in the same manner as in the first embodiment by the above-described equation (2). The first to sixth timing signals Ga1 to Gc2 are compared with the sawtooth wave Vt by the same control signal forming circuit 55 as in the first embodiment, and the first, second and second methods are used in the same manner as in the first embodiment. 3 control signals Vga, Vgb and Vgc are formed.
[0073]
When the first, second, and third continuity command signals Drs, Dst, and Dtr are formed as shown in FIG. 16E by applying the correction of ΔI, the first continuity command value in FIG. When Drs becomes zero in the interval of 0 to 60 degrees and 180 to 240 degrees with respect to the R-phase voltage, the first control signal Vga is maintained at zero, and the first and second switches S1 and S2 are turned off. Kept.
When the third energization rate command value Dtr becomes zero in the sections of 60 to 120 degrees and 240 to 300 degrees, the third control signal Vgc is maintained at zero, and the fifth and sixth switches S5 and S6 are turned off. Kept.
When the second energization rate command value Dst becomes zero at 120 to 180 degrees and 300 to 360 degrees, the second control signal Vgb is kept zero, and the third and fourth switches S3 and S4 are kept off. It is.
Since the on / off operation of the first to sixth switches S1 to S6 is interrupted during the period in which the control signal is maintained at zero, the number of switching operations per unit time of the first to sixth switches S1 to S6 is reduced. In addition, the switching loss is reduced and the efficiency is improved.
[0074]
[Seventh embodiment]
FIG. 17 shows a control circuit 5f of the seventh embodiment. The control circuit 5f in FIG. 17 adds a correction computing unit 74 'and correction first, second and third subtractors 75', 76 'and 77' to the control circuit 5 in FIG. Is configured in the same manner as in FIG. The correction computing unit 74 'has the same purpose as the correction computing unit 74 in FIG. 15, and forms a correction signal based on the line voltages Vrs, Vst, Vtr of the lines 6a, 7a, 8a. The first, second and third subtractors 75 ', 76' and 77 'are connected between the lines 6a, 7a and 8a and the multipliers 43, 44 and 45, and the first, second and third subtractors are connected. The correction value of the correction calculator 74 'is subtracted from the line voltages Vrs, Vst, Vtr. The correction by the subtracters 75 ', 76', 77 'is made so that the current command values Irs, Ist, Itr in FIG. 17 are the same as the corrected current command values Irs', Ist ', Itr' in FIG. Do. Thereby, the same effect as that of the sixth embodiment can be obtained by the seventh embodiment.
[0075]
[Eighth embodiment]
Next, an eighth embodiment will be described with reference to FIG.
The transformer 2 includes a voltage Vrs during the ON period of the first and second switches S1 and S2, Vst during the ON period of the third and fourth switches S3 and S4, and the ON of the fifth and sixth switches S5 and S6. Vtr is applied during the period, and when any of the first to sixth switches S1 to S6 is OFF, a terminal voltage of 0 is applied. The average of the terminal voltage applied to the transformer 2 within one period of the sawtooth wave Vt is as follows.
Average transformer terminal voltage = Vrs × Drs + Vst × Dst + Vtr × Dtr (9)
[0076]
When the equation (9) is set to zero and the correction value ΔI is solved using the equations (1) and (2), the correction value ΔI becomes the following equation (10).
When Irs × Ist × Itr ≧ 0 or Vrs × Vst × Vtr ≧ 0,

When Irs × Ist × Itr <0 or Vrs × Vst × Vtr <0,

[0077]
FIG. 18 shows the operation according to the equation (10) as in FIG. When the correction current command values Irs ′, Ist ′, Itr ′ change as shown in FIG. 18D based on the correction value ΔI of FIG. 18C, the first, second, and third current ratio command values Drs, Dst, and Dtr change as shown in FIG. The first to sixth timing signals Ga1 to Gc2 are determined by equation (2).
[0078]
According to the eighth embodiment, as apparent from the above, the average terminal voltage of the transformer can be made zero. Therefore, an increase in the excitation current of the transformer is prevented, and the transformer 2 is less likely to be saturated.
The same correction as in the sixth, seventh, and eighth embodiments can be applied to the second to seventh embodiments.
[0079]
[Ninth Embodiment]
In FIG. 19, the DC-AC converter according to the ninth embodiment omits the current detector 10 shown in FIG. 1, and instead uses the input lines 14, 16, and 18 of the first, second, and third phase converter circuits. The first, second and third current detectors 97a, 97b and 97c are connected in series, and the detected values Ia, Ib and Ic are sent to the control circuit 5g, and the others are the same as in FIG. It is composed.
[0080]
As shown in FIG. 20, the control circuit 5g replaces the dividers 47, 48 and 49 of the control circuit 5 of FIG. 3 with subtractors 47 ′, 48 ′ and 49 ′, and the first, second and third of FIG. The detection currents Ia, Ib and Ic of the current detectors 97a, 97b and 97c are input to the subtractors 47 ', 48' and 49 'via the filters 98a, 98b and 98c, and the other configurations are the same as in FIG. It is a thing.
From the first, second and third subtractors 47 ', 48' and 49 ', the first, second and third current command values Irs, Ist and Itr and the first, second and third detections. Differences ΔIrs, ΔIst, ΔItr from the current values Ia, Ib, Ic are obtained, and based on these, the amplifiers 50, 51, 52 form the first, second and third current ratio command values Drs, Dst, Dtr. To do.
[0081]
According to the ninth embodiment, in addition to obtaining the same effect as in the first embodiment, each line current Ia, Ib, Ic is detected and fed back, so that the control response is improved. can get.
[0082]
[Tenth embodiment]
The first, second, and third bidirectional switches Qa, Qb, Qc of the first to ninth embodiments can be configured as shown in FIG.
The bidirectional switches Qa, Qb or Qc in FIG. 21 are the first, second, third and fourth switches Q1, Q2, Q3 and Q4 and the first, second, third and fourth diodes made of FETs. It consists of D1, D2, D3, D4 and a capacitor C, and is connected in series to the line 14, 16 or 18. The first and second switches Q1 and Q2 have opposite directions and are connected between the terminal P1 and the terminal P2. The third and fourth switches Q3 and Q4 have opposite directions and are connected between the terminals P1 and P2. The third and fourth switches Q3 and Q4 have opposite directions with respect to the first and second switches Q1 and Q2. The first, second, third and fourth diodes D1, D2, D3, D4 are connected in reverse parallel to the first, second, third and fourth switches Q1, Q2, Q3, Q4. . The capacitor C is connected between the interconnection point P3 of the first and second switches Q1 and Q2 and the interconnection point P4 of the third and fourth switches Q3 and Q4. The second terminal P2 is connected to the primary winding N1a, N1b or N1c.
[0083]
When a current in the first direction (positive direction) from the top to the bottom is supplied to the bidirectional switch Qa, Qb or Qc in FIG. 21, an on-control signal is given to the first and fourth switches Q1, Q4, The second and third switches Q2 and Q3 are kept off, and when a current in the second direction (negative direction) flows, an on-control signal is given to the second and third switches Q2 and Q3, and the first and fourth switches The switches Q1 and Q4 are kept off. The current in the first direction flows through both the path of the first switch Q1 and the second diode D2, and the path of the third diode D3 and the fourth switch Q4. The current in the second direction flows through both the path of the second switch Q2 and the first diode D1, and the path of the fourth diode D4 and the third switch Q3.
[0084]
When the first and fourth switches Q1 and Q4 are turned off while the current in the first direction is flowing, the capacitor C is connected in parallel to the first switch Q1 via the third diode D3. In addition, it is connected in parallel to the fourth switch Q4 via the second diode D2, and acts as a snubber capacitor to prevent the first and fourth switches Q1 and Q4 from being overvoltage.
When the second and third switches Q2 and Q3 are turned off while the current in the second direction is flowing, the capacitor C is connected in parallel to the second switch Q2 via the fourth diode D4. And connected in parallel to the third switch Q3 via the first diode D1, acting as a snubber capacitor, preventing the second and third switches Q2, Q3 from overvoltage. The electric charge of the capacitor C is discharged to zero through the transformer 2 when the bidirectional switch is turned on.
[0085]
When the bidirectional switches Qa, Qb, Qc of FIG. 21 are used, the snubber effect of the four switches Q1-Q4 can be obtained with one capacitor C. Although the third and fourth switches Q3 and Q4 and the third and fourth diodes D3 and D4 are added, they are used as a main current path, and the main current is divided and flows. In comparison, the current capacities of the first to fourth switches Q1 to Q4 can be reduced, and the switches Q3 and Q4 are not wasted.
[0086]
[Eleventh embodiment]
The first, second and third bidirectional switches Qa, Qb and Qc in FIGS. 1 and 19 are arranged separately on one side and the other side of the windings of the forward direction switch means and the reverse direction switch means. Can be configured. In FIG. 22 showing a modification of the first bidirectional switch Qa in FIG. 1, the first switch means Qa1 is connected to one side of the same first primary winding N1a as in FIG. The second switch means Qa2 is connected, and the same switching as the first bidirectional switch Qa of FIG. 1 is achieved by the combination of the first and second switch means Qa1 and Qa2.
[0087]
The first switch means Qa1 comprises a first switch S1 comprising a controllable semiconductor switch (eg FET or transistor or IGBT) and a first diode D1 connected in reverse parallel to the first switch S1. . The first main terminal (source or emitter) of the first switch S 1 is connected to the R-phase line 14. The second main terminal (drain or collector) of the first switch S1 is connected to one end of the first primary winding N1a as an AC load. The first diode D1 has a directivity that allows a current in the first direction from the R-phase line 14 side to the S-phase line 15 to flow through the first primary winding N1a to the first switch S1. Connected in parallel. The first diode D1 may be an individual diode, or may be a built-in diode called a body diode or a parasitic diode of the first switch S1 made of an FET, a transistor, an IGBT (insulated gate bipolar transistor) or the like. Good. The first drive circuit 31 for controlling on / off of the first switch S1 is connected between the R-phase line 14, that is, the first main terminal of the first switch S1 and the control terminal of the first switch S1. Has been. The first drive circuit 31 performs on / off control of the first switch S 1 in response to the first control signal Vga on the line 25.
[0088]
The second switch means Qa2 comprises a second switch S2 comprising a controllable semiconductor switch and a second diode D2 connected in reverse parallel to the second switch S2. The first main terminal (source or emitter) of the second switch S 2 is connected to the S-phase line 15. The second main terminal (drain or collector) of the second switch S2 is connected to the other end of the first primary winding N1a. The second diode D2 has a directivity that allows a current in the second direction from the S-phase line 15 to the R-phase line 14 to flow through the first primary winding N1a to the second switch S2. Connected in parallel. The second diode D2 may be an individual diode, or may be a built-in diode called a body diode or parasitic diode of the second switch S2 made of FET, transistor, IGBT or the like. A second drive circuit 32 for controlling on / off of the second switch S2 is connected between the S-phase line 15, that is, between the first main terminal of the second switch S2 and the control terminal of the second switch S2. Has been. The second drive circuit 32 controls the second switch S2 on / off in response to the first control signal Vga on the line 25.
[0089]
Although those corresponding to the second and third bidirectional switches Qb and Qc in FIG. 1 are not shown in FIG. 22, they are formed in the same manner as the first and second switch means Qa1 and Qa2 in FIG.
[0090]
In FIG. 22, since the source as the first main terminal of the first and second switches S1, S2 is connected to the power supply lines 14, 15, the potential of the source becomes the potential of the power supply lines 14, 15. Even if the voltage of the primary winding Na1 changes suddenly, the source-gate voltage does not change so much, and the first and second switches S1, S2 can be controlled stably.
The eleventh embodiment shown in FIG. 22 is the same as that shown in FIG. 1 except for the bidirectional switch, so that the same effect as that of the first embodiment can be obtained.
[0091]
[Twelfth embodiment]
The power conversion device according to the first embodiment shown in FIG. 23 is provided with an overvoltage prevention circuit 100a obtained by modifying the overvoltage prevention circuit 100 of FIG. 1, and the other configuration is the same as that of FIG. Therefore, in FIG. 23, substantially the same parts as those in FIG. The overvoltage detection circuit 100a of FIG. 23 is formed by adding the first and second diodes D11 and D12 to the overvoltage detection circuit 100 of FIG. The first diode D11 is connected between one end of the secondary winding N2 and the drain of the overvoltage suppression switch Q0, and the second diode D12 is the other end of the secondary winding N2 and the drain of the overvoltage suppression switch Q0. Connected between and. Accordingly, the overvoltage suppressing switch Q is connected in parallel to the first and second portions N2a and N2b of the secondary winding N2 via the first and second diodes D11 and D12. The first diode D11 has a direction of conduction when a voltage in the first direction is generated in the secondary winding N2, and the second diode D2 is opposite to the first direction in the secondary winding N2. It has directionality to conduct when a voltage in the second direction is generated. Since the first and second diodes D11 and D12 function in the same manner as the first and second rectifier elements 21 and 22 in FIG. 1 with respect to the overvoltage suppressing switch Q0, the twelfth embodiment in FIG. Also, the same effect as that of the first embodiment can be obtained.
[0092]
[Thirteenth embodiment]
In the thirteenth embodiment shown in FIG. 24, the transformer 2 in FIG. 23 is provided with a tertiary winding N3, to which the same overvoltage prevention circuit 100a as in FIG. 23 is connected. That is, in FIG. 24, the overvoltage prevention circuit 100a is not connected to the secondary winding N2, but is connected to the tertiary winding N3. Since the tertiary winding N3 is electromagnetically coupled to the primary windings N1a, N1b, N1c and the secondary winding N2, the first and second portions N3a, N3b of the tertiary winding N3 are first and second. If an overvoltage suppressing switch Q0 is connected via two diodes D11 and D12 and this switch Q0 is controlled to be on, overvoltage can be prevented as in FIGS.
[0093]
[Fourteenth Embodiment]
The power conversion device of the fourteenth embodiment is the same as that of FIG. 1 except that a modified overvoltage prevention circuit 100b shown in FIG. 25 is provided. An overvoltage prevention circuit 100b in FIG. 25 is obtained by modifying the overvoltage determination circuit 101 in the overvoltage prevention circuit 100 in FIG. 1 into an overvoltage determination circuit 101a, and the others are formed in the same manner as in FIG. The overvoltage determination circuit 101a shown in FIG. 25 includes a series circuit of a constant voltage diode ZD composed of a Zener diode connected between the cathodes of the first and second rectifying elements 21 and 22 and the center tap 20 and a resistor R1. . The interconnection point between the constant voltage diode ZD and the resistor R1 is connected to the gate of the switch Q0. Accordingly, when the voltage at both ends of the determination circuit 101a becomes higher than a predetermined value, the constant voltage diode ZD is turned on, the voltage of the resistor R1 is increased, and the overvoltage suppression switch Q0 is turned on, as in FIG. Overvoltage is suppressed. Therefore, the same effect as that of the first embodiment of FIG. 1 can be obtained by the fourteenth embodiment of FIG.
[0094]
[Fifteenth embodiment]
The power conversion device of the fifteenth embodiment is provided with an overvoltage determination circuit 101b obtained by modifying the overvoltage determination circuit 101 of FIG. 23 as shown in FIG. 26, and the others are formed in the same manner as FIG. The overvoltage determination circuit 101b of FIG. 26 is formed of a series circuit of a constant voltage diode ZD and a resistor R1 as in FIG. 25, and is connected between the cathodes of the first and second diodes D11 and D12 and the center tap 20. ing. Since the interconnection point between the constant voltage diode ZD and the resistor R1 is connected to the gate of the switch Q0, the switch Q0 is turned on when overvoltage occurs. Therefore, the same effect as that of the twelfth embodiment of FIG. 22 can be obtained by the embodiment of FIG.
[0095]
[Modification]
The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.
(1) In the bidirectional switches Qa, Qb, Qc in FIG. 2, control signals are supplied to both the first switches 30a, 30b, 30c and the second switches 31a, 31b, 31c simultaneously. A control signal is supplied to the first switches 30a, 30b, 30c during the positive half-wave period of the AC voltages Vrs, Vst, Vtr, and a control signal is supplied to the second switches 31a, 31b, 31c during the negative half-wave period. Thus, the control loss of the switch can be reduced. Also, the first switch S1 in FIG. 22 can be controlled with an alternating negative half-wave, and the second switch S2 can be controlled with a positive half-wave.
(2) The configurations of the bidirectional switching elements Qa, Qb, Qc and the switches Qa1, Qa2 shown in FIG. 22 can be variously modified. For example, the switches 30a, 30b, 30c, 31a, 31b, 31c, Q1-Q4, S1 and S2 can be semiconductor switching elements such as IGBTs and transistors. Also, the diodes 32a, 32b, 32c, 33a, 33b, 33c, D1 to D4 can be built-in diodes of the switches 30a, 30b, 30c, 31a, 31b, 31c, Q1 to Q4, S1, and S2.
(3) The functions of the sixth to eighth embodiments can be added to the control circuit 5g of FIG.
(4) In the first to fifteenth embodiments, a part of each can be applied to other embodiments. For example, the bidirectional switches Qa, Qb, and Qc shown in FIG. 21 can be applied to the second to ninth embodiments. Further, the overvoltage prevention circuit 100 of FIG. 19 can be modified to the overvoltage prevention circuits 100a, 100b, 100c, etc. of FIGS. 23, 24, 25, and 26.
(5) An analog / digital converter (ADC) can be provided at the input stage of the control circuits 5 to 5g, and the control circuit can be configured as a digital circuit.
(6) In the fourth and fifth embodiments,
When F = 1, Ga ≦ Gc ≦ Gb,
When F = 2, Gb ≦ Ga ≦ Gc,
Gc ≦ Gb ≦ Ga when F = 3, but others are in order, for example,
When F = 1, Gb ≦ Gc ≦ Ga,
Gc ≦ Ga ≦ Gb when F = 2,
The same effect can be obtained when Ga ≦ Gb ≦ Gc when F = 3.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an AC-DC power converter according to a first embodiment.
FIG. 2 is a circuit diagram showing in detail the first, second and third bidirectional switches and the transformer of FIG. 1;
FIG. 3 is a circuit diagram showing in detail the control circuit of FIG. 1;
4 is a circuit diagram showing a control signal forming circuit of FIG. 3;
5 is a waveform diagram showing the state of each part in FIG. 3. FIG.
FIG. 6 is a circuit diagram showing a control circuit of a second embodiment.
7 is a circuit diagram showing the control signal forming circuit of FIG. 6. FIG.
FIG. 8 is a waveform diagram showing the state of each part in FIG. 6;
FIG. 9 is a circuit diagram showing a control circuit of a third embodiment.
10 is a waveform diagram showing the state of each part in FIG. 9;
FIG. 11 is a circuit diagram showing a control circuit of a fourth embodiment.
12 is a circuit diagram showing the control signal forming circuit of FIG. 11. FIG.
FIG. 13 is a circuit diagram showing a control circuit of a fifth embodiment.
14 is a waveform diagram showing the state of each part in FIG. 13;
FIG. 15 is a circuit diagram showing a control circuit of a sixth embodiment.
16 is a waveform diagram showing the state of each part in FIG. 15;
FIG. 17 is a circuit diagram showing a control circuit of a seventh embodiment.
FIG. 18 is a waveform diagram showing the state of each part of the control circuit of the eighth embodiment.
FIG. 19 is a circuit diagram showing an AC-DC power converter according to a ninth embodiment.
20 is a circuit diagram showing in detail the control circuit of FIG. 19;
FIG. 21 is a circuit diagram showing a bidirectional switch of the AC-DC power converter of the tenth embodiment.
FIG. 22 is a circuit diagram showing a part of the power converter of the eleventh embodiment.
FIG. 23 is a circuit diagram showing a power conversion apparatus according to a twelfth embodiment.
FIG. 24 is a circuit diagram showing a part of a power conversion apparatus according to a thirteenth embodiment.
FIG. 25 is a circuit diagram showing a part of a power conversion apparatus according to a fourteenth embodiment.
FIG. 26 is a circuit diagram showing a part of a power conversion apparatus according to a fifteenth embodiment.
[Explanation of symbols]
1r, 1s, 1t 3-phase AC input terminal
2 transformer
3 Full-wave rectification smoothing circuit
5-5g Control circuit
100, 100a, 100b, 100c Overvoltage prevention circuit
Qa, Qb, Qc first, second and third bidirectional switches
N1a, N1b, N1c Primary winding
N2 secondary winding

Claims (6)

First, second and third AC input terminals connected to a three-phase AC power source;
A first primary winding connected between the first AC input terminal and the second AC input terminal;
A second primary winding connected between the second AC input terminal and the third AC input terminal;
A third primary winding connected between the third AC input terminal and the first AC input terminal;
A secondary winding electromagnetically coupled to each of the first, second and third primary windings;
A first current for flowing a current in a first direction through the first primary winding with on / off control and a current in a second direction opposite to the first direction through on / off control. Two-way switch means,
A second for flowing a current in a first direction through the second primary winding with on / off control and a current in a second direction opposite to the first direction through on / off control. Two-way switch means,
A third for flowing a current in a first direction through the third primary winding with on / off control and flowing a current in a second direction opposite to the first direction with on / off control. Two-way switch means,
A rectifying / smoothing circuit connected to the secondary winding;
Forming first, second and third control signals for on / off control of the first, second and third bidirectional switch means at a frequency higher than the frequency of the AC voltage of the three-phase AC power supply The first, second, and third bidirectional switch means are supplied to the first, second, and third bidirectional switch means so that all the first, second, and third bidirectional switch means are turned off at the same time. And a control circuit for forming the first, second and third control signals. Furthermore, an overvoltage determination means for determining that the voltage of the secondary winding is an overvoltage or a possibility of becoming an overvoltage,
And an overvoltage suppression switch unit for short-circuiting the secondary winding when an output indicating that there is an overvoltage or a risk of overvoltage is obtained from the determination unit. The power conversion device according to claim 1. A third winding electromagnetically coupled to the first, second and third primary windings and the secondary winding;
Overvoltage determination means for determining that the secondary winding or the tertiary winding is overvoltage or may be overvoltage;
And an overvoltage suppression switch means for short-circuiting the tertiary winding when an output indicating that there is an overvoltage or a possibility of overvoltage is obtained from the overvoltage determination means. The power conversion device according to claim 1. The power converter according to claim 2 or 3, wherein the overvoltage determining means detects a period in which the first, second and third bidirectional switch means are simultaneously turned off as a period in which there is a possibility of overvoltage. The secondary winding has a center tap,
The rectifying / smoothing circuit includes a first rectifying element connected to one end of the secondary winding, a second rectifying element connected to the other end of the secondary winding, and the first and second rectifying elements. A smoothing circuit connected to the interconnection point of the output terminals of the rectifying element and the center tap,
The overvoltage suppression switch means is connected between the connection point of the output terminals of the first and second rectifying elements and the center tap, and is configured to respond to the output of the overvoltage determination means. The power conversion device according to claim 2, wherein the power conversion device is a switch that can be used. The secondary winding has a center tap,
The rectifying / smoothing circuit includes a first rectifying element connected to one end of the secondary winding, a second rectifying element connected to the other end of the secondary winding, and the first and second rectifying elements. A smoothing circuit connected to the interconnection point of the output terminals of the rectifying element and the center tap,
The overvoltage suppression switch means includes a first overvoltage suppression diode connected to one end of the secondary winding, a second overvoltage suppression diode connected to the other end of the secondary winding, A controllable switch connected between the interconnection point of the output terminals of the first and second overvoltage suppression diodes and the center tap and configured to respond to the output of the overvoltage determination means; The power converter according to claim 2 characterized by things.

Images