JP4668001B2 - Dicing / die-bonding sheet and method for manufacturing semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sheet shared by dicing and die bonding which is easily pasted to a semiconductor wafer and reducing damage of a bonding wire, as well as reducing variation in height of a semiconductor device which is caused by poor precision in thickness of an adhesive layer for bonding semiconductor chips together, variation in height from a substrate to the surface of a semiconductor chip in the top layer, inclination of the semiconductor chip in the top layer, and the like. <P>SOLUTION: A sheet 10 shared by dicing and die bonding consists of: a base material 11; a wire embedded layer 12 which is stacked on the base material for peeling; and an insulating layer 13 stacked on the wire embedded layer. The wire embedded layer 12 has a storage modulus of 1&times;10<SP>4</SP>Pa or less at 120&deg;C. The insulating layer 13 has such adhesion as can be pasted to an object 2 at 60&deg;C or less. The elasticity ratio (insulating layer/wire embedded layer) between the insulating layer 13 and the wire embedded layer 12 at 120&deg;C is 10 or higher. A voluminal resistivity of the wire embedded layer 12 and the insulating layer 13 is 1&times;10<SP>13</SP>&Omega;cm or higher, respectively. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a dicing / die-bonding sheet and a method for manufacturing a stacked semiconductor device using the same.

  In order to increase the speed and size of a semiconductor device, a plurality of semiconductor chips (hereinafter simply referred to as chips) are two-dimensionally mounted on a single substrate. Such a semiconductor device is called a multi-chip module. As a further miniaturized structure, there is one in which chips are three-dimensionally stacked. Thus, a package in which chips are three-dimensionally stacked is also called a “stacked semiconductor device”.

  As such an apparatus, an apparatus in which a small chip is stacked on a large chip (see Japanese Patent Application Laid-Open Nos. 57-34466 and 7-38053), and an apparatus in which the positions of the chips are shifted and stacked (Japanese Patent Application Laid-Open No. 57-57). 34466), a device in which chips having a step formed on the peripheral edge are stacked (see JP-A-6-244360), two chips are joined back to back, one chip is directly joined to the substrate, and the other chip A device for bonding to a substrate with a bonding wire (see Japanese Patent Laid-Open No. 7-273275) has been proposed.

However, each of the above-described devices has the following drawbacks.
In a structure in which a small chip is stacked on a large chip, it is natural that a chip of the same size cannot be stacked, and in the case of stacking by shifting the position of the chip, no electrode pad is provided on the entire periphery of the chip. Has some disadvantages. Usually, the chips in circulation often have pads on the entire circumference. When the chip position is limited, there arises a problem that these chips cannot be used.

  In addition, in the configuration in which chips with a step formed at the peripheral portion are stacked, a space is generated in the electrode pad portion due to the step, so that even if chips of the same size are stacked, the bonding wire is not damaged. However, there is a disadvantage that the yield of the chip is lowered. Furthermore, since the chip peripheral portion has a thin plate thickness, the mechanical strength is lowered, and mechanical damage may occur during wire bonding.

  Also, in the configuration using chips bonded back to back, only two chips can be stacked, bumps need to be formed on the electrode pads in order to bond the chips directly to the substrate, and the chip is connected to the substrate However, there are inconveniences in that two types of bonders, ie, a flip chip die bonder and a wire bonder, are necessary for two chips.

  In order to solve such a problem, Patent Document 1 discloses a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate, in which electrode pads are formed on the periphery of the semiconductor chips, and A semiconductor device is disclosed in which the substrate is connected by a bonding wire, and an adhesive layer having a thickness of 25 μm or more and 300 μm or less is interposed between semiconductor chips.

  According to such an invention of Patent Document 1, chips of the same size can be three-dimensionally stacked without special processing on the chips or without any particular restrictions on the chip size, electrode pad arrangement, or the like. There is an advantage.

  However, since the adhesive layer in Patent Document 1 is formed by applying and curing a liquid adhesive, it is difficult to control the thickness and region of the adhesive layer. For this reason, problems such as contamination of the substrate and the semiconductor chip due to bleeding (bleeding) of the adhesive constituting the adhesive layer and inclination of the stacked semiconductor chips are caused.

  In particular, when the semiconductor chip is multi-layered, the variation in the height of the semiconductor device, the variation in the height from the substrate to the surface of the uppermost semiconductor chip, the inclination of the uppermost semiconductor chip, etc. are increased. This causes a problem that stable production becomes difficult, for example, it becomes impossible to recognize the position for wire bonding on the upper surface of the semiconductor chip. That is, when the number of stacked layers is two, the variation and inclination of the height are increased as the number of stacked semiconductor chips is increased to three and four even though the variation and inclination are not serious problems. As a result, the problem that stable production of semiconductor devices becomes difficult is caused.

  Patent Document 2 discloses a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate, and electrode terminals provided on each of the semiconductor chips are electrically connected to the substrate by bonding wires. A semiconductor device is disclosed in which an insulating layer is formed between a bonding wire and a semiconductor chip stacked on the bonding wire side of the semiconductor chip to which the bonding wire is connected. ing. As a method for manufacturing this semiconductor device, claim 11 of Patent Document 2 states that “a sheet made of an insulating layer and an adhesive layer is placed on a wafer before the semiconductor chip is divided, and the insulating layer side of the sheet is on the wafer. A sheet affixing process for adhering to the sheet, a dividing process for dividing the wafer affixed with the sheet into semiconductor chips by dicing, and a semiconductor chip to which the adhesive layer is affixed by the adhesive layer And a bonding step of bonding to a semiconductor chip electrically connected to the substrate by a bonding wire.

As the insulating layer, it is described that a resin having excellent heat resistance and less plastic deformation at 100 ° C. to 200 ° C., particularly a polyimide resin is preferable (see paragraph 0060).
The adhesive layer is preferably a thermosetting resin that is melted from a solid to a liquid by heating and then cured, and among them, an epoxy resin is particularly preferable (see paragraph 0063).

  In order to attach a sheet composed of an insulating layer and an adhesive layer to a semiconductor wafer, it is necessary to heat to a temperature at which the insulating layer exhibits fluidity to some extent and develops an adhesive force, that is, 100 ° C. to 200 ° C. or higher. There is. However, the heating to such a high temperature may cause the thermosetting resin constituting the adhesive layer to be liquefied and may be cured in some cases.

  When the adhesive layer is liquefied, the adhesive layer may flow due to pressure when the insulating layer is applied, and the thickness accuracy of the adhesive layer may be impaired. Thus, when the thickness accuracy of the adhesive layer is impaired, as in the case of the liquid adhesive in Patent Document 1, the height of the semiconductor device varies from the substrate to the surface of the uppermost semiconductor chip. And the inclination of the uppermost semiconductor chip becomes large, causing a problem that stable production becomes difficult.

Further, when the adhesive layer is cured, the wire is crushed when the semiconductor chip is bonded.
Therefore, in the method of Patent Document 2 (Claim 11), it is necessary to apply the sheet at a temperature at which the insulating layer exhibits adhesiveness and at a temperature at which the adhesive layer does not flow or harden. It becomes difficult.
Japanese Patent Laid-Open No. 10-027880 JP 2002-222913 A

  The present invention is a dicing / die-bonding sheet used in the manufacture of the above-described so-called “stacked semiconductor device”, which can be attached to a semiconductor wafer without requiring complicated temperature control, and moreover, a bonding wire generated at the time of stacking In addition to reducing damage, semiconductor device height variations due to poor thickness accuracy of the adhesive layer that bonds the semiconductor chips together, height variations from the substrate to the surface of the uppermost semiconductor chip, and the uppermost layer An object of the present invention is to provide a dicing / die-bonding sheet that can reduce the inclination of the semiconductor chip.

This invention which solves such a subject contains the following matters as a summary.
(1) A base material, a wire embedding layer laminated on the base material in a peelable manner, and an insulating layer laminated on the wire embedding layer,
The wire embedded layer has a storage elastic modulus at 120 ° C. of 1 × 10 ⁴ Pa or less,
The insulating layer has adhesiveness that can be applied to an adherend at a temperature of 60 ° C. or less,
The elastic modulus ratio (insulating layer / wire embedding layer) of the insulating layer and the wire embedding layer at 120 ° C. is 10 or more,
A sheet for both dicing and die bonding, in which the volume resistivity of both the buried wire layer and the insulating layer is 1 × 10 ¹³ Ω · cm or more.

(2) A base material, a wire embedding layer laminated on the base material in a peelable manner, a heat resistant insulating film laminated on the wire embedding layer, and formed on the heat resistant insulating film Consisting of an adhesive layer,
The wire embedded layer has a storage elastic modulus at 120 ° C. of 1 × 10 ⁴ Pa or less,
A dicing / die-bonding sheet in which the wire embedding layer, the heat-resistant insulating film, and the adhesive layer all have a volume resistivity of 1 × 10 ¹³ Ω · cm or more.

  (3) The wire embedding layer has energy beam curability, and the elastic modulus according to claim 1 and 2 is a value measured at 120 ° C. for the wire embedding layer after energy beam curing (1) Or the dicing / die-bonding sheet according to (2).

(4) The dicing / die-bonding sheet according to (1) or (2), which is used for bonding and fixing between semiconductor chips of a stack type semiconductor device.
(5) Affixing the dicing / die-bonding sheet according to (1) on the back surface of the semiconductor wafer on which the semiconductor chip constituting the upper layer than the second layer of the stack type semiconductor device is formed,
The semiconductor wafer is subjected to full-cut dicing together with an insulating layer and a wire buried layer for each semiconductor chip,
Pick up a semiconductor chip having an insulating layer and a wire embedding layer on the back surface from the substrate,
Separately, preparing a substrate on which a semiconductor chip constituting the first layer to which wires are connected is mounted, heating the substrate,
A method of manufacturing a stacked semiconductor device, comprising: embedding a wire embedding layer surface of the semiconductor chip in a wire forming surface of the substrate, and bringing the wire embedding layer surface into contact with a semiconductor chip surface constituting a first layer.

(6) Affixing the dicing / die-bonding sheet according to (2) on the back surface of the semiconductor wafer on which the semiconductor chip constituting the upper layer than the second layer of the stack type semiconductor device is formed,
For each semiconductor chip, the semiconductor wafer is subjected to full-cut dicing together with an adhesive layer, a heat-resistant insulating film and a wire embedding layer,
Picking up a semiconductor chip having an adhesive layer, a heat-resistant insulating film and a wire embedding layer on the back surface from the substrate,
Separately, preparing a substrate on which a semiconductor chip constituting the first layer to which wires are connected is mounted, heating the substrate,
A method of manufacturing a stacked semiconductor device, comprising: embedding a wire embedding layer surface of the semiconductor chip in a wire forming surface of the substrate, and bringing the wire embedding layer surface into contact with a semiconductor chip surface constituting a first layer.

  According to the present invention, a dicing / die-bonding sheet that can be attached to a semiconductor wafer without requiring complicated temperature control is provided. According to such an invention, in a so-called stack type semiconductor device, bonding wires generated at the time of stacking are provided. In addition to reducing damage, semiconductor device height variations due to poor thickness accuracy of the adhesive layer that bonds the semiconductor chips together, height variations from the substrate to the surface of the uppermost semiconductor chip, and the uppermost layer This can eliminate the inclination of the semiconductor chip and contribute to improving the quality and productivity of the semiconductor device.

Hereinafter, the present invention will be described more specifically with reference to the drawings.
As shown in FIG. 1, a first dicing / die-bonding sheet 10 according to the present invention includes a base material 11, a wire embedding layer 12 which is detachably laminated on the base material 11, and the wire embedding. The insulating layer 13 is laminated on the layer 12.

  Further, as shown in FIG. 2, the second dicing / die-bonding sheet 20 according to the present invention includes a base material 21, a wire embedding layer 22 detachably laminated on the base material 21, and the wire It consists of a heat resistant insulating film 24 laminated on the buried layer 22 and an adhesive layer 23 formed on the heat resistant insulating film 24.

The dicing / die-bonding sheets 10 and 20 of the present invention can take any shape such as tape and label.
Hereinafter, the substrate, the wire embedding layer, the insulating layer, the adhesive layer, and the heat resistant insulating film will be described.

"Base materials 11, 21"
Specific examples and preferred examples of the base materials 11 and 21 in the first and second dicing / die-bonding sheets are the same.

  Examples of the base material include polyethylene film, polypropylene film, polybutene film, polybutadiene film, polymethylpentene film, polyvinyl chloride film, vinyl chloride copolymer film, polyethylene terephthalate film, polyethylene naphthalate film, polybutylene terephthalate film, Polyurethane film, ethylene vinyl acetate film, ionomer resin film, ethylene / (meth) acrylic acid copolymer film, ethylene / (meth) acrylic acid ester copolymer film, polystyrene film, polycarbonate film, polyimide film, fluororesin film, etc. A film is used. These crosslinked films are also used. Furthermore, these laminated films may be sufficient. Furthermore, these films may be transparent films, colored films or opaque films. When the below-described wire embedding layer, insulating layer, and adhesive layer are light (ultraviolet) curable, a transparent film or a colored transparent film is selected. Note that a wire embedding layer, an insulating layer, an adhesive layer, and a heat-resistant insulating film, which will be described later, may be collectively referred to as a “sheet constituent layer”.

In the method for manufacturing a semiconductor device according to the present invention, as will be described later, since the sheet constituent layer is fixedly left on the back surface of the chip and picked up from the base material, the base material and the wire embedding layers 12 and 22 can be peeled off. It is laminated like this. For this reason, the surface tension of the surface of the substrate in contact with the wire embedding layer is preferably 40 mN / m or less, more preferably 37 mN / m or less, and particularly preferably 35 mN / m or less. Such a base material having a low surface tension can be obtained by appropriately selecting the material, and a mold release agent such as silicone resin or alkyd resin is applied to the surface of the base material to perform a release treatment. It can also be obtained by applying

The thickness of such a substrate is usually about 10 to 500 μm, preferably about 15 to 300 μm, and particularly preferably about 20 to 250 μm.
"Wire buried layer"
Specific examples and preferred examples of the base materials 11 and 21 in the first and second dicing / die-bonding sheets are the same.

The storage elastic modulus at 120 ° C. of the wire embedded layer is 1 × 10 ⁴ Pa or less, preferably 5.0 × 10 ³ Pa or less, more preferably 1.0 × 10 ^{2 to} 5.0 × 10 ³ Pa. It is. Further, the volume resistivity of the wire buried layer is 1 × 10 ¹³ Ω · cm or more, preferably 1.0 × 10 ¹⁴ Ω · cm or more. Furthermore, the wire embedding layer is preferably room temperature pressure-sensitive adhesive, has thermosetting properties, and further has energy ray curable properties.

  In such a dicing / die-bonding sheet of the present invention, the wire embedding layer is used as a part of the sheet constituting layer for fixing the wafer during wafer dicing, and finally for fixing the semiconductor chips together. In particular, in the manufacturing method of the stack type semiconductor device of the present invention to be described later, the semiconductor wafer is diced while being fixed with a dicing / die-bonding sheet, and then a semiconductor chip having a sheet constituting layer on the back surface is picked up from the substrate. Then, the wire buried layer transferred to the semiconductor chip is gradually buried in the wire forming surface of the substrate, and the wire buried layer surface is brought into contact with the surface of the semiconductor chip constituting the first layer. At this time, the wire forming surface is heated to a temperature slightly higher than the melting temperature of the wire embedding layer and not higher than its curing temperature. For this reason, if the wire buried layer is too soft, the thickness accuracy of the wire buried layer may be reduced. The heating temperature of the wire forming surface is not particularly limited, but is usually around 120 ° C.

  In the present invention, the storage elastic modulus at 120 ° C. of the wire embedded layer is in the above range. When the storage elastic modulus of the wire buried layer is in such a range, the wire buried layer is hardly deformed during the manufacture of the stacked semiconductor device, and the thickness accuracy of the wire buried layer is maintained.

  Further, when the wire embedded layer is too hard during the pressure contact of the semiconductor chip, the wire may be crushed or disconnected. On the other hand, when the wire buried layer is too soft, the wire buried layer is fluidized, and various problems due to poor thickness accuracy of the wire buried layer occur. Note that the storage elastic modulus of the wire embedded layer is measured at 120 ° C. by a dynamic viscoelasticity measuring device at a measurement frequency of 1 Hz.

  In the present invention, the wire buried layer is preferably thermosetting and energy ray curable as described above. In this case, the above-mentioned various physical properties excluding volume resistivity show characteristics before energy curing after energy beam curing. The volume resistivity indicates a value after thermosetting.

  The wire buried layer eventually constitutes a part of the semiconductor device and has a function of preventing a short circuit of the wire and an electrical connection between the wire and the semiconductor chip. Therefore, the wire buried layer is insulative and has a volume resistivity as described above.

The wire embedding layer preferably contains the following adhesive component (A), thermosetting component (B), and energy ray curable component (C), and, if necessary, other additives (D) are blended. .
Hereinafter, the components (A) to (D) will be described.

"Adhesive component (A)"
As the adhesive component (A), an acrylic polymer is usually preferably used. Examples of the repeating unit of the acrylic polymer include a repeating unit derived from a (meth) acrylic acid ester monomer and a (meth) acrylic acid derivative. Here, as the (meth) acrylic acid ester monomer, (meth) acrylic acid cycloalkyl ester, (meth) acrylic acid benzyl ester, and (meth) acrylic acid alkyl ester having 1 to 18 carbon atoms in the alkyl group are used. . Among these, (meth) acrylic acid alkyl esters in which the alkyl group has 1 to 18 carbon atoms are particularly preferable, such as methyl acrylate, methyl methacrylate, ethyl acrylate, ethyl methacrylate, propyl acrylate, and propyl methacrylate. Butyl acrylate, butyl methacrylate and the like are used. Examples of (meth) acrylic acid derivatives include glycidyl (meth) acrylate.

  In particular, it preferably includes a glycidyl (meth) acrylate unit and at least one alkyl (meth) acrylate unit. In this case, the content of the component unit derived from glycidyl (meth) acrylate in the copolymer is usually 0 to 80% by mass, preferably 5 to 50% by mass. By introducing a glycidyl group, compatibility with an epoxy resin as a thermosetting component described later is improved, and Tg after curing is increased, thereby improving heat resistance. As the (meth) acrylic acid alkyl ester, it is preferable to use methyl (meth) acrylate, ethyl (meth) acrylate, butyl (meth) acrylate, or the like. Further, by introducing a hydroxyl group-containing monomer such as hydroxyethyl acrylate, it becomes easy to control the adhesion to the adherend and the physical properties of the adhesive.

The weight average molecular weight of the acrylic polymer is preferably 100,000 or more, more preferably 150,000 to 1,000,000.
"Thermosetting component (B)"
The thermosetting component (B) is not cured by energy rays, but has a property of forming a three-dimensional network when heated and bonding the adherend firmly. Such a thermosetting component (B) is generally formed from a thermosetting resin such as epoxy, phenol, resorcinol, urea, melamine, furan, unsaturated polyester, and silicone, and an appropriate curing accelerator. ing. Various such thermosetting components are known, and various conventionally known thermosetting components can be used in the present invention without particular limitation. As an example of such a thermosetting component, an adhesive component composed of (B-1) an epoxy resin and (B-2) a thermally activated latent epoxy resin curing agent can be exemplified.

As the epoxy resin (B-1), conventionally known various epoxy resins are used. Usually, those having a weight average molecular weight of about 300 to 2,000 are preferred, particularly 300 to 500, preferably 330 to 400. It is desirable to use a liquid epoxy resin blended with a normal solid epoxy resin having a weight average molecular weight of 400 to 2000, preferably 500 to 1500. Moreover, the epoxy equivalent of the epoxy resin preferably used in the present invention is usually 50 to 5000 g / eq. Specific examples of such an epoxy resin include glycidyl ethers of phenols such as bisphenol A, bisphenol F, resorcinol, phenyl novolak, and cresol novolac; glycidyl ethers of alcohols such as butanediol, polyethylene glycol, and polypropylene glycol; Glycidyl ethers of carboxylic acids such as phthalic acid, isophthalic acid and tetrahydrophthalic acid; glycidyl type or alkyl glycidyl type epoxy resins in which active hydrogen bonded to a nitrogen atom such as aniline isocyanurate is substituted with a glycidyl group; vinylcyclohexane diepoxide; 3,4-epoxycyclohexylmethyl-3,4-dicyclohexanecarboxylate, 2- (3,4-epoxy) cyclohexyl-5,5-spiro (3,4- Such as in the epoxy) cyclohexane -m- dioxane, carbon in the molecule - epoxy is introduced by for example oxidation to carbon double bond include a so-called alicyclic epoxides. Further, a dicyclopentadiene skeleton-containing epoxy resin having a dicyclopentadiene skeleton and a reactive epoxy group in the molecule may be used.

Among these, in the present invention, bisphenol glycidyl type epoxy resin, o-cresol novolac type epoxy resin and phenol novolac type epoxy resin are preferably used.

These epoxy resins can be used alone or in combination of two or more.
The thermally activated latent epoxy resin curing agent (B-2) is a type of curing agent that does not react with the epoxy resin at room temperature but is activated by heating at a certain temperature or more and reacts with the epoxy resin.

  The activation method of the thermally activated latent epoxy resin curing agent (B-2) includes a method in which an active species (anion, cation) is generated by a chemical reaction by heating; A method in which a dispersion is stably dispersed and dissolved with an epoxy resin at a high temperature to start a curing reaction; a method in which a molecular sieve encapsulated type curing agent is eluted at a high temperature to start a curing reaction; a method using a microcapsule, etc. Exists.

  These thermally activated latent epoxy resin curing agents can be used singly or in combination of two or more. Of these, dicyandiamide, an imidazole compound or a mixture thereof is particularly preferable.

  The thermally activated latent epoxy resin curing agent (B-2) as described above is usually 0.1 to 20 parts by mass, preferably 0.5 to 15 parts by mass with respect to 100 parts by mass of the epoxy resin (B-1). Parts, particularly preferably 1 to 10 parts by weight.

"Energy ray curable component (C)"
The wire buried layer is preferably blended with an energy ray curable component (C). By curing the energy ray curable component (C), the adhesive strength of the wire embedding layer can be reduced, so that delamination between the substrate and the wire embedding layer can be easily performed.

  The energy ray curable component (C) is a compound that is polymerized and cured when irradiated with energy rays such as ultraviolet rays and electron beams. Specifically, this energy beam polymerizable compound includes trimethylolpropane triacrylate, tetramethylolmethane tetraacrylate, pentaerythritol triacrylate, dipentaerythritol monohydroxypentaacrylate, dipentaerythritol hexaacrylate, or 1,4-butylene glycol. Acrylate compounds such as diacrylate, 1,6-hexanediol diacrylate, polyethylene glycol diacrylate, oligoester acrylate, urethane acrylate oligomer, epoxy-modified acrylate, polyether acrylate, and itaconic acid oligomer are used. Such a compound has at least one polymerizable double bond in the molecule, and usually has a weight average molecular weight of about 100 to 30,000, preferably about 300 to 10,000.

Furthermore, as another example of the energy beam polymerizable compound, a compound having a dicyclopentadiene skeleton can be used.
The energy ray-curable component (C) is 0 to 50 parts by mass, preferably 1 to 30 parts by mass, particularly preferably 2 to 20 parts by mass, with respect to 100 parts by mass in total of the components (A) and (B). Used at a rate of about parts.

  The adhesive composition containing the energy ray-curable component (C) as described above is cured by irradiation with energy rays. Specifically, ultraviolet rays, electron beams, etc. are used as the energy rays.

When ultraviolet rays are used as energy rays, the polymerization curing time and the amount of light irradiation can be reduced by mixing a photopolymerization initiator.
Specific examples of such a photopolymerization initiator include benzophenone, acetophenone, benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzoin isobutyl ether, benzoin benzoic acid, methyl benzoin benzoate, benzoin dimethyl ketal, 2,4-diethylthioxanthone, α-hydroxycyclohexyl phenyl ketone, benzyldiphenyl sulfide, tetramethylthiuram monosulfide, azobisisobutyronitrile, benzyl, dibenzyl, diacetyl, β-chloranthraquinone or 2,4,6 -Trimethyl benzoyl diphenyl phosphine oxide etc. are mentioned.

The photopolymerization initiator is used in an amount of about 0.01 to 20 parts by mass, preferably about 0.1 to 15 parts by mass with respect to 100 parts by mass of the energy ray curable component (C).
"Other ingredients (D)"
A coupling agent (D1) may be blended in the wire embedding layer. The coupling agent (D1) desirably has a group that reacts with the functional groups of the components (A) to (C), preferably the component (B).

  The coupling agent (D1) is considered to react with the thermosetting component (B) (particularly preferably epoxy resin) during the curing reaction, and without impairing the heat resistance of the cured product. Adhesion and adhesion can be improved, and water resistance (moisture heat resistance) is also improved.

  The coupling agent (D1) is preferably a silane (silane coupling agent) because of its versatility and cost merit. The coupling agent (D1) is usually 0.1 to 20 parts by weight, preferably 0.3 to 15 parts by weight, particularly preferably 100 parts by weight of the thermosetting component (B). It is used at a ratio of 0.5 to 10 parts by mass.

In order to adjust the initial adhesive force and cohesive force of the wire embedding layer, a crosslinking agent (D2) such as an organic polyvalent isocyanate compound or an organic polyvalent imine compound can also be added.
Examples of the organic polyvalent isocyanate compounds include aromatic polyvalent isocyanate compounds, aliphatic polyvalent isocyanate compounds, alicyclic polyvalent isocyanate compounds, trimers of these polyvalent isocyanate compounds, Examples thereof include terminal isocyanate urethane prepolymers obtained by reacting a polyvalent isocyanate compound and a polyol compound. Specific examples of the organic polyvalent isocyanate compound include 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate, 1,3-xylylene diisocyanate, and 1,4-xylene diisocyanate. Narate, diphenylmethane-4,4′-diisocyanate, diphenylmethane-2,4′-diisocyanate, 3-methyldiphenylmethane diisocyanate, hexamethylene diisocyanate, isophorone diisocyanate, dicyclohexylmethane-4,4 ′ -Diisocyanate, dicyclohexylmethane-
2,4'-diisocyanate, lysine isocyanate and the like.

Specific examples of the organic polyvalent imine compound include N, N′-diphenylmethane-4,4′-bis (1-aziridinecarboxamide), trimethylolpropane-tri-β-aziridinylpropionate, tetramethylol. Examples thereof include methane-tri-β-aziridinylpropionate, N, N′-toluene-2,4-bis (1-aziridinecarboxamide) triethylenemelamine, and the like. The crosslinking agent (D2) as described above is usually blended at a ratio of 0.1 to 20 parts by mass, preferably 0.2 to 10 parts by mass with respect to 100 parts by mass of the adhesive component (A).

  Moreover, in order to control the thermal responsiveness (melt physical property) of a wire embedding layer, you may mix | blend the thermoplastic resin (D3) which has a glass transition point at 60-150 degreeC. Examples of the thermoplastic resin (D3) include polyester resin, polyvinyl alcohol resin, polyvinyl butyral, polyvinyl chloride, polystyrene, polyamide resin, cellulose, polyethylene, polyisobutylene, polyvinyl ether, polyimide resin, phenoxy resin, polymethyl methacrylate, styrene. -An isoprene-styrene block copolymer, a styrene-butadiene-styrene block copolymer, etc. are mentioned. Among these, polyester resins and phenoxy resins are particularly preferable because of excellent compatibility with other components of the wire embedding layer.

  The blending ratio of the thermoplastic resin (D3) in the wire embedding layer is preferably 1 to 50 parts by weight, more preferably 2 to 40 parts per 100 parts by weight in total of the adhesive component (A) and the thermosetting component (B). It is used in a proportion of 3 parts by mass, particularly preferably 3 to 30 parts by mass. Further, when an acrylic polymer is used as the adhesive component (A), the weight ratio of the acrylic polymer to the thermoplastic resin (acrylic polymer / thermoplastic resin) is 9/1 to 3/7. Preferably it is.

  In addition, fillers such as asbestos, silica, glass, mica, chromium oxide, titanium oxide, and pigment may be added to the wire embedding layer. These fillers may be blended at a ratio of about 0 to 400 parts by mass with respect to 100 parts by mass in total of the components (excluding the filler) constituting the wire embedding layer.

The wire embedding layer of the present invention has the physical properties as described above.
The first factor that affects the physical properties of the wire embedding layer is the ratio of the adhesive component (A) and the thermosetting component (B) in the blend. Since the adhesive component (A) is a high molecular weight substance, the fluidity during heating is inhibited as the addition amount increases, and the fluidity is exhibited when the addition amount is small. On the other hand, the thermosetting component (B) has a low molecular weight, does not change by irradiation with energy rays, and exhibits fluidity. Therefore, in order to show appropriate fluidity and to have fluidity that does not bleed, the blending amount of the adhesive component (A) with respect to the thermosetting component (B) is important. A preferable blending ratio of the thermosetting component (B) is preferably 10 to 10 parts by mass of the total of the pressure-sensitive adhesive component (A) and the thermosetting component (B) ((A) + (B)). 99 mass parts, More preferably, it is 50-97 mass parts, Most preferably, it is 83-95 mass parts.

  In addition, when the wire embedded layer includes the energy beam curable component (C), the wire embedded layer is die-bonded after curing the energy beam curable component. Since the density is increased and the wire embedding layer is hardened, the fluidity is lowered and the die bonding property is deteriorated.

Furthermore, when a thermoplastic resin is contained in a large amount, the fluidity becomes excessive, and a desired elastic modulus and melt viscosity may not be obtained.
Therefore, when the energy beam curable component (C) and the thermoplastic component are blended, the blending ratio thereof is appropriately selected within the above-described range so as to meet the intended elastic modulus and melt viscosity.

The thickness of the wire-embedded layer composed of the above components is −5 more than the wire height (the distance between the top of the wire and the upper surface of the semiconductor chip to which the wire is connected, “A” shown in FIG. 5). A thickness of about ˜50 μm is preferred. Although the wire height varies depending on the type of semiconductor device and the manufacturing method, it is generally about 20 to 80 μm, so the thickness of the wire buried layer is 15 to 130 μm.
In view of coating workability, it is preferably 40 to 100 μm. If the wire buried layer is thin, the wire may penetrate the wire buried layer, contact the back surface of the chip, and be deformed. In some cases, the wire may also penetrate the insulating layer. When the wire penetrates the insulating layer, the semiconductor chip laminated on the upper surface and the wire come into contact with each other and short-circuit. Moreover, if the thickness of the wire embedding layer is thin, there is a risk of disconnection due to bonding pressure.

  The wire embedding layer composed of the above-mentioned preferred components has pressure-sensitive adhesiveness and heat-curing property, and adheres to the base material during dicing and contributes to fixing of the wafer. It can be used as an adhesive that bonds the wire forming surface to the wire forming surface. In particular, since the wire embedding layer of the present invention exhibits the unique high-temperature properties as described above, the wire is not damaged even when pressed against the heated wire forming surface, and the wire embedding layer is fluidized. Therefore, the thickness accuracy of the wire embedding layer is not impaired. Finally, a cured product with high impact resistance can be obtained through thermal curing, and it has an excellent balance between shear strength and peel strength, and can maintain sufficient adhesive properties even under severe heat and humidity conditions. .

"Insulating layer 13"
In the first dicing / die-bonding sheet 10 according to the present invention, an insulating layer 13 is laminated on the wire embedding layer 12. The insulating layer 13 is located on the lower surface of the semiconductor chip constituting the second or higher stage in the stacked semiconductor device. For this reason, even if the wire connected to the lower semiconductor chip penetrates the wire embedding layer, the insulating layer 13 prevents the wire from contacting the upper chip. For this purpose, the insulating layer 13 has a higher storage elastic modulus (120 ° C.) than the wire buried layer 12. If the storage elastic modulus of the insulating layer 13 is approximately the same as that of the wire buried layer, the wire penetrating the wire buried layer may also penetrate the insulating layer 13 and the wire and the upper chip may come into contact with each other.

For this reason, the elastic modulus ratio (insulating layer / wire embedding layer) of the insulating layer and the wire embedding layer at 120 ° C. is 10 or more, preferably 15 to 10 ⁶ times. The elastic modulus of the insulating layer 13 is
It is measured in the same manner as the wire buried layer.

  The insulating layer 13 finally constitutes a part of the semiconductor device and has a function of preventing electrical connection between the wire and the semiconductor chip. Therefore, the insulating layer 13 has the same volume resistivity as that of the wire buried layer.

  The first dicing / die-bonding sheet 10 of the present invention is adhered to an adherend such as a semiconductor wafer by an insulating layer 13 and is fixed during the dicing process. When the insulating layer 13 is applied to the adherend, it may be heated. However, if excessive heating is performed, the wire embedding layer fluidizes as described above, and the thickness accuracy of the wire embedding layer can be maintained. There is no fear. Therefore, the insulating layer 13 has adhesiveness that can be attached to an adherend such as a semiconductor wafer at a temperature of 60 ° C. or lower, preferably 40 ° C. or lower.

  The composition of the insulating layer 13 is not particularly limited as long as it has the above-mentioned physical properties, but it is preferably thermosetting and has energy ray-curing properties like the wire embedded layer 12. In this case, the above-mentioned various physical properties indicate characteristics after energy beam curing and before heat curing.

Therefore, a preferred composition example of the insulating layer 13 is the same as that exemplified for the wire buried layer 12. In this case, the composition of the insulating layer 13 is appropriately set so that the elastic modulus ratio (insulating layer / wire embedded layer) of the insulating layer and the wire embedded layer at 120 ° C. is 10 or more. As a specific method, the blending ratio of the epoxy resin (B) to the adhesive component (A) is set so that the value of the insulating layer is larger than the value of the wire embedding layer. By providing a difference in the blending ratio of the adhesive component (A) having a high molecular weight in this manner, the fluidity is drastically reduced at the interface between the wire embedding layer and the insulating layer, and the wire is deformed to penetrate to the back of the chip Can be prevented.

  When the energy ray curable component (C) or the crosslinking agent (D2) is used, the blending ratio in the insulating layer should be larger than the ratio of the component (C) in the wire embedding layer. The same effect can be obtained by.

  In addition, the molecular weight of the adhesive component of the insulating layer is made higher than that of the adhesive component of the wire embedding layer, the Tg of the epoxy resin of the insulating layer is made higher than the epoxy resin of the wire embedding layer, the filler The elastic modulus of the insulating layer and the wire buried layer can also be adjusted by adjusting the addition amount. By blending the insulating layer and the wire embedding layer in this way, the elastic modulus ratio (insulating layer / wire embedding layer) at 120 ° C. is appropriately set to be 10 or more.

  The thickness of the insulating layer 13 is sufficient as long as the contact between the semiconductor chip and the wire can be prevented, even when the wire penetrates the wire embedded layer, preferably 1 to 50 μm, more preferably 5 to 30 μm.

"Heat-resistant insulating film 24"
In the second dicing / die-bonding sheet 20 according to the present invention, a laminate of the heat-resistant insulating film 24 and the adhesive layer 23 is used instead of the insulating layer 13 of the first dicing / die-bonding sheet 10. . That is, as shown in FIG. 2, the second dicing / die-bonding sheet 20 includes a base material 21, a wire embedding layer 22 detachably laminated on the base material 21, and the wire embedding layer 22. It consists of a heat resistant insulating film 24 laminated on top and an adhesive layer 23 formed on the heat resistant insulating film 24.

The base material 21 and the wire embedding layer 22 are the same as those described in the first dicing / die-bonding sheet.
The heat-resistant insulating film 24 used for the second dicing / die-bonding sheet 20 is interposed between the wire embedding layer 22 and the adhesive layer 23, and the wire connected to the lower semiconductor chip has the wire embedding layer. Even in the case of penetration, the heat-resistant insulating film 24 prevents contact between the wire and the upper chip. Therefore, the heat-resistant insulating film 24 is
In order to prevent electrical connection between the wire and the semiconductor chip, it has the same volume resistivity as that of the wire embedding layer at the temperature at which the wire embedding layer is embedded in the wire. .

  The heat-resistant insulating film 24 desirably has a melting point of 260 ° C. or higher, more preferably 300 ° C. or higher. Even a film having no melting point may have a thermal decomposition temperature of 260 ° C. or higher. Examples of such a heat resistant insulating film 24 include a polyethylene terephthalate film, a polyethylene naphthalate film, a polybutylene terephthalate film, a polyimide film, a polyetherimide film, a polyaramid film, a polyetherketone film, and a polyetheretherketone film. , A polyphenylene sulfide film, a polyethersulfone film, a poly (4-methylpentene-1) film, a liquid crystal polymer film, and the like are used, and a polyimide film and a liquid crystal polymer film are preferably used.

The thickness of the heat-resistant insulating film 24 is not particularly limited, but is preferably 5 to 100 μm, more preferably 10 to 50 μm, and particularly preferably 10 to 30 μm in consideration of operability.
It is.

"Adhesive layer 23"
In the second dicing / die-bonding sheet 20, an adhesive layer 23 is laminated on the heat-resistant insulating film 24.

  In the second dicing / die-bonding sheet 20, the adhesive layer 23 fixes an adherend such as a semiconductor wafer in the dicing process. Since the adhesive layer 23 eventually constitutes a part of the semiconductor device, it is preferably insulative and has a volume resistivity similar to that of the wire embedding layer. In the finally obtained semiconductor device, the adhesive layer 23 is preferably in a cured state from the viewpoints of heat resistance and durability.

  Accordingly, a preferred example of the adhesive layer 23 is the same as that described with respect to the wire embedding layer 12 and the insulating layer 13 and preferably has thermosetting properties, but energy beam curable properties are not necessarily required. Further, the elastic modulus is not particularly limited.

"Dicing / Die Bond Sheet"
The first dicing / die-bonding sheet 10 has a structure in which a wire embedding layer 12 is detachably laminated on a substrate 11 and an insulating layer 13 is laminated on the wire embedding layer 12. In order to protect 13, a release film may be laminated on the upper surface of the insulating layer 13. As the release film, a general-purpose release film obtained by subjecting a film such as polyethylene terephthalate to a release treatment with a release agent such as a silicone resin can be used.

  The manufacturing method of such a dicing / die-bonding sheet 10 is not particularly limited, and is manufactured by sequentially applying and drying the composition constituting the wire embedding layer 12 and the insulating layer 13 on the substrate 11. Alternatively, a wire embedding layer and an insulating layer may be provided on separate release films and transferred to a substrate in sequence.

Further, a ring frame fixing adhesive sheet for fixing the ring frame may be provided on the outer peripheral portion of the surface of the insulating layer 13.
In the second dicing / die-bonding sheet 20, the wire embedding layer 22 is detachably laminated on the base material 21, and the heat resistant insulating film 24 and the adhesive layer 23 are sequentially laminated on the wire embedding layer 22. It is the structure which was made. Similarly to the first dicing / die-bonding sheet, the above-described release film may be laminated in order to protect the adhesive layer 23.

  The method for producing such a dicing / die-bonding sheet 20 is not particularly limited, and the composition constituting the wire embedding layer 22 is applied and dried on the substrate 21, and the heat-resistant insulating film 24 is formed thereon. It is also possible to manufacture by laminating and sequentially applying and drying the composition constituting the adhesive layer 23. Also, the wire embedding layer and the insulating layer are provided on separate release films, respectively. You may manufacture by transferring to a material, laminating | stacking the heat resistant insulating film 24 on it, and also transferring the adhesive bond layer 23 further.

Further, a ring frame fixing adhesive sheet for fixing the ring frame may be provided on the outer peripheral portion of the surface of the insulating layer 23.
In the following description, the sheet constituting layer means the wire embedding layer 12 and the insulating layer 13 in the first dicing / die-bonding sheet 10, and in the second dicing / die-bonding sheet 20, The wire embedding layer 22, the heat-resistant insulating film 24, and the adhesive layer 23 are meant.

"Manufacturing method of stack type semiconductor device"
Next, a method for manufacturing a stacked semiconductor device according to the present invention using the dicing / die-bonding sheet will be described. Hereinafter, the first dicing / die-bonding sheet 10 will be described as an example, but the second dicing / die-bonding sheet 20 can also be applied to the same process.

In the manufacturing method of the present invention, first, the insulating layer 13 of the dicing / die-bonding sheet 10 is attached to the back surface of the semiconductor wafer on which the semiconductor chip constituting the second layer of the stacked semiconductor device is formed,
The semiconductor wafer is subjected to full-cut dicing for each semiconductor chip together with the sheet constituent layer, and the semiconductor chip having the sheet constituent layer cut in the same shape as the chip on the back surface is picked up from the substrate, and the sheet constituent layer is provided on the back surface. A semiconductor chip is obtained.

  Specifically, first, as shown in FIG. 3, the dicing / die-bonding sheet 10 is fixed on the dicing apparatus by the ring frame 1, and one surface of the semiconductor wafer 2 is insulated on the dicing / die-bonding sheet 10. The wafer 2 is placed on the substrate 13 and lightly pressed to fix the wafer 2. In the second dicing / die-bonding sheet, the wafer 2 is fixed to the adhesive layer 23.

  Thereafter, when the wire embedding layer 12 has energy beam curability, the energy embedding force of the wire embedding layer 12 is increased by irradiating energy rays from the base material 11 side. Reduce the adhesive strength between the two. The energy beam irradiation may be performed after dicing, or may be performed after the expanding step described later.

  Next, using a cutting means such as a dicing saw, the semiconductor wafer 2 is cut for each circuit as shown in FIG. 4 to obtain semiconductor chips. The cutting depth at this time is a depth that takes into account the total thickness of the semiconductor wafer and the thickness of the sheet constituent layers (insulating layer 13 and wire embedding layer 12) and the amount of wear of the dicing saw. The constituent layers are also cut. In the second dicing / die-bonding sheet 20, the adhesive layer 23, the heat-resistant insulating film 24, and the wire embedding layer 22, which are sheet constituent layers, are cut together with the wafer 2.

  Then, if necessary, if the dicing / die-bonding sheet is expanded, the interval between the semiconductor chips is expanded, and the semiconductor chips can be picked up more easily. At this time, a deviation occurs between the wire embedding layer and the base material, the adhesive force between the wire embedding layer and the base material is reduced, and the pick-up property of the chip is improved.

  When the semiconductor chip is picked up in this manner, the insulating layer 13 and the wire embedding layer 12 cut in the same shape as the chip can be fixedly left on the back surface of the semiconductor chip 3 and peeled off from the substrate.

  On the other hand, separately from the above, as shown in FIG. 5, a substrate 6 on which a semiconductor chip 5 constituting a first layer to which wires 4 are connected is mounted is prepared. The wire 4 is used to electrically connect the electrode terminal on the semiconductor chip 5 and the outer lead on the substrate 6, and is usually composed of a gold wire or the like. The substrate 6 on which the semiconductor chip 5 having such a configuration is mounted can be obtained by various known methods. Further, the substrate 6 and the semiconductor chip 5 are bonded through a normal thermosetting adhesive such as an epoxy adhesive or an adhesive layer of a general-purpose dicing / die-bonding adhesive sheet. Further, it may be bonded via the wire embedding layer 3 of the dicing / die-bonding sheet 1 of the present invention.

By laminating the wire embedding layer 12 of the semiconductor chip 3 to the wire forming surface side of the semiconductor chip 5, the semiconductor chips are stacked. At this time, by heating the lower substrate 6, the wire 4 and the semiconductor chip 5 are heated to the melting temperature or higher of the wire embedded layer 12. Since the wire embedding layer 12 has the physical properties as described above, when the wire embedding layer 12 comes into contact with the wire 4, the wire embedding layer quickly melts and softens at the contact portion, and the wire embedding layer 12 is located away from the wire. Since the resin of the buried layer has little heat conducted from the wire and from the lower chip body, the melt softening is delayed. For this reason, the wire 4 is embedded in the wire embedding layer 12 without damaging the wire 4, but deformation due to melt softening is suppressed at a position away from the wire. Thereafter, the wire embedding layer 12 is brought into close contact with the surface of the semiconductor chip 5, and a predetermined pressure is applied to the wire embedding layer 12 by a bonding apparatus. At this time, most of the wire embedded layer is not yet sufficiently heated and maintains a high viscosity, and the chip does not tilt due to bleeding out of the resin from the end of the semiconductor chip or uneven bonding pressure. . After that, heat is sufficiently transferred from the lower chip body to the wire buried layer 12, but the pressurization by the bonding apparatus is finished and the hardening of the wire buried layer 12 also proceeds. It can be suppressed.

  Even if the wire embedding layer 12 is excessively softened and the wire 4 penetrates the wire embedding layer 12, the insulating layer 13 formed on the wire embedding layer 12 causes the wire 4 and the semiconductor to be The tip 3 is prevented from contacting. That is, the storage elastic modulus at 120 ° C. of the insulating layer 13 is 10 times or more the storage elastic modulus of the wire embedding layer 12, so that even if the wire embedding layer is softened, the insulating layer 13 has a certain amount of In order to maintain rigidity, the wire is prevented from penetrating the insulating layer 13. When the second dicing / die-bonding sheet 20 is used, the heat-resistant insulating film 24 performs the same function as the insulating layer 13.

  In this way, the semiconductor chip 3 is laminated on the semiconductor chip 5 as the second layer, and the electrode chip of the semiconductor chip 3 and the outer lead of the substrate 6 are connected by the wire 7, whereby the two-layer structure shown in FIG. The stack type semiconductor device is obtained. When the second dicing / die-bonding sheet 20 is used, a stack type semiconductor device having the configuration shown in FIG. 7 is obtained. In the same manner as described above, a third-layer semiconductor chip may be laminated on the surface of the second-layer semiconductor chip 3 and wire bonding may be performed, or four or five layers may be multilayered.

  In the stack type semiconductor device obtained in this way, the wire embedded layer having unique high-temperature properties is used, so that the wire is not easily crushed or disconnected, and the thickness of the wire embedded layer is inaccurate. Problems caused by the problem are also eliminated.

The obtained stack type semiconductor device may be subjected to various finishing processes known in the manufacture of semiconductor devices, such as resin sealing, if necessary.
(Example)
EXAMPLES The present invention will be described below with reference to examples, but the present invention is not limited to these examples.

In the following examples and comparative examples, “storage modulus”, “volume resistivity”, “wire penetration test”, and “damage to wire” were evaluated as follows.
"Storage modulus"
The wire embedding layer or the insulating layer is formed as a single layer, and the resin compositions (1), (2) and (4) of the resin layer are laminated so as to have a thickness of 200 μm, and ultraviolet rays are irradiated from both sides. The sample was further laminated to a thickness of 3 mm to obtain a measurement sample. In addition, the resin compositions (3) and (5) were laminated to a thickness of 3 mm as they were to obtain measurement samples. For these samples, the shear elastic modulus (G ′) was measured at a frequency of 1 Hz using a dynamic viscoelasticity measuring device (RDA-II manufactured by Rheometrics), and the value at 120 ° C. was stored at 120 ° C. It was.

  In addition, the storage elastic modulus of the insulating film was measured by using a dynamic viscoelasticity measuring device (Q-800 manufactured by TA Instruments Japan Co., Ltd.), with a temperature rising rate of 3 ° C./min and a frequency of 1 Hz. The rate (E ′) was measured to calculate G ′ = E ′ / 3, and G ′ at 120 ° C. was defined as the storage elastic modulus at 120 ° C.

"Volume resistivity"
Regarding the wire embedding layer, the insulating layer, and the adhesive layer, a resin layer for forming these was laminated so as to have a thickness of 200 μm, irradiated with ultraviolet rays from both sides, and cured by heating to obtain a sample. The heat curing conditions were 160 ° C. and 60 minutes.

The volume resistivity of the obtained sample and the heat-resistant insulating film was measured using a digital electrometer (R8252 manufactured by Advantest).
"Wire penetration test", "Damaged wire"
About the semiconductor device manufactured by the Example and the comparative example, the continuity test of the wire wired by the semiconductor chip of the 1st layer was performed, and the presence or absence of the damage to the back of a chip | tip and the wire was evaluated.

Each component which comprises a wire embedding layer, an insulating layer, and an adhesive bond layer is demonstrated below.
Adhesive component A1: Weight average molecular weight of about 800, obtained by copolymerizing 55 parts by mass of butyl acrylate, 10 parts by mass of methyl acrylate, 20 parts by mass of glycidyl methacrylate, and 15 parts by mass of 2-hydroxyethyl acrylate. 000, copolymer having a glass transition temperature of -28 ° C. Adhesive component A2: weight average molecular weight of about 800,000, glass transition obtained by copolymerizing 85 parts by mass of methyl acrylate and 15 parts by mass of 2-hydroxyethyl acrylate Copolymer having a temperature of 4 ° C. Thermosetting component B1: Acrylic rubber fine particle dispersed bisphenol A type liquid epoxy resin (manufactured by Nippon Shokubai Co., Ltd., BPA 328, epoxy equivalent 230)
Thermosetting component B2: bisphenol A type solid epoxy resin (manufactured by Nippon Shokubai Co., Ltd., Epicoat 1055, epoxy equivalent 875-975)
Thermosetting component B3: o-cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., EOCN-104S,
Epoxy equivalents 213 to 223)
Thermosetting component B4: Oligomer type modified bisphenol A type liquid epoxy resin (Dainippon Ink, Epicron EXA-4850-150)
Thermosetting component B5: Dicyandiamide curing agent (Adeka Hardener 3636AS, manufactured by Asahi Denka Co., Ltd.)
Thermosetting component B6: Imidazole curing accelerator (Shikoku Kasei Kogyo Co., Ltd. Curesol 2PHZ)
Energy ray curable component C1: Dipentaerythritol hexaacrylate (Nippon Kayaku Co., Ltd., Kayarad DPHA)
Energy ray-curable component C2: Dicyclopentadiene skeleton-containing acrylate (Kayarad R684, manufactured by Nippon Kayaku Co., Ltd.)
Photopolymerization initiator C3: 2,4,6-trimethylbenzoyldiphenylphosphine oxide)
Other ingredients:
D1: Silane coupling agent (MKC silicate MSEP2 manufactured by Mitsubishi Chemical Corporation)
D2: Polyisocyanate-based cross-linking agent (manufactured by Toyo Ink Manufacturing Co., Ltd., Olivevine BHS8515)
D3: Flexible component (byron 220, manufactured by Toyobo Co., Ltd.)
The composition of each component constituting the wire embedding layer, the insulating layer and the adhesive layer and the physical properties of the blended resin composition are shown below.

Moreover, Ube Industries UL-27 was used as a polyimide resin. The elastic modulus at 120 ° C. of the resin was 3.0 × 10 ⁵ Pa, and the volume resistivity was 2.3 × 10 ¹⁴ W · cm.
In addition, as a polyimide film, Kapton 100H (thickness 25 μm) manufactured by Toray DuPont was used. The elastic modulus at 120 ° C. of the film was 6.3 × 10 ⁸ Pa, and the volume resistivity was 1.0 × 10 ¹⁵ W · cm.

Example 1
(1) Manufacture of sheet for dicing and die bonding The roll of resin composition (2) is applied to the release-treated surface of a release film (manufactured by Lintec Corporation, thickness 38 μm, SP-PET 3811) so that the dry film thickness is 40 μm. It was applied using a knife coater, dried (100 ° C., 2.5 minutes), and laminated on a 100 μm-thick base material (polyethylene film, surface tension 31 mN / m) to obtain a resin layer for a buried wire layer. Similarly, the resin composition (1) was applied to the release treatment surface of a release film (Lintec Corporation, thickness 38 μm, SP-PET 3811) using a roll knife coater so that the dry film thickness was 20 μm. A resin layer for an insulating layer was produced by drying (100 ° C., 1.5 minutes), and the release film was laminated while peeling the release film from the resin layer for wire embedding layer to produce a sheet.

As a pressure-sensitive adhesive sheet for fixing a ring frame, a pressure-sensitive adhesive sheet (a shape obtained by cutting and removing a circle having an inner diameter of 165 mm) prepared by forming a re-peelable acrylic pressure-sensitive adhesive (10 μm) on a polyvinyl chloride film (80 μm) was prepared. The insulating layer surface and the polyvinyl chloride film surface of the sheet prepared above are laminated and cut into a concentric donut shape with an outer diameter of 207 mm to obtain a dicing / die-bonding sheet having a ring frame fixing adhesive sheet on the outer periphery. It was.

(2) Production of Semiconductor Chip with Wire Embedding Layer A simulated circuit (aluminum wiring) having a bonding pad portion on the mirror surface of a silicon wafer (150 mm diameter) was formed by sputtering. The back surface of this silicon wafer was ground to a thickness of 350 μm by a wafer grinding apparatus.

Next, the dicing / die-bonding sheet obtained in (1) was applied to the back of the silicon wafer with a tape laminator (Lintec, Adwill RAD2500m / 8) at a table temperature of 40.
The mixture was heated to 0 ° C. and attached, and fixed to a dicing ring frame (Disco, 2-6-1). Thereafter, the substrate was irradiated with ultraviolet rays (illuminance 350 mW / cm ² , light amount 180 mJ / cm ² ) using an ultraviolet irradiation device (Adwill RAD2000, manufactured by Lintec Corporation). Next, the silicon wafer was diced to a chip size of 5.0 × 5.0 mm using a dicing apparatus (AWD-4000B, manufactured by Tokyo Seimitsu Co., Ltd.). At this time, the substrate was further cut by 20 μm beyond the wire embedding layer.

(3) Manufacture of a two-stage stack type semiconductor device A glass epoxy substrate (90 μm) coated with a solder resist was prepared as a simulated substrate for an IC package. In addition, copper foil, nickel plating, and gold plating are patterned in order on the part where the solder resist on one side of the simulated board is not applied to form a wire bond terminal, and a solder ball mounting area provided on the opposite side of the simulated board and Conducted via hole.

The die-bonding device (manufactured by NEC Machinery Co., Ltd., CPS-100) is prepared by using the semiconductor chip with a buried wire layer (still fixed to the dicing / die-bonding sheet) created in (2) above.
), And pressure-bonded to the die pad portion of the simulated substrate under the conditions of 120 ° C., 60 kPa, 1 second, and then the wire embedded layer is cured under the conditions of 160 ° C., 60 minutes, so that the first layer semiconductor The chip was mounted on the chip. Next, wire bond equipment (made by Shinkawa, UTC-400)
Thus, wire bonding was performed between the die pad portion of the first-layer semiconductor chip and the die pad portion of the substrate. At this time, the wire height was about 40 μm.

  Further, the die bonding step and the wire bonding step of the second layer semiconductor chip were performed on the upper surface of the first layer semiconductor chip under the same conditions and the same conditions as those of the first layer semiconductor chip. .

(Example 2)
The resin composition (2) is applied to a release-treated surface of a release film (manufactured by Lintec Corporation, thickness 38 μm, SP-PET 3811) using a roll knife coater so that the dry film thickness is 50 μm and dried (100 And laminated on a 100 μm-thick base material (polyethylene film, surface tension 31 mN / m) to obtain a resin layer for a buried wire layer. Next, the resin composition (3) was applied to a polyimide film (Kapton 100H manufactured by Toray DuPont Co., Ltd., thickness 25 μm) using a roll knife coater so that the dry film thickness was 10 μm, and dried (100 ° C., 1 minute) to prepare a laminated sheet of the heat-resistant insulating film and the adhesive layer. While peeling the release film from the wire embedding layer resin layer, the polyimide film side of the laminated sheet was laminated on the wire embedding layer resin layer to prepare a sheet.

Thereafter, a dicing / die-bonding sheet was obtained in the same manner as in Example 1.
(Example 3)
A dicing / die-bonding sheet was obtained in the same manner as in Example 1 except that the resin composition (5) was used as the wire embedding layer.

(Comparative Example 1)
A thermoplastic polyimide resin (UL-27 manufactured by Ube Industries) was used as the insulating layer, and dried at 130 ° C. for 2.5 minutes to prepare an insulating layer resin layer. Further, a resin layer for a wire embedding layer was prepared in the same manner as in Example 1, and a resin layer for an insulating layer was laminated while peeling the release film from the resin layer for wire embedding layer, thereby producing a sheet.

  A double-sided pressure-sensitive adhesive sheet prepared by further providing a strong pressure-sensitive adhesive layer (10 μm) on the polyvinyl chloride film side of the pressure-sensitive adhesive sheet for fixing the ring frame used in Example 1 and cutting the same size as in Example 1 was prepared. The double-sided pressure-sensitive adhesive sheet of the double-sided pressure-sensitive adhesive sheet is laminated with the insulating layer surface of the sheet prepared above, cut into a concentric donut shape having an outer diameter of 207 mm, and a dicing having a ring-frame fixing pressure-sensitive adhesive sheet on the outer periphery -A die bond combined sheet was obtained.

(Comparative Example 2)
A dicing / die-bonding sheet was obtained in the same manner as in Example 1 except that the resin composition (4) was used as the insulating layer.

(Comparative Example 3)
A dicing / die-bonding sheet was obtained in the same manner as in Example 1 except that the resin composition (1) was used as the wire embedding layer.

  The results are shown in Table 2.

1) Second dicing / die-bonding sheet 2) Polyimide film 3) Polyimide resin 4) Heating at 100 ° C. failed to attach to the wafer.

  According to the present invention, a dicing / die-bonding sheet that can be attached to a semiconductor wafer without requiring complicated temperature control is provided. According to the present invention, in a so-called stack type semiconductor device, bonding wire damage occurring during stacking is reduced. In addition, the variation in the height of the semiconductor device due to poor thickness accuracy of the adhesive layer that bonds the semiconductor chips to each other, the variation in the height from the substrate to the surface of the uppermost semiconductor chip, and the uppermost semiconductor chip This can eliminate the inclination and contribute to improvement of the quality and productivity of the semiconductor device.

1 shows a first dicing / die-bonding sheet according to the present invention. The 2nd dicing die-bonding sheet | seat which concerns on this invention is shown. One process of the manufacturing method concerning this invention is shown. One process of the manufacturing method concerning this invention is shown. One process of the manufacturing method concerning this invention is shown. 1 shows an example of a stacked semiconductor device obtained by the present invention. 1 shows an example of a stacked semiconductor device obtained by the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ring frame 2 ... Semiconductor wafer 3 ... Semiconductor chip (Chip for stacks (2nd layer))
4, 7 ... Wire 5 ... Semiconductor chip (bottom chip (first layer))
6 ... Substrate 10, 20 ... Dicing / die-bonding sheet 11, 21 ... Base material 12, 22 ... Wire embedding layer 13 ... Insulating layer 23 ... Adhesive layer 24 ... Heat resistant insulating film

Claims (5)

A substrate, a wire embedding layer that is releasably laminated on the substrate, and an insulating layer that is laminated on the wire embedding layer,
A storage modulus at 120 ° C. of the wire buried layer is ^{1.0 × 10 2 ~ 1 × 10} 4 P a,
The insulating layer has adhesiveness that can be attached to a semiconductor wafer at a temperature of 60 ° C. or less,
The blending ratio of the energy beam curable component (C) in the insulating layer is larger than the blending ratio of the energy beam curable component (C) in the wire embedded layer,
The storage elastic modulus ratio (insulating layer / wire embedding layer) of the insulating layer and the wire embedding layer at 120 ° C. is 10 or more,
However, the storage elastic modulus is the value after energy ray curing,
Wire buried layer and the volume resistivity of the insulating layer der both 1 × 10 ¹³ Ω · cm or more is,
A dicing / die-bonding sheet used for bonding and fixing between semiconductor chips of a stacked semiconductor device . The wire embedding layer includes an adhesive component (A), a thermosetting component (B), and an energy ray curable component (C), and has thermosetting property and energy ray curable property,
The insulating layer includes an adhesive component (A), a thermosetting component (B), and an energy ray curable component (C), and has thermosetting property and energy ray curable property.
The dicing / die-bonding sheet according to claim 1 . In the wire embedding layer, the blending ratio of the thermosetting component (B) is 10 to 99 parts by mass in a total of 100 parts by mass of the adhesive component (A) and the thermosetting component (B). The dicing die-bonding of Claim 2 whose compounding ratio of a sclerosing | hardenable component (C) is 1-50 mass parts with respect to a total of 100 mass parts of an adhesion component (A) and a thermosetting component (B). Combined seat. The dicing / die-bonding sheet according to any one of claims 1 to 3 is affixed to a back surface of a semiconductor wafer on which a semiconductor chip constituting an upper layer than the second layer of the stacked semiconductor device is formed,
For each semiconductor chip, the semiconductor wafer is subjected to full-cut dicing together with an insulating layer and a wire embedding layer, provided that energy rays are irradiated from the base material side of the sheet before or after dicing,
Pick up a semiconductor chip having an insulating layer and a wire embedding layer on the back surface from the substrate,
Separately, preparing a substrate on which a semiconductor chip constituting the first layer to which wires are connected is mounted, heating the substrate,
A method of manufacturing a stacked semiconductor device, comprising: embedding a wire embedding layer surface of the semiconductor chip in a wire forming surface of the substrate, and bringing the wire embedding layer surface into contact with a semiconductor chip surface constituting a first layer. The manufacturing method of a stack type semiconductor device according to claim 4, wherein the substrate and the semiconductor chip constituting the first layer are heated by heating the substrate.

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