JP4658987B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simply and accurately execute change in the arrangement of bonding pads. <P>SOLUTION: A semiconductor chip 40, having a plurality of bonding pads 41, is firmly fixed on a die pad 31. A relay chip 50 is firmly fixed on the semiconductor chip 40. The relay chip 50 has a plurality of bonding pads 51, and the bonding pads 51 are connected with one another via a wiring pattern 52 of a multilayer wiring structure, to change the arrangement of the bonding pads 41 on the semiconductor chip 40 side to a different direction. The bonding pads 41 are connected to the bonding pads 51 with wires 61, and the bonding pads 51 are connected to bonding pads 33 on a lead frame 30 side via wires 62. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device to be mounted by wire bonding.

  2. Description of the Related Art Conventionally, semiconductor devices in package forms such as SOP (Small Outline Package), DIP (Dual Inline Package), PGA (Pin Grid Array), and QFP (Quad Flat Package) in which a semiconductor chip is contained in a package are known. In order to improve the mounting density, various semiconductor devices in the form of a multichip package in which a plurality of semiconductor chips are accommodated in one package have been proposed.

  For example, there are the following documents concerning semiconductor devices in the form of a multichip package.

JP 2000-332194 A JP 2001-7277 A

  14A and 14B are schematic configuration diagrams of a conventional SOP type semiconductor device, in which FIG. 14A is a plan view and FIG. 14B is a longitudinal sectional view. 15A and 15B are schematic configuration diagrams of a conventional SOP type semiconductor device in which the lead position for external lead is different from that in FIG. 14, and FIG. 15A is a plan view and FIG. FIG. (B) is a longitudinal sectional view.

  In the semiconductor device of FIG. 14, a semiconductor chip 20A is mounted using a lead frame 10A. As shown in FIG. 14 (A), the lead frame 10A has a die pad 11A for mounting a semiconductor chip having a substantially rectangular plane, and a plurality of lead frames 10A are vertically spaced apart from the upper and lower sides of the die pad 11A by a predetermined distance. A lead 12A is disposed. Each lead 12A is provided with a bonding pad 13A on the inner inner lead portion, and the outer outer lead portion is drawn to the outside.

  On the die pad 11A, a semiconductor chip 20A having a rectangular plane is fixed. On the surface of the semiconductor chip 20A, as shown in FIG. 14A, a plurality of bonding pads 21A are arranged in the vicinity of the upper side and the lower side corresponding to the arrangement positions of the bonding pads 13A on the lead frame side. Yes. The plurality of bonding pads 21A on the semiconductor chip side are connected to the plurality of bonding pads 13A on the lead frame side by a plurality of wires 14A. The semiconductor chip 20A and the plurality of wires 14A are resin-sealed by a resin member 15A.

  In the semiconductor device of FIG. 15, the lead frame 10B of FIG. 14 is mounted using a lead frame 10B having a different lead drawing direction. Therefore, the bonding pad arrangement position with respect to the semiconductor chip 20A of FIG. Different semiconductor chips 20B are used.

  That is, in the lead frame 10B of FIG. 15, as shown in FIG. 15A, a plurality of leads 12B are disposed in the lateral direction at a predetermined distance from the left and right sides of the die pad 11B having a rectangular plane. Yes. Each lead 12B is provided with a bonding pad 13B on the inner inner lead portion, and the outer outer lead portion is pulled out in the lateral direction.

  The semiconductor chip 20B having a rectangular plane fixed on the die pad 11B has the same function as the semiconductor chip 20A of FIG. 14, but in order to correspond to the arrangement position of the bonding pad 13B on the lead frame side, In addition, it is newly created separately from the semiconductor chip 20A of FIG. 14 so that a plurality of bonding pads 21B are arranged in the vicinity of the right side. The plurality of bonding pads 21B of the semiconductor chip 20B are connected to the plurality of bonding pads 13B on the lead frame side by a plurality of wires 14B, and then the semiconductor chip 20B and the plurality of wires 14B are made of resin. Resin-sealed by the member 15B.

  16A, 16B, and 16C are schematic configuration diagrams showing a conventional semiconductor device in the form of a multichip package. FIG. 16A is a plan view seen from the surface, and FIG. ) Is a bottom view seen from the back side, and FIG. 10C is a longitudinal sectional view. Elements common to those in FIG. 15 are denoted by common reference numerals.

  In this semiconductor device, for example, for the purpose of doubling the memory capacity, semiconductor chips 20B and 20C having the same function are mounted on both the front and back surfaces of the die pad 11B of the lead frame 10B as shown in FIG. .

  As shown in FIG. 16A, the lead frame 10B has a die pad 11B having a rectangular plane, and a plurality of leads 12B are arranged in a lateral direction at a predetermined distance from the left and right sides. . The plurality of leads 12B have bonding pads 13B (left bonding pads 13B-11, 13B-12,..., Right bonding pads 13B-21, 13B-22,...) On inner inner lead portions. Provided, and the outer outer lead portion is pulled out in the lateral direction.

  On the surface of the semiconductor chip 20B on the front side of the die pad 11B, a left side and a right side corresponding to the bonding pads 13B-11, 13B-12,..., 13B-21, 13B-22,. A plurality of bonding pads 21B (left bonding pads 21B-11, 21B-12,..., Right bonding pads 21B-21, 21B-22,...) Are disposed in the vicinity. The left bonding pads 21B-11, 21B-12,... Are connected to the left bonding pads 13B-11, 13B-12,. The right bonding pads 21B-21, 21B-22,... Are connected to the right bonding pads 13B-21, 13B-22,.

  When a chip having the same configuration as the front-side semiconductor chip 20B (that is, the same arrangement of bonding pads) is used as the semiconductor chip 20C on the back side of the die pad 11B, the arrangement of bonding pads is left and right as viewed from the front side of the die pad 11B. Or since it is reversed up and down, the some wire 14C cross | intersects and shorts. In order to prevent this, the semiconductor chip 20C on the back side is reversed so that the arrangement of internal element circuits and bonding pads is rotationally symmetric with respect to the semiconductor chip 20B on the front side (that is, the mirror so that the front and the back face each other). Inverted mirror chips and structures are used.

  The semiconductor chip 20C having the mirror chip structure corresponds to the bonding pads 13B-11, 13B-12,..., 13B-21, 13B-22,. Then, a plurality of bonding pads 21C (right bonding pads 21C-11, 21C-12,...) In the vicinity of the right side and the left side (as viewed from the back side, the left and right are reversed). .. Are provided on the left side bonding pads 21C-21, 21C-22,. The right bonding pads 21C-11, 21C-12,... Are connected to the left bonding pads 13B-11, 13B-12,... As viewed from the surface on the lead frame side by a plurality of wires 14C. The The right bonding pads 21C-21, 21C-22,... Are connected to the right bonding pads 13C-21, 13C-22,.

  The semiconductor chips 20B and 20C and the plurality of wires 14B and 14C are resin-sealed by the resin member 15B.

  However, the conventional semiconductor devices of FIGS. 14 and 15 and the conventional FIG. 16 have the following problems (1) and (2).

(1) Problems of Conventional FIG. 14 and FIG. 15 For example, when the semiconductor chip 20A of FIG. 14 is mounted on the package of FIG. It cannot be connected with the wire 14A. Therefore, it is necessary to newly create the semiconductor chip 20B of FIG. 15 which has the same function as the semiconductor chip 20A and moves the position of the bonding pad.

  As described above, in the semiconductor device as shown in FIGS. 14 and 15, it is necessary to design and create a semiconductor chip for the package every time the package shape is changed. Because it is necessary to verify (operation check test), a great amount of cost and development time are required. Further, by arranging the bonding pads of the semiconductor chip 20B in accordance with the package of FIG. 15, it becomes necessary to increase the chip size or to have inventory for each semiconductor chip.

  In order to eliminate such inconvenience, for example, a metal wiring film for pad position conversion described in Document 1 is provided on the semiconductor chip 20A of FIG. 14, and the semiconductor of FIG. It is also conceivable to connect the bonding pad 21A on the chip side and the bonding pad 13B on the lead frame side in FIG. 15 with a wire. Alternatively, the signal position conversion unit having the wiring pattern described in Document 2 is fixed to the die pad 11B in FIG. 15, and the semiconductor chip 20A in FIG. 14 is mounted on the signal position conversion unit. It is also conceivable to connect the bonding pads 21A on the semiconductor chip side 14 and the bonding pads 13B on the lead frame side in FIG. 15 with wires.

  However, in the configuration or method in which the metal wiring film as in Reference 1 or the signal position conversion unit as in Reference 2 is provided and wire bonding is performed between the bonding pads, the wiring structure for relaying has not been established. With the change in the position of the bonding pads on the semiconductor chip side and the lead frame side, the wiring structure for relaying, etc. will be changed. For example, when probing etc. for verification of operation confirmation, new peripheral devices There was a risk that the cost would increase significantly.

(2) Problem of Conventional FIG. 16 Since it is necessary to prepare two types of semiconductor chips, a semiconductor chip 20B on the front side and a semiconductor chip 20C on the back side which is a mirror chip thereof, the package changes each time the package shape changes. It is necessary to design and create two kinds of semiconductor chips for the purpose, and further, it is necessary to verify the quality (probing test) by probing the two kinds of created semiconductor chips. The chip size becomes large, or it is necessary to have inventory for each semiconductor chip.

  In order to eliminate such inconvenience, for example, it is conceivable to use a metal wiring film for pad position conversion described in Document 1 or a signal position conversion unit having a wiring pattern described in Document 2. Similar to the above (1), for example, when probing or the like is performed for verification of operation confirmation, a new peripheral device is required, and there is a concern that the cost may be significantly increased.

  An object of the present invention is to solve the problems of the prior art and to provide a semiconductor device capable of easily and accurately changing the arrangement of bonding pads.

  In order to solve the above problems, in a semiconductor device of the present invention, a semiconductor chip mounting substrate on which a plurality of electrodes are arranged, and a silicon substrate mounted on the substrate and having a plurality of first bonding pads are arranged. A semiconductor chip to be used, and a second bonding pad and a third bonding pad which are mounted so as to fit inside the outer edge of the surface of the semiconductor chip and to expose the first bonding pad on the semiconductor chip. And a relay chip using a silicon substrate on which a plurality of wirings that electrically connect the second bonding pad and the third bonding pad are disposed, and provided between the semiconductor chip and the relay chip A plurality of shock-absorbing materials, electrically connecting the first bonding pad and the second bonding pad, respectively. 1 wire and a plurality of second wires that electrically connect the electrode and the third bonding pad, respectively, and the relay chip has the wiring on the silicon substrate with an interlayer insulating film interposed therebetween. It is characterized by having a multilayer wiring structure laminated.

  According to the present invention, the relay chip is stacked on the semiconductor chip, and the pad arrangement is converted using the relay chip. Therefore, in order to correspond to the arrangement form of the substrate side electrode, the pad arrangement on the semiconductor chip side is changed. There is no need to change, and wire bonding can be performed to the substrate-side electrodes in various arrangement forms. In particular, since the wiring pattern of the relay chip has a multilayer wiring structure, a complicated wiring pattern can be easily formed without causing a short circuit between the wirings. Furthermore, since the relay chip is fixed so as to fit inside the outer edge of the surface of the semiconductor chip, the relay chip can be firmly fixed at a predetermined position, and the impact force applied to the semiconductor chip by the shock absorbing material can be reduced. The failure rate of the semiconductor chip can be reduced.

  A semiconductor device includes a semiconductor chip mounting substrate on which a plurality of electrodes are disposed, a semiconductor chip mounted on the substrate and using a silicon substrate on which a plurality of first bonding pads are disposed, and the semiconductor chip The second bonding pad, the third bonding pad, the second bonding pad, and the third bonding pad are mounted on the semiconductor chip so as to be inside the outer edge of the surface and to expose the first bonding pad. A relay chip using a silicon substrate in which a plurality of wirings that electrically connect the bonding pads are arranged, an impact cushioning material provided between the semiconductor chip and the relay chip, and the first A plurality of first wires electrically connecting the bonding pads and the second bonding pads, the electrodes and the third wires; A down loading pad respectively and a plurality of second wire electrically connecting. The relay chip has a multilayer wiring structure in which the wiring is laminated on a silicon substrate via an interlayer insulating film.

(Constitution)
FIGS. 1A, 1B, and 1C are schematic configuration diagrams of an SOP type semiconductor device showing Embodiment 1 of the present invention, and FIG. FIG. 2B is a cross-sectional view of FIG. 2A cut in the horizontal direction, and FIG. 2C is a cross-sectional view of FIG. 1A cut in the vertical direction.

  This SOP type semiconductor device uses, for example, a lead frame 30 as a substrate for mounting a semiconductor chip. As shown in FIG. 1A, the lead frame 30 includes a die pad 31 for mounting a semiconductor chip having a substantially rectangular plane, and a plurality of lead frames 30 are laterally separated from the left and right sides of the die pad 31 by a predetermined distance. A lead 32 is disposed. The plurality of leads 32 are formed on the inner lead portion on the inner side by a first bonding pad 33 (left bonding pads 33-11, 33-12,..., Right bonding pads 33-21, 33-22,... -) Is provided, and the outer outer lead portion is pulled out in the lateral direction.

  A semiconductor chip 40 having a substantially rectangular plane is fixed to the surface of the die pad 31. The semiconductor chip 40 is formed with a semiconductor memory, a semiconductor integrated circuit (hereinafter referred to as “IC”) or the like on a substrate such as silicon, and a plurality of second bonding pads 41 (on the upper side) near the upper and lower sides of the surface. , Bonding pads 41-11, 41-12,..., And lower bonding pads 41-21, 41-22,.

  A relay chip 50 having a substantially rectangular plane is fixed by an insulating adhesive 45 so as to fit inside the outer edge of the surface of the semiconductor chip 40. The relay chip 50 has a thin substrate such as silicon or glass epoxy resin, and a plurality of third bonding pads 51 (upper bonding pads 51-11, 51-12,. .., Lower bonding pads 51-21, 51-22,..., Left bonding pads 51-31, 51-32,..., Right bonding pads 51-41, 51-42,.・) Is arranged.

  A wiring pattern 52 made of a conductive film or the like is formed on the substrate of the relay chip 50, and a plurality of bonding pads 51 are connected to each other by the wiring pattern 52. For example, the upper half of the upper bonding pads 51-11, 51-12,... Are connected to the upper half of the left bonding pads 51-31, 51-32,. The right halves of 51-11, 51-12,... Are connected to the upper halves of the right bonding pads 51-41, 51-42,. ,... Are connected to the lower half of the left bonding pads 51-31, 51-32,..., And the lower bonding pads 51-21, 51-22,. The right half is connected to the lower half of the right bonding pads 51-41, 51-42,.

  A plurality of bonding pads 41 on the semiconductor chip side are connected to a plurality of bonding pads 51 on the relay chip side by a plurality of wires 61, and are connected to the plurality of bonding pads 51 via wiring patterns 52. The plurality of bonding pads 51 are connected to the plurality of bonding pads 33 on the lead frame side by a plurality of wires 62.

  For example, the left half of the bonding pads 41-11, 41-12,... On the upper side of the semiconductor chip 40 is connected to the bonding pads 33-11, 33- on the left side of the lead frame 30 via the wires 61 and the relay chip 50. The right half of the bonding pads 41-11, 41-12,... Connected to the upper half of the semiconductor chip 40 is connected to the lead frame 30 via the wire 61 and the relay chip 50. Are connected to the upper half of the right bonding pads 33-21, 33-22,. Similarly, the left half of the bonding pads 41-21, 41-22, ... on the lower side of the semiconductor chip 40 is the lower half of the bonding pads 33-11, 33-12, ... on the left side of the lead frame 30. The right half of the bonding pads 41-21, 41-22,... On the lower side of the semiconductor chip 40 is below the bonding pads 33-21, 33-22,. Connected in half.

  The die pad 31, the semiconductor chip 40, the relay chip 50, the wires 61 and 62, and the bonding pad 33 portion of the lead frame 32 are sealed with a resin member 70. The outer lead portion of the lead 32 protrudes from the resin member 70 and is bent downward substantially in an L shape.

(Production method)
FIG. 2 is a diagram illustrating an example of a manufacturing method of the semiconductor device of FIG.
The semiconductor device of FIG. 1 is manufactured by, for example, (1) a chip bonding process, (2) a mounting process, (3) a wire bonding process, and (4) a sealing process. Hereinafter, each manufacturing process will be described.

(1) Chip Bonding Process The semiconductor chip 40 is held by a die bonder, and the back surface of the semiconductor chip 40 is fixed to the surface of the die pad 31 of the lead frame 30 with an adhesive such as silver paste.

(2) Mounting process An insulating adhesive 45 is formed on the substantially central portion of the surface of the semiconductor chip 40 or on the back surface of the relay chip 50. As the adhesive material 45, for example, a low-stress paste material using an epoxy resin or the like, or a film material such as a thermoplastic resin or a thermosetting resin may be used.

  The relay chip 50 is held by the die bonder, and the back surface of the relay chip 50 is fixed by the adhesive 45 so as to be inside the outer edge of the front surface of the semiconductor chip 40.

  At the time of fixing, it is desirable to reduce the impact force received by the semiconductor chip 40 by adjusting the contact pressure and moving speed of the die bonder. Further, in order to buffer the impact force, an adhesive 45 having an impact buffer function may be used, or an impact buffer pad or the like may be separately provided between the semiconductor chip 40 and the relay chip 50.

(3) Wire Bonding Process Using a wire bonder, the bonding pad 41 of the semiconductor chip 40 and the bonding pad 51 of the relay chip 50 are connected by the wire 61, and the bonding pad 51 of the relay chip 50 and the bonding pad of the lead frame 30 are connected. 33 is connected by a wire 62.

(4) Sealing Step, etc. The lead frame 30 on which the semiconductor chip 40 and the relay chip 50 are mounted is set in, for example, a mold molding machine, and the semiconductor chip 40 is relayed by molding with a resin member 70 such as epoxy resin. The chip 50 and the wires 61 and 62 are sealed with resin.

  If the resin, burrs, unnecessary portions and the like of the lead frame 30 are removed and the outer lead portion of the lead 32 is bent into a desired shape, the manufacture of the semiconductor device of FIG. 1 is completed. Thereafter, the quality is verified by a tester as necessary.

(Operation)
In the semiconductor device of FIG. 1, since the outer lead portion of the lead 32 and the semiconductor chip 40 are electrically connected via the relay chip 50 and the wires 61 and 62, signal input to the outer lead portion. If output is performed, a predetermined electrical operation is performed.

(Effects etc.)
In Example 1, the following effects (a) to (g) are obtained.

  (A) The relay chip 50 is stacked on the semiconductor chip 40, and the pad arrangement is changed to a substantially right angle direction so that the relay chip 50 can be connected to the bonding pad 33 on the lead frame 30 side. Therefore, for example, even if the conventional semiconductor chip 20B as shown in FIG. 15 is not formed, it can be mounted on the package as shown in FIG.

  (B) Since the relay chip 50 can be configured by only the bonding pad 51 and the wiring pattern 52, the cost required for redesign and verification of operation, compared to the case of creating the conventional semiconductor chip 20B as shown in FIG. Development costs can be reduced.

  (C) Since the relay chip 50 is stacked on the semiconductor chip 40 without increasing the chip size by arranging the pads in accordance with the conventional semiconductor chip 20B as shown in FIG. The area required to place the is not increased.

  (D) Since the relay chip 50 is fixed so as to be inside the outer edge of the surface of the semiconductor chip 40, the relay chip 50 can be firmly fixed at a predetermined position. Therefore, the relay chip 50 is not displaced from the predetermined mounting position due to the force applied when the relay chip is mounted or wire bonding, and the relay chip mounting and wire bonding can be performed easily and accurately.

  (E) For example, when an adhesive having an impact buffering function is used as the adhesive 45, or an impact buffer pad or the like is separately provided between the semiconductor chip 40 and the relay chip 50, when the relay chip 50 is fixed, The impact force received by the semiconductor chip 40 can be reduced, and thereby the failure rate of the semiconductor chip 40 can be reduced.

  (F) The wiring pattern 52 of the relay chip 50 can be changed into various forms corresponding to the conversion direction of the pad arrangement. At this time, if the wiring state becomes complicated and inconveniences such as short-circuiting between the wirings occur, the wiring pattern 52 may have a multilayer wiring structure as shown in FIG. 3, for example.

(G) FIG. 3 is a schematic enlarged sectional view showing an example of a multilayer wiring structure.
The relay chip 50 includes a thin substrate 50a such as silicon or glass epoxy resin. On the substrate 50a, conductive films 50b for forming the wiring patterns 52 and interlayer insulating films 50c are alternately arranged and formed in a stacked state. The conductive film 50b is connected to the bonding pad 51 through a contact hole 50d or the like. By using such a laminated structure, a complicated wiring pattern 52 can be easily formed without causing a short circuit between the wirings.
[Reference Example 1]

(Configuration etc.)
FIG. 4 is a schematic plan view in which a part of the SOP type semiconductor device showing the reference example 1 of the present invention is omitted, and is common to the elements common to the elements in FIGS. The code | symbol is attached | subjected.

  In this SOP type semiconductor device, instead of the relay chip 50 of FIG. 1, a plurality of (for example, four divided vertically and horizontally) substantially rectangular relay chips 50A-1, 50A-2, 50A-3, 50A. -4, these relay chips 50A-1 to 50A-4 are fixed so as to fit inside the outer edge of the surface of the semiconductor chip 40 similar to FIG.

Each relay chip 50A-1 to 50A-4 has the same configuration, and a plurality of bonding pads 51 are disposed in the vicinity of two adjacent sides, and a plurality of bonding pads 51 on each side are connected to the wiring. The patterns 52 are connected to each other. These relay chips 50A-1 to 50A-4 rotate the position of the bonding pad 51 so as to face the bonding pads 33 and 41 in order to shorten the lengths of the bonding pad wires 61 and 62. The semiconductor chips 40 are arranged near the four corners of the surface, and are connected to the bonding pads 41 of the semiconductor chip 40 and the bonding pads 33 of the lead frame 30 by wires 61 and 62 in substantially the same manner as in FIG.
Other configurations and operations are substantially the same as those in FIG.

(Production method)
The relay chips 50A-1 to 50A-4 can be manufactured, for example, by cutting the relay chip 50 of FIG.

  As in the manufacturing method of FIG. 2, the semiconductor chip 40 is fixed on the die pad 31 in the chip bonding step. In the mounting process, in order to align the bonding pads 51 in the relay chips 50A-1 to 50A-4, the relay chips 50A-1 to 50A-4 are rotated, and the adhesive 45 is placed on the semiconductor chip 40. Stick. Next, in the wire bonding step, each of the relay chips 50A-1 to 50A-4 is connected to the bonding pad 41 of the semiconductor chip 40 and the bonding pad 33 of the lead frame 30 by wires 61 and 62.

  Thereafter, in the sealing step, the semiconductor chip 40, the relay chips 50A-1 to 50A-4, the wires 61 and 62, and the like are resin-sealed with the resin member 70, and, in addition, if processing substantially similar to FIG. The manufacture of the semiconductor device of FIG.

(Effects etc.)
In this reference example 1 , since the plurality of relay chips 50A-1 to 50A-4 are used in place of the one relay chip 50 of the first embodiment and the pad arrangement is changed in a substantially perpendicular direction , the embodiment There are substantially the same effects as the effects (a) to (g) of 1. Further, there are effects such as the following (h) to (j).

(H) Since placed near the four corners of each relay chips 50A-1~50A-4 to the surface of the semiconductor chip 40, compared with Example 1, it is possible to shorten the length of the wire 61, 62 .

  (I) Since each of the relay chips 50A-1 to 50A-4 has a smaller chip size than the relay chip 50 of the first embodiment, the disconnection of the wiring pattern 52 at the time of manufacture is reduced to increase the yield of the chips. Thus, the cost of the relay chips 50A-1 to 50A-4 can be reduced.

  (J) Although four relay chips 50A-1 to 50A-4 are used, other numbers of relay chips (for example, two, three, 5 etc.).

(Configuration etc.)
FIGS. 5A and 5B are schematic configuration diagrams of an SOP type semiconductor device showing Embodiment 2 of the present invention. FIG. 5A is a plan view with a part omitted, and FIG. These are the enlarged views of the wiring pattern of the relay chip in FIG. In these drawings, elements common to those in FIGS. 1 to 4 showing Example 1 and Reference Example 1 are denoted by common reference numerals.

  In this SOP type semiconductor device, instead of the four relay chips 50A-1, 50A-2, 50A-3, 50A-4 in FIG. 4, four substantially rectangular relay chips 50B-1, 50B-2, 50B-3 and 50B-4 are fixed by adhesives 45 near the four corners so as to fit inside the plurality of bonding pads 41 on the surface of the semiconductor chip 40. Each relay chip 50B-1 to 50B-4 has the same configuration, and a schematic plan view of the relay chip 50B-1 is shown in FIG.

  For example, the relay chip 50B-1 has a multilayer wiring structure as shown in FIG. 3, and a wiring pattern 52B having a multilayer wiring structure including a conductive film 50b and an interlayer insulating film 50c is formed on a thin substrate 50a. In addition, a plurality of third bonding pads 51 are formed thereon. Each bonding pad 51 is connected to the wiring pattern 52B through the contact hole 50d.

  The plurality of bonding pads 51 are arranged in the vicinity of the four sides of the surface of the relay chip 50B-1 (the upper bonding pads 51-11, 51-12,..., The lower bonding pads 51-21). , 51-22,..., Left-side bonding pads 51-31, 51-32,..., Right-side bonding pads 51-41, 51-42,. Bonding pads on one side (for example, the left side bonding pad 51-31) are bonded to bonding pads on the other three sides (for example, the upper side bonding pad 51-11, the lower side bonding pad 51-21, and the right side bonding pad 51-21). The bonding pads 51-41) are connected by the conductive film 50b of the wiring pattern 52B.

Therefore, even if the four relay chips 50B-1 to 50B-4 in FIG. 5A face the same direction, it is possible to have the same function as the relay chips 50A-1 to 50A-4 in FIG. is there. These relay chips 50B-1 to 50B-4 are connected to the bonding pads 41 of the semiconductor chip 40 and the bonding pads 33 of the lead frame 30 by wires 61 and 62, as in FIG.
Other configurations and operations are substantially the same as those in FIGS.

(Production method)
The four relay chips 50B- 1 to 50B-4 are used in the same manner as in Reference Example 1 .

(Effects etc.)
In the second embodiment , since a plurality of relay chips 50B-1 to 50B-4 are used and the pad arrangement is changed in a substantially right angle direction, the first embodiment and the first embodiment (a) to (j) are changed. There are almost the same effects and the like. Further, there are effects such as the following (k) and (l).

(K) In FIG. 4 of Reference Example 1 , it is necessary to rotate and mount the relay chips 50A-1 to 50A-4, whereas in FIG. 5 of this embodiment , each of the relay chips 50B-1 to 50B. -4 does not need to be rotated. This simplifies the mounting process.

  (L) Since the conversion direction of the pad arrangement can be 360 °, the degree of freedom in the wire bonding direction is further increased, and it is possible to deal with packages having various pad arrangements.

(Configuration etc.)
6A to 6C are schematic configuration diagrams of a semiconductor device in the form of a multichip package showing a third embodiment of the present invention. FIG. 6A is a plan view with a part omitted. The figure, the figure (B) is the bottom view which abbreviate | omitted a part seeing from the back surface, and the figure (C) is the longitudinal cross-sectional view which abbreviate | omitted a part. FIG. 7 is an enlarged plan view of FIG. In these drawings, elements common to those in FIGS. 1 to 5 showing the first and second embodiments are denoted by the same reference numerals.

  In this multichip package semiconductor device, the lead frame 30 shown in FIG. 1 is used, and semiconductor chips 40A-1 and 40A-2 having a substantially rectangular plane are fixed to the front and back surfaces of the die pad 31, respectively. Further, the relay chip 50C having a substantially rectangular plane is formed by the adhesive 45 so as to fit inside the outer edge of the surface of one of the semiconductor chips 40A-1 and 40A-2 (for example, the semiconductor chip 40A-2 on the back side). Is fixed.

  In the vicinity of the left and right sides of the surface of each semiconductor chip 40A-1, 40A-2, a plurality of second bonding pads 41 (left bonding pads 41-11, 41-12,. The right side bonding pads 41-21, 41-22,...

  The relay chip 50C fixed to substantially the center of the semiconductor chip 40A-2 on the back surface side has, for example, a multilayer wiring structure as shown in FIG. 3 bonding pads 51 (left bonding pads 51-11, 51-12,..., 51-1J,..., Right bonding pads 51-21, 51-22,..., 51-2i) Is arranged. The left bonding pads 51-11, 51-12,..., 51-1J,... And the right bonding pads 51-21, 51-22,. The wiring patterns 52C are connected to each other so that the wiring state is reversed vertically and horizontally.

  The plurality of bonding pads 51 are connected to the plurality of bonding pads 41 of the semiconductor chip 40A-2 by a plurality of wires 61, and the lead frame is formed by the plurality of wires 62-1 and 62-2. It is connected to a plurality of bonding pads 33 on the 30 side.

  For example, the bonding pad 33-11 on the lead frame 30 side is connected to the bonding pad 41-11 of the semiconductor chip 40A-1 on the front surface side by the wire 62-1 and the relay chip 50C on the back surface side by the wire 62-2. Are connected to the bonding pad 51-2i. The bonding pad 51-2i is connected to the opposing bonding pad 51-1j by the wiring pattern 52C, and this bonding pad 51-1j is connected to the bonding pad 41-11 of the semiconductor chip 40A-21 on the back surface side by the wire 61. Has been. As a result, the bonding pad 33-11 on the lead frame 30 side is connected to the bonding pad 41-11 of the semiconductor chip 40A-1 on the front surface side and also to the bonding pad 41-11 of the semiconductor chip 40A-21 on the back surface side. Will be connected.

  The semiconductor chips 40A-1, 40A-2, the relay chip 50C, the wires 61, 62-1, 62-2 and the like are resin-sealed with a resin member 70 as in FIG. Other configurations and operations are substantially the same as those in FIG.

(Production method)
As in the manufacturing method of FIG. 1, in the chip bonding step, the semiconductor chip 40A-1 is fixed to the surface of the die pad 31, and the semiconductor chip 40A-2 having the same configuration is fixed to the back surface of the die pad 31. In the mounting step, the relay chip 50C is fixed with the adhesive 45 so as to fit inside the outer edge of the surface of the semiconductor chip 40A-2. Next, in the wire bonding step, the bonding pad 41 of the semiconductor chip 40A-1 on the front surface side is connected to the bonding pad 33 on the lead frame 30 side by the wire 62-1.

  Further, the bonding pad 51 of the relay chip 50C is connected to the bonding pad 51 of the semiconductor chip 40A-2 on the back surface side by the wire 61, and is connected to the bonding pad 33 on the lead frame 30 side by the wire 62-2. Thereafter, in the sealing step, the semiconductor chips 40A-1, 40A-2, the relay chip 50C, the wires 61, 62-1, 62-2 and the like are resin-sealed with the resin member 70, and the others are almost the same as those in FIG. If the above process is performed, the manufacture of the semiconductor device of FIG. 6 is completed.

(Effects etc.)
In the third embodiment , there are substantially the same effects as the effects (b) to (e) of the first embodiment and the following effects (1) to (3).

  (1) Using two semiconductor chips 40A-1 and 40A-2 having the same configuration, the relay chip 50C changes the pad arrangement direction of one semiconductor chip 40A-2 to the pad arrangement of the other semiconductor chip 40A-1. Therefore, it is possible to easily manufacture a semiconductor device in the form of a multi-chip package without using a mirror chip that has been conventionally required. For this reason, it is possible to reduce the development period and production period of the mirror chip, which was necessary in the past, and it is not necessary to have an extra inventory of mirror chips as in the prior art.

(2) Even if the relay chip 50 </ b> C is fixed on the semiconductor chip 40 </ b> A- 1 on the front surface side instead of the back surface side, the same operation and effect as in the embodiment can be obtained.

  (3) The wiring pattern 52C of the relay chip 50C can be changed into various forms corresponding to the conversion direction of the pad arrangement and the like.

(Configuration etc.)
FIGS. 8A to 8C are schematic configuration diagrams of a semiconductor device in the form of a multi-chip package showing a fourth embodiment of the present invention, and FIG. The figure, the figure (B) is the bottom view which abbreviate | omitted a part seeing from the back surface, and the figure (C) is the longitudinal cross-sectional view which abbreviate | omitted a part. 9A and 9B are enlarged plan views of FIGS. 8A and 8B. Keep these drawings, the elements common to those in FIGS. 1 and 6 show the Examples 1 and 3 are denoted by the same reference numerals.

  In this multi-chip package semiconductor device, the lead frame 30 of FIG. 1 is used, and semiconductor chips 40-1 and 41-2 having the same configuration as the semiconductor chip 40 of FIG. Further, the same relay chip 50 as in FIG. 1 is fixed by the same adhesive 45-1 as in FIG. 1 so as to be inside the outer edge of the surface of the front surface side semiconductor chip 40-1, and the rear surface side semiconductor. A relay chip 50C having a multilayer wiring structure different from that of the relay chip 50 in FIG. 1 is fixed by the same adhesive 45-2 as in FIG. 1 so as to be inside the outer edge of the surface of the chip 40-2.

  The relay chip 50D fixed to the surface of the semiconductor chip 40-2 on the back side has, for example, a multilayer wiring structure as shown in FIG. 3, and this surface has the same structure as the semiconductor chip 40-1 on the front side. A plurality of third bonding pads 51 (upper bonding pads 51-11, 51-12,..., Lower bonding pads 51-21, 51-22,. Bonding pads 51-31, 51-32,..., And right-side bonding pads 51-41, 51-42,. The plurality of bonding pads 51 are connected to each other by a wiring pattern 52D having a multilayer wiring structure so that the wiring state is inverted vertically and horizontally with respect to the wiring pattern 52 of the semiconductor chip 40-1 on the surface side. .

  That is, in the backside relay chip 50D, the left half of the upper bonding pads 51-11, 51-12,... Is connected to the right half side, and the lower bonding pads 51-21, 51-22. Are connected to the right half side, and the left side bonding pads 51-31, 51-32,... Are connected to the right side bonding pads 51-41, 51-42,. ing.

  In the plurality of bonding pads 51 of the relay chip 50 on the front side, the upper bonding pads 51-11, 51-12,... Are connected to the upper side of the semiconductor chip 40-1 by the plurality of wires 61-1. Are connected to the bonding pads 41-11, 41-12,..., And the lower bonding pads 51-21, 51-22,. Are connected to the bonding pads 41-21, 41-22,. Further, the left side bonding pads 51-31, 51-12,... Are connected to the bonding pads 33-11, 33-12,. Are connected to the bonding pads 33-21, 33-22,... On the lead frame 30 side by a plurality of wires 62-1.

  In the plurality of bonding pads 51 of the relay chip 50D on the back surface side, the upper bonding pads 51-11, 51-12,... Are connected to the upper side of the semiconductor chip 40-2 by the plurality of wires 61-2. The lower bonding pads 51-21, 51-22,... Are connected to the bonding pads. Side bonding pads..., 41-12, 41-11. Furthermore, the left bonding pads 51-31, 53-12,... Are connected to the bonding pads .about.33-22, 33-21 on the lead frame 30 side by a plurality of wires 62-2, and the right-hand bonding pads 51-31, 53-12,. The bonding pads 51-41, 54-42, ... are connected to the bonding pads ..., 33-12, 33-11 on the lead frame 30 side by a plurality of wires 62-2.

  Therefore, for example, the bonding pad 33-11 on the lead frame 30 side is connected to the bonding pad 41-11 of the semiconductor chip 40-1 on the front surface side and the bonding pad 41-11 of the semiconductor chip 40-2 on the back surface side. Will be connected to.

  These semiconductor chips 40-1, 40-2, relay chips 50, 50D, wires 61-1, 61-2, 62-1, 62-2, etc. are resin-sealed by the resin member 70, as in FIG. It has been stopped. Other configurations and operations are substantially the same as those in FIG.

(Production method)
Similar to the manufacturing method of FIG. 6, in the chip bonding step, the semiconductor chip 40-1 is fixed to the surface of the die pad 31, and the semiconductor chip 40-2 having the same configuration is fixed to the back surface of the die pad 31. In the mounting process, the relay chip 50 is fixed with an adhesive 45-1 so as to be inside the outer edge of the surface of the semiconductor chip 40-1, and the relay chip 50D is fixed with the adhesive 45-2. It adheres to fit inside the outer edge of the surface. Next, in the wire bonding step, the bonding pad 41 of the semiconductor chip 40-1 on the surface side is connected to the bonding pad 51 of the relay chip 50 by the wire 61-1, and this bonding pad 51 is read by the wire 62-1. Connected to the bonding pad 33 on the frame 30 side.

  Further, the bonding pad 41 of the semiconductor chip 40-2 on the back surface side is connected to the bonding pad 51 of the relay chip 50D by the wire 61-2, and this bonding pad 51 is connected to the bonding frame on the lead frame 30 side by the wire 62-2. Connect to pad 33.

  Thereafter, in the sealing step, the semiconductor chips 40-1 and 40-2, the relay chips 50 and 50D, the wires 61-1, 61-2, 62-1, and 62-2 are sealed with the resin member 70. In addition, the manufacturing of the semiconductor device shown in FIG.

(Effects etc.)
In the fourth embodiment, there are effects such as the necessity of producing the conventional semiconductor chip 20B as shown in FIG. 15 and the like, almost the same as the effects (a) to (e) of the first embodiment. Further, almost the same effects as the effects (1) and (3) of the third embodiment, there is an effect that it is not necessary to prepare a mirror chip.

(Configuration etc.)
FIGS. 10A to 10C are schematic configuration diagrams of a semiconductor device in the form of a multichip package showing a fifth embodiment of the present invention, and FIG. The figure, the figure (B) is the bottom view which abbreviate | omitted a part seeing from the back surface, and the figure (C) is the longitudinal cross-sectional view which abbreviate | omitted a part. 11A and 11B are enlarged plan views of FIGS. 10A and 10B. In these drawings, the elements common to those in FIGS. 1 and 8 show the Examples 1 and 4 are denoted by the same reference numerals.

  In the semiconductor device in the form of a multichip package, semiconductor chips 40-1 and 40-2 having the same configuration are fixed to the front and back surfaces of the die pad 31 of the lead frame 30 in FIG. The same configuration different from that of FIG. 8 is provided by adhesives 45-1 and 45-2 similar to those in FIG. The substantially rectangular relay chips 50E-1 and 50E-2 are fixed to each other.

  Each of the relay chips 50E-1 and 50E-2 on the front side and the back side has a multilayer wiring structure as shown in FIG. 3, for example, and a plurality of third bonding pads are provided in the vicinity of the four sides of the front side. 51 (upper bonding pads 51-11, 51-12,..., Lower bonding pads 51-21, 51-22,..., Left bonding pads 51-31, 51-32,. , Right side bonding pads 51-41, 51-42,. The plurality of bonding pads 51 are connected to each other by respective wiring patterns 52E-1 and 52E-2 on the front surface side and the back surface side of the multilayer wiring structure.

  That is, in each relay chip 50E-1, 50E-2, the plurality of upper bonding pads 51-11, 51-12,... In the left half are the plurality in the right half and the left bonding pads. 51-31, 51-32,... Are respectively connected to a plurality in the upper half. .. In the right half of the upper bonding pads 51-11, 51-12,... Are in the upper half of the left bonding pads 51-31, 51-32,. Are connected to the right bonding pads 51-41, 51-42,.

  .. In the left half of the lower bonding pads 51-21, 51-22,... Each is connected to a plurality of halves. The lower half of the bonding pads 51-11, 51-12, ... on the lower side is the lower half of the bonding pads 51-31, 51-32, ... on the left side. Are connected to a plurality of the inner half and a plurality of lower right half of the bonding pads 51-41, 51-42,.

  In the plurality of bonding pads 51 of the front surface side relay chip 50E-1, the upper bonding pads 51-11, 51-12,... Are connected to the semiconductor chip 40-1 by the plurality of wires 61-1. Are connected to the upper bonding pads 41-11, 41-12,..., And the lower bonding pads 51-21, 51-22,. Are connected to the lower bonding pads 41-21, 41-22,. Further, the left bonding pads 51-31, 53-12,... Are connected to the bonding pads 33-11, 33-12,. The bonding pads 51-41, 54-42,... Are connected to the bonding pads 33-21, 33-22,.

  Further, in the plurality of bonding pads 51 of the relay chip 50E-2 on the back surface side, the upper bonding pads 51-11, 51-12, ... are connected to the semiconductor chip 40-2 by the plurality of wires 61-2. The upper bonding pads..., 41-22, 41-21 are connected to the lower bonding pads 51-21, 51-22,. Are connected to the lower bonding pads..., 41-12, 41-11. Further, the left bonding pads 51-31, 51-12,... Are connected to the bonding pads. Are connected to the bonding pads..., 33-12 and 33-11 on the lead frame 30 side by a plurality of wires 62-2.

  Therefore, for example, the bonding pad 33-11 on the lead frame 30 side is connected to the bonding pad 41-11 of the semiconductor chip 40-1 on the front surface side and the bonding pad 41-11 of the semiconductor chip 40-2 on the back surface side. Will be connected to.

  These semiconductor chips 40-1, 40-2, relay chips 50E-1, 50E-2, wires 61-1, 61-2, 62-1, 62-2, etc. are the same as in FIGS. The resin member 70 is resin-sealed. Other configurations and operations are substantially the same as those in FIGS.

(Production method)
As in the manufacturing method of FIG. 8, in the chip bonding step, the semiconductor chip 40-1 is fixed to the surface of the die pad 31, and the semiconductor chip 40-2 having the same configuration is fixed to the back surface of the die pad 31. In the mounting step, the relay chip 50E-1 is fixed with an adhesive 45-1 so as to be inside the outer edge of the surface of the semiconductor chip 40-1, and the relay chip 50E- having the same configuration as the relay chip 50E-1 is fixed. 2 is fixed with an adhesive 45-2 so as to fit inside the outer edge of the surface of the semiconductor chip 40-2. Next, in the wire bonding step, a plurality of bonding pads 41 of the semiconductor chip 40-1 on the surface side are connected to a plurality of bonding pads 51 of the relay chip 50E-1 by wires 61-1, and this bonding pad 51 is connected. The other plurality is connected to the bonding pad 33 on the lead frame 30 side by the wire 62-1.

  Further, a plurality of bonding pads 41 of the semiconductor chip 40-2 on the back surface side are connected to a plurality of bonding pads 51 of the relay chip 50E-2 by wires 61-2, and the other plurality of bonding pads 51 are connected. The wire 62-2 is connected to the bonding pad 33 on the lead frame 30 side.

  Thereafter, in the sealing process, the semiconductor chips 40-1 and 40-2, the relay chips 50E-1 and 50E-2, the wires 61-1, 61-2, 62-1, and 62-2 are resinated with a resin member. If the sealing and other processes similar to those in FIG. 8 are performed, the manufacturing of the semiconductor device in FIG. 10 is completed.

(Effects etc.)
The fifth embodiment has the following effects (A) to (D).

  (A) Almost the same as the effects (a) to (e) of the first embodiment, there is an effect that it is not necessary to form the conventional semiconductor chip 20B as shown in FIG.

(B) In almost the same manner as the effects (1) and (3) of the third embodiment, there is an effect that it is not necessary to create a mirror chip.

  (C) With one type of relay chip 50E-1, 50E-2, it is possible to manufacture a semiconductor device in the form of a multichip package. Moreover, since the main part of the conventional semiconductor device can be used as it is, no new peripheral device is required when probing for verification or the like is performed, and the cost can be greatly reduced.

  (D) Although the bonding pad 33 for the lead frame 30 and the bonding pad 51 for the relay chips 50E-1 and 50E-2 connected by the wires 62-1 and 62-2 are used separately, the front and back are distinguished. Distinguishes the front and back by properly using the bonding pads 40 for the semiconductor chips 40-1 and 40-2 and the bonding pads 51 for the relay chips 50E-1 and 50E-2 connected by the wires 61-1 and 61-2. You may make it do.

(Configuration etc.)
FIGS. 12A and 12B are schematic configuration diagrams of a semiconductor device in the form of a multi-chip package showing Embodiment 6 of the present invention, and FIG. The figure and the figure (B) are the longitudinal cross-sectional views which abbreviate | omitted one part, and the same code | symbol is attached | subjected to the element which is common in the element in FIG.

In the semiconductor device of this multi-chip package form, a plurality of (for example, two) semiconductor chips 40A-1 and 40A- 2 having a substantially rectangular plane are fixed to the surface of the die pad 31 of the lead frame 30 as shown in FIG. Further, one relay chip having a substantially rectangular plane is formed by an adhesive 45 similar to that shown in FIG. 1 so as to fit inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2. 50F is fixed.

  Each of the semiconductor chips 40A-1 and 40A-2 is provided with a plurality of bonding pads 41 in the vicinity of two opposing sides of the surface. The relay chip 50F is provided with a plurality of bonding pads 51 in the vicinity of the two opposing sides of the surface corresponding to the plurality of bonding pads 41 of the semiconductor chips 40A-1 and 40A-2. The plurality of bonding pads 51 are connected to each other by a wiring pattern 52F having a multilayer wiring structure as shown in FIG.

  A plurality of bonding pads 51 on the relay chip 50F side are connected to a plurality of bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side by a plurality of wires 61. Are connected to a plurality of bonding pads 33 (33-1, 33-2,...) On the lead frame 30 side by a plurality of wires 62.

  The semiconductor chips 40A-1 and 40A-2, the relay chip 50F, the wires 61 and 62, and the like are resin-sealed by the resin member 70 as in FIG. Other configurations and operations are substantially the same as those in FIG.

(Production method)
As in the manufacturing method of FIG. 1, in the chip bonding step, the back surfaces of the semiconductor chips 40A-1 and 40A-2 are fixed to the surface of the die pad 31. In the mounting process, the relay chip 50F is fixed with the adhesive 45 so as to be inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2. Next, in the wire bonding step, a plurality of bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side are connected to a plurality of bonding pads 51 on the relay chip 50F side by wires 61. The other plurality are connected to bonding pads 33 (33-1, 33-2,...) On the lead frame 30 side by wires 62.

  Thereafter, in the sealing step, the semiconductor chips 40A-1 and 40A-2, the relay chip 50F, the wires 61 and 62, and the like are resin-sealed with the resin member 70. The manufacture of the semiconductor device of FIG.

(Effects etc.)
The sixth embodiment has the following effects (I) to (V).

  (I) The relay chip 50F is stacked on the semiconductor chips 40A-1 and 40A-2, and the pad arrangement direction is changed so that the relay chip 50F can be connected to the bonding pad 33 on the lead frame 30 side. . Therefore, a semiconductor device in the form of a multichip package can be manufactured without being restricted by the pad arrangement.

  (II) Since the relay chip 50F is composed only of the bonding pad 51 and the wiring pattern 52F having a multilayer wiring structure, the cost required for redesign and verification of operation is higher than when a semiconductor chip with a changed pad arrangement is created. Or, development costs can be reduced.

  (III) Since the relay chip 50F is fixed so as to be inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2, the relay chip 50F can be firmly fixed at a predetermined position. . For this reason, the relay chip 50F is not displaced from the predetermined mounting position due to the force applied at the time of relay chip mounting or wire bonding, and the relay chip mounting and wire bonding can be performed easily and accurately.

  (IV) For example, if an adhesive having an impact buffer function is used as the adhesive 45, or if an impact buffer pad or the like is separately provided between the semiconductor chips 40A-1, 40A-2 and the relay chip 50F, the relay chip When 50F is fixed, the impact force received by the semiconductor chips 40A-1 and 40A-2 can be reduced, thereby reducing the failure rate of the semiconductor chips 40A-1 and 40A-2.

  (V) Three or more semiconductor chips 40A-1 and 40A-2 may be provided. Further, the wiring pattern 52F of the relay chip 50F can be changed into various forms corresponding to the conversion direction of the pad arrangement.

(Configuration etc.)
FIGS. 13A and 13B are schematic configurations of a semiconductor device in the form of a multi-chip package showing Embodiment 7 of the present invention, and FIG. FIG. 5B is a longitudinal sectional view with a part omitted, and the elements common to the elements in FIGS. 1 and 12 showing the first and sixth embodiments are denoted by the same reference numerals. .

In this multi-chip package semiconductor device, a plurality of (for example, two) semiconductor chips 40A-1 and 40A- 2 similar to those in FIG. 12 are fixed to the surface of the die pad 31 of the lead frame 30 as shown in FIG. Further, the planar substantially rectangular relay chips 50G-1 and 50G-2 are formed by an adhesive 45 similar to that shown in FIG. 1 so as to fit inside the outer edges of the surfaces of the semiconductor chips 40A-1 and 40A-2. Each is fixed.

  The relay chips 50G-1 and 50G-2 fixed on the semiconductor chips 40A-1 and 40A-2 correspond to the plurality of bonding pads 41 of the semiconductor chips 40A-1 and 40A-2. A plurality of bonding pads 51 are disposed in the vicinity of the two opposing sides. Further, a plurality of bonding pads 51 are also provided near the other side of each relay chip 51G-1, 51G-2 as necessary. The plurality of bonding pads 51 are connected to each other by wiring patterns 52G-1 and 52G-2 having a multilayer wiring structure as shown in FIG.

  A plurality of bonding pads 51 on the relay chips 50G-1 and 50G-2 side are connected to a plurality of bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side by a plurality of wires 61, and further, bonding pads. 51 is connected to a plurality of bonding pads 33 (33-1, 33-2,...) On the lead frame 30 side by a plurality of wires 62. When connection between the relay chip 50G-1 and the relay chip 50G-2 is necessary, the bonding pad 51 on the relay chip 50G-1 side and the bonding pad 51 on the relay chip 50G-2 side are connected to the wire 63. Connect with.

  These semiconductor chips 40A-1, 40A-2, relay chips 50G-1, 50G-2, wires 61, 62, 63, and the like are resin-sealed by a resin member 70 as in FIGS. Yes. Other configurations and operations are substantially the same as those in FIGS.

(Production method)
In substantially the same manner as the manufacturing method of FIGS. 1 and 12, the back surfaces of the semiconductor chips 40A-1 and 40A-2 are fixed to the surface of the die pad 31 in the chip bonding step. In the mounting step, the relay chips 50G-1 and 50G-2 are fixed with the adhesive 45 so as to be inside the outer edges of the surfaces of the semiconductor chips 40A-1 and 40A-2.

  Next, in the wire bonding process, a plurality of bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side are connected to a plurality of bonding pads 51 on the relay chips 50G-1 and 50G-2 by a wire 61. The other plurality of bonding pads 51 are connected to bonding pads 33 (33-1, 33-2,...) On the lead frame 30 side by wires 62. When the connection between the relay chip 50G-1 and the relay chip 50G-2 is necessary, the bonding pad 51 on the relay chip 50G-1 side and the bonding pad 51 on the relay chip 50G-2 side are connected by the wire 63. To do.

  Thereafter, in the sealing step, the semiconductor chips 40A-1, 40A-2, the relay chips 50G-1, 50G-2, the wires 61, 62, 63, and the like are resin-sealed with the resin member 70. If substantially the same processing as that in FIG. 12 is performed, the manufacture of the semiconductor device in FIG. 13 is completed.

(Effects etc.)
In Example 7 , in addition to the effects (I) to (V) of Example 6 , there are also the following effects (VI).

(VI) Compared to the sixth embodiment , the relay chip 50F in FIG. 12 is divided into the relay chip 50G-1 and the relay chip 50G-2 to reduce the relay chip size, thereby reducing disconnection and the like and improving the yield. The cost can be reduced.

The present invention is not limited to the above- described embodiments and reference examples , and various modifications and usage forms are possible. Examples of such modifications and usage forms include the following (i) to (iii).

(I) In the embodiments and reference examples , the SOP type package has been described. However, by changing the lead shape of the outer lead portion of the lead frame 30, other package shapes such as QFP can be used. In addition to the resin-encapsulated package, other packages such as a hollow package may be used.

  (Ii) Although the example in which the die pad 31 of the lead frame 30 is used as the substrate for mounting the semiconductor chip has been described, other substrates such as a wiring substrate, a semiconductor substrate, a glass epoxy substrate may be used.

  (Iii) The illustrated pad arrangement and the wiring pattern of the relay chip are examples, and can be changed to various forms in accordance with the conversion direction of the pad arrangement. Moreover, a manufacturing method and a manufacturing material can be changed arbitrarily.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the semiconductor device which shows Example 1 of this invention. It is a figure which shows an example of the manufacturing method of FIG. It is a general | schematic expanded sectional view which shows an example of a multilayer wiring structure. It is the schematic plan view which abbreviate | omitted a part of semiconductor device which shows the reference example 1 of this invention. It is a schematic block diagram of the semiconductor device which shows Example 2 of this invention. It is a schematic block diagram of the semiconductor device which shows Example 3 of this invention. FIG. 7 is an enlarged plan view of FIG. It is a schematic block diagram of the semiconductor device which shows Example 4 of this invention. FIG. 9 is an enlarged plan view of FIGS. 8 (A) and (B). It is a schematic block diagram of the semiconductor device which shows Example 5 of this invention. It is an enlarged plan view of Drawing 10 (A) and (B). It is a schematic block diagram of the semiconductor device which shows Example 6 of this invention. It is a schematic block diagram of the semiconductor device which shows Example 7 of this invention. It is a schematic block diagram of the conventional semiconductor device. It is a schematic block diagram of the conventional semiconductor device. It is a schematic block diagram of the conventional semiconductor device.

30 Lead frame 31 Die pad 32 Lead 33, 41, 51 Bonding pad 40, 40-1, 40-2, 40A-1 to 40A-4 Semiconductor chip 45, 45-1, 45-2 Adhesive 50, 50A-1 50A-4, 50B-1 to 50B-4, 50C, 50D, 50E-1, 50E-2, 50F, 50G-1, 50G-2 Relay chip 52, 52B, 52C, 52D, 52E-1, 52E-2 , 52F, 52G-1, 52G-2 wiring pattern 61, 61-1, 61-2, 62, 62-1, 62-2 wire

Claims (7)

A substrate for mounting a semiconductor chip on which a plurality of electrodes are arranged;
A semiconductor chip using a silicon substrate mounted on the substrate and provided with a plurality of first bonding pads;
A second bonding pad, a third bonding pad, and the second bonding pad are mounted so as to fit inside the outer edge of the surface of the semiconductor chip and to expose the first bonding pad on the semiconductor chip. And a relay chip using a silicon substrate in which a plurality of wirings that electrically connect the third bonding pads are arranged,
An impact buffer provided between the semiconductor chip and the relay chip;
A plurality of first wires that electrically connect the first bonding pad and the second bonding pad, respectively;
A plurality of second wires that electrically connect the electrode and the third bonding pad, respectively;
The relay chip includes a multilayer wiring structure in which the wiring is laminated on a silicon substrate via an interlayer insulating film.   The semiconductor device according to claim 1, wherein the wiring of the relay chip includes a bent portion.   3. The semiconductor device according to claim 1, wherein the wirings of each layer constituting the multilayer wiring structure of the relay chip cross each other.   The interval between the second bonding pads arranged adjacent to each other is narrower than the interval between the first bonding pads arranged adjacent to each other. Semiconductor device.   The semiconductor device according to claim 1, wherein an interval between the third bonding pads arranged adjacent to each other is narrower than an interval between the electrodes arranged adjacent to each other.   The semiconductor device according to claim 1, wherein a plurality of the relay chips are provided.   The semiconductor device according to claim 1, wherein the semiconductor chip, the relay chip, and the first and second wires are resin-sealed.

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