JP4649777B2 - Delta-sigma modulation apparatus and method, and digital signal processing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delta-sigma modulation apparatus and method, and a digital signal processing apparatus and method for generating a 1-bit digital signal by subjecting an analog input signal or a multi-bit digital input signal to delta-sigma (ΔΣ) modulation processing.
[0002]
[Prior art]
The ΔΣ modulated high-speed 1-bit audio signal has a very high sampling frequency and short data compared to the data format used in conventional digital audio (for example, sampling frequency 44.1 kHz, data word length 16 bits). It has a word length (for example, sampling frequency is 64 times 44.1 kHz and data word length is 1 bit), and features a wide transmittable frequency band. Also, even with a 1-bit signal by ΔΣ modulation, a high dynamic range can be ensured in an audio band that is low with respect to an oversampling frequency of 64 times. This feature can be applied to high-quality recorders and data transmission.
[0003]
The delta-sigma modulator itself is not a new technology in particular, and the circuit configuration is suitable for IC integration, and the AD conversion accuracy can be obtained relatively easily. It is.
[0004]
The signal subjected to ΔΣ modulation can be returned to an analog audio signal by passing through a simple analog low-pass filter.
[0005]
In addition, the general configuration of this ΔΣ modulator is composed of a combination of an arbitrary number of integrators, one quantizer, and a feedback system for the output of the quantizer, and includes a nonlinear quantizer. Therefore, when an equivalent circuit is evaluated by a transfer function or the like, it is general to analyze by replacing the quantizer approximately.
[0006]
FIG. 20 shows a first conventional example of a ΔΣ modulator. This first conventional example is composed of a combination of one integrator 7, one 1-bit quantizer 8, and a feedback system of the quantized output. Specifically, an adder 6 in which an input signal G is supplied to a positive input terminal and a feedback output to be described later is supplied to a negative input terminal, an integrator 7 that performs integration processing on the addition output of the adder 6, and the integration A 1-bit quantizer 8 that quantizes the integrated output of the generator 7 into a 1-bit digital signal every sampling period. The quantized output H of the 1-bit quantizer 8 is fed back as a negative sign to the adder 6 and added (subtracted as a result) to the input signal G. A 1-bit digital signal H is derived from the 1-bit quantizer 8 as a quantized output. The integrator 7 includes an adder 7a and a delay unit 7b.
[0007]
Here, as shown in FIG. 21, the 1-bit quantizer 8 applies a quantization process to the input signal X (n) with reference to a threshold value Th that is constant with respect to time and is always 0. 1-bit output signal Y (n) is generated. That is, the 1-bit quantizer 8 determines a binary level between 0 and less than 0 with respect to the input signal X (n) as a boundary, and performs a quantization process.
[0008]
[Problems to be solved by the invention]
Incidentally, the ΔΣ modulation apparatus shown in FIG. 20 comprises a combination of one integrator 7, one nonlinear 1-bit quantizer 8 as shown in FIG. 21 and a feedback system of the quantizer output. Therefore, when a high-speed 1-bit audio signal having a desired frequency signal is generated, distortion depending on the input signal occurs in the ΔΣ modulator.
[0009]
FIG. 22 shows a spectrum distribution of a 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the conventional ΔΣ modulator. (FFT analysis result) is shown. It can be seen that harmonic noise is generated in the vicinity of frequencies 2, 3, 4, and 6 KHz. This harmonic noise is distortion depending on the input signal.
[0010]
The present invention has been made in view of the above circumstances, and provides a delta-sigma modulation apparatus and method for generating a 1-bit digital signal obtained by suppressing distortion depending on an input signal and ΔΣ-modulating only a desired signal component. Objective.
[0011]
In addition, the present invention has been made in view of the above circumstances, and a digital signal that suppresses distortion depending on an input signal peculiar to ΔΣ modulation without deteriorating sound quality by giving frequency characteristics to random noise. It is an object of the present invention to provide a processing device and a digital signal processing method.
[0012]
[Means for Solving the Invention]
In order to solve the above-described problem, a delta-sigma modulation apparatus according to the present invention is a delta-sigma modulation apparatus that performs a delta-sigma modulation process on an input signal and outputs a 1-bit digital signal. An arithmetic means for subtracting a certain 1-bit digital signal, and a plurality of stages for integrating the differential signal in the arithmetic means Composed of integrators Integrating means; quantizing means for quantizing the integrated output of the integrating means to output a 1-bit digital signal; and a feedback loop for feeding back the quantized output of the quantizing means to the computing means as the feedback signal The threshold level referred to in the quantization process in the quantization means is variably controlled relative to the time axis, and the integration of the final stage connected immediately before the quantization means From the vessel Amplitude of only Based on the above, the variable range of the threshold level is determined.
[0013]
In order to solve the above-described problem, the delta-sigma modulation method according to the present invention is a delta-sigma modulation method for performing a delta-sigma modulation process on an input signal and outputting a 1-bit digital signal. An arithmetic step for subtracting a certain 1-bit digital signal, an integration step for integrating the differential signal in the arithmetic step a plurality of times, and a quantum that performs an quantization process on the integration output of the integration step and outputs a 1-bit digital signal And a feedback step that feeds back the quantized output of the quantization step to the calculation step as the feedback signal, and the threshold level referenced in the quantization process in the quantization step is relative to the time axis. And the amplitude in the final stage integration processing performed immediately before the quantization step. only Based on the above, the variable range of the threshold level is determined.
[0014]
In order to solve the above problems, a digital signal processing apparatus according to the present invention includes a calculation unit that calculates a difference between a feedback signal and an input signal, and a plurality of stages that integrates an output signal of the calculation unit. Composed of integrators Integrating means; noise generating means for generating random noise; adding means for adding random noise output from the noise generating means to the integrated output of the integrating means; and adding output from the adding means is 1-bit quantized. Quantizing means, and 1 bit output from the quantizing means Digital A feedback loop means that feeds back a signal to the arithmetic means as the feedback signal, and an integral of the final stage connected immediately before the adding means From the vessel Amplitude of only And a gain adjusting means for adjusting the gain of the random noise generated by the noise generating means, and the adding means is supplied with the random noise whose gain is adjusted by the gain adjusting means. .
[0015]
In order to solve the above problems, a digital signal processing method according to the present invention includes a calculation step of calculating a difference between a feedback signal and an input signal, an integration step of integrating the output signal of the calculation step a plurality of times, and random noise. A noise generation step that occurs, an addition step of adding random noise output from the noise generation step to an integration output of the integration step, a quantization step of quantizing the added output from the addition step by 1 bit, and 1 bit output from the quantization process Digital A feedback step of returning a signal as the feedback signal to the calculation step, and an amplitude in the integration process at the final stage of the integration step performed immediately before the addition step only And a gain adjusting step for adjusting the gain of the random noise generated in the noise generating step, and the adding step is supplied with random noise whose gain has been adjusted in the gain adjusting step. .
[0016]
In order to solve the above problems, a digital signal processing apparatus according to the present invention includes a calculation unit that calculates a difference between a feedback signal and an input signal, and a plurality of stages that integrates the difference signal in the calculation unit. Composed of integrators Integration means, noise generation means for generating random noise, filter means for extracting high frequency components of a noise signal output from the noise generation means, and gain adjustment for performing gain adjustment on the output from the filter means Means for adding the noise signal composed of the high frequency component gain-adjusted by the gain adjusting means and the output signal from the integrating means, and a quantum for quantizing the added output from the adding means by 1 bit And a feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal, and integrating the last stage of the plurality of stages of integration means From the vessel Integral value of only Based on the above, a threshold value in the gain adjusting means is determined.
[0017]
In order to solve the above problems, a digital signal processing method according to the present invention includes a calculation step of calculating a difference between a feedback signal and an input signal, an integration step of integrating the difference signal in the calculation step a plurality of times, and random noise. A noise generating step for generating noise, a filtering step for extracting a high frequency component of a noise signal output from the noise generating step, a gain adjusting step for performing gain adjustment on the output from the filtering step, and the gain adjustment An addition step of adding a noise signal composed of a high frequency component whose gain has been adjusted in the step and an output signal from the integration step, a quantization step of quantizing the added output from the addition step by 1 bit, and the quantum A feedback step of feeding back the 1-bit digital signal output from the conversion step as the feedback signal, and integrating the final stage of the integration step The resultant integral value only On the basis of the threshold value in the gain adjustment step.
[0018]
In order to solve the above problems, a digital signal processing apparatus according to the present invention includes a calculation unit that calculates a difference between a feedback signal and an input signal, an integration unit that integrates the difference signal in the calculation unit, and a random 1 bit. Noise generating means for generating a digital signal, phase modulating means for phase-modulating a random 1-bit digital signal output from the noise generating means, and gain adjusting means for performing gain adjustment on the output from the phase modulating means Adding means for adding a noise signal composed of a high frequency component gain-adjusted by the gain adjusting means and an output signal from the integrating means; and a quantizing means for 1-bit quantizing the output from the adding means; Feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal, and the phase modulation means comprises: An input random 1-bit digital signal is output as a positive-phase output and a negative-phase output based on a first clock, and has a clock double the first clock with respect to the positive-phase output and the negative-phase output. Alternate output based on second clock The integrating means has a plurality of stages of integrators, and the threshold value in the gain adjusting means is determined based only on the integrated value in the final stage integrator. .
[0019]
In order to solve the above problems, a digital signal processing method according to the present invention includes a calculation step of calculating a difference between a feedback signal and an input signal, an integration step of integrating the difference signal in the calculation step, and a random 1 bit. A noise generating step for generating a digital signal, a phase modulation step for phase-modulating a random 1-bit digital signal output from the noise generating step, and a gain adjusting step for performing gain adjustment on the output from the phase modulation step An addition step of adding a noise signal composed of a high frequency component gain-adjusted in the gain adjustment step and an output signal from the integration step, and a quantization step of quantizing the output from the addition step by 1 bit A feedback step of feeding back the 1-bit digital signal output from the quantization step as the feedback signal. In the phase modulation step, The random 1-bit digital signal is output as a positive-phase output and a negative-phase output based on a first clock, and has a second clock that is double the first clock with respect to the positive-phase output and the negative-phase output. Alternate output based on 2 clocks In the integration step, a plurality of stages of integration processing are performed, and the threshold value in the gain adjustment step is determined based only on the integration value in the final stage integration processing. .
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, several embodiments of the present invention will be described with reference to the drawings.
First, in the first embodiment of the present invention, an analog audio signal or a multi-bit digital audio signal is used as an input signal, and this input signal is subjected to delta-sigma (ΔΣ) modulation processing to generate a high-speed 1-bit audio signal. The ΔΣ modulation device.
[0021]
As shown in FIG. 1, this ΔΣ modulation apparatus includes an adder 1 that adds an input signal A and a negative feedback signal D (1-bit digital signal), and an integration that integrates a difference signal B from the adder 1. The sign of the quantizer 2, the 1-bit quantizer 3 that performs the quantization process on the integral output C of the integrator 2 and outputs a 1-bit digital signal E, and the quantized output E of the 1-bit quantizer 3 And a feedback loop 4 that feeds back to the adder 1 as the feedback signal D.
[0022]
Here, the integrator 2 includes an adder 2a that adds the integrated output C to the difference signal B using the feedback input F as a feedback input F, and a delay unit 2b that delays the added output of the adder 2a.
[0023]
The 1-bit quantizer 3 is a quantizer in which the threshold level Th referred to in the quantization process is variable with respect to the time axis. That is, as shown in FIG. 2, the 1-bit quantizer 3 randomly changes the threshold Th that is referred to when the input signal X (n) is quantized within a range of ± Δq with respect to the time axis. .
[0024]
Next, the ΔΣ modulation processing operation performed on the input signal A by the ΔΣ modulation apparatus shown in FIG.
First, the integrator 2 applies the difference signal B based on the input signal A, that is, the difference signal B obtained by adding the feedback input D obtained by negatively feeding back the 1-bit signal from the 1-bit quantizer 3 to the input signal A. Perform integration processing. At this time, the integrator 2 delays the addition output from the internal adder 2a by the delay unit 2b and then feeds it back to the adder 2a.
[0025]
Next, the 1-bit quantizer 3 varies the threshold level Th with respect to n [time] randomly and within a range of ± Δq, quantizes the integral output C, and outputs a 1-bit signal E. The 1-bit signal E from the 1-bit quantizer 3 is output to the outside, is converted to a negative sign through the feedback loop 4 (feedback input D), and is returned to the adder 1. The adder 1 adds the feedback input D to the input signal A, outputs a difference signal B, and supplies it to the integrator 2.
[0026]
As described above, the ΔΣ modulation apparatus shown in FIG. 1 sets the threshold level Th referred to in the quantization process in the 1-bit quantizer 3 to a variable threshold level that is randomly varied with respect to the time axis. This variable threshold level is randomly selected in a range of ± Δq with respect to the time axis.
[0027]
Next, a method for calculating the optimum value of the variable threshold level in the 1-bit quantizer 3 will be described.
The behavior of the 1-bit quantizer 3 using the variable threshold level is equivalent to adding a component corresponding to the variable threshold level to the signal input to the conventional 1-bit quantizer. Therefore, the effect of suppressing distortion depends on the relative variable amount with respect to the signal input to the conventional 1-bit quantizer.
[0028]
Here, since the signal input to the conventional 1-bit quantizer is an output signal of the final stage integrator described later, the relative variable obtained based on the amplitude of the final stage integrator is It affects the effect of suppressing distortion.
[0029]
The ΔΣ modulator generally includes a plurality of integrators corresponding to the order. FIG. 3 is a schematic configuration diagram of an example of an Nth-order ΔΣ modulator. First stage integrator 2 ₁ To final stage integrator 2 _e Up to N integrators. And the final stage integrator 2 _e Are output to the 1-bit quantizer 3.
[0030]
The actual optimum variable threshold level is calculated by the integrator 2 in the final stage. _e Is performed based on the amplitude obtained in the above. Specifically, as shown in the following equation (1), the last-stage integrator 2 _e The maximum value D of the amplitude of the signal generated within _end The value SαD multiplied by the constant Sα _end Is the optimum variable threshold level Δq.
[0031]
Δq = SαD _end ... (1)
If this calculation method is used, a result obtained by multiplying a constant uniquely determined by any ΔΣ modulation configuration can be set to an optimum variable threshold level.
[0032]
In this way, for any ΔΣ modulator, the optimum amount is obtained by the above calculation method based on the amplitude of the signal in the final-stage integrator used therein, and the threshold is set with the appropriate amount of random noise. Can be suppressed in a stable operation and without deteriorating the S / N without depending on the input signal peculiar to ΔΣ modulation.
[0033]
FIG. 4 shows a flowchart for designing a ΔΣ modulator using the variable threshold level calculation method. First, in step S1, a desired ΔΣ modulator is configured. Next, in step S2, the amplitude of the signal in the final stage integrator is measured. In step S3, the variable threshold level Δq is calculated using the equation (1). Thereafter, the variable threshold level Δq is set in step S4, and in step S5, it is determined whether or not to continue the use change process of the ΔΣ modulator, and if so, the process from step S1 is repeated. If the use change process is terminated (NO), the series of processes is terminated.
[0034]
According to the design flow shown in FIG. 4, in any ΔΣ modulation design, ΔΣ modulation can be flexibly reconfigured by using the variable threshold level quantization of the present invention, and the above effect can be expected. That is, even when the configuration of the ΔΣ modulator is changed according to the purpose, the above effect can be expected as long as the fluctuation width in the signal in the final stage integrator can be known.
[0035]
By using the method for calculating the variable threshold level Δq, it is possible to determine the effective range of the threshold level to be varied randomly, for example, within 75%. If the threshold level is greater than 75%, the distortion depending on the input signal A cannot be sufficiently suppressed.
[0036]
Next, FIG. 5 shows a configuration of a ΔΣ modulator 80 including a plurality of integrators including the ΔΣ modulator shown in FIG. In FIG. 5, the adder 1, integrator 2, and 1-bit quantizer 3 constituting the ΔΣ modulator of FIG. 1 are an adder 75, an integrator 76, and a 1-bit quantizer 78. A bit length converter 79 is disposed on the negative feedback path from the 1-bit quantizer 78.
[0037]
The ΔΣ modulator 80 shown in FIG. 5 is a fifth-order ΔΣ modulator provided with five integrators 63, 66, 69, 73 and 76. The fifth-order ΔΣ modulation apparatus includes a local feedback loop unit 81 that attenuates the output of the fifth integrator 76 and then re-quantizes it and feeds it back to the input of the previous integrator 73. The local feedback loop unit 81 includes a local feedback attenuator 77 and a noise shaper 82.
[0038]
In addition, this ΔΣ modulator 80 includes adders 62, 65, 68, 72 for adding a multi-bit digital signal to each integrator before the five integrators 63, 66, 69, 73, and 76. 75, four attenuators 64, 67, 71 and 74 connected after the first to fourth integrators 63, 66, 69 and 73 of the five integrators; A 1-bit quantizer 78 similar to the 1-bit quantizer 3 connected after the integrator 76 and the bit length of the 1-bit digital signal from the 1-bit quantizer 78 are converted into multiple bits. A bit length converter 79 is provided to be supplied to adders 62, 65, 68, 72 and 75 so as to be input to five integrators 63, 66, 69, 73 and 76.
[0039]
The first integrator 63 integrates the input signal supplied via the input terminal 61 and the adder 62. Therefore, the output from the adder similar to the adder 2a shown in FIG. 1 is delayed by a delay similar to the delay 2b and returned to the adder. The same applies to the second to fifth integrators 66, 69, 73 and 76.
[0040]
The integrated output from the fifth integrator 76 is supplied to a 1-bit quantizer 78 and a local feedback attenuator 77 of the local feedback loop unit 81.
[0041]
The 1-bit quantizer 78 sets the threshold level Th referred to in the quantization process to Δq shown in the equation (1). That is, the amplitude D of the signal inside the fifth integrator 76 at the final stage _end Δq is calculated based on the above.
[0042]
Therefore, in the quantization process performed by the 1-bit quantizer 78 on the integrated output of the fifth integrator 76, the threshold level to be referred to is appropriately and randomly variable with respect to the time axis. The dependent distortion is not generated. This 1-bit output signal is derived from the output terminal 83 and supplied to the bit length converter 79.
[0043]
The bit length converter 79 converts the 1-bit signal from the 1-bit quantizer 78 into a multi-bit digital signal, adds a negative sign to the adders 62, 65, 68, 72 and 75 and feeds back. Therefore, the adders 62, 65, 68, 72 and 75 are supplied from the signals supplied from the input terminal 61 and the previous integrators 63, 66, 69 and 73 through the attenuators 64, 67, 71 and 74, respectively. The output signal of the bit length converter 78 is subtracted.
[0044]
Attenuators 64, 67, 71, and 74 attenuate the respective integral outputs of integrators 63, 66, 69, and 73 using coefficients K1, K2, K3, and K4, and add them to adders 65, 68, 72, and 75, respectively. Supply.
[0045]
The local feedback attenuator 77 of the local feedback loop unit 81 attenuates the integrated output from the fifth integrator 76 using the coefficient Kf and supplies the attenuated output to the noise shaper 82.
[0046]
Although not shown, the noise shaper 82 includes an adder, a delay unit, and a multibit quantizer, and requantizes the attenuated output from the local feedback attenuator 77 without causing truncation of the data word length. . Specifically, the requantization error is shifted out of the audible band.
[0047]
Therefore, the ΔΣ modulator 80 makes the threshold level referred to in the quantization process in the 1-bit quantizer 78 appropriately and randomly variable with respect to the time axis, so that distortion depending on the input signal is generated. In addition, since a local feedback loop is provided, a high-quality 1-bit audio signal can be output.
[0048]
FIG. 6 shows a spectrum distribution of a 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to the ΔΣ modulator 80 having the fifth-order local feedback loop shown in FIG. (FFT analysis result) is shown. Harmonic noise in the vicinity of frequencies 2, 3, 4, and 6 KHz, which is seen in the spectrum distribution in the ΔΣ modulator having the fifth-order local feedback loop including the conventional ΔΣ modulator shown in FIG. 22, is suppressed. . That is, it can be seen that distortion depending on the input signal can be suppressed.
[0049]
As described above, in the delta-sigma modulation apparatus according to the first embodiment, when any delta-sigma modulation design is designed using quantization of a variable threshold level, the amplitude of the signal in the final stage integrator is used. Can be calculated, the optimum variable threshold level can be calculated. Therefore, even when ΔΣ modulation is flexibly reconfigured according to the purpose with an optimal variable threshold level by simulation or the like, it is possible to suppress the occurrence of distortion depending on the input signal peculiar to ΔΣ modulation. Note that the optimal variable threshold level means that the operation of ΔΣ modulation itself is stable and that the S / N does not deteriorate as a characteristic, other than suppressing the occurrence of distortion depending on the input signal peculiar to ΔΣ modulation. Means.
[0050]
In the first embodiment, the optimum variable threshold level is calculated using the final integrator 2. _e This is performed based on the amplitude obtained in the above, but may be performed in another method. For example, the last stage integrator 2 _e Limiter value L for limiting the amplitude obtained within _end May be used. Limiter value L here _end Is for clipping the signal when an over level of 0 dB or more is input as an input signal to the ΔΣ modulator. Thereby, the upper limit of the input signal can be determined.
Used to prevent oscillation and system instability.
[0051]
Incidentally, the distortion dependent on the input signal generated by the ΔΣ modulator shown in FIG. 20 using the nonlinear 1-bit quantizer 8 shown in FIG. 21 will be described below. Some measures have been taken. A ΔΣ modulation apparatus that has taken several measures will be described as first to third comparative examples.
[0052]
First, in the first comparative example, a random signal r such as a dither signal is supplied to the adder 6 from the random signal generator 14 together with the input signal A as in the ΔΣ modulator shown in FIG. .
[0053]
However, when the random signal r is input together with the input signal A in this way, the 1-bit audio signal E ′ generated through the integrator 7 and the 1-bit quantizer 8 includes, in addition to a desired signal component, A component (random signal r) added to suppress distortion is also included.
[0054]
Spectrum distribution (FFT analysis) of a 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG. The results are shown in FIG. Since random noise is added, compared to the spectrum distribution based on the present embodiment shown in FIG. 6, the level of the noise floor up to 20 KHz is generally flat and increased by about 20 dB. Noise is hidden by random noise added by the adder 6 to the input signal.
[0055]
Next, in the second comparative example, an appropriate DC component d is supplied from the DC signal generator 18 to the adder 6 together with the input signal A as in the ΔΣ modulator shown in FIG.
[0056]
However, when the DC component d is input together with the input signal A in this way, the 1-bit audio signal E ｀ generated through the integrator 7 and the 1-bit quantizer 8 includes, in addition to the desired signal component, Components added to suppress distortion (DC components) are also included.
[0057]
Spectrum distribution (FFT analysis) of 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG. The results are shown in FIG. Since random noise is added, the level of the noise floor from 1 KHz to 10 KHz is flat compared to the spectrum distribution based on the present embodiment shown in FIG. The DC component added to the input signal by the adder 6 hides noise from 1 KHz to 10 KHz.
[0058]
Next, in the third comparative example, as in the ΔΣ modulator shown in FIG. 11, the distortion component due to the input signal A is obtained, and the distortion component is supplied from the distortion canceller 22 to the adder 6.
[0059]
However, in the third comparative example, since distortion is determined from the result of passing the input signal A through the ΔΣ modulator in advance, it is difficult to predict the distortion in advance, and the distortion canceller 22 is used. In theory, there was a risk of distortion due to the influence of self-confidence.
[0060]
In contrast to the third comparative example, the ΔΣ modulator according to the present embodiment shown in FIG. 1 can suppress distortion in advance and needs an additional component to suppress distortion along with the input signal. Therefore, it is possible to generate a high-speed 1-bit signal in which only a desired signal component is ΔΣ-modulated.
[0061]
Next, a second embodiment of the present invention will be described. In the second embodiment, an analog audio signal or a multi-bit digital audio signal is used as an input signal, and the input signal is subjected to integration processing and quantization processing to generate a high-speed 1-bit audio signal. It is a ΔΣ modulation device which is a kind of device.
[0062]
As shown in FIG. 12, the ΔΣ modulator of the second embodiment includes an adder 1, an integrator 2, a random signal generator 11, an adder 12, and a 1-bit quantizer 8. Prepare. Further, this ΔΣ modulation apparatus includes a feedback loop 4 that makes the sign of the quantized output E of the 1-bit quantizer 8 negative and feeds back to the adder 1 as a feedback signal D.
[0063]
In the ΔΣ modulation apparatus of the second embodiment, an adder 12 is inserted between the integrator 2 and a conventional general 1-bit quantizer 8, and a random signal generator 11 supplies a random signal to the adder 12. It features a configuration that adds a simple signal.
[0064]
Next, a ΔΣ modulation operation performed on the input signal A by the ΔΣ modulation apparatus shown in FIG.
First, the integrator 2 applies the difference signal B based on the input signal A, that is, the difference signal B obtained by adding the feedback input D obtained by negatively feeding back the 1-bit signal from the 1-bit quantizer 3 to the input signal A. An integration process is performed, and an integration output is supplied to the adder 12.
[0065]
The adder 12 is also supplied with a random signal r ′ from the random signal generator 11, and adds the random signal r ′ to the integrated output C ′. The addition output I of the adder 12, that is, the integration output I to which the random signal r ′ is added, is supplied to a 1-bit quantizer 8 similar to the conventional one.
[0066]
The 1-bit quantizer 8 performs a quantization process on the integrated output I to which the random signal r ′ is added, and outputs a 1-bit digital signal E.
[0067]
In the ΔΣ modulator shown in FIG. 12, a random signal r ′ is added to the integral output C ′ immediately before the integral output C ′ is quantized. This is equivalent to the threshold value of the 1-bit quantizer 8 changing randomly.
[0068]
Spectrum distribution of 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the second embodiment (FFT analysis result) is the same as the characteristic shown in FIG.
[0069]
The ΔΣ modulation apparatus shown in FIG. 7 as the first comparative example also uses the random signal generator 14, but adds a random signal to the input signal to the ΔΣ modulation apparatus. The configuration is clearly different from the ΔΣ modulator shown in FIG. 12 which adds a random signal to the internal integral output. Further, as apparent from comparison between the spectrum distributions of FIG. 6 and FIG. 8, the spectrum distribution (FIG. 8) of the ΔΣ modulation device of FIG. 12 has a generally flat noise floor level up to 20 KHz. In addition, it can be seen that the feature of increasing by about 20 dB is not seen, and it is possible to generate a high-speed 1-bit signal in which only a desired signal component is ΔΣ-modulated.
[0070]
Therefore, even in the ΔΣ modulation apparatus according to the second embodiment, distortion can be suppressed in advance and a component to be added to suppress distortion along with the input signal is not required. Therefore, only a desired signal component is ΔΣ modulated. A high-speed 1-bit signal can be generated. Furthermore, since it is sufficient to add a random signal generator immediately before quantization based on an existing ΔΣ modulator, a simple configuration can be achieved.
[0071]
Next, a modification of the ΔΣ modulation apparatus according to the second embodiment will be described with reference to FIGS. The ΔΣ modulation device according to this modification includes a plurality of integrators corresponding to the orders. FIG. 13 is a schematic configuration diagram of an example of an Nth-order ΔΣ modulator. First stage integrator 2 ₁ To final stage integrator 2 _e Up to N integrators. Then, the random noise signal from the random signal generator 11, the gain of which has been adjusted by the gain adjuster 31, is added to the output of the final stage integrator 2 e by the adder 12. FIG. 14 shows a random noise signal R whose gain is adjusted by the gain adjuster 31. _n The time domain characteristic (a) and the frequency domain characteristic (b) are shown.
[0072]
As described above, the modification of the ΔΣ modulator shown in FIG. 13 includes the gain adjuster 31, and adjusts the gain of the random noise signal from the random signal generator 11, and then the final stage integrator 2. _e Is added to the integral output.
[0073]
The gain adjuster 31 has a random noise signal R as shown in the following equation (2). _n Is the final stage integrator 2 immediately before the adder 12 _e Random noise signal R so that it is less than or equal to variable threshold Δq based on the amplitude of the internal signal. _n Adjust the gain to be multiplied by.
[0074]
｜ R _n | ≦ Δq (2)
The random noise signal R with the gain adjusted in this way _n Is added by the adder 12 to the final stage integrator 2. _e The integrated output signal is quantized by the 1-bit quantizer 8.
[0075]
Therefore, the ΔΣ modulator shown in FIG. 13 can vary the quantization at an optimum variable threshold level, so that it can operate stably and does not deteriorate the S / N, so that an input signal unique to the ΔΣ modulator can be obtained. The dependent distortion can be suppressed.
[0076]
In addition, since the calculation method of the appropriate amount is based on the amplitude of the signal in the final-stage integrator, the amplitude of the signal in the final-stage integrator used inside any ΔΣ modulator is used. If the optimal amount is calculated with the above calculation method based on the above, and the threshold value is varied with the appropriate amount of random noise, it depends on the input signal peculiar to ΔΣ modulation with stable operation and without deteriorating the S / N. Distortion can be suppressed.
[0077]
Next, a third embodiment of the present invention will be described. In the third embodiment, an analog audio signal or a multi-bit digital audio signal is used as an input signal, and the input signal is subjected to integration processing and quantization processing to generate a high-speed 1-bit audio signal. It is a ΔΣ modulation device which is a kind of device.
[0078]
The ΔΣ modulation apparatus according to the third embodiment also includes a plurality of integrators corresponding to the orders. FIG. 15 is a schematic configuration diagram of an example of an Nth-order ΔΣ modulator. First stage integrator 2 ₁ To final stage integrator 2 _e Up to N integrators. And the final stage integrator 2 _e The random noise signal Dth_hf whose gain is adjusted by the gain adjuster 34 is added by the adder 12.
[0079]
FIG. 16 shows a time domain characteristic (a) and a frequency domain characteristic (b) of a random noise signal Dth_hf from which a high frequency component has been extracted by the HPF filter 33.
[0080]
The gain adjuster 34 adjusts the gain of the random noise signal Dth_hf from which the high frequency component has been extracted by the HPF filter 33. The HPF filter 33 extracts a high frequency component of the random noise Dth generated by the multilevel dither generator 32.
[0081]
That is, in the ΔΣ modulation apparatus shown in FIG. 15, the gain adjuster 34 adjusts the gain of the random noise signal Dth_hf, which is a high frequency component of the random noise Dth generated by the multilevel dither generator 32. Then, the random noise signal Dth_hf whose gain has been adjusted is converted into the final stage integrator 2. _e Is added by the adder 12.
[0082]
As described above, the ΔΣ modulation apparatus shown in FIG. 15 includes the gain adjuster 34, and after adjusting the gain of the random noise signal Dth_hf from which the high-frequency component is extracted by the HPF filter 33, the final-stage integrator 2 _e Is added to the integral output.
[0083]
As shown in the following equation (3), the gain adjuster 34 has the absolute value of the random noise signal Dth_hf in the final stage integrator 2 immediately before the adder 12. _e The gain to be multiplied by the random noise signal Dth_hf is adjusted so as to be equal to or less than the variable threshold value Δq based on the amplitude of the internal signal.
[0084]
| Dth_hf | ≦ Δq (3)
The random noise signal Dth_hf whose gain is adjusted in this way is added to the final stage integrator 2 by the adder 12. _e The integrated output signal is quantized by the 1-bit quantizer 8. The 1-bit output signal Y (n) obtained by the 1-bit quantizer 8 is supplied to the integrator 2 via the feedback loop 4 and is derived to the outside.
[0085]
Focusing on the frequency characteristics of an optimal amount of random noise added immediately before quantization, the effect of suppressing distortion that depends on the input signal peculiar to ΔΣ modulation is how fast the quantization threshold level is at high speed with respect to time. Therefore, if only the variable quantization threshold level of the high frequency component is used, the effect of suppressing distortion can be expected.
[0086]
That is, when an appropriate amount of random noise is added immediately before a normal 1-bit quantizer, distortion can be suppressed only with high-frequency component random noise. This is because random noise of a low frequency component (which corresponds to an audible bandwidth component in a high-speed 1-bit audio stream) that has an adverse effect on sound quality is not required.
[0087]
Therefore, the ΔΣ modulation apparatus shown in FIG. 15 uses the variable quantization threshold level having frequency characteristics to suppress distortion dependent on the input signal peculiar to ΔΣ modulation without any deterioration in sound quality. Realized.
[0088]
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, an analog audio signal or a multi-bit digital audio signal is used as an input signal, and the input signal is subjected to integration processing and quantization processing to generate a high-speed 1-bit audio signal. It is a ΔΣ modulation device which is a kind of device.
[0089]
The ΔΣ modulation apparatus of the fourth embodiment also includes a plurality of integrators corresponding to the orders. FIG. 17 is a schematic configuration diagram of an example of an Nth-order ΔΣ modulator. First stage integrator 2 ₁ To final stage integrator 2 _e Up to N integrators. And the final stage integrator 2 _e The random noise signal Dth_pm whose gain is adjusted by the gain adjuster 38 is added by the adder 12.
[0090]
The gain adjuster 38 includes a phase modulator 37. _i Random noise signal Dth_pm from which high frequency components are extracted _(I) Adjust the gain.
[0091]
Phase modulator 37 _i Is a cascade in which a sampling frequency generated by the 1-bit dither generator 36 is subjected to multiple phase modulation on a 32-Fs 1-bit dither signal that is 32 times the sampling frequency 44.1 KHz (= Fs) used in a compact disk, for example. Connected phase modulator 37 ₁ ... 37 _i Is configured. Phase modulator 37 ₁ Performs a phase modulation process on the 1-bit dither signal from the 1-bit dither generator 36. Multiple phase modulation is to perform phase modulation several times in order to obtain a desired frequency characteristic.
[0092]
Phase modulator 37 ₁ The detailed configuration of this example is shown in FIG. Phase modulator 37 ₁ Consists of a D latch 43 composed of a D flip-flop and a changeover switch 44. The D latch 43 outputs a normal phase output and a reverse phase output of the 1-bit dither signal with a clock CK equal to the transmission rate when the 1-bit dither signal is supplied from the clock input terminal 42. The changeover switch 45 alternately outputs the normal phase output and the reverse phase output in accordance with the clock CK to generate a phase modulation signal.
[0093]
The clock CK is a clock 64 times the sampling frequency 44.1 KHz (= Fs) used in, for example, a compact disk (hereinafter referred to as 64 Fs clock). That is, if the transmission rate of the 1-bit dither signal output after being subjected to ΣΔ modulation by the ΣΔ modulator is 32 times Fs, the 1-bit audio signal input to the phase modulation unit 37 at the data rate of 32 Fs is 64 Fs clock. For example, it is latched by the D latch 43 at the rising edge by CK.
[0094]
The D latch 43 supplies the positive phase output from the positive terminal Q to the selected terminal a of the changeover switch 44 and the reverse phase output from the inverting terminal Q bar (referred to as Q *) to the selected terminal b of the changeover switch 44. To do.
[0095]
The changeover switch 44 generates a phase modulation signal by alternately arranging the reverse phase output of the D latch 43 when the 64 Fs clock CK is “1” and the positive phase output when the 64 Fs clock is “0”. The movable switching piece c is switched to the selected terminal a or the selected terminal b.
[0096]
Phase modulation is a modulation method in which polarity is inverted when data is “1” and downward when “0”. When the data rate after modulation is double that before modulation, “1” is obtained. The data is converted to 01 when it is “0”, and 10 when it is “0”.
[0097]
Therefore, the phase modulation signal Dth_pm output after being switched by the selector switch 44 ₍₁₎ Becomes a 1-bit dither signal of 64 Fs. This 64-Fs 1-bit dither signal is supplied to the next phase modulator 37. ₂ 1 bit at 32 Fs.
[0098]
By repeating such phase modulation processing and performing multiple phase modulation, the phase modulator 37 is finally obtained. _i Phase modulation signal Dth_pm output from _(I) The audible noise component is sufficiently reduced, and only the high frequency component is obtained.
[0099]
Further, the phase modulator 37 ₁ FIG. 19 shows a detailed configuration of another specific example. Another specific example includes a D latch 53 and a shift register 54. The D latch 53 is the same as the D latch 43 shown in FIG.
[0100]
The shift register 54 controls the loading and shifting of data input with the 32 Fs clock CK, and sends a 1-bit dither signal phase-modulated with the 64 Fs clock CK to the outside from the output terminal 56.
[0101]
Since this shift register 54 is synchronous load, when the 32 Fs clock CK is “1”, the positive phase output and the reverse phase output of the D latch 53 are loaded from the input terminal H and the input terminal G at the rising edge of the 64 Fs clock CK. When the 32 Fs clock CK is “0”, the positive phase output and the negative phase output are shifted at the rising edge of the 64 Fs clock CK. In this way, a 1-bit dither signal is generated at 64 Fs.
[0102]
As described above, in the ΔΣ modulation apparatus shown in FIG. 17, the 1-bit dither signal is used, so that the audible range component can be attenuated with the 1-bit signal. The audible range component can be attenuated while eliminating the need for the HPF filter used in the third embodiment. Further, the phase modulator 37 is applied to the 1-bit dither signal. ₁ ... 37 _i Multiple phase modulation using can be performed, and the audible range component can be further attenuated.
[0103]
That is, by performing phase modulation several times, it is possible to generate random noise that is a frequency characteristic having no audible range component as it is as a 1-bit signal. Further, when an HPF filter is used as shown in FIG. 15 when configured with hardware or the like, the scale becomes large in designing a filter that can sufficiently attenuate the audible range component. However, as shown in FIG. The configuration using the modulation has an advantage that it can be easily configured on a small scale.
[0104]
As described above, the delta-sigma modulation device according to the third embodiment and the delta-sigma modulation device according to the fourth embodiment deteriorate the sound quality by providing frequency characteristics in the quantization of the variable threshold level. And the effect of suppressing distortion depending on the input signal peculiar to ΔΣ modulation is realized.
[0105]
In addition, the ΔΣ modulation apparatus according to the fourth embodiment that gives frequency characteristics to random noise such as dither while maintaining a high-speed 1-bit audio stream can be realized easily and on a small scale by using multiple phase modulation. This is very advantageous in terms of hardware design and the like compared to using a filter.
[0106]
Also in the third and fourth embodiments, the optimum variable threshold level is calculated by the final integrator 2. _e The limiter value L is calculated based on the amplitude obtained in the _end May be used.
[0107]
【The invention's effect】
In the delta-sigma modulation device according to the present invention, the threshold level referenced in the quantization process performed by the quantization unit is relatively variable with respect to the time axis, so that distortion depending on the input signal is suppressed and desired It is possible to generate a 1-bit digital signal obtained by subjecting only the signal component to ΔΣ modulation.
[0108]
In the delta-sigma modulation method according to the present invention, the threshold level referenced in the quantization process in the quantization step is relatively variable with respect to the time axis, so that distortion depending on the input signal is suppressed, and a desired signal component It is possible to generate a 1-bit digital signal obtained by subjecting only the signal to ΔΣ modulation.
[0109]
The digital signal processing apparatus and digital signal processing method according to the present invention suppress the distortion depending on the input signal peculiar to ΔΣ modulation without deteriorating the sound quality by giving the frequency characteristics to the random noise.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a ΔΣ modulation apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a 1-bit quantizer used in the ΔΣ modulator.
FIG. 3 is a schematic configuration diagram of an example of an Nth-order ΔΣ modulator.
FIG. 4 is a flowchart for designing a ΔΣ modulator using a variable threshold level calculation method.
FIG. 5 is a block diagram showing a configuration of a ΔΣ modulation apparatus including a plurality of integrators.
6 is a spectrum distribution diagram of a 1-bit audio signal (64 Fs) generated when a sine wave signal having a frequency of 1 KHz is input to the ΔΣ modulator having a fifth-order local feedback loop shown in FIG. 5; is there.
FIG. 7 is a block diagram showing a configuration of a ΔΣ modulation apparatus as a first comparative example.
FIG. 8 shows a 1-bit audio signal (64 Fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the first comparative example. FIG.
FIG. 9 is a block diagram showing a configuration of a ΔΣ modulation apparatus as a second comparative example.
FIG. 10 shows a 1-bit audio signal (64 Fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the second comparative example. FIG.
FIG. 11 is a block diagram showing a configuration of a ΔΣ modulation apparatus as a third comparative example.
FIG. 12 is a block diagram showing a configuration of a ΔΣ modulation apparatus according to a second embodiment of the present invention.
FIG. 13 is a block diagram showing a schematic configuration of an Nth-order ΔΣ modulation apparatus, which is a modification of the second embodiment.
14 shows a random noise signal R from a random signal generator constituting the Nth-order ΔΣ modulator shown in FIG. _n It is a figure which shows the time domain characteristic (a) of this, and a frequency domain characteristic (b).
FIG. 15 is a block diagram showing a schematic configuration of an Nth-order ΔΣ modulation apparatus according to a third embodiment of the present invention.
16 is a random noise signal D from which high-frequency components have been extracted by the HPF filter constituting the Nth-order ΔΣ modulator shown in FIG. 15; _{th_hf} It is a figure which shows the time domain characteristic (a) of this, and a frequency domain characteristic (b).
FIG. 17 is a block diagram illustrating a schematic configuration of an Nth-order ΔΣ modulation apparatus according to a fourth embodiment of the present invention.
18 is a diagram showing a configuration of a specific example of a phase modulator that constitutes the Nth-order ΔΣ modulation device shown in FIG. 17;
FIG. 19 is a diagram showing a configuration of another specific example of the phase modulator constituting the Nth-order ΔΣ modulation apparatus shown in FIG. 17;
FIG. 20 is a block diagram showing a configuration of a conventional ΔΣ modulator.
FIG. 21 is a diagram for explaining a 1-bit quantizer used in the ΔΣ modulation apparatus shown in FIG. 20;
22 shows a 1-bit audio signal (64 Fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG. It is a spectrum distribution map.
[Explanation of symbols]
1 adder, 2 integrator, 3 1-bit quantizer, 78 1-bit quantizer, 80 ΔΣ modulator, 81 local feedback loop

Claims (10)

In a delta-sigma modulation device that performs delta-sigma modulation processing on an input signal and outputs a 1-bit digital signal,
Arithmetic means for subtracting the input signal and the 1-bit digital signal as a feedback signal;
Integrating means composed of a plurality of stages of integrators for integrating the difference signal in the calculating means;
Quantization means for applying a quantization process to the integration output of the integration means and outputting a 1-bit digital signal;
A feedback loop that feeds back the quantized output of the quantizing means to the computing means as the feedback signal;
Based on only the amplitude from the last stage integrator connected immediately before the quantization means, while controlling the threshold level referred to in the quantization process in the quantization means to be variable relative to the time axis. A delta-sigma modulator that determines a variable range of the threshold level.   2. The integration means comprises a plurality of cascaded integrators, and the quantization means performs a quantization process only on the integration output of the integrator connected immediately before and outputs a 1-bit digital signal. The delta-sigma modulation device described. In a delta-sigma modulation method of performing a delta-sigma modulation process on an input signal and outputting a 1-bit digital signal,
An arithmetic step of subtracting the input signal and a 1-bit digital signal as a feedback signal;
An integration step of integrating the difference signal in the calculation step multiple times;
A quantization step of performing a quantization process on the integration output of the integration step and outputting a 1-bit digital signal;
A feedback step of returning the quantized output of the quantization step to the calculation step as the feedback signal,
The threshold level referred to in the quantization process in the quantization process is variably controlled relative to the time axis, and based only on the amplitude in the final stage integration process performed immediately before the quantization process. A delta-sigma modulation method for determining a variable range of the threshold level.   4. The delta according to claim 3, wherein the integration step is a step of cascading a plurality of integrations, and the quantization step performs a quantization process only on the output of the integration performed immediately before to output a 1-bit digital signal. Sigma modulation method. A computing means for computing the difference between the feedback signal and the input signal;
Integrating means composed of a plurality of stages of integrators for integrating the output signal of the computing means;
Noise generating means for generating random noise;
Adding means for adding random noise output from the noise generating means to the integrated output of the integrating means;
Quantization means for 1-bit quantization of the addition output from the addition means;
Feedback loop means for feeding back the 1-bit digital signal output from the quantization means to the computing means as the feedback signal;
Gain adjusting means for adjusting the gain of the random noise generated by the noise generating means based only on the amplitude from the integrator of the final stage connected immediately before the adding means,
A digital signal processing device, wherein random noise whose gain is adjusted by the gain adjusting means is supplied to the adding means. A calculation step of calculating a difference between the feedback signal and the input signal;
An integration step of integrating the output signal of the calculation step a plurality of times;
A noise generation process for generating random noise;
An addition step of adding random noise output from the noise generation step to an integration output of the integration step;
A quantization step of quantizing the addition output from the addition step by 1 bit;
A feedback step of feeding back the 1-bit digital signal output from the quantization step to the calculation step as the feedback signal;
A gain adjustment step of adjusting the gain of the random noise generated by the noise generation step based only on the amplitude in the integration processing at the final stage of the integration step performed immediately before the addition step,
A digital signal processing method in which random noise whose gain has been adjusted in the gain adjusting step is supplied to the adding step. A computing means for computing the difference between the feedback signal and the input signal;
Integrating means composed of a plurality of stages of integrators for integrating the difference signal in the calculating means;
Noise generating means for generating random noise;
Filter means for extracting a high frequency component of a noise signal output from the noise generating means;
Gain adjusting means for performing gain adjustment on the output from the filter means;
Adding means for adding a noise signal composed of a high frequency component gain-adjusted by the gain adjusting means and an output signal from the integrating means;
Quantization means for 1-bit quantization of the addition output from the addition means;
Feedback loop means for feeding back a 1-bit digital signal output from the quantization means as the feedback signal;
A digital signal processing apparatus that determines a threshold value in the gain adjusting means based only on an integration value from a last-stage integrator of the plurality of stages of integrating means. A calculation step of calculating a difference between the feedback signal and the input signal;
An integration step of integrating the difference signal in the calculation step multiple times;
A noise generation process for generating random noise;
A filtering step of extracting a high frequency component of a noise signal output from the noise generation step;
A gain adjustment step of performing gain adjustment on the output from the filtering step;
An addition step of adding a noise signal composed of a high frequency component gain-adjusted in the gain adjustment step and an output signal from the integration step;
A quantization step of quantizing the addition output from the addition step by 1 bit;
A feedback step of feeding back the 1-bit digital signal output from the quantization step as the feedback signal,
A digital signal processing method for determining a threshold value in the gain adjustment step based only on an integration value obtained by the integration processing in the final stage of the integration step. A computing means for computing the difference between the feedback signal and the input signal;
Integrating means for integrating the difference signal in the computing means;
Noise generating means for generating a random 1-bit digital signal;
Phase modulation means for phase modulating a random 1-bit digital signal output from the noise generation means;
Gain adjusting means for performing gain adjustment on the output from the phase modulating means;
An adding means for adding a noise signal composed of a high frequency component gain-adjusted by the gain adjusting means and an output signal from the integrating means;
Quantization means for 1-bit quantization of the output from the addition means;
Feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal,
The phase modulation means outputs an input random 1-bit digital signal as a normal phase output and a reverse phase output based on a first clock, and the first clock with respect to the normal phase output and the reverse phase output. Output alternately based on a second clock having twice as many clocks ,
The digital signal processing apparatus, wherein the integrating means includes a plurality of stages of integrators, and a threshold value in the gain adjusting means is determined based only on an integrated value in the final stage integrator . A calculation step of calculating a difference between the feedback signal and the input signal;
An integration step of integrating the difference signal in the calculation step;
A noise generating step for generating a random 1-bit digital signal;
A phase modulation step of phase modulating a random 1-bit digital signal output from the noise generation step;
A gain adjustment step for performing gain adjustment on the output from the phase modulation step;
An addition step of adding a noise signal composed of a high frequency component gain-adjusted in the gain adjustment step and an output signal from the integration step;
A quantization step for quantizing the output from the addition step by 1 bit;
A feedback step of feeding back the 1-bit digital signal output from the quantization step as the feedback signal,
In the phase modulation step, an input random 1-bit digital signal is output as a normal phase output and a negative phase output based on a first clock, and the first clock is output with respect to the positive phase output and the negative phase output. Output alternately based on a second clock having twice as many clocks ,
A digital signal processing method in which a plurality of stages of integration processing are performed in the integration step, and a threshold value in the gain adjustment step is determined based only on an integration value in the final stage integration processing .

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