JP4645225B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and more particularly to a semiconductor laminated structure for improving the electrostatic withstand voltage characteristics of the element and its It relates to a manufacturing method. However, the semiconductor element referred to here includes a semiconductor light receiving element and the like in addition to a semiconductor light emitting element such as a semiconductor laser or a light emitting diode.
The present invention is very useful for improving the electrostatic withstand voltage characteristics of semiconductor elements.

  The electrostatic withstand voltage characteristic of a semiconductor element is, for example, an endurance test (eg, an ESD test of a human body model (HBM)) in which a reverse electrostatic voltage of about 200 V to 2000 V is applied to the semiconductor element. It can be evaluated by the survival rate of the semiconductor element. For example, as a nitride semiconductor device proposed for the purpose of improving the electrostatic withstand voltage characteristics, those described in Patent Document 1 below are known. FIG. 3 of the present application shows a cross-sectional view (FIG. 1 in Patent Document 1) of the semiconductor element (LED) described in Example 1 in Patent Document 1. As shown in the figure, the semiconductor element includes a substrate 1, a buffer layer 2, an undoped GaN layer 3, an n-side contact layer 4, an n-side first multilayer film layer 5, an n-side second multilayer film layer 6, and an active layer 7. , A p-side multilayer clad layer 8, a p-side GaN contact layer 9, a p-electrode 10, an n-electrode 12, and the like. In particular, the n-side first multilayer film layer 5 and the n-side second multilayer film layer 6 are portions that contribute to the improvement of the electrostatic withstand voltage of this conventional semiconductor element.

In the conventional n-side first multilayer film layer 5 and n-side second multilayer film layer 6 that provide a structure that contributes to an improvement in electrostatic withstand voltage, there is only one semiconductor layer doped with impurities. That is, among the n-side first multilayer film layer 5 and the n-side second multilayer film layer 6, each semiconductor other than the Si-doped n-type intermediate layer 5 b constituting a part of the n-side first multilayer film layer 5. The layers are all formed from an undoped semiconductor.
Japanese Patent No. 3063757

  However, in the multilayer film structure (n-side first multilayer film layer 5 and n-side second multilayer film layer 6) as described above that provides a structure that contributes to improvement in electrostatic withstand voltage, each film thickness is optimized. Even when a high electrostatic voltage is applied, however, the phenomenon of carriers concentrating on defects in the crystal structure in the device cannot always be sufficiently mitigated.

  For example, in a conventional light emitting diode as described above, when an endurance test (an ESD test of a human body model (HBM)) applying a reverse electrostatic voltage of about 1000 V to 1800 V is performed, sufficient output performance is achieved. It was difficult to sufficiently increase the survival rate after the test while maintaining the above.

  In general, providing a structure that contributes to an improvement in electrostatic withstand voltage, for example, as the thickness of an additive-free semiconductor layer in the multilayer film structure as described above increases, the electrostatic withstand voltage characteristics do not improve, but the crystal growth temperature Depending on the setting, there may be an additive-free semiconductor layer in which the electrostatic withstand voltage characteristic of the device is improved rather as the film thickness is smaller, and the tendency is not simply constant. Further, as the film thickness of such an additive-free semiconductor layer is increased, the output performance of the element is lowered against the increase. Therefore, it is difficult to improve the electrostatic withstand voltage characteristics of the semiconductor element while maintaining the output performance of the semiconductor element.

  The present invention has been made to solve the above-mentioned problems, and its purpose is to maintain or improve the light emitting performance or light receiving performance of a semiconductor element to the conventional level, while maintaining the electrostatic withstand voltage of the semiconductor element. The characteristic is to improve compared to the conventional one.

In order to solve the above problems, the following means are effective.
That is, the first means of the present invention is a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and comprises an active layer and an n-type contact layer. from the side of the n-type contact layer between, additive-free semiconductor layer of impurity-free addition, the withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added 2 set has an emission peak wavelength or the light receiving peak wavelength of the active layer is 450nm or more 480nm or less, the additive-free semiconductor layer constituting the second set of withstand voltage structure counted from the side of the n-type contact layer of the In the method for manufacturing a semiconductor element having a thickness of 100 nm to 300 nm , the crystal growth temperature of the added semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the n-type Counting from the contact layer side The crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures are all set to 800 ° C. or more and 900 ° C. or less, and the first set of withstand voltage structures constituting the first set of withstand voltage structures are counted from the n-type contact layer side. A method for manufacturing a semiconductor element, wherein the crystal growth temperature of the additional semiconductor layer is set to 1000 ° C. or more and 1200 ° C. or less. The film thickness of the additive-free semiconductor layer is more preferably 160 nm or more and 240 nm or less.

Further, the above structure may be applied simultaneously to both the n-side and p-side contact layers.
In addition, a plurality of types of impurities may be added at the same time. Further, an n-type impurity and a p-type impurity may be added simultaneously. However, when one additive semiconductor layer is formed by mixing both types of impurities, for example, an n-type contact layer uses n-type impurities at a higher concentration than p-type impurities. And
The semiconductor element may be a semiconductor light emitting element such as a light emitting diode or a semiconductor laser, or a semiconductor light receiving element. The active layer may have an MQW structure or an SQW structure.

A second means of the present invention is a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and comprises an active layer and an n-type contact layer. from the side of the n-type contact layer between, additive-free semiconductor layer of impurity-free addition, the withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added 2 set has an emission peak wavelength or the light receiving peak wavelength of the active layer, the following 550nm inclusive 510 nm, no additives constituting the withstand voltage structure of the second set are counted from the side of the n-type contact layer of the In the method for manufacturing a semiconductor element in which the thickness of the semiconductor layer is 10 nm or more and 50 nm or less , the crystal growth temperature of the added semiconductor layer constituting the first set of withstand voltage structures counted from the n-type contact layer side, and on the n-type contact layer side The crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures are all set to 800 ° C. to 900 ° C., and the first set of withstand voltage structures are configured from the n-type contact layer side. The semiconductor element manufacturing method is characterized in that the crystal growth temperature of the additive-free semiconductor layer is 1000 ° C. or more and 1200 ° C. or less. The film thickness of this additive-free semiconductor layer is more preferably 25 nm or more and 35 nm or less.

According to a third means of the present invention, in the first or second means described above, the additive-free semiconductor layer is made of gallium nitride (GaN) to which no impurity is added.
According to a fourth means of the present invention, in any one of the first to third means, the additive semiconductor layer is made of gallium nitride (GaN) to which silicon (Si) is added. is there.

  More preferably, the crystal growth temperature of the additive-free semiconductor layer is 1050 ° C. or higher and 1150 ° C. or lower.

  More desirably, the crystal growth temperature of the added semiconductor layer is 830 ° C. or higher and 870 ° C. or lower.

  By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

The effects obtained by the above-described means of the present invention are as follows.
In other words, according to the first or second means of the present invention, the above-mentioned withstand voltage structure constituted by one set of two layers is formed in two sets of semiconductor elements, so that the improvement of the electrostatic withstand voltage characteristics is achieved. In the portion composed of the two sets of withstand voltage structures that contribute to the above, at least two or more additional semiconductor layers are provided. According to this configuration, when a high electrostatic voltage is applied, the phenomenon of carriers concentrating on the defects in the crystal structure in the device can be alleviated better than before. Therefore, according to the first or second means of the present invention, the electrostatic withstand voltage characteristic of the element is improved as compared with the prior art while ensuring the light emitting performance or light receiving performance of the element such as the light emission intensity and the threshold voltage at least sufficiently. It can be obtained even better.

In the case where an n-type semiconductor layer is stacked on the lower side, which is closer to the crystal growth substrate, and a p-type semiconductor layer is stacked on the upper side, which is the opposite side, the first or second of the present invention. According to the means, two sets of the withstand voltage structures are formed adjacent to or close to the contact layer on the side close to the crystal growth substrate. Therefore, according to the first or second means of the present invention, even if a high-temperature growth layer for crystal growth at a temperature higher than the crystal growth temperature of the active layer is formed in the above-mentioned withstand voltage structure, the crystal growth There is no risk of heat damage to the active layer in the high temperature environment of the process.

  Therefore, when an n-type semiconductor layer is stacked on the lower side, which is closer to the crystal growth substrate, and a p-type semiconductor layer is stacked on the upper side, which is the opposite side, the crystal quality of the active layer and the above-mentioned It is possible to ensure a high crystal quality of the withstand voltage structure at the same time, so that the light emitting performance or light receiving performance of the device can be effectively maintained or improved.

In addition, when a processed substrate having an uneven surface on the crystal growth surface is used as the crystal growth substrate in order to improve external quantum efficiency, crystal defects are easily formed by the uneven surface, and therefore a high electrostatic voltage is applied to the device. Concentration of carriers to defects at the time of occurrence is more likely to occur on the side closer to the processed substrate.
Therefore, when the n-type semiconductor layer is stacked on the lower side that is the side close to such a processed substrate and the p-type semiconductor layer is stacked on the upper side that is the opposite side, the first or second of the present invention. The above carrier is more effective than the case where an n-type semiconductor layer is stacked on the lower side, which is closer to the processing substrate, and the above-mentioned withstand voltage structure is formed only on the p side. Can be relaxed.
Further, in each semiconductor element that emits or receives light of each wavelength, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while ensuring the light emission performance or the light reception performance. If the film thickness of the additive-free semiconductor layer of the second set of withstand voltage structure is too thin, the resistance of the additive-free semiconductor layer itself becomes too small, making it difficult to improve the electrostatic withstand voltage characteristics. Further, if the film thickness of the additive-free semiconductor layer is too thick, it becomes difficult to ensure the light emitting performance or light receiving performance of the device more than the conventional one for any of the following reasons.
(Reason 1) The resistance of the additive-free semiconductor layer itself becomes too large.
(Reason 2) When the additive-free semiconductor layer is grown at a relatively low crystal growth temperature of about 800 ° C. to 900 ° C., which will be described later, moderate roughness can be formed on the surface of the additive-free semiconductor layer. At this time, if the film thickness of the additive-free semiconductor layer is too thick, the crystal quality of the additive-free semiconductor layer and the crystal quality of the semiconductor layer such as an active layer to be subsequently grown are ensured by the surface roughness. Because it becomes difficult.
In addition, the crystal quality of the semiconductor layer such as the active layer is deteriorated as the surface roughness or thickening of the second set of withstand voltage structure additive-free semiconductor layer at a crystal growth temperature of about 800 ° C. to 900 ° C. This phenomenon is more prominent in a green light-emitting or green light-receiving semiconductor element that uses a relatively large amount of indium (In) that easily causes lattice mismatch due to a large atomic radius.

  In addition, according to the third or fourth means of the present invention, a suitable or optimal withstand voltage structure that exhibits the above-described effects can be easily formed using a general material.

Further, according to the first and second means of the present invention, the crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counting from the n-type contact layer side is set to a relatively high temperature. Therefore, the crystal quality of the additive-free semiconductor layer can be ensured satisfactorily. For this reason, since the crystal quality of each semiconductor layer to be subsequently crystal-grown is ensured, the output performance or input performance of the element can be secured satisfactorily.

According to the first and second means of the present invention, the crystal growth temperature of the added semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the contact layer side Since the crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures counted from the above are set to relatively low temperatures, moderate roughness can be formed on the surfaces of these semiconductor layers. Therefore, according to this onset bright, it can be carriers when the high static voltage is applied to relieve than before the phenomenon of concentration in defects in the crystal structure in the device. Therefore, according to this onset bright, while a light-emitting performance or the light receiving device performance such as emission intensity and the threshold voltage was sufficiently secured, it is possible to obtain an electrostatic withstand voltage characteristics of the device more than before.

  When the emission wavelength or the light reception wavelength in the active layer is set to 450 nm or more and 480 nm or less, the film thickness of each semiconductor layer constituting each second withstand voltage structure counted from the contact layer side. It is more preferable that the total value of the sum of the values and the value of the film thickness of the added semiconductor layer constituting the first set of withstand voltage structures counted from the contact layer side be 140 nm or more and 600 nm or less.

  With this configuration, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while maintaining the light emitting characteristic or the light receiving characteristic more than the conventional one. If the film thickness is too thick, the light emission performance or light reception performance due to the above (reason 1) or (reason 2) is reduced. If the film thickness is too thin, the resistance of these semiconductor layers themselves becomes too small. It becomes difficult to improve the electrostatic withstand voltage characteristics.

  Further, when the emission wavelength or the light reception wavelength in the active layer is set to 510 nm or more and 550 nm or less, the film thickness of each semiconductor layer constituting each withstand voltage structure of the second and subsequent sets counted from the contact layer side. It is more desirable that the total value of the sum of the values and the thickness value of the added semiconductor layer constituting the first withstand voltage structure counted from the contact layer side be 50 nm or more and 250 nm or less.

  With this configuration, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while maintaining the light emitting characteristic or the light receiving characteristic more than the conventional one. If the film thickness is too thick, the light emission performance or light reception performance due to the above (reason 1) or (reason 2) is reduced. If the film thickness is too thin, the resistance of these semiconductor layers themselves becomes too small. It becomes difficult to improve the electrostatic withstand voltage characteristics.

  The thickness of the additive-free semiconductor layer constituting the first set of withstand voltage structures counted from the contact layer side is more preferably 100 nm or more and 300 nm or less. If this film thickness is too thick, the light emitting performance or light receiving performance due to the above (reason 1) is deteriorated. If this film thickness is too thin, the resistance of the additive-free semiconductor layer itself becomes too small and the electrostatic withstand voltage characteristics are reduced. It becomes difficult to improve.

  Further, it is more desirable that the thickness of the added semiconductor layer constituting the first set of withstand voltage structure counted from the contact layer side be 10 nm or more and 100 nm or less. If this film thickness is too thick, the light emission performance or light receiving performance due to the above-mentioned (reason 2) is deteriorated. If this film thickness is too thin, the dispersing action in the lateral direction of the carrier is insufficient, and the electrostatic withstand voltage characteristics. It becomes difficult to improve.

  Further, it is more preferable that the thickness of the added semiconductor layer constituting the second withstand voltage structure counted from the contact layer side is 20 nm or more and 40 nm or less. If this film thickness is too thick, the light emission performance or light receiving performance due to the above-mentioned (reason 2) is deteriorated. If this film thickness is too thin, the dispersing action in the lateral direction of the carrier is insufficient, and the electrostatic withstand voltage characteristics. It becomes difficult to improve.

Note that in the present specification, "Group III nitride compound semiconductor" generally, binary, ternary, or quaternary _{"Al 1-xy Ga y In x} N; 0 ≦ x ≦ 1,0 ≦ y ≦ A semiconductor having an arbitrary mixed crystal ratio represented by a general formula of 1,0 ≦ 1−x−y ≦ 1 is included, and a semiconductor to which a p-type or n-type impurity is added is also included in these “ This is a category of “Group III nitride compound semiconductor”.

Further, at least a part of the above group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or at least a part of nitrogen (N) is phosphorus (P ), Arsenic (As), antimony (Sb), bismuth (Bi), or the like.
Moreover, as said p-type impurity (acceptor), well-known p-type impurities, such as magnesium (Mg) or calcium (Ca), can be added, for example.

As the n-type impurity (donor), for example, known n-type impurities such as silicon (Si), sulfur (S), selenium (Se), tellurium (Te), or germanium (Ge) are used. Can be added.
Moreover, two or more elements may be added simultaneously to these impurities (acceptor or donor), or both types (p-type and n-type) may be added simultaneously.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

FIG. 1 is a cross-sectional view of the light emitting diode 100 according to the first embodiment.
The light emitting diode 100 includes a buffer layer 120, an n-type contact layer 130, an electrostatic withstand voltage portion 140, an n-type cladding layer 150, an MQW active layer 160, a p-type cladding layer 170 on the crystal growth surface of the sapphire substrate 110, The p-type contact layer 180 is obtained by sequentially growing crystals. However, the electrostatic withstand voltage portion 140 is formed by sequentially laminating each semiconductor layer by crystal growth in the order of the additive-free semiconductor layer 141, additive semiconductor layer 142, additive-free semiconductor layer 143, and additive semiconductor layer 144 from the lower side. It is. In the electrostatic withstand voltage portion 140, the additive-free semiconductor layer 141 and the additive semiconductor layer 142 constitute the first set of withstand voltage structure of the present invention. Further, the additive-free semiconductor layer 143, the additive semiconductor layer 144, Thus, the second withstand voltage structure of the present invention is formed.

Hereinafter, a method for manufacturing the light emitting diode 100 will be described with reference to FIG.
Each of the semiconductor layers of the light emitting diode 100 is a crystal grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ : hereinafter referred to as “TMG”), and trimethylindium ( In (CH ₃ ) ₃ : hereinafter referred to as “TMI”), trimethylaluminum (Al (CH ₃ ) ₃ : hereinafter referred to as “TMA”), silane (SiH ₄ ), and cyclopentadienyl magnesium ( Mg (C ₅ H ₅ ) ₂ : hereinafter referred to as “CP ₂ Mg”).
However, as a method for crystal growth of these semiconductor layers, in addition to the above-mentioned organometallic compound vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE), etc. Can be used.

  First, a processed substrate (sapphire substrate 110) having parallel stripe grooves having a triangular cross section as shown in FIG. 1 is set in a MOVPE reaction vessel, and the temperature of the substrate is adjusted while flowing hydrogen. The temperature is raised to 1050 ° C., and the substrate is cleaned.

Here, the purpose of using the sapphire substrate 110 having the sapphire a surface subjected to the above-described concavo-convex processing is at least one of the following, although it depends on the mounting method (power supply form) to the mount or submount, etc. One.
(A) External quantum efficiency is improved when manufacturing a face-down type LED.
(B) Contributes to ELO (semiconductor crystal lateral growth).
(C) Relieve stress generated between the substrate and the semiconductor layer.

(Buffer layer 120)
Subsequently, the temperature is lowered to 510 ° C., hydrogen is used as a carrier gas, ammonia and TMA (trimethylaluminum) are used as a source gas, and a buffer layer 120 made of AlN is grown on the sapphire substrate 110 to a thickness of about 15 nm.

(N-type contact layer 130)
After growth of the buffer layer 120, only TMG is stopped and the temperature is raised to 1100 ° C. When the temperature reaches 1100 ° C., TMG, ammonia gas, and silane gas are used as the source gas, and the n-type contact layer 130 made of GaN doped with Si of 4.5 × 10 ¹⁸ [cm ⁻³ ] is formed to a thickness of 4 μm. Grow in.

(Electrostatic pressure resistant part 140)
(1) Additive-free semiconductor layer 141
Next, only the silane gas is stopped, and an undoped semiconductor layer 141 made of undoped GaN is grown to a thickness of 200 nm using TMG and ammonia gas at 1100 ° C.
(2) Additive semiconductor layer 142
Subsequently, the TMG is turned off and the temperature is lowered to 850 ° C. When the temperature reaches 850 ° C., TMG and silane gas are added, and an additive semiconductor layer 142 made of GaN doped with Si of 4.5 × 10 ¹⁸ [cm ⁻³ ] is grown to a thickness of 50 nm.
The two semiconductor layers of the additive-free semiconductor layer 141 and the additive semiconductor layer 142 constitute the first set of withstand voltage structure of the present invention counted from the n-type contact layer 130 side.

(3) Additive-free semiconductor layer 143
Thereafter, only the silane gas is stopped and an undoped semiconductor layer 143 made of undoped GaN is grown to a thickness of 200 nm at the same temperature (850 ° C.).
(4) Added semiconductor layer 144
Finally, silane gas is added, and an additive semiconductor layer 144 made of GaN doped with Si of 4.5 × 10 ¹⁸ [cm ⁻³ ] is grown at the same temperature (850 ° C.) to a thickness of 30 nm.
The two semiconductor layers of the additive-free semiconductor layer 143 and the additive semiconductor layer 144 constitute a second set of withstand voltage structures of the present invention counted from the n-type contact layer 130 side.

(N-type cladding layer 150)
Next, silane gas and TMG are stopped and the temperature is raised to 1050 ° C. When the temperature reaches 1050 ° C., TMG is added, and a first nitride semiconductor layer made of undoped GaN is grown to 4 nm. Next, the temperature is set to 800 ° C., and TMG, TMI, and ammonia are used to undoped In _0.13 Ga _0.87. A second nitride semiconductor layer made of N is grown by 2 nm. Then, these operations are repeated, and 10 layers are alternately stacked in the order of 1 + 2, and finally, an n-type cladding made of a multilayer film having a superlattice structure in which a first nitride semiconductor layer made of GaN is grown to 4 nm. Layer 150 is grown to a thickness of 64 nm.

(MQW active layer 160)
Next, the temperature is set to 800 ° C., and a barrier layer made of additive-free GaN with a thickness of 20 nm and a well layer made of additive-free In _0.2 Ga _0.8 N with a thickness of 3 nm are alternately stacked. An MQW active layer 160 is grown.

(P-type cladding layer 170)
Next, a third layer of p-type Al _0.2 Ga _0.8 N doped with 1 × 10 ²⁰ [cm ⁻³ ] Mg using TMG, TMA, ammonia, CP ₂ Mg (cyclopentadienyl magnesium) at a temperature of 1050 ° C. Indium doped with 1 × 10 ²⁰ [cm ⁻³ ] of Mg using TMG, TMI, ammonia, CP ₂ Mg at a temperature of 800 ° C. _A fourth nitride semiconductor layer made of _0.03 Ga _0.97 N is grown to a thickness of 2.5 nm. Then, these operations are repeated, and 5 layers are alternately stacked in the order of 3 + 4, and finally a p-type formed of a multilayer film having a superlattice structure in which a third nitride semiconductor layer is grown to a thickness of 4 nm. The cladding layer 170 is grown to a thickness of 36.5 nm.

(P-type contact layer 180)
Subsequently, a p-type contact layer 180 made of p-type GaN doped with 1 × 10 ²⁰ [cm ⁻³ ] of Mg is grown to a thickness of 70 nm using TMG, ammonia, and CP ₂ Mg at 1050 ° C.

  Thereafter, a mask having a predetermined shape is formed on the surface of the uppermost p-type contact layer 180, and etching is performed from the p-type contact layer 180 side by an RIE (reactive ion etching) apparatus. As shown in FIG. A part of the contact layer 130 is exposed.

Next, a light-transmitting p-electrode 191 a is deposited on the p-type contact layer 180, and an n-electrode 192 is deposited on the n-type contact layer 130. The p-electrode 191a includes a first layer made of cobalt (Co) having a thickness of about 1.5 nm directly bonded to the p-type contact layer 180 and a first layer made of gold (Au) having a thickness of about 6 nm bonded to the cobalt film. It is configured by sequentially laminating two layers.
Further, the p-pad electrode 191b deposited on the translucent p-electrode 191a is a first layer made of vanadium (V) having a thickness of about 18 nm and a first layer made of gold (Au) having a thickness of about 1.5 μm _. Two layers and a third layer made of aluminum (Al) having a thickness of about 10 nm are sequentially stacked.
On the other hand, the n-electrode 192 having a multilayer structure includes a first layer made of vanadium (V) having a thickness of about 18 nm and an aluminum (Al ) And the second layer are sequentially laminated.

Note that a protective film made of a SiO ₂ film may be formed on the exposed surface of the translucent p-electrode 191a, the side wall surface of each semiconductor layer exposed by etching, or the like. Further, a reflective metal layer made of, for example, aluminum (Al) having a film thickness of about 500 nm may be deposited on the outermost lowermost portion corresponding to the bottom surface of the sapphire substrate 110. When such a reflective metal layer is formed, nitrides such as TiN and HfN may be used as the material in addition to metals such as Rh, Ti and W.

The light emitting diode 100 produced as described above has a light emission peak wavelength of about 470 nm (blue light emission), and a drive voltage Vf at a forward current of 20 mA is about 3.5V. A durability test (: ESD test of human body model (HBM)) in which a reverse electrostatic voltage of 1000 V to 1800 V was applied to the light emitting diode 100 was performed. The survival rate of the light emitting diode 100 with respect to each static voltage at that time is as follows, and in any case, a significantly higher survival rate was obtained than before.
(A) Survival rate when static voltage is -1000 V: about 83%
(B) Survival rate when static voltage is -1200V: about 83%
(C) Survival rate when static voltage is -1800V: about 82%

  In addition, even if the film thickness of the additive semiconductor layer 142 is varied within the range of 10 nm to 100 nm, the electrostatic breakdown voltage characteristics (survival rate), output characteristics (drive voltage Vf), etc., change significantly. I found that there was no.

On the other hand, in order to compare with the above ESD test, an LED having a conventional structure was prototyped and its survival rate was determined. The comparison LED used here has the same structure as that of the light emitting diode 100 except for the following differences.
(Difference) Instead of stacking three layers of the additive-free semiconductor layer 141, the additive semiconductor layer 142, and the additive-free semiconductor layer 143, a semiconductor composed of 300 nm-thick undoped GaN grown at a crystal growth temperature of 850 ° C. The layer was laminated between the additive semiconductor layer 144 and the n-type contact layer 130. Also in this case, as in the conventional structure illustrated in FIG. 3, the number of semiconductor layers to which impurities are added in the portion that contributes to the electrostatic withstand voltage characteristics is the Si doping corresponding to the added semiconductor layer 144. There is only one semiconductor layer.

As a result of conducting the ESD test similar to the above on the LED for comparison, the survival rate of the LED for comparison was as follows.
(A) Survival rate when static voltage is -1000 V: about 45%
(B) Survival rate when static voltage is -1200V: about 43%
(C) Survival rate when static voltage is -1800V: about 42%

  Further, the output characteristics of the comparative LED were equivalent to those of the light emitting diode 100 described above. From these results, it was found that the electrostatic withstand voltage characteristics can be greatly improved by the means of the present invention while maintaining excellent output performance in the semiconductor element.

FIG. 2 is a cross-sectional view of the light emitting diode 200 according to the second embodiment. The light emitting diode 200 has an emission peak wavelength of about 530 nm (green light emission), and has the same structure as the light emitting diode 100 of Example 1 except for the following differences.
(Difference 1)
The sapphire a surface was used for the crystal growth surface without performing the uneven processing shown in Example 1 on the sapphire substrate 210.

(Difference 2)
In the electrostatic withstand voltage portion 240 of the light emitting diode 200 corresponding to the electrostatic withstand voltage portion 140 of the light emitting diode 100, the undoped constituting the lower layer side of the second withstand voltage structure of the present invention, counted from the n-type contact layer 130 side. The semiconductor layer (additive semiconductor layer 243) was stacked under the following crystal growth conditions.
<Crystal growth conditions> A semiconductor layer (undoped semiconductor layer 243) made of undoped GaN was grown to a thickness of 30 nm at a crystal growth temperature of 850 ° C.

(Difference 3)
The composition of each well layer constituting the MQW active layer 260 was changed. That is, in order to emit green light, each well layer was formed from a semiconductor layer having a thickness of about 3 nm made of undoped In _0.4 Ga _0.6 N.
And about the point other than the above, the light emitting diode 200 of this Example 2 was manufactured on the manufacturing conditions equivalent to the light emitting diode 100 of Example 1. FIG.

In the light emitting diode 200 manufactured in this way, the drive voltage Vf at a forward current of 20 mA was about 3.5V. A durability test (: ESD test of human body model (HBM)) in which a reverse electrostatic voltage of 1000 V was applied to the light emitting diode 200 was performed. The survival rate of the light-emitting diode 200 with respect to the static voltage at that time is as follows, and a significantly higher survival rate than the conventional one was obtained.
(A) Survival rate when static voltage is -1000 V: about 77%

On the other hand, in order to compare with the above ESD test, an LED having a conventional structure was prototyped and its survival rate was determined. The comparison LED used here has the same structure as that of the light emitting diode 200 except for the following differences.
(Difference) Instead of stacking three layers of the additive-free semiconductor layer 141, the additive semiconductor layer 142, and the additive-free semiconductor layer 243, a semiconductor made of undoped GaN having a film thickness of 300 nm grown at a crystal growth temperature of 850 ° C. The layer was laminated between the additive semiconductor layer 144 and the n-type contact layer 130.

As a result of conducting the ESD test similar to the above on the LED for comparison, the survival rate of the LED for comparison was as follows.
(A) Survival rate when static voltage is −1000 V: about 4.1%

  Further, the output characteristics of the comparative LED were equivalent to those of the light emitting diode 200 described above. From these results, it was found that the electrostatic withstand voltage characteristics can be greatly improved by the means of the present invention while maintaining excellent output performance in the semiconductor element.

As a semiconductor element that can obtain the functions and effects of the present invention by applying the present invention, there is a semiconductor light receiving element in addition to a semiconductor light emitting element such as a semiconductor laser or a light emitting diode.
Similarly, the present invention can be applied to other semiconductor devices (semiconductor elements) formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate. The operation and effect of can be obtained.

1 is a cross-sectional view of a light emitting diode 100 of Example 1. Sectional drawing of the light emitting diode 200 of Example 2. FIG. Sectional drawing of the conventional light emitting diode.

100: light emitting diode 110: sapphire substrate 120: buffer layer 130: n-type contact layer 140: electrostatic withstand voltage portion 141: additive-free semiconductor layer (additive-free GaN)
142: Additive semiconductor layer (Si-doped GaN)
143: additive-free semiconductor layer (additive-free GaN)
144: Additive semiconductor layer (Si-doped GaN)
150: n-type cladding layer (superlattice structure)
160: MQW active layer 170: p-type cladding layer (superlattice structure)
180: p-type contact layer 191a: p electrode 191b: p pad electrode 192: n electrode

200: light emitting diode 210: sapphire substrate 220: buffer layer 240: electrostatic withstand voltage portion 243: additive-free semiconductor layer (additive-free GaN)
260: MQW active layer

Claims (4)

The semiconductor layer composed of a Group III nitride compound semiconductor is a semiconductor device formed by a plurality of layers stacked on the substrate, from the side of the n-type contact layer between the active layer and the n-type contact layer , n-type impurity is not added semiconductor layer of additive-free, has two sets of withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added, the active layer The light emission peak wavelength or the light reception peak wavelength is 450 nm or more and 480 nm or less, and the film thickness of the additive-free semiconductor layer constituting the second withstand voltage structure counted from the n-type contact layer side is 100 nm or more and 300 nm or less. In the method for manufacturing a semiconductor element,
The crystal growth temperature of the additional semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the second and subsequent sets counted from the n-type contact layer side. The crystal growth temperature of the semiconductor layer constituting the withstand voltage structure is 800 ° C. or more and 900 ° C. or less,
The crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side is set to 1000 ° C. or more and 1200 ° C. or less.
A method for manufacturing a semiconductor device, comprising: The semiconductor layer composed of a Group III nitride compound semiconductor is a semiconductor device formed by a plurality of layers stacked on the substrate, from the side of the n-type contact layer between the active layer and the n-type contact layer , n-type impurity is not added semiconductor layer of additive-free, has two sets of withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added, the active layer The light emission peak wavelength or the light reception peak wavelength is 510 nm or more and 550 nm or less, and the film thickness of the additive-free semiconductor layer constituting the second set of withstand voltage structure counted from the n-type contact layer side is 10 nm or more and 50 nm. In the following method for manufacturing a semiconductor element:
The crystal growth temperature of the additional semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the second and subsequent sets counted from the n-type contact layer side. The crystal growth temperature of the semiconductor layer constituting the withstand voltage structure is 800 ° C. or more and 900 ° C. or less,
The crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side is set to 1000 ° C. or more and 1200 ° C. or less.
A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor element according to claim 1, wherein the additive-free semiconductor layer is made of gallium nitride (GaN) having no impurity added . 4. The method of manufacturing a semiconductor device according to claim 1, wherein the additional semiconductor layer is made of gallium nitride (GaN) to which silicon (Si) is added . 5.