JP4539489B2 - Manufacturing method of multilayer capacitor - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer capacitor.

As a conventional method of manufacturing a multilayer capacitor, a method of forming an element as follows is known (see Patent Document 1 below). First, one ceramic green layer is formed on a support, the support is peeled off from the formed ceramic green layer, and an electrode pattern is formed on the top surface of the peeled ceramic green layer. A multilayer body is formed by laminating a plurality of ceramic green layers on which the electrode patterns are formed.
JP 2002-198249 A

  In recent years, in order to increase the capacitance of a multilayer capacitor, the thickness of the ceramic green layer is reduced to reduce the interval between the electrode patterns. However, when the thickness of the ceramic green layer is reduced, it becomes difficult to peel the support from the ceramic green layer, and the peeling surface of the ceramic green layer is likely to be deformed. In a multilayer capacitor manufactured by laminating such ceramic green layers, stacking faults such as formation of bubbles between the ceramic green layers are generated. This stacking fault causes a characteristic failure as a multilayer capacitor, and also causes delamination between the stacks.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a multilayer capacitor that suppresses a stacking failure of ceramic green layers.

  The multilayer capacitor manufacturing method of the present invention includes a first layer forming step of forming a first ceramic green layer on a support, and a first electrode forming step of forming a first electrode pattern on the upper surface of the first ceramic green layer. A second layer forming step of forming a second ceramic green layer by laminating on the upper surfaces of the first ceramic green layer and the first electrode pattern, and an upper surface of the second ceramic green layer, the first seen from the laminating direction. A second electrode forming step of forming a second electrode pattern at a position overlapping with the electrode pattern, and a laminate in which the first ceramic green layer, the first electrode pattern, the second ceramic green layer, and the second electrode pattern are laminated A peeling step for peeling the support, an element forming step for preparing a plurality of laminates from which the support has been peeled off, and laminating the plurality of laminates, and a plurality of laminations The first terminal electrode is formed on the outer surface of the element so as to be connected to the first electrode pattern and the second electrode pattern included in the predetermined stacked body of the body, and included in the predetermined stacked body among the plurality of stacked bodies And a terminal forming step of forming a second terminal electrode on the outer surface of the element so as to be connected to the first electrode pattern and the second electrode pattern.

  According to the multilayer capacitor manufacturing method of the present invention, a multilayer body in which the first ceramic green layer, the first electrode pattern, the second ceramic green layer, and the second electrode pattern are formed on the support, Since the support is peeled from the body, the thickness of the laminate when peeling from the support is made thicker than when the ceramic green layer and one electrode pattern are stacked and then peeled off from the support. Can be set. Therefore, the support can be easily peeled from the laminated body, and deformation of the peeled surface of the laminated body can be suppressed. Therefore, it is possible to stack the laminates with less deformation of the peeling surface and suppress the stacking failure of the ceramic green layers in the multilayer capacitor.

  Preferably, in the first electrode forming step, a plurality of first electrode patterns are two-dimensionally arranged, and in the second layer forming step, the second ceramic green layer and the plurality of first ceramic green layers are formed. In the second electrode forming step, a plurality of second electrode patterns are formed on the upper surface of the second ceramic green layer, and are respectively formed on the upper surfaces of the electrode patterns and viewed from the stacking direction. In the element formation step, the plurality of stacked bodies are arranged in a predetermined arrangement direction of the first electrode patterns adjacent to each other in the stacking direction of the stacked bodies. An assembly is formed by stacking so as to deviate by a predetermined pitch, and is adjacent to a first cut surface that is parallel to a predetermined arrangement direction and passes between adjacent first electrode patterns and perpendicular to the predetermined arrangement direction. First Forming a plurality of elements by cutting the assembly at the surface and the second cutting surface is a plane passing through the center of the first electrode pattern between the electrode patterns.

  In this case, a plurality of first electrode patterns and a plurality of second electrode patterns are two-dimensionally arranged so as to overlap each other, and the stacked body is stacked so as to deviate by a predetermined pitch. Since a plurality of elements are formed by cutting the first cut surface and the second cut surface, the multilayer capacitor can be formed efficiently. Therefore, it is possible to efficiently manufacture a plurality of multilayer capacitors while suppressing the stacking failure of the ceramic green layers.

  In the multilayer capacitor manufacturing method of the present invention, in the second electrode forming step, the contour line of the second electrode pattern is formed so as to be inside from the contour line of the first electrode pattern as viewed from the stacking direction. Is also preferable.

  By doing in this way, in the element, the contour line of the second electrode pattern is formed so as to be inside from the contour line of the corresponding first electrode pattern as viewed from the stacking direction. Accordingly, it is possible to suppress variation in the area where the first electrode pattern and the second electrode pattern included in one stacked body in the element overlap. Therefore, variation in the overlapping area when viewed from the stacking direction of the first electrode pattern and the second electrode pattern included in one adjacent stacked body and the first electrode pattern and the second electrode pattern included in the other stacked body is caused. Can be suppressed. Therefore, variation in the capacitance of the multilayer capacitor can be suppressed.

  In the multilayer capacitor manufacturing method of the present invention, it is also preferable to adjust the capacitance of the multilayer capacitor by adjusting the thickness of the first ceramic green layer in the first layer forming step.

  In this way, the thickness of the multilayer body when peeling the support is set to a thickness that facilitates peeling, and the thickness of the first ceramic green layer is adjusted to facilitate the capacitance of the multilayer capacitor. Can be adjusted.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the multilayer capacitor which suppresses the lamination | stacking defect of a ceramic green layer can be provided.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  First, the configuration of the multilayer capacitor according to this embodiment will be described. FIG. 1 is a perspective view of the multilayer capacitor 1 according to the present embodiment. As shown in FIG. 1, the multilayer capacitor 1 includes a substantially rectangular parallelepiped element 5 and a pair of first terminal electrode 2 and second terminal electrode 4 formed on the element 5.

  The element 5 has a pair of end faces opposed to the longitudinal direction of the element 5, a pair of side faces opposed to the stacking direction of the element 5, and a pair of side faces opposed to the longitudinal direction and the direction perpendicular to the stacking direction. Yes. The first terminal electrode 2 is formed so as to cover the entire surface of one end surface, and a part of the first terminal electrode 2 wraps around each side surface. The second terminal electrode 4 is formed so as to cover the entire surface of the other end face, and a part of which wraps around each side face. One of the pair of side surfaces facing the stacking direction of the element 5 is a surface facing the external substrate when the multilayer capacitor 1 is mounted on the external substrate.

  The configuration of the element 5 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the multilayer capacitor 1 according to the present embodiment. The element 5 includes an inner layer part 9 in which a plurality of rectangular internal electrodes are formed, and two outer layer parts 7 sandwiching the inner layer part 9. The inner layer portion 9 generates a capacitance component of the multilayer capacitor 1, and the outer layer portion 7 has a function of protecting the inner layer portion 9 and adjusting the thickness dimension of the multilayer capacitor 1.

  In the inner layer portion 9, a plurality of pairs of first internal electrode pairs A each including a first internal electrode 11 </ b> A and a second internal electrode 13 </ b> A that are electrically connected to the first terminal electrode 2 are formed. One side of each first internal electrode 11A and each second internal electrode 13A formed in a rectangular shape is exposed at the end face where the first terminal electrode 2 is formed, and mechanically and electrically with the first terminal electrode 2 It is connected. In the present embodiment, two pairs of first internal electrode pairs A are formed. The first internal electrode 11A and the second internal electrode 13A included in the pair of first internal electrode pairs A have substantially the same shape and are formed so as to overlap each other through the dielectric layer 20 when viewed from the stacking direction. Yes. In the pair of first internal electrodes A, the second internal electrode 13A has a smaller area than the first internal electrode 11A, and the outline excluding the connection portion of the second internal electrode 13A with the first terminal electrode 2 is the first internal electrode. The electrode 11 </ b> A is formed so as to be on the inner side when viewed from the stacking direction with respect to the contour line excluding the connection portion with the first terminal electrode 2. For example, the outline of the second internal electrode 13A is formed so as to be approximately 30 μm inside the outline of the first internal electrode 11A.

  The inner layer portion 9 is formed with a plurality of second internal electrode pairs B including a first internal electrode 11B and a second internal electrode 13B that are electrically connected to the second terminal electrode 4. One side of each of the first internal electrodes 11B and the second internal electrodes 13B formed in a rectangular shape is exposed at the end surface where the second terminal electrode 4 is formed, and mechanically and electrically connected to the second terminal electrode 4. It is connected. In the present embodiment, two pairs of second internal electrode pairs B are formed. The first internal electrode 11B and the second internal electrode 13B included in the pair of second internal electrode pairs B have substantially the same shape and are formed so as to overlap each other through the dielectric layer 20 when viewed from the stacking direction. Yes. In the pair of second internal electrodes B, the second internal electrode 13B has a smaller area than the first internal electrode 11B, and the outline excluding the connection portion of the second internal electrode 13B with the second terminal electrode 4 is the first internal electrode. The electrode 11B is formed so as to be on the inner side when viewed from the stacking direction with respect to the contour line excluding the connection portion between the electrode 11B and the second terminal electrode 4. For example, the contour line of the second internal electrode 13B is formed to be about 30 μm inside the contour line of the first internal electrode 11B.

  The first internal electrode 11A and the first internal electrode 11B have substantially the same shape and the same area, and the second internal electrode 13A and the second internal electrode 13B have substantially the same shape and the same area. The thickness of the dielectric layer 20 between the first internal electrode 11A and the second internal electrode 13A included in the pair of first internal electrodes A and the first internal electrode included in the second internal electrode pair B The thickness D1 of the dielectric layer 20 between 11B and the second internal electrode 13B is approximately the same.

  In the inner layer portion 9, the first internal electrode pairs A and the second internal electrode pairs B are alternately stacked via the dielectric layers 20. The first internal electrode pair A and the second internal electrode pair B are different from each other in a predetermined dimension by the first internal electrode pair A on the first terminal electrode 2 side and the second internal electrode pair B on the second terminal electrode 4 side. Are stacked. Further, the thickness of the dielectric layer 20 between the second internal electrode 13A, the first internal electrode 11B adjacent to the second internal electrode 13A and the dielectric layer 20, the second internal electrode 13B, The thickness of the dielectric layer 20 between the internal electrode 13B and the adjacent first internal electrode 11A across the dielectric layer 20 is approximately the same thickness D2.

  The capacitance of the multilayer capacitor 1 is determined between the second internal electrode 13A, the second internal electrode 13A and the first internal electrode 11B adjacent to the dielectric layer 20, and the second internal electrode 13B, 2 mainly occurs between the internal electrode 13B and the first internal electrode 11A adjacent to each other with the dielectric layer 20 in between. That is, the capacitance of the multilayer capacitor 1 mainly depends on the thickness D2.

  Subsequently, a method for manufacturing the multilayer capacitor 1 according to the present embodiment will be described. FIG. 3 shows the procedure of the manufacturing method of the multilayer capacitor 1 of the present embodiment. As shown in FIG. 3, the manufacturing method of the multilayer capacitor 1 of the present embodiment includes a first layer forming step S1, a first electrode forming step S2, a second layer forming step S3, a second electrode forming step S4, and a peeling step S5. The device forming step S6 and the terminal forming step S7 are provided.

  First, as a process of forming the laminated body 10, the first layer forming process S1, the first electrode forming process S2, the second layer forming process S3, the second electrode forming process S4, and the peeling process S5 will be described with reference to FIG. While explaining. FIG. 4 is a cross-sectional view of the multilayer body 10 formed in the manufacturing process of the multilayer capacitor 1 according to the present embodiment.

  In the first layer forming step S1, the first ceramic green layer 21 is formed on the PET film P1 (support). The first ceramic green layer 21 is obtained by adding a ceramic slurry obtained by adding and mixing a binder resin (for example, an organic binder resin), a solvent, a plasticizer, etc. to a dielectric material mainly composed of barium titanate. It is formed by applying and drying on P1. The thickness D2 of the first ceramic green layer 21 is, for example, about 3.5 μm.

  Next, in the first electrode formation step S <b> 2, a plurality of first electrode patterns 11 are formed on the upper surface of the first ceramic green layer 21. The first electrode pattern 11 is formed by printing an electrode paste on the upper surface of the first ceramic green layer 21 and then drying it. The electrode paste is a paste-like composition obtained by mixing a binder resin, a solvent, or the like with a metal powder such as Ni, Ag, or Pd. For example, screen printing or the like is used as the printing means. The thickness of the first electrode pattern 11 is, for example, about 1.1 to 1.2 μm.

  Next, in the second layer forming step S <b> 3, the second ceramic green layer 23 is formed on the upper surfaces of the first ceramic green layer 21 and the plurality of first electrode patterns 11. Similar to the first ceramic green layer 23, the second ceramic green layer 23 is formed by applying a ceramic slurry and then drying it. The second ceramic green layer 23 covers the upper surface of the first electrode pattern 11 and is filled between the plurality of first electrode patterns 11, and the upper surface of the second ceramic green layer 23 is formed in a planar shape. The thickness D1 of the second ceramic green layer 23 from the upper surface of the first electrode pattern 11 to the upper surface of the second ceramic green layer 23 is about 1.6 μm.

  Next, in the second electrode formation step S4, a plurality of second electrode patterns 13 are formed on the upper surface of the second ceramic green layer 23 at positions overlapping with the plurality of first electrode patterns 11 when viewed from the stacking direction. To do. Similar to the first electrode pattern 11, the second electrode pattern 13 is formed by printing and drying the electrode paste. The thickness of the second electrode pattern 13 is, for example, about 1.1 to 1.2 μm.

  In the second electrode formation step S4, when the second electrode pattern 13 is printed, the second ceramic green layer 23 is dissolved by the solvent contained in the printed electrode paste, and the second electrode pattern 13 and the first electrode pattern 11 May be electrically connected. As will be described later, since the first electrode pattern 11 and the second electrode pattern 13 are electrically connected to the terminal electrode of the same polarity, in the multilayer capacitor of this embodiment, the second electrode pattern 13 and the first electrode Even when the pattern 11 is electrically connected, there is no problem in performance.

  After the second electrode forming step S4, the auxiliary layer 25 is formed on the second ceramic green layer 23 by printing and drying the ceramic paste on the blank portion where the second electrode pattern 13 is not formed. The ceramic paste forming the auxiliary layer 25 and the ceramic slurry may be the same component or different components. At this time, the auxiliary layer 25 and the second electrode pattern 13 have the same thickness. With this configuration, as will be described later, it is possible to stack the layers more accurately without causing a difference in thickness when another layer is stacked on the second electrode pattern 13. . Note that the auxiliary layer 25 is not necessarily formed.

  Through the above steps, the laminate 10 in which the first ceramic green layer 21, the plurality of first electrode patterns 11, the second ceramic green layer 23, and the plurality of second electrode patterns 13 are formed is completed. The thickness D3 of the laminated body 10 is about 7.3 to 7.5 μm.

  Next, in peeling process S5, PET film P1 is peeled from the laminated body 10. FIG. The laminated body 10 formed in this way is shown in FIG. FIG. 5 is a plan view of the multilayer body 10 formed in the manufacturing process of the multilayer capacitor 1 according to the present embodiment.

  As shown in FIG. 5, in the first electrode formation step S2, a plurality of first electrode patterns 11 are two-dimensionally arranged. Thereafter, after the second ceramic green layer 23 is formed, a plurality of second electrode patterns 13 are formed on the upper surface of the second ceramic green layer 23 in the second electrode forming step S4. The plurality of second electrode patterns 13 are formed in a two-dimensional arrangement so as to overlap each other with the plurality of first electrode patterns 11 when viewed from the stacking direction.

  The first electrode pattern 11 and the second electrode pattern 13 are each substantially rectangular and are formed to have substantially the same shape. In the second electrode formation step S4, the length of one side of the second electrode pattern 13 is 2 · d1 shorter than the length of one side of the first electrode pattern 11, and the length of the other side of the second electrode pattern 13 is the first length. The electrode pattern 11 is formed to be shorter by 2 · d1 than the length of the other side. That is, when viewed from the stacking direction of the first electrode pattern 11 and the second electrode pattern 13, the contour line of the second electrode pattern 13 is formed so as to be located inside the distance d 1 from the contour line of the first electrode pattern 11. To do. For example, the distance d1 is about 30 μm.

  Subsequently, the element formation step S6 will be described with reference to FIG. FIG. 6 is a cross-sectional view showing the assembly 30 formed in the multilayer capacitor manufacturing process according to the present embodiment. In the element forming step S <b> 6, a plurality of laminated bodies 10 from which the PET film P <b> 1 is peeled off are prepared, the plurality of laminated bodies 10 are laminated to form the aggregate 30, and the aggregate 30 is cut to thereby form a plurality of elements 5. Form. For example, four stacked bodies 10A to 10D are prepared, and the prepared stacked bodies 10A to 10D are stacked as shown in FIG. The assembly 30 includes an outer layer portion 7 and a plurality of laminated bodies 10A to 10D. The outer layer portion 7, the laminated body 10A, the laminated body 10B, the laminated body 10C, the laminated body 10D, and the outer layer portion 7 are laminated in this order and are pressure-bonded. Is formed. The outer layer portion 7 is formed by laminating a plurality of ceramic green layers on which no electrode pattern is formed.

  The stacked bodies 10 </ b> A to 10 </ b> D are stacked so that the first electrode patterns 11 adjacent in the stacking direction are shifted by a predetermined pitch in the predetermined array direction of the first electrode patterns 11. That is, the stacked bodies 10 </ b> A to 10 </ b> D are stacked so as to be shifted by approximately a half pattern for each layer in a direction perpendicular to the stacking direction and in a direction parallel to the predetermined arrangement direction of the first and second electrode patterns 11 and 13. . When the formation interval of the first electrode patterns 11 on the first ceramic green layer 21 is dx, the stacked bodies 10 are stacked while being shifted by dx / 2.

  Subsequently, the assembly 30 is cut along a first cut surface (not shown) and a second cut surface L that are orthogonal to each other, thereby forming a plurality of elements 5. The first cut surface is a surface that is perpendicular to the stacking direction and parallel to the predetermined arrangement direction, and is a surface that passes between the first and second electrode patterns 11 and 13 formed in an array. The second cut surface L is a surface perpendicular to the stacking direction and the predetermined arrangement direction, and passes through the central portion of the first and second electrode patterns 11 and 13 and the first and second electrode patterns 11 and 13. And a plane passing through the middle of

  After cutting, the binder contained in the first ceramic green layer 21, the second ceramic green layer 23, and the auxiliary layer 25 of the element 5 is removed and fired.

  Next, in the terminal formation step S <b> 7, the first terminal electrode 2 and the second terminal electrode 4 are formed on the outer surface of the element 5. First and second terminal electrodes 2 and 4 are formed on the cut surfaces of the element 5 that are cut by the second cut surface L and facing each other. The first electrode pattern 11 and the second electrode pattern 13 that are exposed at the side surface of the element 5 by being cut by the second cut surface L are electrically connected via the formed first and second terminal electrodes 2 and 4. Connected.

  For example, the first electrode pattern 11 and the second electrode pattern 13 included in the stacked body 10A and the stacked body 10C and cut at the center are connected to the first terminal electrode 2, and the stacked body 10B and the stacked body The first electrode pattern 11 and the second electrode pattern 13 which are included in 10D and whose central portion is cut are connected to the second terminal electrode 4.

  Thus, the 1st electrode pattern 11 and the 2nd electrode pattern 13 which the center part was cut | disconnected and connected to the 1st terminal electrode 2 are respectively the 1st internal electrode 11A and 2nd internal electrode 13A of the multilayer capacitor 1 which were mentioned above. It corresponds to. The first electrode pattern 11 and the second electrode pattern 13 that are cut at the center and connected to the second terminal electrode 4 are respectively the first internal electrode 11B and the second internal electrode 13B of the multilayer capacitor 1 described above. It corresponds to. Note that the first ceramic green layer 21, the second ceramic green layer 23, and the auxiliary layer 25 constitute the dielectric layer 20. The multilayer capacitor 1 is completed through the steps described above.

  In the multilayer capacitor 1 manufactured as described above, the second internal electrode 13A, the thickness of the dielectric layer between the second internal electrode 13A and the first internal electrode 11B adjacent to the dielectric layer, and the second The thickness of the dielectric layer between the internal electrode 13B and the first internal electrode 11A adjacent to the second internal electrode 13B with the dielectric layer interposed therebetween corresponds to the thickness D2 of the first ceramic green layer 21. That is, the capacitance of the multilayer capacitor 1 mainly depends on the thickness D2 of the first ceramic green layer 21.

  The thickness D2 of the first ceramic green layer 21 is set according to the desired capacitance of the multilayer capacitor 1. Furthermore, the thickness D3 of the laminated body 10 is set to a dimension that allows the PET film P1 to be more easily peeled from the laminated body 10. The thickness D2 is set so that the set thickness D3 of the laminated body 10 can be obtained.

  Then, the effect of the manufacturing method of the multilayer capacitor 1 according to this embodiment will be described.

  According to the method for manufacturing the multilayer capacitor 1 of the present embodiment, the multilayer body 10 in which the first ceramic green layer 21, the first electrode pattern 11, the second ceramic green layer 23, and the second electrode pattern 13 are formed is a PET film. Since the PET film is peeled off from the laminate 10 after being formed on the P1, the PET film P1 is peeled off from the case where it is peeled off from the PET film P1 after one ceramic green layer and one electrode pattern are laminated. The thickness of the laminated body 10 at the time of peeling can be set thick. Therefore, it is easy to peel the PET film P1 from the laminate 10, and deformation of the peeled surface of the PET film P1 in the laminate 10 can be suppressed. Therefore, it is possible to stack the laminated body 10 with less deformation of the peeling surface, and to suppress the stacking failure of the ceramic green layers in the multilayer capacitor 1.

  Moreover, in the manufacturing method of the multilayer capacitor 1 of the present embodiment, the PET film is adjusted by adjusting the capacitance of the multilayer capacitor 1 by adjusting the thickness of the first ceramic green layer 11 in the first layer forming step S1. It is possible to easily adjust the capacitance of the multilayer capacitor 1 by adjusting the thickness of the first ceramic green layer 11 while setting the thickness of the multilayer body 10 at the time of peeling P1 to be easily peelable. it can.

  In the above description, the thickness D2 of the first ceramic green layer 21 is about 3.5 μm, and the thickness D1 of the dielectric layer between the upper surface of the first electrode pattern 11 and the lower surface of the second electrode pattern 13 is about 1.6 μm. The thickness D3 of the laminate 10 was set to about 7.3 to 7.5 μm. For example, the capacitance value of the multilayer capacitor 1 can be increased by making the thickness D2 of the first ceramic green layer 21 smaller than 3.5 μm. At that time, in order to keep the thickness D3 of the laminated body 10 at about 7.3 to 7.5 μm which is easy to peel from the PET film P1, the upper surface of the first electrode pattern 11 and the second electrode pattern 13 The thickness D1 of the dielectric layer between the lower surface can be further increased.

  Further, according to the method for manufacturing the multilayer capacitor 1 of the present embodiment, the plurality of first electrode patterns 11 and the plurality of second electrode patterns 13 are two-dimensionally arranged so as to overlap each other, and the multilayer body 10 is formed. Since the plurality of elements 5 are formed by cutting the first cut surface and the second cut surface L after forming the aggregate 30 so as to be shifted by a predetermined pitch, the multilayer capacitor 1 is efficiently formed. be able to. Therefore, it is possible to efficiently manufacture a plurality of multilayer capacitors 1 while suppressing the stacking failure of the ceramic green layers.

  Further, in the method for manufacturing the multilayer capacitor 1 of the present embodiment, in the second electrode formation step S4, the contour line of the second electrode pattern 13 is more inside than the contour line of the first electrode pattern 11 when viewed from the stacking direction. In the element 5, the contour line of the second electrode pattern 13 excluding the cutting line by the second cutting plane L is viewed from the stacking direction more than the contour line of the corresponding first electrode pattern 11. Will be formed inside. Therefore, it is possible to suppress variation in the area where the first internal electrode 11A and the second internal electrode 13A, and the first internal electrode 11B and the second internal electrode 13B included in one laminated body 10 in the element 5 overlap. it can. Therefore, the first internal electrode 11A and the second internal electrode 13A included in one adjacent stacked body 10 and the first internal electrode 11B and the second internal electrode 13B included in the other stacked body are viewed from the stacking direction. Variation in overlapping areas can be suppressed. Therefore, variations in the capacitance of the multilayer capacitor 1 can be suppressed.

1 is a perspective view of a multilayer capacitor according to an embodiment. It is sectional drawing of the multilayer capacitor which concerns on this embodiment. It is a flowchart which shows the procedure of the manufacturing method of the multilayer capacitor which concerns on this embodiment. It is sectional drawing of the laminated body formed in the manufacturing process of the multilayer capacitor which concerns on this embodiment. It is a top view of the laminated body formed in the manufacturing process of the multilayer capacitor concerning this embodiment. It is sectional drawing of the aggregate | assembly formed in the manufacturing process of the multilayer capacitor concerning this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 2 ... 1st terminal electrode, 4 ... 2nd terminal electrode, 5 ... Element, 7 ... Outer layer part, 9 ... Inner layer part, 10, 10A-10D ... Laminated body, 11 ... 1st electrode pattern, 11A ... 1st internal electrode, 11B ... 1st internal electrode, 13 ... 2nd electrode pattern, 13A ... 2nd internal electrode, 13B ... 2nd internal electrode, 20 ... Dielectric layer, 21 ... 1st ceramic green layer, 23 ... 2nd ceramic green layer, 25 ... auxiliary layer, 30 ... aggregate, A ... internal electrode pair, B ... internal electrode pair, D1-D3 ... thickness, d1 ... distance, L ... second cut surface, P1 ... PET film .

Claims (2)

A first layer forming step of forming a first ceramic green layer on a support;
A first electrode forming step of forming a plurality of first electrode patterns two-dimensionally on the upper surface of the first ceramic green layer;
A second layer forming step of forming a second ceramic green layer by laminating the first ceramic green layer and the plurality of first electrode patterns;
Forming a second electrode on the upper surface of the second ceramic green layer to form a plurality of second electrode patterns that are two-dimensionally arranged so as to overlap with the plurality of first electrode patterns as viewed from the stacking direction. Process,
A peeling step of peeling the support from a laminate in which the first ceramic green layer, the first electrode pattern, the second ceramic green layer, and the second electrode pattern are laminated;
A plurality of the laminates from which the support has been peeled are prepared, and the plurality of laminates are adjacent to each other in the stacking direction of the laminate, with the first ceramic green layer and the plurality of second electrode patterns facing each other. The first electrode patterns are stacked so as to be shifted by a predetermined pitch in a predetermined arrangement direction of the first electrode patterns to form an aggregate, and the first electrodes adjacent to each other in parallel to the predetermined arrangement direction A first cut surface that passes between the patterns, a second cut surface that is a surface that is perpendicular to the predetermined arrangement direction and is adjacent to the first electrode pattern, and a surface that passes through the center of the first electrode pattern; The element forming step of forming a plurality of elements by cutting and firing the aggregate in
To connect to the internal electrode made of one of the exposed end face and fired the second electrode pattern exposed is and baked on one end face of the inner electrode and the element consisting of the first electrode pattern of the element the first terminal electrodes are formed on the outer surface of the element, it is exposed and baked in the other end face of the other exposed end face and fired internal electrode and the element consisting of the first electrode pattern of the element And a terminal forming step of forming a second terminal electrode on the outer surface of the element so as to be connected to the internal electrode comprising the second electrode pattern,
In the second electrode forming step, the second electrode pattern is formed so that the entire contour line of the second electrode pattern is located inside the entire contour line of the first electrode pattern when viewed from the stacking direction. A manufacturing method of a multilayer capacitor.   2. The method of manufacturing a multilayer capacitor according to claim 1, wherein, in the first layer forming step, a capacitance of the multilayer capacitor is adjusted by adjusting a thickness of the first ceramic green layer.

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