JP4535853B2 - Constant voltage power circuit - Google Patents

Description

  The present invention relates to a constant voltage power supply circuit that outputs a DC voltage of a predetermined voltage, and more particularly to a constant voltage power supply circuit that can be easily reduced in size and increased in output and can stably obtain a desired voltage value.

  In a “mag amplifier control type” constant voltage power supply circuit using a supersaturated reactor, it is common to insert a supersaturated reactor on the output power line to control the output voltage to a constant voltage.

FIG. 10 shows a configuration of a conventional master-slave multi-output power supply circuit using a supersaturated reactor.
In the circuit configuration shown in the figure, the PWM control IC 39 constituting the voltage control loop exists on the master output side, so that the converter on the slave side performs the switching operation with the ON duty determined on the master side regardless of the output fluctuation. Do.
In order to stabilize the output voltage on the slave side, a supersaturated reactor 18 is inserted in the output line on the slave side, and constant voltage control is performed by this function.

  However, in the conventional mag-amp control system, since the supersaturated reactor is inserted into the output line, the shape of the supersaturated reactor, the winding diameter, and the number of turns must be selected according to the output voltage and current.

  In general, it is necessary to enlarge the supersaturated reactor as the output voltage increases, and to increase the winding diameter as the output current increases. Accordingly, a supersaturated reactance inserted into an output line through which a high voltage and a large current flow must be applied with a thick and large winding. This not only hinders miniaturization of the power supply circuit, but also increases the cost.

As a conventional technique for performing constant voltage control of a switching power supply circuit using a supersaturated reactor, there is a “resonant switching power supply device” disclosed in Patent Document 1.
The invention disclosed in Patent Document 1 is intended to stabilize the output voltage by changing the on-time of the transistor.
JP 7-87737 A

  In the invention disclosed in Patent Document 1, a control winding is provided in a common magnetic core (core) in addition to a primary winding and a secondary winding for two transistors. By changing the control current flowing through the control winding, the time until the magnetic core reaches saturation is controlled by the self-feedback of the primary winding. However, when the control current changes, the inductance of the winding also changes, so that the on / off time of the transistor deviates from a desired value. For this reason, a desired voltage cannot be obtained or it takes time to obtain the desired voltage.

  Further, since the control winding is provided in a common magnetic core in addition to the primary winding and the secondary winding for each of the two transistors, it is difficult to increase the number of outputs.

  Thus, conventionally, there has not been provided a constant voltage power supply circuit that can be easily reduced in size and increased in output and can stably obtain a desired voltage value.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a constant voltage power supply circuit that can be easily reduced in size and increased in output and can stably obtain a desired voltage value.

  In order to achieve the above object, according to a first aspect of the present invention, a DC voltage supplied from a DC power source is switched by a field effect transistor to be converted into a primary AC voltage, and the primary AC voltage is converted to 2 by a transformer. A constant voltage power supply circuit that transforms into a secondary AC voltage and rectifies the secondary AC voltage to generate an output voltage, the output terminal of a clock generator that generates a clock of a predetermined period, and the gate terminal of a field effect transistor A bypass circuit for bypassing a discharge current generated at the gate terminal by a parasitic capacitance between the gate and the source of the field effect transistor when the field effect transistor is turned off, and an output. A voltage detection circuit that detects the voltage value of the voltage, and a discharge current in the bypass circuit according to the output from the voltage detection circuit. There is provided a constant voltage power supply circuit and having a feedback circuit for changing the rate of bypassed to Chi source terminal.

  In the first aspect of the present invention, it is preferable to have a smoothing circuit for suppressing pulsation of the output voltage.

  In any of the above configurations of the first aspect of the present invention, it is preferable to rectify the secondary AC voltage by a diode rectification method. Alternatively, it is preferable to rectify the secondary AC voltage using the FET synchronous rectification method. In addition, the flyback voltage generated in the transformer when the field effect transistor is off is clamped in parallel with the primary coil of the transformer. More preferably, the feedback circuit further preferably drives the clamp circuit in accordance with the output from the voltage detection circuit.

  In order to achieve the above object, as a second aspect of the present invention, a master FET and a slave FET that switch a DC voltage supplied from a DC power source into a primary AC voltage and a master FET that outputs the master FET are provided. A master transformer that transforms a primary AC voltage into a master secondary AC voltage, a slave transformer that transforms a slave primary AC voltage output from a slave FET into a slave secondary AC voltage, and a master that rectifies the master secondary AC voltage A master rectifier circuit that outputs an output voltage, a slave rectifier circuit that rectifies a slave secondary AC voltage and outputs a slave output voltage, a clock generator that supplies a clock of a predetermined period to the gate terminal of the master FET, and a clock generator Oversaturation reactor located between the output terminal of the detector and the gate terminal of the slave FET A bypass circuit for bypassing a discharge current generated at the gate terminal of the slave FET by a parasitic capacitance between the gate and source of the slave FET when the slave FET is turned off to the source terminal of the slave FET, and a voltage of the master output voltage Master voltage detection circuit that detects the value, master feedback circuit that changes the period of the clock supplied to the gate terminals of the master FET and slave FET according to the output from the master voltage detection circuit, and the voltage value of the slave output voltage A constant voltage power supply comprising: a slave voltage detection circuit configured to perform the operation; and a slave feedback circuit configured to change a ratio of the discharge current bypassed to the source terminal of the slave FET in the bypass circuit according to an output from the slave voltage detection circuit. Provide circuit Is shall.

  In the second aspect of the present invention, the power supply circuit may be a multi-output power supply including a plurality of slave FETs, a supersaturated reactor, a slave transformer, a bypass circuit, a slave voltage detection circuit, and a slave feedback circuit. preferable.

  In any of the above configurations of the second aspect of the present invention, it is preferable to have a master smoothing circuit for suppressing pulsation of the master output voltage. Moreover, it is preferable to have a slave smoothing circuit for suppressing the pulsation of the slave output voltage.

  In any of the above configurations of the second aspect of the present invention, it is preferable to rectify the master secondary AC voltage by a diode rectification method. Alternatively, it is preferable to rectify the master secondary AC voltage by the FET synchronous rectification method, and in addition to this, a flyback voltage generated in the master transformer in parallel with the primary side coil of the master transformer when the master FET is off. More preferably, the master feedback circuit further includes a master clamp circuit, and more preferably, the master feedback circuit drives the master clamp circuit in accordance with an output from the master voltage detection circuit.

  In any of the above configurations of the second aspect of the present invention, it is preferable to rectify the slave secondary AC voltage by a diode rectification method. Alternatively, it is preferable to rectify the slave secondary AC voltage by the FET synchronous rectification method, and in addition to this, the flyback voltage generated in the slave transformer when the slave FET is off in parallel with the primary coil of the slave transformer. More preferably, the master feedback circuit drives the slave clamp circuit according to the output from the master voltage detection circuit.

  According to the present invention, it is possible to provide a constant voltage power supply circuit that can be easily reduced in size and increased in output and can stably obtain a desired voltage value.

[Principle of the Invention]
As a method of performing constant voltage control of the switching power supply, the present invention inserts a supersaturated reactor in series with respect to the gate terminal of the switching field effect transistor, and controls the discharge current of the field effect transistor flowing to the supersaturated reactor. The output effect is stabilized by controlling the turn-on timing of the field effect transistor.

  FIG. 1 shows a functional configuration of a power supply circuit to which the present invention is applied. The power supply circuit includes an input source 1, an input smoothing capacitor 2, a clock generator 3, a supersaturated reactor 4, a bypass circuit 5, a gate parasitic capacitor 6, a field effect transistor 7, a transformer 8, a rectifying / smoothing circuit 9, a feedback circuit 10, and a voltage. It has a detection circuit 11 and applies a voltage to the load 12.

The input source 1 is a power source that supplies a DC voltage to each unit. The input smoothing capacitor 2 removes (smooths) the pulsation of the DC voltage supplied to each part by the input source 1. The clock generator 3 generates a rectangular wave (clock) that switches between ON and OFF at a predetermined timing. The supersaturated reactor 4 delays the turn-on timing of the field effect transistor 7. The bypass circuit 5 is a circuit that bypasses the discharge current of the gate parasitic capacitor 6 by a necessary amount in accordance with a control signal from the feedback circuit 10. The gate parasitic capacitor 6 is a gate parasitic capacitance formed inside the field effect transistor 7. The field effect transistor 7 is a main switch element of the switching power supply. The field effect transistor 7 repeats ON / OFF according to the output of the supersaturated reactor 4. The transformer 8 transforms the voltage input from the primary side to a predetermined voltage and outputs it. The rectifying / smoothing circuit 9 converts the output voltage (secondary voltage) of the transformer 8 to DC and removes pulsation. The feedback circuit 10 outputs a control signal corresponding to the fluctuation of the output voltage on the secondary side to the bypass circuit 5. The voltage detection circuit 11 is a circuit that detects the output voltage on the secondary side.
Here, the input source 1 is a DC power supply. However, as a matter of course, an AC power supply (commercial power supply or the like) may be rectified and a DC voltage smoothed by a capacitor may be supplied.

  In the power supply circuit, the discharge current generated when the field effect transistor 7 is turned off uses the reset current of the supersaturated reactor 4. Thereby, the turn-on timing of the field effect transistor 7 can be controlled. More specifically, if a large amount of reset current is supplied to the supersaturated reactor 4, the time until the field effect transistor 7 is turned on becomes longer, and the ON time becomes shorter in the next cycle. Therefore, the feedback loop can be formed by setting the ratio of the discharge current used as the reset current to a value corresponding to the fluctuation of the output voltage.

  The constant voltage control method of the present invention is an indirect control method of a switching power supply using a fixed clock. Therefore, in the master-slave multi-output power source, the effect is exhibited by using it for the slave side output voltage control, a small power supply circuit can be constructed at low cost, and the output voltage control with high stability is possible.

  Hereinafter, a preferred embodiment of the present invention based on the above principle will be described.

[First Embodiment]
A first embodiment in which the present invention is suitably implemented will be described. FIG. 2 shows the configuration of the multi-output power supply circuit according to this embodiment. This multi-output power supply circuit includes an input source 1, input smoothing capacitors 13, 27, PWM control IC 39, transformers 31, 17, field effect transistors 29, 15, gate parasitic capacitors 30, 16, diodes 35, 36, 23, 24. Coils 32 and 20, capacitors 33 and 25, error amplifiers 34 and 22, photocouplers 40 and 43, resistors 37, 21, 47 and 28, a bypass circuit 41, a supersaturated reactor 42 and a resistor 14.

For the same components as in FIG. 1, the overlapping description is omitted, and only the first-described components are described.
The input smoothing capacitors 13 and 27 remove the pulsation of the DC voltage supplied from the input source 1. The PWM control IC 39 is an integrated circuit for controlling the master side output by PWM. The transformer 31 performs transformation so that the output voltage on the master side becomes a predetermined voltage. The transformer 17 performs transformation so that the output voltage on the slave side becomes a predetermined voltage. The field effect transistor 29 is a switching element of the output converter on the master side. The field effect transistor 15 is a switch element of the output converter on the slave side. The gate parasitic capacitor 30 is parasitic inside the field effect transistor 29 and has a capacitance between the gate and the source. The gate parasitic capacitor 16 is parasitic inside the field effect transistor 15 and has a capacitance between the gate and the source. The diodes 35 and 36 are diodes for the rectifier circuit of the output converter on the master side. The diodes 23 and 24 are diodes for the rectifier circuit of the output converter on the slave side. The coil 32 is a choke coil of the output converter on the master side. The coil 20 is a choke coil of a slave-side output converter. The capacitor 33 is an output smoothing capacitor for the output converter on the master side. The capacitor 33 is an output smoothing capacitor for the output converter on the master side. The error amplifier 34 detects a voltage change of the output on the master side and outputs a control signal for stabilizing the output to the bypass circuit 41 via the photocoupler 43 (43a, 43b). The bypass circuit 41 is a circuit including a transistor 48, resistors 44, 45, and 47, a diode 46, and a photocoupler light receiving side 43b. The bypass circuit 41 bypasses the discharge current of the capacitor 16 by a necessary amount in accordance with the control signal obtained from the photocoupler light emission side 43a. The supersaturated reactor 42 is an element that delays the turn-on timing of the field effect transistor 15. The resistor 37 limits the current flowing through the photocoupler 40. The resistor 21 limits the current flowing through the photocoupler light emission side 43a.

  The above multi-output power supply circuit is a multi-output power supply circuit based on a forward converter circuit system, but the output principle of the secondary voltage in this circuit is well known and is not a feature of the present invention. Description is omitted.

The operation of stabilizing the output voltage in the multi-output power supply circuit will be described.
On the master side, the PWM control IC 39, the error amplifier 34, and the photocoupler 40 form a feedback circuit to perform PWM control and stabilize the output voltage. On the slave side, on the other hand, the PWM control IC 39 obtains the ON duty clock waveform determined on the master side, and controls the ON time of the field effect transistor 15 using the delay time caused by the oversaturated reactor 42.

  The operation of the supersaturated reactor 42 will be described. The supersaturated reactor 42 forms a magnetic switch by using the saturated region and the unsaturated region of the core. By using this characteristic, the ON pulse time applied to the gate of the field effect transistor 15 is changed.

A magnetization curve when a pulse voltage is applied to the supersaturated reactor 42 is shown in FIG. The process of changing the magnetization state of the supersaturated reactor 42 will be described using this.
When an ON pulse is applied from the PWM control IC 39, a charge current flows through the supersaturated reactor 42, and the magnetization state changes as indicated by "I" in FIG. At this time, since the magnetization state of the supersaturated reactor 42 is an unsaturated state, the inductance is very high, and the applied voltage is carried by both ends of the supersaturated reactor 42. In other words, the applied voltage drops to almost the GND level in the supersaturated reactor 42, and almost no voltage is applied to the gate terminal of the field effect transistor 15. That is, the supersaturated reactor 42 is in an OFF state, and is in a state where an ON pulse is prevented from being transmitted to the field effect transistor 15.

  When a charge current is further supplied to the supersaturated reactor 42, the magnetization state of the supersaturated reactor 42 becomes a saturated state, and the magnetic flux density becomes a constant value (that is, a saturated state) as shown by “II” in FIG. . Since the inductance of the supersaturated reactor 42 becomes small when the saturation reactor 42 shifts to a saturated state, a voltage is applied to the gate terminal of the field effect transistor 15. In other words, the supersaturated reactor 42 is turned on.

  When the pulse from the PWM control IC 39 is switched from ON to OFF, a discharge current for discharging the capacity of the gate parasitic capacitor 16 flows to the supersaturated reactor 42, and the magnetization state of the core of the supersaturated reactor 42 is “III” in FIG. Change and reset as shown.

Changes in “I”, “II”, and “III” are repeated with the operation clock output from the clock generator 3 as a cycle.
When repeating these, the bypass circuit 41 adjusts the proportion of the discharge current as a reset current to the supersaturated reactor 42 according to the change in the output voltage, thereby changing the next ON pulse blocking time. Let

  FIG. 4 shows the relationship between the ON pulse and the blocking time. t0 is the rising start point of the ON pulse. The core of the supersaturated reactor 42 always has a residual magnetic flux density Br and has a dead angle (an uncontrollable region). Therefore, even when the reset current is zero, that is, when all the discharge currents of the field effect transistor 15 flow to the bypass circuit 41, the blocking times t0 to t1 always occur. t3 is the maximum blocking time when the bypass circuit 41 is turned off and the discharge current of the gate of the field effect transistor 15 is all the reset current of the oversaturated reactor. t2 changes according to the output voltage fluctuation by the feedback circuit including the error amplifier 22, the photocouplers 43a and 43b, and the bypass circuit 41. That is, the PWM control can be performed by changing the turn-on timing t2 of the field effect transistor 15 between t1 and t3.

The multi-output power supply circuit according to the present embodiment has a supersaturated reactor inserted in the gate of the field effect transistor, so that the circuit scale can be reduced as compared with the conventional configuration.
In addition, the wire diameter of the supersaturated reactor can be selected without being influenced by fluctuations in the output voltage and current, so that the power supply circuit can be standardized.
In addition, since a slave output circuit configuration can be easily added, it is easy to increase the number of outputs.
In addition, the power supply circuit can be easily reduced in price.

  Furthermore, since the multi-output power supply circuit according to the present embodiment improves the cross regulation of the slave output, the output voltage exhibits high stability.

[Second Embodiment]
A second embodiment in which the present invention is suitably implemented will be described. FIG. 5 shows the configuration of the multi-output power supply circuit according to this embodiment.
This multi-output power supply circuit has substantially the same configuration as the multi-output power supply circuit according to the first embodiment, but the secondary side rectification method is different. In the present embodiment, the circuit is configured by an FET synchronous rectification method using an FET as a secondary side rectifier circuit.

  Since the secondary output rectifier circuit is configured as a synchronous rectifier circuit using FETs 49, 50, 53, and 54 in the multi-output power supply circuit according to the present embodiment, the multiple output power supply circuit according to the first embodiment using the diode rectifier system is used. Compared with the output power supply circuit, the conversion efficiency is greatly improved.

  Since the FET synchronous rectification method does not become intermittent even at a load current below the critical point of the choke coil, the output voltage jumps at a light load is small as compared with diode rectification, and good load fluctuation characteristics can be obtained.

  However, if no control for stabilizing the output on the slave side is performed, the output voltage naturally fluctuates according to the load current as shown in FIG.

  For this reason, by performing the PWM control in the same manner as in the first embodiment, it is possible to perform output control with low fluctuation in output voltage and high stability.

Further, when the output on the master side is a diode rectification method, when the load current is less than or equal to the critical point of the choke coil, a sudden narrowing of the ON width occurs to suppress the jump of the output voltage, resulting in an intermittent oscillation state. For this reason, in the diode rectification method, it is necessary to insert a pseudo load (dummy resistor or the like) to flow a load current above the critical point and secure an ON width that does not cause an intermittent oscillation state.
On the other hand, in the case of the FET synchronous rectification method, the ON width is not narrowed down rapidly, and an ON width that does not cause intermittent oscillation can be easily secured. Therefore, it is possible to easily secure the ON width necessary to obtain the slave side output even with a light load.

  This means that the range in which the turn-on timing t2 of the field effect transistor 15 changes in the FET synchronous rectification multi-output power supply circuit can be reduced, in other words, the value of t3 can be reduced. Therefore, it is possible to narrow the control range t1 to t3, and the supersaturated reactor 42 can be further downsized.

[Third Embodiment]
A third embodiment in which the present invention is preferably implemented will be described. FIG. 7 shows the configuration of the multi-output power supply circuit according to this embodiment.
This multi-output power supply circuit has a configuration in which active clamp circuits 57 and 60 are added to the multi-output power supply circuit according to the second embodiment.

  By using the active clamp circuit, the utilization efficiency of the transformer is improved and the conversion efficiency is further improved.

  Further, in the multi-output power supply circuit according to the second embodiment, the flyback voltage generated when the field effect transistors 15 and 29 as the main switching elements are OFF is the input winding of the transformers 17 and 31 and the field effect transistor 15. , 29 has a resonance waveform due to the parasitic capacitance between the drain and source. Therefore, a signal having a waveform shown in FIG. 8 is applied to the gates of the commutation-side FETs 50 and 54, and a period during which a sufficient gate voltage cannot be obtained occurs. During this period, the load current flows through the body diodes of the commutation side FETs 50 and 54, and loss occurs.

  Since the multi-output power supply circuit according to the present embodiment uses an active clamp circuit, the flyback voltage is clamped to have a substantially rectangular waveform, and the gates of the commutation side FETs 50 and 54 have waveforms as shown in FIG. Is applied. Thereby, the commutation side FETs 50 and 54 are turned on in almost all the time, and the loss due to the body diode can be reduced.

  The difference between the active clamp PWM control IC 63 and the PWM control IC 39 provided in the multi-output power supply circuit according to the second embodiment is to output a pulse for turning on / off the field effect transistor of the active clamp circuit. The terminal OUT2 is added, and the other is the same.

OUT1 and OUT2 are output terminals for control signals of the field effect transistors 15 and 29 of the main switch element and the field effect transistor 58 for active clamping, and output a pulse waveform having a waveform so as to alternately turn on and off them. In order to prevent the switching field effect transistor and the active clamp field effect transistor from being turned on simultaneously, a dead time is provided for the pulses output from each of OUT1 and OUT2.
The active clamp circuit 60 on the master output side is composed of a field effect transistor 61 and a capacitor 62. The active clamp circuit 60 is turned ON / OFF by a pulse output from OUT2 of the active clamp PWM control IC 63, and is generated in the input winding of the transformer 31. Clamp the back voltage. The active clamp circuit 57 on the slave output side is composed of a field effect transistor 58 and a capacitor 59. The active clamp circuit 57 is turned ON / OFF by a pulse output from OUT2 of the active clamp PWM control IC 63, and is generated in the input winding of the transformer 17. Clamp the back voltage.

  Since the effect of the combination of the active clamp circuit and the FET synchronous rectification method and the operation of the circuit are known, detailed description thereof is omitted.

Each of the above embodiments is an example of a preferred embodiment of the present invention, and the present invention is not limited to this.
For example, in each of the above-described embodiments, the configuration in which there is one output on the slave side is taken as an example, but it goes without saying that a plurality of circuits on the slave side can be provided.
Further, the present invention is not limited to the illustrated circuit configuration, and a control method similar to the above can be applied to any power supply circuit using a field effect transistor.
As described above, the present invention can be variously modified.

It is a figure which shows the principle of this invention. It is a figure which shows the structure of the constant voltage power supply circuit which concerns on 1st Embodiment which implemented this invention suitably. It is a figure which shows the magnetization curve of a supersaturated reactor. It is a figure which shows the relationship between ON pulse applied to a supersaturated reactor, and blocking time. It is a figure which shows the structure of the constant voltage power supply circuit concerning 2nd Embodiment which implemented this invention suitably. It is a figure which shows a load fluctuation characteristic. It is a figure which shows the structure of the constant voltage power supply circuit which concerns on 3rd Embodiment which implemented this invention suitably. It is a figure which shows the gate waveform of a commutation side FET when there is no active clamp circuit. It is a figure which shows the gate waveform of a commutation side FET in case an active clamp circuit exists. It is a figure which shows the structure of the constant voltage power supply circuit by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input source 2, 13, 27 Input smoothing capacitor 3 Clock generator 4, 18, 42 Supersaturated reactor 5 Bypass circuit 6, 16, 30 Gate parasitic capacitor 7, 15, 29, 49, 58, 61 Field effect transistor 8, 17 , 31 Transformer 9 Rectification / smoothing circuit 10 Feedback circuit 11 Voltage detection circuit 12, 26, 38 Load 14, 21, 28, 37, 44, 45, 47, 51, 52, 55, 56 Resistor 19, 46 Diode 20, 32 Coil 22, 34 Error amplifier 23, 35 Diode (rectifier side)
24, 36 Diode (commutation side)
25, 33 Output smoothing capacitor 39 PWM control IC
40, 43 Photocoupler 43a Photocoupler light emission side 43b Photocoupler light reception side 49, 53 FET (rectification side)
50, 54 FET (commutation side)
57, 60 Active clamp circuit 59, 62 Capacitor 63 Active clamp PWM control IC

Claims (18)

A DC voltage supplied from a DC power source is switched by a field effect transistor to convert it to a primary AC voltage, the primary AC voltage is transformed into a secondary AC voltage by a transformer, and the secondary AC voltage is rectified and output. A constant voltage power supply circuit for generating a voltage,
A supersaturated reactor disposed between an output terminal of a clock generator for generating a clock of a predetermined period and a gate terminal of the field effect transistor;
A bypass circuit for bypassing a discharge current generated at the gate terminal by a parasitic capacitance between the gate and the source of the field effect transistor to the source terminal when the field effect transistor is off;
A voltage detection circuit for detecting a voltage value of the output voltage;
A constant voltage power supply circuit, comprising: a feedback circuit that changes a ratio of bypassing the discharge current to the source terminal in the bypass circuit according to an output from the voltage detection circuit.   2. The constant voltage power supply circuit according to claim 1, further comprising a smoothing circuit for suppressing pulsation of the output voltage.   3. The constant voltage power supply circuit according to claim 1, wherein the secondary AC voltage is rectified by a diode rectification method.   3. The constant voltage power supply circuit according to claim 1, wherein the secondary AC voltage is rectified by an FET synchronous rectification method.   5. The constant voltage power supply circuit according to claim 4, further comprising: a clamp circuit that clamps a flyback voltage generated in the transformer when the field effect transistor is off, in parallel with a coil on the primary side of the transformer.   6. The constant voltage power supply circuit according to claim 5, wherein the feedback circuit drives the clamp circuit in accordance with an output from the voltage detection circuit. A master FET and a slave FET that switch a DC voltage supplied from a DC power source into a primary AC voltage;
A master transformer for transforming the master primary AC voltage output from the master FET into a master secondary AC voltage;
A slave transformer for transforming a slave primary AC voltage output from the slave FET into a slave secondary AC voltage;
A master rectifier circuit that rectifies the master secondary AC voltage and outputs a master output voltage;
A slave rectifier circuit that rectifies the slave secondary AC voltage and outputs a slave output voltage;
A clock generator for supplying a clock of a predetermined period to the gate terminal of the master FET;
A supersaturated reactor disposed between the output terminal of the clock generator and the gate terminal of the slave FET;
A bypass circuit for bypassing a discharge current generated at the gate terminal of the slave FET to the source terminal of the slave FET by a parasitic capacitance between the gate and the source of the slave FET when the slave FET is off;
A master voltage detection circuit for detecting a voltage value of the master output voltage;
A master feedback circuit that changes a cycle of a clock supplied to the gate terminals of the master FET and the slave FET according to an output from the master voltage detection circuit,
A slave voltage detection circuit for detecting a voltage value of the slave output voltage;
A constant voltage power supply circuit comprising: a slave feedback circuit that changes a ratio of bypassing the discharge current to the source terminal of the slave FET in the bypass circuit in accordance with an output from the slave voltage detection circuit.   The multi-output power supply circuit comprising a plurality of the slave FET, the oversaturated reactor, the slave transformer, the bypass circuit, the slave voltage detection circuit, and the slave feedback circuit. 8. The constant voltage power supply circuit according to 7.   9. The constant voltage power supply circuit according to claim 7, further comprising a master smoothing circuit for suppressing pulsation of the master output voltage.   The constant voltage power supply circuit according to any one of claims 7 to 9, further comprising a slave smoothing circuit for suppressing pulsation of the slave output voltage.   11. The constant voltage power supply circuit according to claim 7, wherein the master secondary AC voltage is rectified by a diode rectification method.   The constant voltage power supply circuit according to any one of claims 7 to 10, wherein the master secondary AC voltage is rectified by an FET synchronous rectification method.   13. The constant voltage power supply according to claim 12, further comprising a master clamp circuit that clamps a flyback voltage generated in the master transformer when the master FET is off in parallel with a primary side coil of the master transformer. circuit.   14. The constant voltage power supply circuit according to claim 13, wherein the master feedback circuit drives the master clamp circuit in accordance with an output from the master voltage detection circuit.   The constant voltage power supply circuit according to any one of claims 7 to 14, wherein the slave secondary AC voltage is rectified by a diode rectification method.   15. The constant voltage power supply circuit according to claim 7, wherein the slave secondary AC voltage is rectified by an FET synchronous rectification method.   17. The constant voltage power supply according to claim 16, further comprising a slave clamp circuit that clamps a flyback voltage generated in the slave transformer when the slave FET is turned off in parallel with a primary side coil of the slave transformer. circuit.   18. The constant voltage power circuit according to claim 17, wherein the master feedback circuit drives the slave clamp circuit according to an output from the master voltage detection circuit.

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