JP4518586B2 - Data recording apparatus and rewrite determination method thereof - Google Patents

Description

【００８１】
一方、本実施の形態におけるリライト率Ｐｂは、（２）式で表される。
【００８２】
【数２】

【００８３】
図５は、フラグメントエラーレートＰｆとリライト率Ｐａ，Ｐｂの関係を示している。本実施の形態においては、従来例と比較して、フラグメントエラーレートが１×１０^-2であるときのリライト率は、５桁以上改善されることがわかる。
【００８４】
実際の系はバーストエラーとランダムエラーが混在しているので、本実施の形態においては、上述双方のメリットを得ることができる。
【００８５】
また、本実施の形態においては、ドロップインであると判定されたフラグメントの個数を、第２の誤り訂正符号の系列に係るインターリーブ毎にカウントし、データが良であると判定されたフラグメント数のカウント結果と、このドロップインであると判定されたフラグメント数のカウント結果に基づいて、リライトの決定をするものである。したがって、ドロップインの発生に起因してデータを正しく再生できなくなるおそれがあるときは、確実にリライトを実行させることができる。
【００８６】
なお、上述実施の形態においては、フラグメントのデータにエラーがないとき、そのフラグメントのデータが良であると判定するものであった。すなわち、検出／カウント部８１（図３参照）に、０エラー検出回路８３（図４参照）を使用している。しかし、フラグメントのデータにエラーがあっても、そのエラーが第１の誤り訂正符号Ｃ１で訂正可能であるときは、そのフラグメントのデータを良であると判定する構成としてもよい。
【００８７】
例えば、フラグメントの２つのＣ１系列のデータがそれぞれ０エラーまたは１エラーであるとき、そのフラグメントのデータを良であると判定する構成とする場合、図３に示す検出／カウント部８１の０エラー検出回路８３の代わりに、図６に示す０エラー／１エラー検出回路８７を使用すればよい。この検出回路８７は、計算処理部８２Ａで求められる第１のＣ１系列に係るシンドロームＳ₀〜Ｓ₅に基づき、そのＣ１系列のデータが０エラーまたは１エラーであるか否かを検出する検出処理部８７Ａと、計算処理部８２Ｂで求められる第２のＣ１系列に係るシンドロームＳ₀〜Ｓ₅に基づき、そのＣ１系列のデータが０エラーまたは１エラーであるか否かを検出する検出処理部８７Ｂと、これら検出処理部８７Ａ，８７Ｂより出力される検出信号ＳＤ３，ＳＤ４の論理積をとって検出信号Ｓdet1を得るアンド回路８７Ｃとからなっている。
【００８８】
検出処理部８７Ａは、第１のＣ１系列に係る各８ビットのシンドロームＳ₀〜Ｓ₅を使用した演算をする４個のガロア体積和演算器９４ａ〜９４ｄと、これら演算器９４ａ〜９４ｄからの８ビットの演算結果に対し、それぞれ各ビットを反転した後に論理積をとる４個のアンド回路９５ａ〜９５ｄと、これらアンド回路９５ａ〜９５ｄの出力データの論理積をとるアンド回路９６とからなっている。この場合、第１のＣ１系列のデータが０エラーまたは１エラーであるときは、アンド回路９６、従って検出処理部８７Ａより「１」レベルの検出信号ＳＤ３が得られる。詳細説明は省略するが、検出処理部８７Ｂも、上述した検出処理部８７Ａと同様に構成される。そして、第２のＣ１系列のデータが０エラーまたは１エラーであるときは、この検出処理部８７Ｂより「１」レベルの検出信号ＳＤ４が得られる。よって、各フラグメント毎に、第１および第２のＣ１系列のデータの双方が０エラーまたは１エラーであるときには、アンド回路８７Ｃより「１」レベルの検出信号Ｓdet1が得られる。
【００８９】
上述したように、フラグメントの２つのＣ１系列のデータがそれぞれ０エラーまたは１エラーであるとき、そのフラグメントのデータを良であると判定する構成とする場合には、ランダムエラーに対して、リライト率Ｐｃは、（３）式で表される。ここで、Ｐｓはシンボルエラーレート、Ｐｆ１は２エラー以上のフラグメントエラーレートを示している。
【００９０】
【数３】

【００９１】
図７は、フラグメントエラーレートＰｆとリライト率Ｐａ，Ｐｃの関係を示しており、リライト率の大幅改善になっていることがわかる。
【００９２】
また、図６に示すシンドローム計算回路８２および０エラー／１エラー検出回路８７においては、第１のＣ１系列に対応して計算処理部８２Ａおよび検出処理部８７Ａが設けられると共に、第２のＣ１系列に対応して計算処理部８２Ｂおよび検出処理部８７Ｂが別個独立して設けられるものを示したが、計算処理部および検出処理部を１系統のみとして、第１のＣ１系列と第２のＣ１系列とで時分割的に使用する構成としてもよい。さらに、計算処理部内のシンドロームレジスタを１個として時分割的に使用する構成とすると共に、検出処理部内のガロア体積和演算器を１個として時分割的に使用する構成としてもよい。これにより、回路規模を大幅に低減することが可能となる。このような回路規模の低減は、図４に示すシンドローム計算回路８２および０エラー検出回路８３についても、同様に当てはめることができる。
【００９３】
また、上述実施の形態では、第１のカウント手段（カウンタ８４ａ〜８４ｃ）でデータが良であるフラグメント（ブロック）の個数をカウントする構成としているが、逆にデータが良でないフラグメントの個数をカウントする構成としてもよい。また、同様に、第２のカウント手段（カウンタ８６ａ〜８６ｃ）でドロップインであると判定されたフラグメントの個数をカウントする構成としているが、逆にドロップインでないと判定されたフラグメントの個数をカウントする構成としてもよい。
【００９４】
また、上述実施の形態においては、この発明をＤＡＴを使用したデータレコーダに適用したものであるが、この発明は、積符号を構成する第１および第２の誤り訂正符号が付加された記録データを記録媒体に記録するその他のデータ記録装置に同様に適用することができる。
【００９５】
【発明の効果】
この発明によれば、積符号を構成する第１および第２の誤り訂正符号が付加された記録データを記録媒体に記録した後にその記録データを再生し、再生されたデータに関し、第１の誤り訂正符号が生成されるブロック毎にそのデータの良否を判定すると共に、データが良である、あるいは良でないと判定されたブロックの個数を第２の誤り訂正符号の系列に係るインターリーブ内でカウントし、ドロップインである、あるいはドロップインでないと判定されたブロックの個数を、第２の誤り訂正符号の系列に係るインターリーブ毎にカウントし、ドロップインであるブロック数を所定倍した数と、データが良でないブロック数とを加算した数が所定値を超過した場合に、記録データを記録媒体に再記録するものである。
【００９６】
したがって、再生時にデータを正しく再生できなくなるおそれを増加させることなく、リライト率を大幅に改善できる。また、ドロップインの発生に起因してデータを正しく再生できなくなるおそれがあるときは、確実にリライトを実行させることができる。
【図面の簡単な説明】
【図１】実施の形態としてのＤＡＴを使用したデータレコーダの構成を示すブロック図である。
【図２】トラッキングエラーの検出原理を説明するための図である。
【図３】リライト機能部を構成する検出／カウント部の構成を示すブロック図である。
【図４】シンドローム計算回路および０エラー検出回路の構成を示すブロック図である。
【図５】フラグメントエラーレートとリライト率の関係を示す図である。
【図６】シンドローム計算回路および０エラー／１エラー検出回路の構成を示すブロック図である。
【図７】フラグメントエラーレートとリライト率の関係を示す図である。
【図８】磁気テープのトラックフォーマット例を示す図である。
【図９】メインデータの誤り訂正符号の構成を示す図である。
【図１０】１フラグメントのデータ部に配される２つのＣ１（６２，５６）符号を示す図である。
【図１１】Ｃ１系列のデータ構成を示す図である。
【図１２】Ｃ２系列のデータ構成を示す図である。
【図１３】磁気テープのテープフォーマットを示す図である。
【図１４】２パーティション・テープのテープフォーマットを示す図である。
【図１５】従来のデータレコーダの記録に係る部分の構成を示すブロック図である。
【図１６】０エラー検出／カウント部の構成を示すブロック図である。
【図１７】リード・アフター・ライトのしくみを説明するための図である。
【図１８】非リライト時、リライト時のトラックパターン例を示す図である。
【符号の説明】
１０・・・データレコーダ、１１・・・システムコントローラ、２０・・・インタフェースコントローラ、３０・・・記録系信号処理部、４０・・・記録再生部、５０・・・再生系信号処理部、６０・・・トラッキング制御部、８０・・・リライト機能部、８１・・・検出／カウント部、８２・・・シンドローム計算回路、８３・・・０エラー検出回路、８４ａ〜８４ｃ，８６ａ〜８６ｃ・・・カウンタ、８５・・・比較回路、８７・・・０エラー／１エラー検出回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data recording apparatus suitable for being applied to a recording system such as a data recorder using a digital audio tape recorder (DAT), for example, and a rewrite determination method thereof. Specifically, after recording data to which the first and second error correction codes constituting the product code are added is recorded on the recording medium, the recorded data is reproduced, and the first error correction code is related to the reproduced data. The quality of the data is determined for each generated block, and the number of blocks for which the data is determined to be good is counted for each interleaving related to the second error correction code sequence. Based on the count result By determining whether or not to re-record the recording data on the recording medium, a data recording apparatus and a method for determining the rewriting that are intended to greatly improve the rewrite rate without increasing the possibility that the data cannot be correctly reproduced. It is related to.
[0002]
[Prior art]
In a computer, in order to protect data written on a hard disk or the like, these data are transferred to a data recorder called a data streamer and recorded once a day, for example.
[0003]
Conventionally, an ordinary analog audio tape recorder has been often used as a data recorder. However, in this analog audio tape recorder, the amount of magnetic tape consumed is extremely large, and the data rate during recording is low, so it takes time to record and transfer data. Further, the analog audio tape recorder has a drawback in that it takes time to find desired data because a high-speed search operation cannot be performed.
[0004]
Therefore, a helical scan type digital audio tape recorder (DAT) using a rotating head is used as a data recorder. For example, in the DDS3 format, as shown in FIG. 8, for each rotation of the rotating drum, a pair of rotating magnetic heads scans two inclined tracks TA and TB on the magnetic tape 42 to record and reproduce signals. Is supposed to do.
[0005]
In this case, one track is divided into a main data area and margin areas at both ends of the main data area, and 133 symbols are divided into 96 fragments as one fragment (block). Furthermore, one fragment includes a first section of one symbol for recording a synchronization signal, a second section of one symbol for recording a fragment address, a third section of five symbols for recording a subcode, and a header parity. Are divided into a fourth section of 2 symbols for recording data and a fifth section of 124 symbols for recording data, and a subcode and a fragment address are recorded together with the data in each fragment of the main data area.
[0006]
As shown in FIG. 9, error correction codes C2 and C1 constituting a product code are added to the main data recorded in the fifth section of each fragment. Here, two C1 (62, 56) codes (see FIG. 10) that are interleaved in units of two symbols are arranged in the 124 symbol data section of each fragment. Further, a C2 (32, 26) code subjected to interleaving in units of 4 fragments (4 blocks) is formed in the track direction, and the error correction code C2 is arranged at the center of the main data area.
[0007]
FIG. 11 shows a data structure of a C1 sequence subjected to 2-symbol interleaving, and one C1 (62, 56) code is composed of 62 symbols shown in the same figure. FIG. 12 shows a data structure of a C2 sequence subjected to 3-fragment interleaving, and one C2 (32, 26) code is composed of 32 symbols shown in the same figure.
[0008]
In the third section of each fragment, as a subcode, as a subcode, a separator count which is delimiter information indicating a delimiter of main data, a record count indicating the number of records, an area ID indicating each area defined on the tape format, A frame number indicating the absolute position of the recording unit, a group count indicating the number of recording units, a checksum, and the like are recorded.
[0009]
FIG. 13 shows a tape format in the data recorder described above. As shown in the figure, as a region for loading and unloading the magnetic tape, a logical tape start position (LBOT: from a physical tape start position (PBOT: Physical Beginning of Tape) to a head area following the leader tape. A device area up to (Logical Beginning of Tape) is defined, and a reference area and a system area are provided next to the device area. The reference area is used as a physical reference when recording a system log (history information) in the system area. A data area for recording data is provided next to the system area, and an EOD (EOD: End of Data) area is provided next to the data area.
[0010]
Further, as shown in FIG. 14, a two-partition tape having two partitions P1 and P2 each having a reference area, a system area, a data area, and an EOD area is defined.
[0011]
By the way, in the above-described data recorder, in order to correctly reproduce data from the magnetic tape 42 at the time of reproduction, the recorded data is recorded on the magnetic tape 42, and then the recorded data is reproduced (read / after-write). When there is a possibility that the data cannot be obtained sometimes, a rewrite function for re-recording the recording data on the magnetic tape 42 is provided.
[0012]
FIG. 15 shows a part related to recording of a conventional data recorder, that is, a system controller 100 including a microcomputer, a recording system signal processing unit 110 that performs signal processing on the recording data and converts it into a signal of a predetermined format, A signal supplied from the recording system signal processing unit 110 is recorded on an inclined track on the magnetic tape 42 by a pair of recording rotary magnetic heads, and a signal recorded on the inclined track is recorded on a pair of reproducing rotary magnets. A recording / reproducing unit 120 that reproduces by the head, and a rewrite that determines whether or not to rewrite using the data reproduced by the recording / reproducing unit 120 and controls the operation of the recording system signal processing unit 110 according to the decision The functional unit 130 is shown.
[0013]
The recording / reproducing unit 120 includes a rotating drum in which a pair of recording rotating magnetic heads WA and WB are disposed at an angle of 180 °, and a pair of reproducing rotating magnetic heads RA and RB are disposed at an angle of 180 °. 41, and the magnetic tape 42 is run at a predetermined running speed in a state where the magnetic tape 42 is wound around the rotary drum 41 over a range of about 90 °. Each time the rotary drum 41 rotates, the magnetic heads WA and WB and the magnetic heads RA and RB scan the inclined tracks TA and TB (see FIG. 8) on the magnetic tape 42 to record and reproduce signals. It has become. Here, each of the magnetic heads WA and RA is a magnetic head related to + azimuth, and each of the magnetic heads WB and RB is a magnetic head related to -azimuth.
[0014]
The recording system signal processing unit 110 includes a buffer RAM 111 for temporarily storing recording data, an interleaver 112 to which recording data read from the buffer RAM 111 is supplied, and data interleaved by the interleaver 112. The supplied C2 encoder 113, the C1 encoder 114 to which the data to which the error correction code C2 is added by the C2 encoder 113 are supplied, and the data to which the error correction code C1 is added by the C1 encoder 114 are supplied 8 / 10 modulation circuit 115 and a recording amplifier 116 to which a recording signal obtained by converting into 10-bit data by the 8/10 modulation circuit 115 is supplied. The 8/10 modulation circuit 115 converts the data supplied from the C1 encoder 114 from 8 bits to 10 bits in units of 1 byte so as to keep the DC level of the recording signal at approximately 0.
[0015]
The operation of the recording signal processing unit 110 will be described. The recording data is supplied to and stored in the buffer RAM 111. The recording data sequentially read out from the buffer RAM 111 is interleaved by the interleaver 112, and then the C2 encoder 113 generates and adds an error correction code C2 corresponding to the track direction in the C2 encoder 113. An error correction code C1 for each fragment (block) is generated and added.
[0016]
The recording data to which the error correction codes C2 and C1 output from the C1 encoder 114 are added is converted from 8-bit data to 10-bit data by the 8/10 modulation circuit 115, and a signal of a predetermined format as a recording signal is obtained. . Then, this recording signal is supplied to the recording / reproducing unit 120 via the recording amplifier 116 and recorded on the inclined track of the magnetic tape 42.
[0017]
The rewrite function unit 130 includes a 10/8 demodulation circuit 132 to which a reproduction signal reproduced from the inclined track of the magnetic tape 42 by the recording / reproduction unit 120 is supplied via the reproduction amplifier 131, and the 10/8 demodulation circuit 132. 0 error detection / counting unit 133 to which reproduction data RD converted into 8-bit data is supplied, and 0 error count value obtained for each of 96 fragments constituting one track by this 0 error detection / counting unit 133 The system controller 100 determines whether or not to rewrite based on CT0, and controls the operation of the recording system signal processing unit 110 according to the determination.
[0018]
FIG. 16 shows the configuration of the 0 error detection / counting unit 133. The 0 error detection / counting unit 133 is supplied with the reproduction data RD from the 10/8 demodulation circuit 132, and the syndrome S is related to the two C1 series data of each fragment.₀~ S_FiveAnd a syndrome S calculated by the syndrome calculation circuit 133a.₀~ S_FiveFor each fragment, it is detected whether or not both of the two C1 series data are 0 errors. If both are 0 errors, it is determined that the data is good and, for example, “1” level is detected. The number of detection signals Sdet output from the 0 error detection circuit 133b is counted for each of the 96 fragments constituting one track and the 0 error detection circuit 133b that outputs the signal Sdet to obtain a count value CT0 of 0 error. And a counter 133c. The counter 133c is reset at the beginning of each 96 fragment constituting one track under the control of the system controller 100.
[0019]
Since the correction ability of the error correction code C2 is 6 symbols, the system controller 100 may not be able to obtain data correctly during reproduction from the corresponding inclined track when the count value CT0 is 89 or less. Rewrite is determined to record again the recording data recorded on the inclined track. When the system controller 100 determines the rewrite as described above, the system controller 100 controls the reading of the buffer RAM 111 so that the recording is performed again from the recording data.
[0020]
The operation of the above-described rewrite function unit 130 will be described. A reproduction signal reproduced from the inclined track on the magnetic tape 42 by the recording / reproducing unit 120 is supplied to the 10/8 demodulation circuit 132 via the reproduction amplifier 131. In this case, as shown in FIG. 17, the corresponding reproduction signal is reproduced with a delay of a predetermined time t with respect to the recording signal supplied to the recording / reproducing unit 120 and recorded. In the recording signal, “+” and “−” indicate the recording signal for one track recorded by the rotary magnetic heads WA and WB, respectively, and the number assigned is a frame number. Similarly, in the reproduction signal, the “+” and “−” portions indicate the reproduction signal for one track reproduced by the rotary magnetic heads RA and RB, respectively, and the number assigned is the frame number.
[0021]
The reproduction data RD converted into 8-bit data by the 10/8 demodulation circuit 131 is supplied to the 0 error detection / counting unit 133. In the error detection / counting unit 133, the syndrome S is related to the two C1 series data of each fragment.₀~ S_FiveIs calculated and its syndrome S₀~ S_FiveBased on the above, it is detected for each fragment whether or not both of the two C1 series data are 0 errors, the number of both errors is counted, and 0 for every 96 fragments constituting one track. An error count value CT0 is obtained.
[0022]
The count value CT0 is supplied to the system controller 100, and it is determined whether to rewrite based on the count value CT0. That is, when the count value CT0 is 89 or less, the system controller 100 records again the recording data recorded on the inclined track, assuming that there is a possibility that data cannot be obtained correctly during reproduction from the corresponding inclined track. Make a rewrite decision. When rewriting is determined, the system controller 100 controls reading of the buffer RAM 111 so that recording is performed again from the recorded data.
[0023]
For example, when 0 error is detected from the reproduction data of frame number = 6 and it is determined whether or not to rewrite based on the count value CT0, the track pattern on the magnetic tape 42 is shown in FIG. As shown in FIG. 18B, when rewriting is performed, frames with frame numbers 7 to 9 subsequent to the first frame number 6 are extra frames.
[0024]
[Problems to be solved by the invention]
In the data recorder described above, rewriting is performed when the number of fragments in which both of the two C1 series data are zero errors out of 96 fragments constituting one track is 89 or less. Therefore, there is a problem that the number of frames to be rewritten is relatively large, leading to a reduction in recording capacity.
[0025]
Further, a new recording signal is not recorded on the inclined track on the magnetic tape 42 due to the clogs of the recording rotary magnetic heads WA and WB, and the previous recording signal remains without being erased (“ When "drop-in" occurs, in fact, data cannot be correctly reproduced at the time of reproduction from the inclined track, but two of the C1 sequence data out of 96 fragments constituting one track are both zero errors. There is a problem in that the number of the recordings does not become 89 or less and rewriting is not performed.
[0026]
An object of the present invention is to greatly improve the rewrite rate without increasing the possibility that data cannot be correctly reproduced. Another object of the present invention is to reliably execute rewrite when there is a possibility that data cannot be correctly reproduced due to occurrence of drop-in.
[0027]
[Means for Solving the Problems]
  The data recording apparatus according to the present invention generates a first error correction code that constitutes a product code for each block of recorded data, and performs interleaving in units of predetermined blocks to constitute the product code. A data recording apparatus for generating an error correction code and recording the recording data to which the first and second error correction codes are added on a recording medium, the data reproducing the recorded recording data from the recording medium With respect to the data reproduced by the reproducing means and the data reproducing means, the data determining means for determining the quality of the data for each block and the data determining means determined that the data is good or not good First counting means for counting the number of blocks in each interleave associated with the second error correction code sequence, and the data reproduction means With respect to the generated data, drop-in determination means for determining whether or not the reproduction data is drop-in by comparing all the reproduction data with the corresponding recording data for each block, and drop-in determination by the drop-in determination means. The above blocks that are determined to be present or not drop-inofSecond counting means for counting the number for each interleaving related to the second error correction code sequence;The number obtained by adding the number of blocks with bad data counted by the first counting means and the number of blocks counted by the second counting means multiplied by a predetermined number exceeds the predetermined value. In case, Re-recording the recording data on the recording mediumRuAnd a light determining means.
[0028]
In the present invention, a first error correction code C1 constituting a product code is generated for each block of the recording data. Further, a second error correction code C2 constituting the product code is generated by interleaving the recording data in predetermined block units. Then, the recording data to which the first and second error correction codes are added is recorded on a recording medium, for example, an inclined track of a magnetic tape.
[0029]
After the recording data is recorded on the recording medium in this way, the recording data is reproduced. Then, the quality of the reproduced data is determined for each block. For example, it is determined whether or not there is an error in the block data. If there is no error, it is determined to be good. Also, for example, it is determined whether there is an error in the block data, and if there is an error, it can be corrected. If there is no error, or if there is an error, it can be corrected. Determined.
[0030]
Then, the number of blocks for which the data is determined to be good or not good is counted in the interleave relating to the second error correction code sequence. For example, when the data for one track is composed of 96 blocks (96 fragments) and a C2 (32, 26) code is generated by performing interleaving in units of 3 blocks, a sequence of the second error correction code C2 It is counted for every 32 blocks related to.
[0034]
  When drop-in occurs, the data cannot be reproduced correctly, but the number of blocks for which the data is determined to be good does not decrease and may not be rewritten. When it is drop-in, the playback data is different from the recorded data.All ofThe drop-in is determined by comparing the copy with the recorded data.
[0035]
The number of blocks determined to be drop-in or not drop-in is counted in the interleave related to the second error correction code sequence. Then, based on the count result of the number of blocks determined to be good or not good, and the count result of the number of blocks determined to be drop-in or not drop-in, the recorded data is recorded. It is determined whether to re-record on the recording medium. In this case, when correction becomes impossible by the second error correction code C2, rewrite is determined. For example, when the data for one track is composed of 96 blocks and the C2 (32, 26) code is generated by performing interleaving in units of 3 blocks, each 32 bits related to the sequence of the second error correction code C2 is generated. If (block number being drop-in) × 2 + (number of blocks with bad data)> 6 in any of the blocks, rewrite is determined.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a data recorder 10 using DAT as an embodiment. This data recorder 10 uses the above-described DDS3 format (see FIGS. 8 to 14) as a tape format.
[0037]
The data recorder 10 includes a system controller 11 including a microcomputer, an interface controller 20 for exchanging data with the outside, and performs signal processing on data input via the interface controller 20 to perform predetermined processing. The recording system signal processing unit 30 for converting the signal into the format signal and the recording signal supplied from the recording system signal processing unit 30 are recorded on the inclined track on the magnetic tape 42, and the signal recorded on the inclined track is also recorded. A recording / reproducing unit 40 to reproduce, a reproduction signal reproduced by the recording / reproducing unit 40 to perform signal processing, a reproduction system signal processing unit 50 to reproduce the original data, and a tape running system of the recording / reproducing unit 40 are controlled. Whether to rewrite using the data reproduced by the tracking control unit 60 and the recording / reproducing unit 40 Or was a decision made by and the like rewrite function unit 80 that controls the operation of the recording system signal processing section 30 in accordance with the decision.
[0038]
As in the recording / reproducing unit 120 shown in FIG. 15, the recording / reproducing unit 40 includes a pair of recording rotary magnetic heads WA, WB arranged at an angle of 180 ° and a pair of reproducing rotary magnetic heads RA, RB. Includes a rotating drum 41 disposed at an angle of 180 °, and the magnetic tape 42 is run at a predetermined running speed in a state where the magnetic tape 42 is wound around the rotating drum 41 over a range of about 90 °. It is like that. Each time the rotary drum 41 rotates, the magnetic heads WA and WB and the magnetic heads RA and RB scan the inclined tracks TA and TB (see FIG. 8) on the magnetic tape 42 to record and reproduce signals. It has become.
[0039]
The interface controller 20 exchanges data with an external host computer (not shown) via the bus 21, supplies data sent from the host computer to the recording system signal processing unit 30, while the reproduction system signal processing unit 50 provides the data. The reproduced data is sent to the host computer.
[0040]
The recording system signal processing unit 30 is supplied with interleaver / deinterleaver 71 supplied with data input via the interface controller 20, and C2 supplied with data interleaved by the interleaver / deinterleaver 71. The encoder / decoder 72, the C1 encoder / decoder 73 to which the data to which the error correction code C2 is added is supplied by the C2 encoder / decoder 72, and the buffer memory required for executing the processes in these modules 71 to 73 SDRAM (Synchronous DRAM) 74 and a memory controller 75 interposed between each of the modules 71 to 73 and the SDRAM 74.
[0041]
Here, the C2 encoder / decoder 72 generates an error correction code C2 of a data string corresponding to the track direction, and assigns this error correction code C2 to the central portion of the main data area of each track. The C1 encoder / decoder 73 generates an error correction code C1 for each fragment (block) described above.
[0042]
In addition, the recording system signal processing unit 30 includes a subcode addition circuit 31 to which data to which the error correction code C1 is added is supplied by the C1 encoder / decoder 73, and a subcode and fragment address (block) by the subcode addition circuit 31. Header parity adding circuit 32 to which main data to which address is added is supplied, 8/10 modulation circuit 33 to which main data to which header parity is added is supplied by this header parity adding circuit 32, and this 8/10 A synchronizing signal adding circuit 34 to which main data converted into 10-bit data by the modulation circuit 33 is supplied, and a margin adding circuit 35 to which main data to which a synchronizing signal is added for each fragment by the synchronizing signal adding circuit 34 are supplied. And main data to which a margin is added by the margin adding circuit 35. And a recording amplifier 36 to be supplied.
[0043]
The subcode and fragment address added by the subcode addition circuit 31 are supplied from the subcode generation unit 37. The subcode generation unit 37 includes first and second subcode generation circuits 37a and 37b and a system log generation circuit 37c. Based on the data input via the interface controller 20, the subcode generating circuit 37a generates a separator count that is delimiter information indicating a delimiter of main data, a record count that indicates the number of records, and the like. The subcode generation circuit 37b automatically generates an area ID indicating each area defined on the tape format, a frame number, a group count indicating the number of recording units, a checksum, and the like together with a fragment address. Further, the system log generation circuit 37c generates a system log (history information) for each partition P1, P2 defined as the tape format described above.
[0044]
The header parity adding circuit 32 generates a 2-symbol parity for error detection for the subcode and fragment address added to the main data by the subcode adding circuit 31, and adds this parity to the main data. The 8/10 modulation circuit 33 converts the main data, to which the header parity is added by the header parity addition circuit 32, from 8 bits to 10 bits in units of 1 byte so as to keep the DC level of the recording signal substantially at 0. To do.
[0045]
The synchronization signal adding circuit 34 adds a synchronization signal for each fragment (one block) to the main data converted into 10-bit data by the 8/10 modulation circuit 33. Further, the margin adding circuit 35 adds a margin for each track to the main data to which the synchronization signal is added. As described above, the main data to which the margin is added for each track by the margin adding circuit 35 is supplied to the recording / reproducing unit 40 via the recording amplifier 36.
[0046]
The operation of the recording system signal processing unit 30 will be briefly described. Data input via the interface controller 20 is interleaved by the interleaver / deinterleaver 71. Thereafter, an error correction code C2 of a data sequence corresponding to the track direction is generated and added to the input data by the C2 encoder / decoder 72, and further, the error correction code C1 for each fragment is added by the C1 encoder / decoder 73. Is generated and added. As described above, two sequences of C1 (62, 56) codes subjected to 2-symbol interleaving are arranged in each fragment.
[0047]
Subcode and fragment addresses are added by the subcode addition circuit 31 to the main data to which the error correction codes C2 and C1 output from the C1 encoder / decoder 73 are added, and the parity is also added to them by the header parity addition circuit 32. Added. The main data output from the header parity adding circuit 32 is converted from 8-bit data to 10-bit data by the 8/10 modulation circuit 33.
[0048]
With respect to the main data converted into the 10-bit data, a synchronizing signal is added to the head of each fragment by the synchronizing signal adding circuit 34, and a margin is added to both sides of the main data area for each track by the margin adding circuit 35. A signal of a predetermined format as a recording signal is obtained. The recording signal is supplied to the recording / reproducing unit 40 via the recording amplifier 36 and recorded on the inclined track of the magnetic tape 42 by the rotating magnetic heads WA and WB.
[0049]
Further, the reproduction system signal processing unit 50 is supplied with a reproduction signal reproduced from the inclined track of the magnetic tape 42 by the recording / reproduction unit 40 via a reproduction amplifier 51, and reproduced from the clock reproduction circuit 52. A synchronization signal detection circuit 53 to which data is supplied, a 10/8 demodulation circuit 54 to which the reproduction data and the detected synchronization signal are supplied from the synchronization signal detection circuit 53, and the 10/8 demodulation circuit 54 A header parity check circuit 55 to which reproduction data converted into 8-bit data is supplied, and a subcode separation circuit 56 to which reproduction data subjected to parity check by the header parity check circuit 55 is supplied. .
[0050]
The clock reproduction circuit 52 is configured using a PLL (phase-locked loop) circuit, reproduces a channel bit clock signal from a reproduction signal supplied from the recording / reproduction unit 40 via the reproduction amplifier 51, and generates the reproduction clock signal. Playback data synchronized with is generated. The synchronization signal detection circuit 53 detects the synchronization signal arranged at the head of each fragment from the reproduction data from the clock reproduction circuit 52 using the above-described reproduction clock signal. The 10/8 demodulator circuit 54 finds a 10-bit break using the synchronization signal detected by the synchronization signal detection circuit 53 as a timing reference, and converts the reproduction data from 10-bit data to 8-bit data.
[0051]
Further, the header parity check circuit 55 performs a parity check of the subcode and the fragment address added to the main data using the above-described 2-symbol header parity. Then, the subcode separation circuit 56 separates the correct subcode and fragment address parity-checked by the header parity check circuit 55 from the reproduction data and supplies them to the system controller 11 and the like.
[0052]
The reproduction system signal processing unit 50 also includes a C1 encoder / decoder 73 to which reproduction data from which the subcode and fragment address are separated by the subcode separation circuit 56 is supplied, and an error correction code C1 by the C1 encoder / decoder 73. The C2 encoder / decoder 72 to which the error-corrected main data is supplied, and the main data error-corrected by the error correction code C2 by the C2 encoder / decoder 72 are supplied, and deinterleaved and supplied to the interface controller 20 An interleaver / deinterleaver 71, an SDRAM 74 as a buffer memory necessary for executing processing in each of the modules 71 to 73, and a memory controller 75 interposed between the modules 71 to 73 and the SDRAM 74. It has.
[0053]
Here, the C1 encoder / decoder 73 performs error correction processing on the main data for each fragment using the error correction code C1 added for each fragment. Further, the C2 encoder / decoder 72 uses the error correction code C2 added to the central portion of the main data area for the main data for each fragment that has been subjected to the error correction processing by the C1 encoder / decoder 73 as described above. Using this, an error correction process is performed on the data string corresponding to the track direction.
[0054]
The operation of the reproduction system signal processing unit 50 described above will be briefly described. A reproduction signal reproduced from the inclined track of the magnetic tape 42 by the recording / reproducing unit 40 is supplied to a clock reproduction circuit 52 via a reproduction amplifier 51, and a clock signal (channel bit clock signal) is reproduced from the reproduction signal. Reproduction data synchronized with the reproduction clock signal is generated. Then, a sync signal added to the beginning of each fragment is detected by the sync signal detection circuit 53 with respect to this reproduced data, and the 10/8 demodulator circuit 54 converts the detected sync signal into 8-bit data using the timing reference as a timing reference. Conversion is performed.
[0055]
The reproduction data converted into the 8-bit data is supplied to the header parity check circuit 55, and a parity check is performed on the subcode and fragment address added to the main data for each fragment. The correct subcode and fragment address are separated by the subcode separation circuit 56 and supplied to the system controller 11 and the like.
[0056]
The reproduced data from which the subcode and the fragment address are separated by the subcode separation circuit 56 is subjected to error correction processing for each fragment using the error correction code C1 added for each fragment by the C1 encoder / decoder 73. In addition, the C2 encoder / decoder 72 performs an error correction process on the data string in the track direction using the error correction code C2 added to the central portion of the main data area. The error-corrected reproduction data output from the C2 encoder / decoder 72 is deinterleaved by the interleaver / deinterleaver 71 and then sent to the host computer via the interface controller 20.
[0057]
The tracking control unit 60 also includes a fragment address detection circuit 61 to which a fragment address is supplied from the reproduction system signal processing unit 50 via the header parity check circuit 55, and a PG pulse detection to which a PG pulse is supplied from the recording / reproduction unit 40. A circuit 62, a time detection circuit 63 to which each detection output of the fragment address detection circuit 61 and the PG pulse detection circuit 62 is supplied, a tracking servo circuit 64 to which the detection output of this time detection circuit 63 is supplied, and this tracking servo The capstan driving circuit 65 is supplied with the output of the circuit 64.
[0058]
In the tracking control unit 60, the detection circuit 61 detects a correct fragment address whose parity has been checked by the header parity check circuit 55, and supplies a detection output indicating the detection timing to the time detection circuit 63. The PG pulse detection circuit 62 detects a PG pulse indicating the rotation phase of the rotary drum 41 supplied from the recording / reproducing unit 40 and supplies a detection output indicating the detection timing to the time detection circuit 63. The time detection circuit 63 detects a time between the timing when the detection circuit 61 detects a predetermined fragment address and the timing when the detection circuit 62 detects a PG pulse.
[0059]
Here, when the inclined track on the magnetic tape 42 is scanned by the rotary magnetic heads RA and RB having a predetermined rotation phase, as shown in FIG. 2, the scanning distance from the tape edge of the track to the predetermined block is just tracking. In contrast to L in this state, if there is a tracking error, it changes by ± Δ according to the tracking error. Therefore, the time detected by the time detection circuit 63 changes from the time in the just tracking state according to the tracking error.
[0060]
The tracking servo circuit 64 uses the time in the just tracking state as a reference time, detects a time difference between the reference time and the time detected by the time detection circuit 63, that is, a tracking error, and the tracking error becomes zero. A capstan drive circuit 65 that drives a capstan motor (not shown) of the tape running system of the recording / reproducing unit 40 is controlled. Thereby, tracking control can be performed without recording the ATF pattern for tracking control on the magnetic tape.
[0061]
Next, the rewrite function unit 80 will be described. The rewrite function unit 80 includes a detection / counting unit 81 to which reproduction data RD from which the subcode and fragment address are separated is supplied from the subcode separation circuit 56 of the reproduction system signal processing unit 50, and the detection / counting unit 81 Based on the obtained count values CE1 to CE3 and CD1 to CD3, it is determined whether or not to rewrite, and the system controller 11 for controlling the operation of the recording system signal processing unit 30 according to the determination.
[0062]
FIG. 3 shows the configuration of the detection / counting unit 81. The detection / counting unit 81 is supplied with the reproduction data RD from the subcode separation circuit 56, and each of the syndrome S is related to the two C1 series data of each fragment.₀~ S_FiveAnd the syndrome S calculated by the syndrome calculation circuit 133a.₀~ S_FiveThe zero error detection circuit detects whether or not both of the two C1 series data are zero errors for each fragment, and outputs a detection signal Sdet1 of “1” level when both are zero errors. 83 and three counters 84a to 84c for counting the number of detection signals Sdet1 in each interleave (32 fragments) relating to the sequence of the error correction code C2 for every 96 fragments constituting one track. .
[0063]
The counters 84a to 84b are reset at the beginning of each 96 fragment constituting one track under the control of the system controller 11. The counter 84a counts the detection signal Sdet1 in 32 fragments related to the sequence of the code C2 (symbol is shown by a circular figure in FIG. 12) to obtain the count value CE1. The counter 84b counts the detection signal Sdet1 in 32 fragments related to the sequence of the code C2 (symbols are shown in FIG. 12 as triangles) to obtain the count value CE2. Further, the counter 84c counts the detection signal Sdet1 in 32 fragments related to the sequence of the code C2 (symbol is shown in FIG. 12), and obtains the count value CE3.
[0064]
FIG. 4 shows a configuration example of the syndrome calculation circuit 82 and the zero error detection circuit 83.
[0065]
The syndrome calculation circuit 82, based on the reproduction data of the first C1 sequence out of the two C1 sequences constituting each fragment, generates a syndrome S related to the C1 sequence.₀~ S_FiveFrom the calculation processing unit 82A for calculating and calculating reproduction data of the second C1 series, the syndrome S related to the C1 series is calculated.₀~ S_FiveIt is comprised from the calculation process part 82B which calculates | requires and calculates | requires. The calculation processing unit 82A then displays the syndrome S.₀~ S_FiveAre provided in parallel with syndrome registers 91a to 91f that respectively calculate and output. Although a detailed description is omitted, the calculation processing unit 82B is configured similarly to the calculation processing unit 82A.
[0066]
The zero error detection circuit 83 has a syndrome S related to the first C1 sequence obtained by the calculation processing unit 82A.₀~ S_FiveBased on the above, the detection processing unit 83A that detects whether or not the data of the C1 series is a zero error, and the syndrome S related to the second C1 series obtained by the calculation processing unit 82B₀~ S_FiveBased on the above, the detection processing unit 83B that detects whether or not the C1 series data has zero error, and the detection signal SD1 and SD2 output from the detection processing units 83A and 83B, are detected as described above. An AND circuit 83C for obtaining the signal Sdet1.
[0067]
The detection processing unit 83A includes each 8-bit syndrome S related to the first C1 sequence.₀~ S_FiveOn the other hand, each of the AND circuits 92a to 92f takes a logical product after inverting each bit, and an AND circuit 93 takes a logical product of output data of the AND circuits 92a to 92f. In this case, when the first C1 series data is 0 error, the AND circuit 93, and hence the detection processing unit 83A, obtains the detection signal SD1 of “1” level. Although detailed description is omitted, the detection processing unit 83B is also configured in the same manner as the detection processing unit 83A described above. When the second C1 series data has 0 error, a detection signal SD2 of “1” level is obtained from the detection processing unit 83B. Therefore, for each fragment, when both the first and second C1 series data are 0 errors, the AND circuit 83C obtains a detection signal Sdet1 of “1” level.
[0068]
Returning to FIG. 3, the detection / counting unit 81 is supplied with the reproduction data RD from the subcode separation circuit 56, and the recording data WD corresponding to the reproduction data RD is received from the SDRAM 74 via the memory controller 75. The comparison circuit 85 that detects the drop-in described above by comparing the reproduction data RD and the recording data WD is read and supplied, and is output from the comparison circuit 85 for every 96 fragments constituting one track. And three counters 86a to 86c for counting the number of detection signals Sdet2 within each interleave (32 fragments) relating to the sequence of the error correction code C2.
[0069]
When the reproduction data RD and the corresponding recording data WD do not coincide with each other, the comparison circuit 85 outputs a detection signal Sdet2 of “1” level as drop-in. In this case, all the data of 124 symbols of one fragment (see FIG. 8) may be compared, or only a part of the data may be compared. As part of the data, for example, the data of the error correction code C1 is used. Even if there is a slight difference in the original data portion, the error correction code C1 added to the data portion changes greatly. Therefore, the data of the portion of the error correction code C1 is compared, so that it is a drop-in. It can be efficiently determined.
[0070]
The counters 86a to 86b are reset at the beginning of each 96 fragment constituting one track under the control of the system controller 11. The counter 86a counts the detection signal Sdet2 in 32 fragments related to the sequence of the code C2 (symbol is shown by a circle in FIG. 12) to obtain the count value CD1. The counter 86b counts the detection signal Sdet2 in 32 fragments related to the sequence of the code C2 (symbols are shown in FIG. 12 as triangles) to obtain the count value CD2. Further, the counter 86c counts the detection signal Sdet2 in 32 fragments related to the sequence of the code C2 (the symbol is shown in FIG. 12 as a square figure) to obtain the count value CD3.
[0071]
Since the correction capability of the error correction code C2 is 6 symbols, the system controller 11 is based on the count values CE1 to CE3 and CD1 to CD3, for each of 32 fragments related to the sequence of the error correction code C2, When (dropped fragment number) × 2 + (number of fragments with bad data)> 6, it is recorded on the inclined track because there is a possibility that data cannot be obtained correctly during reproduction from the corresponding inclined track. Rewrite to record the recorded data again is determined. Here, the number of fragments whose data is not good is the number of fragments for which a detection signal Sdet1 of “1” level indicating zero error cannot be obtained. When the system controller 11 determines the rewrite as described above, the system controller 11 controls the reading from the SDRAM 74 in the interleaver / deinterleaver 71 so that the recording is performed again from the recording data on which the retry is determined as described above. To.
[0072]
The operation of the above-described rewrite function unit 80 will be described. In the recording / reproducing unit 40, signals recorded on the inclined tracks of the magnetic tape 42 by the rotating magnetic heads WA, WB are subsequently reproduced by the rotating magnetic heads RA, RB. In this case, as shown in FIG. 17, the corresponding reproduction signal is reproduced with a delay of a predetermined time t with respect to the recording signal supplied to the recording / reproducing unit 120 and recorded.
[0073]
The reproduction data RD from the subcode separation circuit 56 is supplied to the detection / counting unit 81. In the detection / counting unit 81, the syndrome S is related to the two C1 series data of each fragment.₀~ S_FiveIs calculated and its syndrome S₀~ S_FiveBased on, it is detected for each fragment whether or not both of the two C1 series data are zero errors. Then, the number of 0 errors in both is counted in each interleave related to the sequence of the error correction code C2, and for each 96 fragments constituting one track, the count values CE1 to CE3 of 0 error in each interleave are obtained. can get.
[0074]
In addition, the detection / counting unit 81 compares the reproduction data RD and the corresponding recording data WD, and performs drop-in detection for each fragment. The number of drop-ins is counted in each interleave related to the sequence of error correction code C2, and the drop-in count values CD1 to CD3 in each interleave are obtained for every 96 fragments constituting one track.
[0075]
The count values CE1 to CE3, CD1 to CD3 are supplied to the system controller 11, and it is determined whether or not to rewrite based on the count values CE1 to CE3 and CD1 to CD3. That is, the system controller 11 responds when (number of fragments that are drop-in) × 2 + (number of fragments whose data is not good)> 6 in any of the 32 fragments of the error correction code C2 sequence. Since there is a possibility that data cannot be obtained correctly at the time of reproduction from the inclined track to be rewritten, it is determined to rewrite the recording data recorded on the inclined track again. When the rewrite is determined, the system controller 11 controls the reading from the SDRAM 74 in the interleaver / deinterleaver 71 so that the recording is performed again from the recording data for which the retry is determined as described above. To do. For example, when 0 error is detected from the reproduction data of frame number = 6 and it is determined whether or not to rewrite based on the count value CT0, the track pattern on the magnetic tape 42 is shown in FIG. As shown in FIG. 18B, when rewriting is performed, frames with frame numbers 7 to 9 subsequent to the first frame number 6 are extra frames.
[0076]
As described above, in the present embodiment, the number of fragments determined to be good data is counted within the interleave related to the sequence of the second error correction code C2, and rewrite is performed based on the count result. Thus, the rewrite rate can be greatly improved and the decrease in recording capacity can be suppressed without increasing the possibility that the data cannot be correctly reproduced.
[0077]
That is, in the conventional example, the rewrite is determined when the number of fragments with bad data out of 96 fragments constituting one track is 7 or more. However, in this embodiment, when the number of drop-ins is set to 0, rewrite is determined when the number of non-good fragments is 7 or more for each interleave (32 fragments). The
[0078]
This has the following advantages over burst (continuous) errors. That is, in the conventional example, rewriting is performed when there is a continuous error having a length of 7 fragments or more, but in this embodiment, rewriting is not performed in the case of a burst error having a length of 18 fragments or less.
[0079]
In addition, there are the following advantages over random errors. The rewrite rate Pa in the conventional example is expressed by equation (1). Where Pf is a fragment error rate.
[0080]
[Expression 1]

[0081]
On the other hand, the rewrite rate Pb in the present embodiment is expressed by equation (2).
[0082]
[Expression 2]

[0083]
FIG. 5 shows the relationship between the fragment error rate Pf and the rewrite rates Pa and Pb. In the present embodiment, the fragment error rate is 1 × 10 6 as compared with the conventional example.^-2It can be seen that the rewrite rate is improved by 5 digits or more.
[0084]
In an actual system, burst errors and random errors are mixed, so that both merits described above can be obtained in this embodiment.
[0085]
Further, in the present embodiment, the number of fragments determined to be drop-in is counted for each interleave related to the second error correction code sequence, and the number of fragments determined to be good data. Rewrite is determined based on the count result and the count result of the number of fragments determined to be drop-in. Therefore, when there is a possibility that data cannot be correctly reproduced due to the occurrence of drop-in, the rewrite can be surely executed.
[0086]
In the above embodiment, when there is no error in the fragment data, it is determined that the fragment data is good. That is, a zero error detection circuit 83 (see FIG. 4) is used for the detection / counting unit 81 (see FIG. 3). However, even if there is an error in the fragment data, if the error can be corrected by the first error correction code C1, the fragment data may be determined to be good.
[0087]
For example, when the two C1 series data of the fragment are 0 error or 1 error, respectively, when the data of the fragment is determined to be good, 0 error detection of the detection / counting unit 81 shown in FIG. Instead of the circuit 83, a 0 error / 1 error detection circuit 87 shown in FIG. The detection circuit 87 includes a syndrome S related to the first C1 series obtained by the calculation processing unit 82A.₀~ S_Five, The detection processing unit 87A that detects whether the C1 series data is 0 error or 1 error, and the syndrome S related to the second C1 series obtained by the calculation processing unit 82B₀~ S_FiveBased on the above, the logical product of the detection processing unit 87B for detecting whether the C1 series data is 0 error or 1 error and the detection signals SD3 and SD4 output from these detection processing units 87A and 87B is obtained. An AND circuit 87C for obtaining the detection signal Sdet1.
[0088]
The detection processing unit 87A includes each 8-bit syndrome S related to the first C1 sequence.₀~ S_FiveAnd four Galois volume sum calculators 94a to 94d that perform calculations using the four-and-four ANDs that take the logical product after inverting each bit for the 8-bit calculation results from these calculators 94a to 94d. The circuits 95a to 95d and an AND circuit 96 that takes the logical product of the output data of the AND circuits 95a to 95d. In this case, when the first C1 series data is 0 error or 1 error, a detection signal SD3 of “1” level is obtained from the AND circuit 96, and hence the detection processing unit 87A. Although detailed description is omitted, the detection processing unit 87B is also configured in the same manner as the detection processing unit 87A described above. When the second C1 series data is 0 error or 1 error, a detection signal SD4 of “1” level is obtained from the detection processing unit 87B. Therefore, for each fragment, when both the first and second C1 series data are 0 error or 1 error, the detection signal Sdet1 of “1” level is obtained from the AND circuit 87C.
[0089]
As described above, when the two C1 series data of the fragment is 0 error or 1 error, respectively, when the data of the fragment is determined to be good, the rewrite rate for the random error Pc is expressed by equation (3). Here, Ps indicates a symbol error rate, and Pf1 indicates a fragment error rate of 2 errors or more.
[0090]
[Equation 3]

[0091]
FIG. 7 shows the relationship between the fragment error rate Pf and the rewrite rates Pa and Pc, and it can be seen that the rewrite rate is greatly improved.
[0092]
Further, in the syndrome calculation circuit 82 and the 0 error / 1 error detection circuit 87 shown in FIG. 6, a calculation processing unit 82A and a detection processing unit 87A are provided corresponding to the first C1 series, and the second C1 series. Although the calculation processing unit 82B and the detection processing unit 87B are separately provided correspondingly to the above, the first C1 sequence and the second C1 sequence are provided with only one calculation processing unit and detection processing unit. It is good also as a structure used by time division. Further, the configuration may be such that one syndrome register in the calculation processing unit is used in a time-sharing manner, and one Galois volume sum calculator in the detection processing unit is used in a time-sharing manner. As a result, the circuit scale can be greatly reduced. Such a reduction in circuit scale can be similarly applied to the syndrome calculation circuit 82 and the zero error detection circuit 83 shown in FIG.
[0093]
In the above embodiment, the number of fragments (blocks) with good data is counted by the first counting means (counters 84a to 84c). Conversely, the number of fragments with bad data is counted. It is good also as composition to do. Similarly, the second counting means (counters 86a to 86c) counts the number of fragments determined to be drop-in, but conversely counts the number of fragments determined not to be drop-in. It is good also as composition to do.
[0094]
In the above-described embodiment, the present invention is applied to a data recorder using DAT. However, the present invention is a recording data to which first and second error correction codes constituting a product code are added. The present invention can be similarly applied to other data recording apparatuses that record the information on the recording medium.
[0095]
【The invention's effect】
  According to the present invention, after the recording data to which the first and second error correction codes constituting the product code are added is recorded on the recording medium, the recording data is reproduced, and the first error is related to the reproduced data. For each block in which the correction code is generated, whether the data is good or bad is determined, and the number of blocks for which the data is good or not good is counted in the interleave relating to the second error correction code sequence. The number of blocks determined to be drop-in or not drop-in is counted for each interleave related to the second error correction code sequence,When the number obtained by multiplying the number of blocks that are drop-in by a predetermined number and the number of blocks having bad data exceeds a predetermined value, the recording data is re-recorded on the recording medium.
[0096]
Therefore, the rewrite rate can be greatly improved without increasing the possibility that data cannot be correctly reproduced during reproduction. AlsoWhen there is a possibility that data cannot be correctly reproduced due to the occurrence of drop-in, rewrite can be surely executed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data recorder using a DAT as an embodiment.
FIG. 2 is a diagram for explaining a tracking error detection principle;
FIG. 3 is a block diagram illustrating a configuration of a detection / counting unit that constitutes a rewrite function unit;
FIG. 4 is a block diagram showing a configuration of a syndrome calculation circuit and a zero error detection circuit.
FIG. 5 is a diagram illustrating a relationship between a fragment error rate and a rewrite rate.
FIG. 6 is a block diagram showing a configuration of a syndrome calculation circuit and a 0 error / 1 error detection circuit.
FIG. 7 is a diagram illustrating a relationship between a fragment error rate and a rewrite rate.
FIG. 8 is a diagram showing an example of a track format of a magnetic tape.
FIG. 9 is a diagram illustrating a configuration of an error correction code of main data.
FIG. 10 is a diagram showing two C1 (62, 56) codes arranged in the data portion of one fragment.
FIG. 11 is a diagram illustrating a data configuration of a C1 series.
FIG. 12 is a diagram illustrating a data configuration of a C2 series.
FIG. 13 is a diagram showing a tape format of a magnetic tape.
FIG. 14 is a diagram showing a tape format of a two-partition tape.
FIG. 15 is a block diagram showing a configuration of a portion related to recording of a conventional data recorder.
FIG. 16 is a block diagram illustrating a configuration of a zero error detection / counting unit.
FIG. 17 is a diagram for explaining a read / after-write mechanism;
FIG. 18 is a diagram showing an example of a track pattern at the time of non-rewrite and at the time of rewrite.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Data recorder, 11 ... System controller, 20 ... Interface controller, 30 ... Recording system signal processing part, 40 ... Recording / reproducing part, 50 ... Reproduction system signal processing part, 60 ... Tracking control unit, 80 ... Rewrite function unit, 81 ... Detection / counting unit, 82 ... Syndrome calculation circuit, 83 ... 0 error detection circuit, 84a to 84c, 86a to 86c,.・ Counter, 85 ... comparison circuit, 87 ... 0 error / 1 error detection circuit

Claims (4)

A first error correction code that constitutes a product code for each block is generated for the recorded data, and a second error correction code that constitutes the product code is generated by performing interleaving for a predetermined block unit, A data recording apparatus for recording recording data to which a first error correction code and a second error correction code are added to a recording medium,
Data reproducing means for reproducing the recorded recording data from the recording medium;
With respect to the data reproduced by the data reproduction means, data determination means for determining the quality of the data for each block,
First counting means for counting the number of blocks in which the data is judged good or not good by the data judging means within each interleave relating to the second error correction code sequence;
Drop-in determination means for determining whether or not the data reproduced by the data reproduction means is a drop-in for each block by comparing all the reproduction data with the corresponding recording data;
Second counting means for counting the number of the blocks determined to be drop-in by the drop-in determination means or not drop-in for each interleaving related to the second error correction code sequence;
The number obtained by adding the number of blocks with bad data counted by the first counting means and the number of blocks counted by the second counting means multiplied by a predetermined number exceeds the predetermined value. when the data recording apparatus characterized by comprising a Brighter light determining means to re-record the recording data on the recording medium. The data recording apparatus according to claim 1, wherein the data determination unit determines whether or not there is an error in the data of the block, and determines that the data of the block without an error is good. The data determination means determines whether or not there is an error in the data of the block, and whether or not the data can be corrected when there is an error. The data recording apparatus according to claim 1, wherein the data is determined to be good. A first error correction code that constitutes a product code for each block is generated for the recorded data, and a second error correction code that constitutes the product code is generated by performing interleaving for a predetermined block unit, A rewrite determination method of a data recording apparatus for determining whether or not to re-record the recording data on the recording medium after recording the recording data to which the first and second error correction codes are added to the recording medium,
A first step of reproducing the recorded data recorded from the recording medium;
A second step for determining the quality of the reproduced data for each block;
A third step of counting the number of the block data is determined to be no good, for each interleave in accordance with the sequence of the second error correcting code,
A fourth step of determining, for each block, whether or not it is a drop-in by comparing all the reproduced data with the recorded data for the reproduced data;
A fifth step of counting the number of blocks determined to be drop-in for each interleaving related to the second error correction code sequence;
When the number obtained by adding the number of blocks with bad data counted in the third step and the number obtained by multiplying the number of blocks that are drop-in counted in the fifth step exceeds a predetermined value rewrite determining method of a data recording apparatus characterized by having a sixth step you re recording the recording data on the recording medium.

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