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JP4517363B2 - Silicon electrode plate for plasma etching - Google Patents

Silicon electrode plate for plasma etching Download PDF

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JP4517363B2
JP4517363B2 JP2005237255A JP2005237255A JP4517363B2 JP 4517363 B2 JP4517363 B2 JP 4517363B2 JP 2005237255 A JP2005237255 A JP 2005237255A JP 2005237255 A JP2005237255 A JP 2005237255A JP 4517363 B2 JP4517363 B2 JP 4517363B2
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JP2007053231A (en
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利玄 臂
孝志 米久
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Mitsubishi Materials Corp
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Description

この発明は、パーティクル発生が少なくかつ使用寿命の長いプラズマエッチング用シリコン電極板に関するものである。   The present invention relates to a silicon electrode plate for plasma etching that generates less particles and has a long service life.

一般に、半導体集積回路を製造する工程において使用するＳｉウエハをエッチングするためのプラズマエッチング装置は、図４に示されるように、真空容器１内にシリコン電極板２および架台３が間隔をおいて設けられており、架台３の上にＳｉウエハ４を載置し、エッチングガス７をシリコン電極板２に設けられた貫通細孔５を通してＳｉウエハ４に向って流しながら高周波電源６により電極板２と架台３の間に高周波電圧を印加し、高周波電圧の印加によりシリコン電極板２と架台３の間の空間にプラズマ１０を発生させ、このプラズマ１０による物理反応と、シリコン−エッチングガス７による化学反応により、Ｓｉウエハ４の表面をエッチングする装置であることは知られている。シリコン電極板２はカーボンで構成された電極板が使用されたこともあったが、近年、主として単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなるシリコン電極板が使用されている。このシリコン電極板を使用してＳｉウエハをプラズマエッチングした場合、シリコン電極板に設けられた貫通細孔５は、シリコン電極板のＳｉウエハに対向する面に向かってラッパ状に広がりながら消耗し、寿命となる。この消耗を極力防止して、シリコン電極板の使用寿命を長くすべく、前記シリコン電極板の貫通細孔内面全面およびウエハと相対向する面（以下、下面という）の全面、さらに必要に応じて上面（下面の反対側の面）の全面に炭化ケイ素またはダイヤモンドライクカーボンなどのシリコンよりも消耗の少ない耐エッチング膜を形成してなる長寿命のプラズマエッチング用シリコン電極板が提案されている（特許文献１参照）。
特開２００３−５１４８５号公報 In general, in a plasma etching apparatus for etching a Si wafer used in a process of manufacturing a semiconductor integrated circuit, as shown in FIG. 4, a silicon electrode plate 2 and a pedestal 3 are provided in a vacuum container 1 at intervals. The Si wafer 4 is placed on the gantry 3, and the etching gas 7 flows through the through-hole 5 provided in the silicon electrode plate 2 toward the Si wafer 4, while the electrode plate 2 is connected to the electrode plate 2 by the high frequency power source 6. A high frequency voltage is applied between the gantry 3 and a plasma 10 is generated in the space between the silicon electrode plate 2 and the gantry 3 by the application of the high frequency voltage. A physical reaction by the plasma 10 and a chemical reaction by the silicon-etching gas 7 are generated. Thus, it is known that the apparatus etches the surface of the Si wafer 4. Although an electrode plate made of carbon has been used as the silicon electrode plate 2, in recent years, a silicon electrode plate mainly made of single crystal silicon, polycrystalline silicon or columnar crystal silicon has been used. When the silicon wafer is plasma etched using this silicon electrode plate, the through-hole 5 provided in the silicon electrode plate is consumed while spreading in a trumpet shape toward the surface of the silicon electrode plate facing the Si wafer, Life is reached. In order to prevent this consumption as much as possible and to prolong the service life of the silicon electrode plate, the entire inner surface of the through-hole of the silicon electrode plate and the entire surface facing the wafer (hereinafter referred to as the lower surface), and further if necessary There has been proposed a long-life silicon electrode plate for plasma etching in which an etching-resistant film that is less consumed than silicon such as silicon carbide or diamond-like carbon is formed on the entire upper surface (the surface opposite to the lower surface) (patent) Reference 1).
JP 2003-51485 A

確かに、従来の耐エッチング膜を形成したパーティクル発生の少ないプラズマエッチング用シリコン電極板は、その使用寿命が延びて長時間のプラズマエッチングが可能となったが、この従来の耐エッチング膜を形成したシリコン電極板を使用してプラズマエッチングを行うと、耐エッチング膜として被覆されている皮膜は炭化ケイ素またはダイヤモンドライクカーボンから構成されているために、プラズマエッチング開始当初は、実質的に、炭化ケイ素またはダイヤモンドライクカーボンからなる電極を使用してプラズマエッチングが行われているのと同じ効果を有し、微量の炭素が不純物としてＳｉウエハのエッチング面に付着したり、また前記炭化ケイ素またはダイヤモンドライクカーボンなどの耐エッチング膜が剥離してパーティクル発生の原因となるなどの問題点があった。   Certainly, the silicon electrode plate for plasma etching with less particle generation formed with the conventional etching resistant film has extended its service life and enabled long-time plasma etching, but this conventional etching resistant film was formed. When plasma etching is performed using a silicon electrode plate, since the film coated as an etching resistant film is composed of silicon carbide or diamond-like carbon, at the beginning of plasma etching, substantially silicon carbide or It has the same effect as plasma etching using an electrode made of diamond-like carbon, and a small amount of carbon adheres to the etched surface of the Si wafer as an impurity, or the silicon carbide or diamond-like carbon The etching resistant film peels off and There is a problem such as the cause of the occurrence.

そこで、本発明者等は、かかる課題を解決すべく研究を行った結果、
（イ）厚さ方向に平行に貫通細孔が設けられている単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなるシリコン電極基板の表面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を形成したプラズマエッチング用シリコン電極板は、従来の単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなる通常のプラズマエッチング用シリコン電極板に比べて、パーティクルの発生数が同等または格段に少なくなり、さらに消耗速度が減少して使用寿命が向上する、
（ロ）その場合、前記シリコン電極基板の少なくとも下面にシリコンの化学蒸着膜を形成されていることが必要である、
（ハ）前記シリコン電極基板の下面の他にさらに前記シリコン電極基板の貫通細孔の内面にシリコンの化学蒸着膜が形成されることが一層好ましい、
（ニ）前記シリコン電極基板に形成されるシリコンの化学蒸着膜は、上面、下面、側面および貫通細孔の内面を含めて全面に形成されることがさらに一層好ましい、
（ホ）前記シリコン電極基板の表面に形成されるシリコンの化学蒸着膜は、平均粒径１μｍ以下の超微細結晶粒を有することがパーティクル発生を一層抑制する、などの研究結果が得られたのである。 Therefore, as a result of conducting research to solve such problems, the present inventors,
(A) The surface of a silicon electrode substrate made of single crystal silicon, polycrystalline silicon, or columnar crystal silicon having through-holes provided in parallel to the thickness direction is made of ultrafine crystal grains having an average grain size of 1 μm or less. The silicon electrode plate for plasma etching in which a chemical vapor deposition film of silicon is formed has the same number of particles as compared to the conventional silicon electrode plate for plasma etching made of single crystal silicon, polycrystalline silicon, or columnar crystal silicon. Remarkably less, and further reduce the consumption rate and improve the service life,
(B) In that case, it is necessary that a chemical vapor deposition film of silicon is formed on at least the lower surface of the silicon electrode substrate.
(C) It is more preferable that a chemical vapor deposition film of silicon is further formed on the inner surface of the through-hole of the silicon electrode substrate in addition to the lower surface of the silicon electrode substrate.
(D) It is still more preferable that the silicon chemical vapor deposition film formed on the silicon electrode substrate is formed on the entire surface including the upper surface, the lower surface, the side surface, and the inner surface of the through-hole,
(E) Since the chemical vapor deposition film of silicon formed on the surface of the silicon electrode substrate has ultrafine crystal grains having an average grain size of 1 μm or less, the results of research have been obtained, etc. is there.

この発明は、かかる研究結果に基づいてなされたものであって、
（１）厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の少なくとも下面全面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなるプラズマエッチング用シリコン電極板、
（２）厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の少なくとも下面全面および前記貫通細孔内面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなるプラズマエッチング用シリコン電極板、
（３）厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の表面全面および前記貫通細孔内面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなるプラズマエッチング用シリコン電極板、
（４）前記シリコン電極基板は、単結晶シリコン、多結晶シリコンおよび柱状晶シリコンの内のいずれかからなる前記（１）、（２）、（３）記載のプラズマエッチング用シリコン電極板、に特長を有するものである。
この発明のプラズマエッチング用シリコン電極板を図面に基づいて一層詳細に説明する。
図１は、厚さ方向に平行に貫通細孔５が設けられているシリコン電極基板２の下面８にシリコンの化学蒸着膜１１が形成されたこの発明のプラズマエッチング用シリコン電極板の断面図である。
図２は、厚さ方向に平行に貫通細孔５が設けられているシリコン電極基板２の下面および貫通細孔５の内面にシリコンの化学蒸着膜１１が形成されたこの発明のプラズマエッチング用シリコン電極板の断面図である。
図３は、厚さ方向に平行に貫通細孔が設けられているシリコン電極基板２の下面８、上面９、側面および貫通細孔５の内面にシリコンの化学蒸着膜１１が形成されたこの発明のプラズマエッチング用シリコン電極板の断面図である。
図１〜３に示されるこの発明のプラズマエッチング用シリコン電極板は、通常の化学蒸着法により通常の単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなるシリコン電極基板２の表面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜１１を形成することにより製造することができる。 The present invention has been made based on the results of such research,
(1) Plasma obtained by coating a chemical vapor deposition film of silicon made of ultrafine crystal grains having an average grain size of 1 μm or less on at least the entire lower surface of a silicon electrode substrate provided with through pores parallel to the thickness direction. Silicon electrode plate for etching,
(2) A chemical vapor deposition film of silicon comprising ultrafine crystal grains having an average grain size of 1 μm or less on at least the entire lower surface of the silicon electrode substrate provided with through pores parallel to the thickness direction and the inner surface of the through pores. A silicon electrode plate for plasma etching, coated with
(3) A silicon chemical vapor deposition film composed of ultrafine crystal grains having an average grain size of 1 μm or less is formed on the entire surface of the silicon electrode substrate in which through-holes are provided in parallel to the thickness direction and on the inner surface of the through-holes. A silicon electrode plate for plasma etching formed by coating;
(4) the silicon electrode substrate, a single crystal silicon, the consisting of any of the polycrystalline silicon and the columnar crystal silicon (1), (2), (3) Symbol mounting of plasma etching silicon electrode plates, the It has features.
The silicon electrode plate for plasma etching according to the present invention will be described in more detail with reference to the drawings.
FIG. 1 is a sectional view of a silicon electrode plate for plasma etching according to the present invention in which a chemical vapor deposition film 11 of silicon is formed on a lower surface 8 of a silicon electrode substrate 2 in which through-holes 5 are provided in parallel to the thickness direction. is there.
FIG. 2 shows the silicon for plasma etching of the present invention in which a chemical vapor deposition film 11 of silicon is formed on the lower surface of the silicon electrode substrate 2 in which the through-holes 5 are provided in parallel with the thickness direction and on the inner surface of the through-holes 5. It is sectional drawing of an electrode plate.
FIG. 3 shows the present invention in which a chemical vapor deposition film 11 of silicon is formed on the lower surface 8, the upper surface 9, the side surface and the inner surface of the through-hole 5 of the silicon electrode substrate 2 in which the through-hole is provided in parallel with the thickness direction. It is sectional drawing of the silicon electrode plate for plasma etching.
The silicon electrode plate for plasma etching of the present invention shown in FIGS. 1 to 3 has an average particle size on the surface of a silicon electrode substrate 2 made of ordinary single crystal silicon, polycrystalline silicon, or columnar crystal silicon by an ordinary chemical vapor deposition method. Can be manufactured by forming a silicon chemical vapor deposition film 11 made of ultrafine crystal grains of 1 μm or less .

前述の如く、前記シリコン電極基板２の表面に形成されるシリコンの化学蒸着膜１１は平均粒径が１μｍ以下の超微細結晶粒を有するが、シリコンの化学蒸着膜１１の平均粒径が１μｍを越えるとパーティクルの発生が増加し、さらに消耗速度が大きくなって使用寿命が短くなるからである。 As described above, the silicon chemical vapor deposition film 11 formed on the surface of the silicon electrode substrate 2 has ultrafine crystal grains having an average grain diameter of 1 μm or less, but the silicon chemical vapor deposition film 11 has an average grain diameter of 1 μm. If it exceeds the limit, the generation of particles increases, the consumption rate increases, and the service life is shortened.

この発明のプラズマエッチング用シリコン電極板は、表面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を形成することによりプラズマエッチング中に発生するパーティクルの数が少なくなり、使用寿命が延びてプラズマエッチングによる半導体集積回路を効率良く生産することができ、半導体装置産業の発展に大いに貢献しうるものである。
The silicon electrode plate for plasma etching of the present invention reduces the number of particles generated during plasma etching by forming a silicon chemical vapor deposition film composed of ultrafine crystal grains having an average grain size of 1 μm or less on the surface, The service life can be extended, semiconductor integrated circuits by plasma etching can be efficiently produced, and can greatly contribute to the development of the semiconductor device industry.

この発明のプラズマエッチング用シリコン電極板を実施例に基づいて具体的に説明する。
実施例１
直径：３００ｍｍの単結晶シリコンインゴットを用意し、このインゴットをダイヤモンドバンドソーにより厚さ：４ｍｍに輪切り切断して単結晶シリコン円板を作製し、この単結晶シリコン円板に内径：２．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：４ｍｍを有する単結晶シリコン電極基板を作製した。 The silicon electrode plate for plasma etching according to the present invention will be specifically described based on examples.
Example 1
A single crystal silicon ingot having a diameter of 300 mm is prepared, and this ingot is cut into a thickness of 4 mm using a diamond band saw to produce a single crystal silicon disk, and an inner diameter of 2.5 mm is penetrated through the single crystal silicon disk. A single crystal silicon electrode substrate having an outer diameter of 300 mm and a thickness of 4 mm was produced by forming the pores with a pitch between the holes of 8 mm.

この作製した外径：３００ｍｍを有する単結晶シリコン電極基板を通常の化学蒸着装置に装入しセットし、原料ガスであるモノシラン（ＳｉＨ４）を化学蒸着装置に導入し、単結晶シリコン電極基板を表１に示される成長温度に加熱し、単結晶シリコン電極基板の下面全面および貫通細孔の内面に、厚さ：１ｍｍを有し表１に示される平均結晶粒径を有するＳｉ化学蒸着膜を形成することにより本発明Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２および比較Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２を作製した。Ｓｉ化学蒸着膜の平均結晶粒径はＦＥＳＥＭ／ＥＢＳＰ法により結晶粒界と結晶粒（面）と分離した画像を抽出し、この画像から各結晶粒の面積を求め、さらにその面積から円相当径を算出することにより求めた。 The produced single crystal silicon electrode substrate having an outer diameter of 300 mm was charged and set in a normal chemical vapor deposition apparatus, and monosilane (SiH 4 ) as a raw material gas was introduced into the chemical vapor deposition apparatus, and the single crystal silicon electrode substrate was A Si chemical vapor deposition film having a thickness of 1 mm and an average crystal grain size shown in Table 1 is heated on the entire lower surface of the single crystal silicon electrode substrate and the inner surface of the through-holes to the growth temperature shown in Table 1. The Si chemical vapor deposition film-coated single crystal silicon electrode plates 1 and 2 and the comparative Si chemical vapor deposition film coated single crystal silicon electrode plates 1 and 2 of the present invention were produced. The average crystal grain size of the Si chemical vapor deposition film is obtained by extracting images separated from the crystal grain boundaries and crystal grains (planes) by the FESEM / EBSP method, obtaining the area of each crystal grain from this image, and further calculating the equivalent circle diameter from the area. Was calculated by calculating.

さらに、前記単結晶シリコン円板に内径：０．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：３ｍｍを有する従来単結晶シリコン電極板を作製した。   Further, a conventional single crystal silicon electrode plate having an outer diameter of 300 mm and a thickness of 3 mm was formed by forming through pores having an inner diameter of 0.5 mm in the single crystal silicon disk with an inter-hole pitch of 8 mm.

このようにして作製した本発明Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２およびＳｉ化学蒸着膜を被覆することのない従来単結晶シリコン電極板をそれぞれエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、
チャンバー内圧力：１０-1Ｔｏｒｒ、
エッチングガス組成：９０sccmＣＨＦ3 ＋４sccmＯ2 ＋１５０sccmＨｅ、
高周波電力：２ｋＷ、
周波数：２０ｋＨｚ、
の条件で、ウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から２５分間経過した時点でのウエハ表面に付着した粒径：０．１６μｍ以上のパーティクル数を測定し、その結果を表１に示した。前記パーティクル数の測定は、トプコン製のパーティクルカウンター（ＷＭ−３０００）を使用し、ウエハ表面をレーザ光により走査し、付着したパーティクルからの光散乱強度を測定することによりパーティクルの位置と大きさを認識することにより行った。 The thus produced Si chemical vapor deposition film-coated single crystal silicon electrode plates 1-2 of the present invention, the comparative Si chemical vapor deposition film coated single crystal silicon electrode plates 1-2, and the conventional single crystal without covering the Si chemical vapor deposition film Each silicon electrode plate is set in an etching apparatus, and a wafer on which a SiO 2 layer is formed in advance by CVD is set in an etching apparatus.
Chamber internal pressure: 10 −1 Torr,
Etching gas composition: 90 sccm CHF 3 +4 sccm O 2 +150 sccm He,
High frequency power: 2kW
Frequency: 20kHz,
Under the above conditions, plasma etching of the SiO 2 layer on the wafer surface was performed, and the number of particles with a particle size of 0.16 μm or more adhered to the wafer surface after 25 minutes from the start of etching was measured. It was shown to. The number of particles is measured using a TOPCON particle counter (WM-3000), the wafer surface is scanned with laser light, and the light scattering intensity from the adhered particles is measured to determine the position and size of the particles. Done by recognizing.

さらにエッチング開始から２５分間経過した時点での本発明Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２および従来単結晶シリコン電極板における中心（Ｘを半径とすると、Ｘ＝０の位置）、中心から５０ｍｍ離れた位置および中心から１００ｍｍ離れた位置における浸食深さ（μｍ）（ここで浸食深さとは電極板の厚さの減少量を示す）をそれぞれ測定し、浸食深さ×６０／２５＝消耗速度（μｍ／時）を求め、その結果を表１―１に示した。   Further, the center of the present invention Si chemical vapor deposition film-coated single crystal silicon electrode plates 1-2, comparative Si chemical vapor deposition film coated single crystal silicon electrode plates 1-2, and the conventional single crystal silicon electrode plate when 25 minutes have elapsed from the start of etching. (Where X is a radius, X = 0 position), erosion depth (μm) at a position 50 mm away from the center and a position 100 mm away from the center (where the erosion depth is the decrease in thickness of the electrode plate) The erosion depth × 60/25 = consumption rate (μm / hour) was determined, and the results are shown in Table 1-1.

Figure 0004517363
Figure 0004517363

Figure 0004517363
Figure 0004517363

実施例２
直径：３００ｍｍの多結晶シリコンインゴットを用意し、このインゴットをダイヤモンドバンドソーにより厚さ：４ｍｍに輪切り切断して多結晶シリコン円板を作製し、この多結晶シリコン円板に内径：２．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：３ｍｍを有する多結晶シリコン電極基板を作製した。 Example 2
A polycrystalline silicon ingot with a diameter of 300 mm is prepared, and this ingot is cut into a thickness of 4 mm with a diamond band saw to produce a polycrystalline silicon disc. The inner diameter of the polycrystalline silicon disc is 2.5 mm. A polycrystalline silicon electrode substrate having an outer diameter of 300 mm and a thickness of 3 mm was formed by forming the pores with a pitch between the holes of 8 mm.

この作製した外径：３００ｍｍを有する多結晶シリコン電極基板を通常の化学蒸着装置に装入しセットし、原料ガスであるモノシラン（ＳｉＨ４）を化学蒸着装置に導入し、多結晶シリコン電極基板を表２に示される成長温度に加熱し、多結晶シリコン電極基板の下面全面および貫通細孔の内面に、厚さ：１ｍｍを有し表２に示される平均結晶粒径を有するＳｉ化学蒸着膜を形成することにより本発明Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２および比較Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２を作製した。Ｓｉ化学蒸着膜の平均結晶粒径はＦＥＳＥＭ／ＥＢＳＰ法により結晶粒界と結晶粒（面）と分離した画像を抽出し、この画像から各結晶粒の面積を求め、さらにその面積から円相当径を算出することにより求めた。 The produced polycrystalline silicon electrode substrate having an outer diameter of 300 mm is set in an ordinary chemical vapor deposition apparatus, and monosilane (SiH 4 ) as a raw material gas is introduced into the chemical vapor deposition apparatus. A Si chemical vapor deposition film having a thickness of 1 mm and an average crystal grain size shown in Table 2 is formed on the entire lower surface of the polycrystalline silicon electrode substrate and the inner surface of the through-holes by heating to the growth temperature shown in Table 2. The Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1 and 2 and the comparative Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1 and 2 of the present invention were produced. The average crystal grain size of the Si chemical vapor deposition film is obtained by extracting images separated from the crystal grain boundaries and crystal grains (planes) by the FESEM / EBSP method, obtaining the area of each crystal grain from this image, and further calculating the equivalent circle diameter from the area. Was calculated by calculating.

さらに、前記多結晶シリコン円板に内径：０．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：４ｍｍを有する従来多結晶シリコン電極板を作製した。   Furthermore, a conventional polycrystalline silicon electrode plate having an outer diameter of 300 mm and a thickness of 4 mm was produced by forming through-holes having an inner diameter of 0.5 mm in the polycrystalline silicon disk with an inter-hole pitch of 8 mm.

このようにして作製した本発明Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２およびＳｉ化学蒸着膜を被覆することのない従来多結晶シリコン電極板をそれぞれエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、
チャンバー内圧力：１０-1Ｔｏｒｒ、
エッチングガス組成：９０sccmＣＨＦ3 ＋４sccmＯ2 ＋１５０sccmＨｅ、
高周波電力：２ｋＷ、
周波数：２０ｋＨｚ、
の条件で、ウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から２５分間経過した時点でのウエハ表面に付着した粒径：０．１６μｍ以上のパーティクル数を測定し、その結果を表２に示した。前記パーティクル数の測定は、トプコン製のパーティクルカウンター（ＷＭ−３０００）を使用し、ウエハ表面をレーザ光により走査し、付着したパーティクルからの光散乱強度を測定することによりパーティクルの位置と大きさを認識することにより行った。 The present invention Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1-2, comparative Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1-2, and conventional polycrystal without coating with Si chemical vapor deposition film silicon electrode plates were each set in an etching apparatus, a wafer was formed a SiO 2 layer was set in an etching apparatus by further advance CVD,
Chamber internal pressure: 10 −1 Torr,
Etching gas composition: 90 sccm CHF 3 +4 sccm O 2 +150 sccm He,
High frequency power: 2kW
Frequency: 20kHz,
Under the conditions described above, plasma etching of the SiO 2 layer on the wafer surface was performed, and the number of particles having a particle size of 0.16 μm or more adhered to the wafer surface when 25 minutes had elapsed from the start of etching was measured. It was shown to. The number of particles is measured using a TOPCON particle counter (WM-3000), the wafer surface is scanned with laser light, and the light scattering intensity from the adhered particles is measured to determine the position and size of the particles. Done by recognizing.

さらにエッチング開始から２５分間経過した時点での本発明Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２および従来多結晶シリコン電極板における中心（Ｘを半径とすると、Ｘ＝０の位置）、中心から５０ｍｍ離れた位置および中心から１００ｍｍ離れた位置における浸食深さ（μｍ）（ここで浸食深さとは電極板の厚さの減少量を示す）をそれぞれ測定し、浸食深さ×６０／２５＝消耗速度（μｍ／時）から消耗速度を求め、その結果を表２―１に示した。   Furthermore, the center of the present invention Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1-2, comparative Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1-2, and the conventional polycrystalline silicon electrode plate after 25 minutes from the start of etching. (Where X is a radius, X = 0 position), erosion depth (μm) at a position 50 mm away from the center and a position 100 mm away from the center (where the erosion depth is the decrease in thickness of the electrode plate) The erosion rate was determined from the erosion depth × 60/25 = consumption rate (μm / hour), and the results are shown in Table 2-1.

Figure 0004517363
Figure 0004517363

Figure 0004517363
Figure 0004517363

実施例３
直径：３００ｍｍの柱状晶シリコンインゴットを用意し、このインゴットをダイヤモンドバンドソーにより厚さ：４ｍｍに輪切り切断して柱状晶シリコン円板を作製し、この柱状晶シリコン円板に内径：２．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：３ｍｍを有する柱状晶シリコン電極基板を作製した。 Example 3
A columnar silicon ingot having a diameter of 300 mm is prepared, and this ingot is cut into a thickness of 4 mm with a diamond band saw to produce a columnar silicon disk, and an inner diameter of 2.5 mm is penetrated through the columnar silicon disk. A columnar crystal silicon electrode substrate having an outer diameter of 300 mm and a thickness of 3 mm was formed by forming the pores at an inter-hole pitch of 8 mm.

この作製した外径：３００ｍｍを有する柱状晶シリコン電極基板を通常の化学蒸着装置に装入しセットし、原料ガスであるモノシラン（ＳｉＨ４）を化学蒸着装置に導入し、柱状晶シリコン電極基板を表３に示される成長温度に加熱し、柱状晶シリコン電極基板の下面全面および貫通細孔の内面に厚さ：１ｍｍを有し、表３に示される平均結晶粒径を有するＳｉ化学蒸着膜を形成することにより本発明Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２および比較Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２を作製した。Ｓｉ化学蒸着膜の平均結晶粒径はＦＥＳＥＭ／ＥＢＳＰ法により結晶粒界と結晶粒（面）と分離した画像を抽出し、この画像から各結晶粒の面積を求め、さらにその面積から円相当径を算出することにより求めた。 The produced columnar silicon electrode substrate having an outer diameter of 300 mm is set in an ordinary chemical vapor deposition apparatus, monosilane (SiH 4 ) as a raw material gas is introduced into the chemical vapor deposition apparatus, and the columnar silicon electrode substrate is mounted. A Si chemical vapor deposition film having a thickness of 1 mm on the entire lower surface of the columnar crystal silicon electrode substrate and the inner surface of the through-holes and having an average crystal grain size shown in Table 3 is heated to the growth temperature shown in Table 3. The Si chemical vapor deposition film-covered columnar silicon electrode plates 1 and 2 and the comparative Si chemical vapor deposition film-coated columnar silicon electrode plates 1 and 2 of the present invention were produced. The average crystal grain size of the Si chemical vapor deposition film is obtained by extracting images separated from the crystal grain boundaries and crystal grains (planes) by the FESEM / EBSP method, obtaining the area of each crystal grain from this image, and further calculating the equivalent circle diameter from the area. Was calculated by calculating.

さらに、前記柱状晶シリコン円板に内径：０．５ｍｍの貫通細孔を孔間ピッチ：８ｍｍで形成することにより外径：３００ｍｍ、厚さ：４ｍｍを有する従来柱状晶シリコン電極板を作製した。   Further, a conventional columnar crystal silicon electrode plate having an outer diameter of 300 mm and a thickness of 4 mm was formed by forming through-holes having an inner diameter of 0.5 mm in the columnar crystal silicon disk with an inter-hole pitch of 8 mm.

このようにして作製した本発明Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２およびＳｉ化学蒸着膜を被覆することのない従来柱状晶シリコン電極板をそれぞれエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、
チャンバー内圧力：１０-1Ｔｏｒｒ、
エッチングガス組成：９０sccmＣＨＦ3 ＋４sccmＯ2 ＋１５０sccmＨｅ、
高周波電力：２ｋＷ、
周波数：２０ｋＨｚ、
の条件で、ウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から２５分間経過した時点でのウエハ表面に付着した粒径：０．１６μｍ以上のパーティクル数を測定し、その結果を表３に示した。前記パーティクル数の測定は、トプコン製のパーティクルカウンター（ＷＭ−３０００）を使用し、ウエハ表面をレーザ光により走査し、付着したパーティクルからの光散乱強度を測定することによりパーティクルの位置と大きさを認識することにより行った。 The present invention Si chemical vapor deposition film coated columnar silicon electrode plates 1-2, comparative Si chemical vapor deposition film coated columnar silicon electrode plates 1-2, and conventional columnar crystals not coated with Si chemical vapor deposition film Each silicon electrode plate is set in an etching apparatus, and a wafer on which a SiO 2 layer is formed in advance by CVD is set in an etching apparatus.
Chamber internal pressure: 10 −1 Torr,
Etching gas composition: 90 sccm CHF 3 +4 sccm O 2 +150 sccm He,
High frequency power: 2kW
Frequency: 20kHz,
Under the conditions, plasma etching of the SiO 2 layer on the wafer surface was performed, and the number of particles having a particle size of 0.16 μm or more adhered to the wafer surface when 25 minutes had elapsed from the start of etching was measured. It was shown to. The number of particles is measured using a TOPCON particle counter (WM-3000), the wafer surface is scanned with laser light, and the light scattering intensity from the adhered particles is measured to determine the position and size of the particles. Done by recognizing.

さらにエッチング開始から２５分間経過した時点での本発明Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２、比較Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２および従来柱状晶シリコン電極板における中心（Ｘを半径とすると、Ｘ＝０の位置）、中心から５０ｍｍ離れた位置および中心から１００ｍｍ離れた位置における浸食深さ（μｍ）（ここで浸食深さとは電極板の厚さの減少量を示す）をそれぞれ測定し、浸食深さ×６０／２５＝消耗速度（μｍ／時）を求め、その結果を表３―１に示した。   Further, the center of the Si chemical vapor deposition film-coated columnar silicon electrode plates 1 and 2 of the present invention, the comparative Si chemical vapor deposition film-coated columnar silicon electrode plates 1 and 2 and the conventional columnar silicon electrode plate when 25 minutes have passed since the start of etching. (Where X is a radius, X = 0 position), erosion depth (μm) at a position 50 mm away from the center and a position 100 mm away from the center (where the erosion depth is the decrease in thickness of the electrode plate) The erosion depth × 60/25 = consumption rate (μm / hour) was determined, and the results are shown in Table 3-1.

Figure 0004517363
Figure 0004517363

Figure 0004517363
Figure 0004517363

表１〜表３−１に示される結果から、
（ａ）Ｓｉ化学蒸着膜を被覆した本発明Ｓｉ化学蒸着膜被覆単結晶シリコン電極板１〜２は、従来単結晶シリコン電極板に比べてパーティクルの発生が同等であり消耗速度が遅いこと、
（ｂ）本発明Ｓｉ化学蒸着膜被覆多結晶シリコン電極板１〜２は、従来多結晶シリコン電極板に比べてパーティクルの発生が格段に少なく消耗速度が遅いこと、
（ｃ）本発明Ｓｉ化学蒸着膜被覆柱状晶シリコン電極板１〜２は従来柱状晶シリコン電極板に比べてパーティクルの発生が格段に少なく消耗速度が遅いこと、などがわかる。 From the results shown in Tables 1 to 3-1,
(A) The present invention Si chemical vapor deposition film-coated single crystal silicon electrode plates 1 and 2 coated with a Si chemical vapor deposition film have the same generation of particles and a slower consumption rate than conventional single crystal silicon electrode plates.
(B) The present invention Si chemical vapor deposition film-coated polycrystalline silicon electrode plates 1 and 2 have significantly less generation of particles than the conventional polycrystalline silicon electrode plates, and the consumption rate is slow.
(C) It can be seen that the Si chemical vapor deposition film-coated columnar crystal silicon electrode plates 1 and 2 of the present invention have much less generation of particles and a slower consumption rate than the conventional columnar crystal silicon electrode plates.

この発明のプラズマエッチング用シリコンシリコン電極板の断面説明図である。It is sectional explanatory drawing of the silicon-silicon electrode plate for plasma etching of this invention. この発明のプラズマエッチング用シリコンシリコン電極板の断面説明図である。It is sectional explanatory drawing of the silicon-silicon electrode plate for plasma etching of this invention. この発明のプラズマエッチング用シリコンシリコン電極板の断面説明図である。It is sectional explanatory drawing of the silicon-silicon electrode plate for plasma etching of this invention. 従来のプラズマエッチング装置の断面説明図である。It is sectional explanatory drawing of the conventional plasma etching apparatus.

符号の説明Explanation of symbols

１：真空容器、２：電極基板、３：架台、４：Ｓｉウエハ、５：貫通細孔、６：高周波電源、７：プラズマエッチングガス、８：下面、９：上面、１０：ブラズマ、１１：シリコンの化学蒸着膜、   1: vacuum container, 2: electrode substrate, 3: mount, 4: Si wafer, 5: through-hole, 6: high frequency power supply, 7: plasma etching gas, 8: lower surface, 9: upper surface, 10: plasma, 11: Chemical vapor deposition film of silicon,

Claims (4)

厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の少なくともウエハと相対向する面（以下、下面という）の全面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなることを特徴とするプラズマエッチング用シリコン電極板。 A silicon electrode substrate having through-holes parallel to the thickness direction is formed of ultrafine crystal grains having an average grain size of 1 μm or less on the entire surface (hereinafter referred to as a lower surface) opposite to the wafer. A silicon electrode plate for plasma etching, which is formed by coating a chemical vapor deposition film. 厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の少なくとも下面の全面および前記貫通細孔内面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなることを特徴とするプラズマエッチング用シリコン電極板。 A silicon chemical vapor deposition film made of ultrafine crystal grains having an average grain size of 1 μm or less is coated on at least the entire lower surface of the silicon electrode substrate provided with through pores parallel to the thickness direction and the inner surface of the through pores. A silicon electrode plate for plasma etching, characterized by comprising: 厚さ方向に平行に貫通細孔が設けられているシリコン電極基板の表面全面および前記貫通細孔内面に、平均粒径が１μｍ以下の超微細結晶粒からなるシリコンの化学蒸着膜を被覆してなることを特徴とするプラズマエッチング用シリコン電極板。 A silicon chemical vapor deposition film composed of ultrafine crystal grains having an average grain size of 1 μm or less is coated on the entire surface of the silicon electrode substrate provided with through pores parallel to the thickness direction and the inner surface of the through pores. A silicon electrode plate for plasma etching, characterized in that 前記シリコン電極基板は、単結晶シリコン、多結晶シリコンおよび柱状晶シリコンの内のいずれかからなることを特徴とする請求項１、２、３のいずれか一項に記載のプラズマエッチング用シリコン電極板。 The silicon electrode substrate is a single crystal silicon, polycrystalline silicon and columnar crystal silicon electrode plate for plasma etching according to any one of claims 1, 2, 3, characterized in that it consists of any of the silicon .
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