JP4511148B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which disconnection and deterioration of step coverage are prevented and which has a BGA of high reliability. <P>SOLUTION: An extended pad electrode 11 formed on the front surface of a silicon chip 10A and a rewiring layer 21 formed on the rear surface of the silicon chip 10A are mutually connected. The both are connected electrically by a columnar terminal which is embedded in a via hole 17. The via hole 17 is formed piercing the silicon chip 10A from its back side so as to reach the extended pad electrode 11. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a BGA (Ball Grid Array) type semiconductor device in which a plurality of ball-shaped conductive terminals are arranged.

In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and as a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.
Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 30 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 30A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 30B is a perspective view of the back side of this BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. On one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101, a plurality of ball-like terminals 106 are arranged in a lattice shape. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. Aluminum wires drawn from the inside of the semiconductor chip 104 are connected to the plurality of second wirings 110, and the respective ball terminals 106 and the semiconductor chip 104 are electrically connected.

  The cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 31 shows a cross-sectional view of a BGA type semiconductor device 101 divided into individual chips along a dicing line. A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 with a resin 105a. The back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 with a resin 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-like conductive terminal 106 is formed on the second wiring extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
Patent Publication 2002-512436

  However, in the above-described BGA type semiconductor device 101, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the first wiring 107.

Therefore, the present invention can suppress the occurrence of disconnection as in the prior art by providing a via hole reaching the pad electrode from the back surface side of the semiconductor chip and embedding a columnar terminal in the via hole . In addition, the bump electrode is formed on the columnar terminal to obtain an electrical connection between the pad electrode and the bump electrode.

Further, according to the present invention, when a pad electrode of a semiconductor chip is connected to a wiring layer extending on the back surface of the semiconductor chip and a bump electrode is formed on the wiring layer , the pad electrode is formed from the back surface side of the semiconductor chip. A reaching via hole was provided, and the electrical connection between the two was obtained by a columnar terminal embedded in the via hole.

  According to the present invention, it is possible to prevent disconnection of wiring from the pad electrode of the semiconductor chip to the bump electrode on the back surface thereof and deterioration of step coverage, and to obtain a semiconductor device having a highly reliable BGA. In addition, according to the present invention, various integrated circuit chips can be mounted on the mounting substrate at a high density. In particular, by applying to an integrated circuit chip of a CCD image sensor, the integrated circuit chip can be mounted on a small mounting substrate of a small portable electronic device such as a mobile phone.

  Next, the best mode for carrying out the present invention (hereinafter referred to as the present embodiment) will be described with reference to the drawings.

  A first embodiment of the present invention will be described in detail with reference to the drawings. First, the structure of this semiconductor device will be described with reference to FIG. 8A is a plan view of the periphery of the dicing line viewed from the back surface of the silicon chip 10A, and FIG. 8B is a cross-sectional view taken along line XX of FIG. 8A. This semiconductor device shows a state in which a silicon wafer that has undergone a process described later is divided into a plurality of chips along a dicing line (chips divided into two in the figure).

  The silicon chip 10A is, for example, a CCD image sensor chip, and an extension pad electrode 11 is formed on the surface thereof. The extended pad electrode 11 is obtained by extending a pad electrode used for normal wire bonding to a dicing line region. The surface of the extension pad electrode 11 is covered with a passivation film such as a silicon nitride film (not shown). A transparent glass substrate 13 as a support substrate is bonded to the surface of the silicon chip 10A on which the extension pad electrode 11 is formed via a resin layer 12 made of, for example, an epoxy resin.

  A via hole 17 reaching the extension pad electrode 11 from the back surface of the silicon chip 10A is opened, and a columnar terminal 20 made of a conductive material such as copper (Cu) is formed so as to be embedded in the via hole 17. . The columnar terminal 20 is electrically connected to the extension pad electrode 11. Further, the columnar terminals 20 and the silicon chip 10 </ b> A are insulated by an insulating layer 30 provided on the side wall of the via hole 17.

  A rewiring layer 21 extends from the columnar terminal 20 on the back surface of the silicon chip 10A. Further, a solder mask 22 is deposited on the rewiring, and a solder bump 23 (bump electrode) is mounted on the opening. Has been. By forming a plurality of solder bumps 23 at desired positions, a BGA structure can be obtained. In this way, wiring from the extended pad electrode 11 of the silicon chip 10A to the solder bump 23 formed on the back surface thereof becomes possible. Since the present invention performs wiring using the columnar terminals 20 embedded in the via holes 17, disconnection hardly occurs and step coverage is excellent. Furthermore, the mechanical strength of the wiring is also high.

  The buffer member 16 may be provided on the back surface of the silicon chip 10 </ b> A so as to correspond to the formation position of the solder bump 23. This is to earn the height of the solder bump 23. This prevents the solder bump 23 and the silicon chip 10 </ b> A from being damaged by the stress generated by the difference in thermal expansion coefficient between the printed board and the solder bump 23 when the semiconductor device is mounted on the printed board. The buffer member 16 may be formed of, for example, a resist material or an organic film, or may be formed of a metal such as copper (Cu).

  Further, the via hole 17 is opened straight as shown in FIG. 8, but the present invention is not limited to this, and as shown in FIG. 9, the cross section of the via hole 17 has a tapered shape that becomes narrower as it gets deeper from the surface. Also good. 9A is a plan view around the dicing line of the silicon wafer, and FIG. 9B is a cross-sectional view taken along the line XX of FIG. 9A. As a result, when the columnar terminal 20 is formed by a plating method as will be described later, there is an advantage that the seeding layer 18 for plating can be formed by sputtering.

  Next, a method for manufacturing this semiconductor device will be described. As shown in FIG. 1, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the surface of the silicon wafer 10. The above-described extension pad electrode 11 is formed on the surface of the silicon wafer 10. The extension pad electrode 11 is made of a metal such as aluminum, an aluminum alloy, or copper, and has a thickness of 1 μm.

  Next, as shown in FIG. 2, for example, a resin layer 12 made of an epoxy resin is applied. Then, as shown in FIG. 3, the glass substrate 13 is bonded to the surface of the silicon wafer 10 through the resin layer 12. The glass substrate 13 functions as a protector or support for the silicon wafer 10. And in the state which this glass substrate 13 adhered, the back surface grinding | polishing of the silicon wafer 10, so-called back grinding, is performed, and the thickness is processed into 100 micrometers. The polished surface may be shaped by chemical etching after mechanical polishing. Further, only wet or dry etching may be performed without polishing.

  Then, as shown in FIG. 4, a buffer member 16 is formed on the back surface of the back-ground silicon wafer 10. The buffer member 16 is formed corresponding to the formation position of the solder bump 23. The buffer member 16 is preferably formed of a resist material or an organic film, for example. The buffer member 16 may be formed as necessary, and may be omitted if it is not necessary depending on the application of the semiconductor device.

  Then, a via hole 17 that penetrates the silicon wafer 10 and reaches the surface of the extension pad electrode 11 is formed. The depth of the via hole 17 is 100 μm. The width is, for example, 40 μm, and the length is 200 μm. In order to form the via hole 17, there are a method of making a hole in the silicon wafer 10 using a laser beam, and a method of making a hole using a wet etching method or a dry etching method. The via hole 17 may be processed into a tapered shape as shown in FIG. 9 by controlling the laser beam.

  Next, a process of forming the columnar terminals 20 and the rewiring layer 21 will be described. As shown in FIG. 5, first, an insulating layer 30 having a thickness of about 100 nm is formed on the entire surface including the inside of the via hole 17 by plasma CVD. This is because the columnar terminals 20 and the silicon wafer 10 are insulated. Since the insulating layer 30 is also formed at the bottom of the via hole 17, this portion of the insulating layer 30 is removed by etching to expose the surface of the extension pad electrode 11 again.

  Next, a seed layer 18 made of copper (Cu) is formed on the entire surface by electroless plating. The seed layer 18 becomes a seed (seed) for plating growth at the time of electrolytic plating described later. Its thickness may be 1 μm. As described above, when the via hole 17 is processed into a tapered shape, a sputtering method can be used for the seed layer 18.

  Then, before electrolytic plating of copper (Cu) is performed, a resist layer 19 is formed in a region where plating is not formed. The formation region of the resist layer 19 is a region painted in gray in the plan view of FIG. That is, it is an area excluding the columnar terminal 20, the rewiring layer 21, and the solder bump formation area.

  Then, electrolytic plating of copper (Cu) is performed to form the columnar terminals 20 and the rewiring layer 21 at the same time. The columnar terminal 20 is electrically connected to the extension pad electrode 11 via the seed layer 18. Although this method is good for reducing the number of processes, the plating thickness of the rewiring layer 21 and the plating thickness grown on the via hole 17 cannot be controlled independently, so that there is a disadvantage that both cannot be optimized.

  Therefore, the columnar terminals 20 may be formed by electrolytic plating, and the rewiring layer 21 may be formed by an Al sputtering method. Thereafter, a barrier metal (not shown) such as Ni / Au is formed on the rewiring layer 21 by sputtering. This is to improve the electrical connection between the rewiring layer 21 and the solder bump 23.

  Then, as shown in FIG. 7, the resist layer 19 is removed. Further, the seed layer 18 remaining under the resist layer 19 is removed by etching using the rewiring layer 21 as a mask. At this time, the rewiring layer 21 is also etched, but there is no problem because the rewiring layer 21 is thicker than the sheath layer 18.

  Next, as shown in FIG. 8, a solder mask 22 is deposited on the rewiring layer 21, solder is printed on a predetermined region of the rewiring layer 21 by using a screen printing method, and the solder is reflowed by heat treatment. As a result, the solder bumps 23 are formed. Note that a desired number of rewiring layers 21 can be formed in a desired region on the back surface of the silicon wafer 10, and the number and formation regions of the solder bumps 23 can be freely selected.

  Then, the silicon wafer 10 is divided into a plurality of silicon chips 10A along the dicing line. In this dicing process, a laser beam can be used. Moreover, in the dicing process using a laser beam, the glass substrate 13 can be prevented from cracking by processing the cut surface of the glass substrate 13 to be tapered.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. First, the structure of this semiconductor device will be described with reference to FIG. 18A is a plan view around the dicing line region of the silicon wafer as viewed from the second glass substrate 215 side, and FIG. 18B is a cross-sectional view taken along line XX in FIG. 18A. It is. This semiconductor device shows a state in which a silicon wafer that has undergone a process described later is divided into a plurality of chips along a dicing line region (chips divided into two in the figure).

  The silicon chip 210A is, for example, a CCD image sensor chip, and an extension pad electrode 211 is formed on the surface thereof. The extended pad electrode 211 is obtained by extending a pad electrode used for normal wire bonding to a dicing line region. The surface of the extension pad electrode 211 is covered with a passivation film such as a silicon nitride film (not shown). A transparent first glass substrate 213 as a support substrate is bonded to the surface of the silicon chip 210A on which the extension pad electrode 211 is formed, via a resin layer 212 made of, for example, an epoxy resin.

  Further, a transparent second glass substrate 215 as a support substrate is bonded to the back surface of the silicon chip 210A via a resin layer 214 made of, for example, an epoxy resin. A via hole 217 reaching the extension pad electrode 211 is opened from the second glass substrate 215 side, and a columnar terminal 220 made of a conductive material such as copper (Cu) is formed so as to fill the via hole 217. ing. The columnar terminal 220 and the silicon chip 210 </ b> A are insulated by an insulating layer 230 provided on the side wall of the via hole 217.

  A rewiring layer 221 extends from the columnar terminal 220 onto the second glass substrate 215. Further, a solder mask 222 is deposited on the rewiring, and a solder bump 223 (bump electrode) is formed in the opening. It is installed. By forming a plurality of solder bumps 223 at desired positions, a BGA structure can be obtained. In this way, wiring from the extended pad electrode 211 of the silicon chip 210A to the solder bump 223 formed on the back surface thereof is possible. Since the present invention performs wiring using the columnar terminals 220 embedded in the via holes 217, disconnection is unlikely to occur and step coverage is excellent. Furthermore, the mechanical strength of the wiring is also high.

  Note that a buffer member 216 may be provided on the surface of the second glass substrate 215 in correspondence with the formation position of the solder bump 223. This is for increasing the height of the solder bump 223. This prevents the solder bump 223 and the second glass substrate 215 from being damaged by the stress generated by the difference in thermal expansion coefficient between the printed board and the solder bump 223 when the semiconductor device is mounted on the printed board. The buffer member 216 may be formed of, for example, a resist material or an organic film, or may be formed of a metal such as copper (Cu).

  In addition, the via hole 217 is opened straight as shown in FIG. 18, but the present invention is not limited to this, and as shown in FIG. 19, the cross section of the via hole 217 has a tapered shape that becomes thinner as it gets deeper from the surface. Also good. FIG. 19A is a plan view around the dicing line region of the silicon wafer, and FIG. 19B is a cross-sectional view taken along line XX in FIG. 19A. As a result, when the columnar terminal 220 is formed by a plating method as described later, there is an advantage that the seeding layer 218 for plating can be formed by sputtering.

  Next, a method for manufacturing this semiconductor device will be described. As shown in FIG. 10, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the surface of the silicon wafer 210. The above-described expansion pad electrode 211 is formed on the surface of the silicon wafer 210. The extension pad electrode 211 is made of a metal such as aluminum, an aluminum alloy, or copper, and has a thickness of 1 μm.

  Next, as shown in FIG. 11, a resin layer 212 made of, for example, an epoxy resin is applied. Then, as shown in FIG. 12, the first glass substrate 213 is bonded to the surface of the silicon wafer 210 via the resin layer 212. The first glass substrate 213 functions as a protector or support for the silicon wafer 210. Then, with the first glass substrate 213 bonded, the back surface of the silicon wafer 210 is polished, so-called back grinding, and the thickness is processed to 100 μm. The polished surface may be shaped by chemical etching after mechanical polishing. Further, only wet or dry etching may be performed without polishing.

  Next, as shown in FIG. 13, a resin layer 214 made of an epoxy resin is applied to the back surface of the silicon wafer 210. Then, the second glass substrate 215 is bonded to the back surface of the silicon wafer 210 using the resin layer 214. The thickness of the second glass substrate 215 is 100 μm. The second glass substrate 215 is bonded to support the main body and to prevent warping.

  Further, the buffer member 216 is formed on the bonded second glass substrate 215. The buffer member 216 is formed in correspondence with the position where the solder bump 223 is formed. The buffer member 216 may be formed of, for example, a resist material or an organic film, or may be formed of a metal such as copper (Cu) by a sputtering method. The buffer member 216 may be formed as necessary, and may be omitted if it is not necessary depending on the use of the semiconductor device.

  Next, as shown in FIG. 14, a via hole 217 that penetrates through the second glass substrate 215 and the silicon wafer 210 and reaches the surface of the extension pad electrode 211 is formed. The depth of the via hole 217 is 200 μm. The width is, for example, 40 μm, and the length is 200 μm.

  In order to form the deep via hole 217 through a plurality of layers having different materials, a method of making a hole in the silicon wafer 210 using a laser beam is suitable. This is because when a hole is formed using a wet etching method or a dry etching method, it is necessary to switch the etching gas for each different layer, which complicates the manufacturing process. The via hole 217 may be processed into a tapered shape as shown in FIG. 19 by controlling the laser beam.

  Next, the columnar terminal 220 and the rewiring layer 221 are formed. Since this step and the subsequent steps are exactly the same as those in the first embodiment, only the drawings are shown and description thereof is omitted (FIGS. 15 to 18).

  Next, a third embodiment of the present invention will be described in detail with reference to the drawings. First, the structure of this semiconductor device will be described with reference to FIG. FIG. 28A is a plan view of the periphery of the dicing line region of the silicon wafer as viewed from the second glass substrate 315 side, and FIG. 28B is a cross-sectional view taken along line XX in FIG. is there. This semiconductor device shows a state in which a silicon wafer that has undergone a process described later is divided into a plurality of chips along a dicing line region (chips divided into two in the figure).

  The silicon chip 310A is, for example, a CCD image sensor chip, and an extension pad electrode 311 is formed on the surface thereof. The extended pad electrode 311 is obtained by extending a pad electrode used for normal wire bonding to a dicing line region. The surface of the extension pad electrode 311 is covered with a passivation film such as a silicon nitride film (not shown). A transparent first glass substrate 313 is bonded to the surface of the silicon chip 310A on which the extension pad electrode 311 is formed via a resin layer 312 made of, for example, an epoxy resin.

  Further, the side surface of the silicon chip 310A and a part of the extended pad electrode 311 are covered with a resin layer 314 made of, for example, an epoxy resin. Then, using this resin layer 314, a transparent second glass substrate 315 is bonded to the back surface of the silicon chip 310A.

A via hole 317 reaching the extension pad electrode 311 is opened from the second glass substrate 315 side, and a columnar terminal 320 made of a conductive material such as copper (Cu) is formed so as to be embedded in the via hole 317. ing. A rewiring layer 321 extends from the columnar terminal 320 onto the second glass substrate 315. Further, a solder mask 322 is deposited on the rewiring, and a solder bump 323 (bump electrode) is mounted on the opening. ing.
By forming a plurality of solder bumps 323 at desired positions, a BGA structure can be obtained. In this way, wiring from the extension pad electrode 311 of the silicon chip 310A to the solder bump 323 formed on the back surface thereof is possible. Since the present invention performs wiring using the columnar terminals 320 embedded in the via holes 317, disconnection hardly occurs and step coverage is also excellent. Furthermore, the mechanical strength of the wiring is also high.

  Note that a buffer member 316 may be provided on the surface of the second glass substrate 315 so as to correspond to the formation position of the solder bump 323. This is for increasing the height of the solder bump 323. This prevents the solder bump 323 and the second glass substrate 315 from being damaged by the stress generated by the difference in thermal expansion coefficient between the printed board and the solder bump 323 when the semiconductor device is mounted on the printed board. The buffer member 316 may be formed of, for example, a resist material or an organic film, or may be formed of a metal such as copper (Cu).

  The via hole 317 is opened straight as shown in FIG. 28. However, the present invention is not limited to this, and as shown in FIG. 29, the via hole 317 has a tapered shape in which the cross section becomes narrower as it gets deeper from the surface. Also good. FIG. 29A is a plan view around the dicing line region of the silicon wafer, and FIG. 29B is a cross-sectional view taken along line XX in FIG. 29A. Thereby, when the columnar terminal 320 is formed by a plating method as will be described later, there is an advantage that the seeding layer 318 for plating can be formed by sputtering.

  Next, a method for manufacturing this semiconductor device will be described. As shown in FIG. 20, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the surface of the silicon wafer 310. The above-described extension pad electrode 311 is formed on the surface of the silicon wafer 310. The extension pad electrode 311 is made of a metal such as aluminum, an aluminum alloy, or copper, and has a thickness of 1 μm.

  Next, as shown in FIG. 21, a first glass substrate 313 is bonded via a resin layer 312 made of, for example, an epoxy resin. The first glass substrate 313 functions as a protector or support for the silicon wafer 310. Then, with the first glass substrate 313 adhered, the back surface of the silicon wafer 310 is polished, so-called back grinding, and the thickness is processed to 100 μm. The polished surface may be shaped by chemical etching after mechanical polishing. Further, only wet or dry etching may be performed without polishing.

  Next, as shown in FIG. 22, the silicon wafer 310 in the dicing line region is partially etched away. That is, the silicon wafer 310 is etched so that one end of the extended pad electrode 311 is exposed. This etching is dry etching using a resist mask.

  Next, as shown in FIG. 23, a resin layer 314 made of an epoxy resin is applied to the back surface of the silicon wafer 310. Thus, the exposed portion of the extended pad electrode 311 and the side surface of the etched silicon wafer 310 are covered with the resin layer 314. Then, the second glass substrate 315 is bonded to the back surface of the silicon wafer 310 using the resin layer 314. The thickness of the second glass substrate 315 is 100 μm. The second glass substrate 315 is bonded to support the main body and to prevent warping.

  Further, a buffer member 316 is formed on the bonded second glass substrate 315. The buffer member 316 is formed in correspondence with the formation position of the solder bump 323. The buffer member 316 may be formed of, for example, a resist material or an organic film, or may be formed by sputtering a metal such as copper (Cu). The buffer member 316 may be formed as necessary, and may be omitted if it is not necessary depending on the use of the semiconductor device.

  Next, as shown in FIG. 24, a via hole 317 that penetrates the second glass substrate 315 and the resin layer 314 and reaches the surface of the extension pad electrode 311 is formed. The depth of the via hole 317 is 200 μm. The width is, for example, 40 μm, and the length is 200 μm. In order to form the deep via hole 317 through such a plurality of different layers, a method of making a hole in the silicon wafer 210 using a laser beam is suitable. This is because when a hole is formed using a wet etching method or a dry etching method, it is necessary to switch the etching gas for each different layer, which complicates the manufacturing process. The via hole 317 may be processed into a tapered shape as shown in FIG. 29 by controlling the laser beam.

  Next, in order to form the columnar terminals 320 and the rewiring layer 321, first, a seed layer 318 made of copper (Cu) is formed on the entire surface by electroless plating. Since this step and the subsequent steps are exactly the same as those in the first embodiment, only the drawings are shown and description thereof is omitted (FIGS. 25 to 28).

  In each of the above-described embodiments, the columnar terminal (20, 220 or 320) is formed in the via hole (17, 217 or 317) by electrolytic plating. However, the present invention is not limited to this, and other methods are used. May be formed. For example, a method of embedding a metal such as aluminum, an aluminum alloy, or copper (Cu) in the via hole by a CVD method or an MOCVD method can be given.

  In each embodiment described above, the solder bump (23, 223, or 323) is formed on the rewiring layer (21, 221 or 321). However, the present invention is not limited to this, and the columnar terminal (20 , 220 or 320) without forming a rewiring layer (21, 221 or 321), solder bumps (20, 220 or 320) on the columnar terminals (20, 220 or 320) embedded in the via holes (17, 217 or 317) 23, 223 or 323) may be formed.

  Furthermore, in each of the embodiments described above, the extended pad electrode (11, 211 or 311) formed by extending the pad electrode used for normal wire bonding to the dicing line region is formed. There is no limitation, and instead of the extended pad electrode (11, 211 or 311), a pad electrode used for normal wire bonding which is not extended to the dicing line region may be used as it is. In this case, the pad electrode may be aligned with the formation position of the via hole (17, 217 or 317), and the other steps are exactly the same.

   Furthermore, in each of the embodiments described above, the present invention is applied to a BGA type semiconductor device having bump electrodes on the back surface of the semiconductor chip. However, the present invention is not limited to this, and bump electrodes are provided on the back surface of the semiconductor chip. The present invention may be applied to a so-called LGA (Land Grid Array) type semiconductor device that does not have. In other words, the semiconductor in a state where the protective film (22, 222, 322) is formed on the surface of the rewiring layer (21, 221 or 321) and the solder bump 23 is not formed in the opening of the protective film (22, 222, 322). It constitutes a device.

  Further, without forming the rewiring layer (21, 221 or 321), a columnar terminal (20, 220 or 320) is formed in the via hole (17, 217 or 317), and this columnar terminal (20, 220 or 320). A semiconductor device in which a protective film (22, 222, 322) is formed such that the surface of the semiconductor device is exposed may be used.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is a figure explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is a figure explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure explaining the semiconductor device which concerns on the 3rd Embodiment of this invention, and its manufacturing method. It is a figure explaining the semiconductor device which concerns on the 3rd Embodiment of this invention, and its manufacturing method. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Claims (4)

Prepare a semiconductor substrate on which pad electrodes are formed,
Bonding a support substrate onto the semiconductor substrate on which the pad electrode is formed;
Forming a via hole reaching the surface of the pad electrode from the back surface of the semiconductor substrate to which the support substrate is bonded;
Forming a columnar terminal electrically connected to the surface of the pad electrode in the via hole;
Forming bump electrodes on the columnar terminals;
And a step of dividing the semiconductor substrate into a plurality of semiconductor chips after forming the bump electrodes. A step of forming a columnar terminal electrically connected to the pad electrode in the via hole and forming a wiring layer extending from the columnar terminal to the back surface of the semiconductor substrate is performed by a plating method. A method for manufacturing a semiconductor device according to claim 1. The method of manufacturing a semiconductor device according to claim 1, wherein the via hole is processed into a tapered shape. A step of forming a columnar terminal electrically connected to the pad electrode in the via hole is performed by a plating method, and a step of forming a wiring layer extending from the columnar terminal to the back surface of the semiconductor substrate is performed by a sputtering method. The method of manufacturing a semiconductor device according to claim 2.

Images