JP4584677B2 - Power supply circuit, semiconductor device - Google Patents

Description

  The present invention relates to a power supply circuit and a semiconductor device used for a device having a low standby function.

  With the progress of miniaturization of elements of a semiconductor integrated circuit, the power supply voltage is decreasing. FIG. 1 of Patent Document 1 discloses a step-down circuit for generating a power supply voltage for such a circuit.

  In this circuit, when Vout> Vref, since the transistor M2 is turned off, a positive voltage is supplied from the node of the power supply voltage Vdd to the gate of the transistor M3 through the transistor M1, and the transistor M3 is turned off. In this case, no current is supplied to the node of the voltage Vout.

When Vout <Vref, the transistor M2 is turned on and the gate voltage of the transistor M3 is lowered. When the gate voltage becomes lower than the power supply voltage Vdd by the absolute value of the threshold voltage of the P-channel transistor M3, the transistor M3 is turned on. In this case, a current is supplied to the node of the voltage Vout through the transistor M3, and the node is stabilized in that the load current Iout and the current flowing through the transistor M3 are balanced. At this time, the output voltage Vout substantially matches the reference voltage Vref. Through the operation described above, the output voltage Vout is set to a step-down setting so as to be substantially the same value as the reference voltage Vref, which is lower than the power supply voltage Vdd, and can operate with low current consumption. It is said.
JP 2001-257315 A

  In the circuit of FIG. 1 of Patent Document 1, the voltage applied to the gate of the transistor M2 is a voltage corresponding to the reference voltage Vref that is the target value of the output voltage Vout + the threshold voltage Vth of the transistor M2. This voltage is a voltage added to the reference voltage Vref by a transistor (not shown) or the like in order to compensate the threshold voltage Vth of the transistor M2. When the amount of current flowing through the transistor and the amount of current flowing through the transistor M2 are different, a shift occurs between the threshold voltages Vth of both transistors. Therefore, the output voltage of the transistor M2 becomes unstable.

  In the above circuit, the amount of current flowing through the transistor M2 varies greatly depending on the magnitude of the load current Iout. That is, when the load current Iout is small or no load is applied, the transistor M1 that should function as a constant current source circuit is lifted up to the power supply voltage Vdd, and almost no current flows. On the other hand, when the load current Iout is large, the transistor M1 must function as a constant current source circuit, and the current also flows through the transistor M2. Thus, the output voltage Vout varies depending on the magnitude of the load current Iout.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a power supply circuit capable of supplying a stable output voltage with reduced dependency on load current.

  In order to solve the above problems, a power supply circuit according to an aspect of the present invention is a power supply circuit that steps down a predetermined fixed potential via an output transistor and supplies power to a predetermined load. A reference signal generation circuit is provided that outputs a reference signal obtained by adding a component corresponding to the step-down amount of the output transistor to the target value of the output voltage of the supply circuit to the control electrode of the output transistor. The reference signal generation circuit adaptively changes the reference signal with respect to fluctuations in the output current. The “predetermined fixed potential” may be a power supply voltage. The “reference signal” may be a voltage value or a current value. The “control electrode” may be a gate or a base. A capacitor for smoothing the “reference signal” and outputting it to the control electrode of the output transistor may be provided. The “reference signal generation circuit” may include a differential amplifier, and the differential amplifier amplifies a difference voltage between a voltage that provides a target value of the output voltage and an output voltage of the power supply circuit, and You may output to the electrode for control.

  According to this aspect, even if the load current fluctuates and the threshold voltage of the output transistor fluctuates, a stable output voltage can be supplied by adaptively changing the signal output to the output transistor.

  According to this aspect, even when the load current fluctuates and the threshold voltage of the output transistor fluctuates, a stable output voltage is supplied by adaptively changing the reference voltage output to the gate of the output transistor. Can do.

  The reference voltage generation circuit may include a compensation transistor for compensating for a voltage stepped down by the output transistor. The current flowing into the compensation transistor may be adaptively changed according to the change in the current flowing into the output transistor. The “compensation transistor” may boost the voltage that is the target value of the output voltage in accordance with the voltage that is stepped down by the output transistor. According to this aspect, the output voltage can be stabilized without consuming more current than necessary by changing the current flowing into the compensation transistor.

  The drive capability of the output transistor may be set higher than the drive capability of the compensation transistor. According to this aspect, the compensation transistor can generate the same gate voltage as the output transistor with a small current, and in particular, when the load current does not flow or is very small, the current consumption can be reduced.

  A first constant current source circuit connected between the fixed potential and the output transistor; a second constant current source circuit connected between the output transistor and the ground potential; and a first constant current source circuit connected between the fixed potential and the load. A current adjusting transistor provided in parallel with a series circuit including one constant current source circuit and an output transistor may be further provided. The current output of the current adjusting transistor may be controlled by the output voltage of the first constant current source circuit.

  According to this aspect, when the output voltage of the power supply circuit decreases, the current adjusting transistor supplies current to the load, and when the output voltage increases, the current to the load is stopped or reduced to further output the current. The voltage can be stabilized. Further, current consumption can be reduced without consuming more current than necessary.

  Yet another embodiment of the present invention is a semiconductor device. This apparatus includes the power supply circuit of the above-described aspect. According to this aspect, a semiconductor device including a power supply circuit that outputs a voltage with reduced dependency on the load current can be realized.

  It should be noted that any combination of the above-described constituent elements and a representation obtained by converting the expression of the present invention between apparatuses, methods, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, a stable output voltage with reduced dependency on load current can be supplied.

(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration of a power supply circuit 1 according to the first embodiment. The power supply circuit 1 includes a direct current stabilizing unit 10, a high frequency response unit 20, and a first capacitor 30. The direct current stabilizing unit 10 includes a reference voltage correction circuit 12. The reference voltage correction circuit 12 has a function of compensating the threshold voltage Vth of the first N-channel MOS transistor (hereinafter referred to as NMOS) 26 due to its internal configuration. The reference voltage correction circuit 12 can be composed of, for example, an operational amplifier. The target voltage Vref of the output voltage Vout of the power supply circuit 1 is input to the non-inverting input terminal of the operational amplifier.

  The output voltage Vout is input to the inverting input terminal of the operational amplifier. The operational amplifier amplifies the difference voltage between the two input terminals and outputs the amplified voltage to the gate of the first NMOS 26. The output voltage of the operational amplifier changes adaptively according to the fluctuation of the output voltage Vout of the high frequency response unit 20.

  The first capacitor 30 is provided between the output terminal of the operational amplifier and the ground. The first capacitor 30 is for preventing oscillation, and smoothes the output voltage of the operational amplifier and outputs it to the gate of the first NMOS 26. The power supply circuit 1 is a circuit that easily oscillates because the direct current stabilizing unit 10 and the high frequency response unit 20 also function as a regulator. Therefore, the first capacitor 30 may be a capacitor having a sufficiently large capacitance value so that oscillation can be absorbed. This capacitance value may be obtained by simulation or experiment.

  The high frequency response unit 20 includes a first constant current source circuit 22, a first P-channel MOS transistor (hereinafter referred to as PMOS) 24, a first NMOS 26, a second constant current source circuit 27, a resistor 28, and a second capacitor 29. Is provided. The input side of the first constant current source circuit 22 and the drain of the first PMOS 24 are connected to the power supply voltage Vdd line. The output side of the first constant current source circuit 22 is connected to the drain of the first NMOS 26 and the gate of the first PMOS 24. The source of the first NMOS 26 and the source of the first PMOS 24 are connected to the output voltage Vout line. A second constant current source circuit 27 is connected between the output voltage Vout line and the ground line, and a series circuit of a resistor 28 and a second capacitor 29 is connected in parallel thereto.

  Note that the first constant current source circuit 22 may use a PMOS or a depletion type PMOS. The first NMOS 26 and the second constant current source circuit 27 may use a depletion type NMOS. If these are used and a diode (not shown) is connected between the drain and source, a current can flow even when the source and gate voltages are equal. In addition, a constant current can be generated relatively easily. The series circuit of the resistor 28 and the second capacitor 29 compensates the phase and stabilizes the potential of the output voltage Vout line, and may be connected in either order.

  Hereinafter, the operation of the high frequency response unit 20 will be described. When the output voltage Vout is larger than the voltage input to the gate of the first NMOS 26, the first NMOS 26 is turned off, so that the power supply voltage Vdd is supplied to the gate of the first PMOS 24 via the first constant current source circuit 22, and the first PMOS 24 is turned off. To do. Then, no current is supplied to the load.

  When the output voltage Vout is smaller than the voltage input to the gate of the first NMOS 26, the first NMOS 26 is turned on and the gate voltage of the first PMOS 24 is lowered. When the gate voltage falls below the threshold voltage of the first PMOS 24 with respect to the power supply voltage Vdd, the first PMOS 24 is turned on. Then, a current is supplied to the load via the first PMOS 24, and the load is stabilized in that the output current Iout and the current flowing through the first PMOS 24 are balanced. At this time, the output voltage Vout is stepped down by the threshold voltage of the first NMOS 26 and substantially coincides with the target voltage Vref.

  In contrast to the high frequency response unit 20 that performs such a stable operation, when the output current Iout increases, the reference voltage correction circuit 12 decreases the reference voltage to be applied to the gate of the first NMOS 26, and the output current Iout is reduced. When the voltage falls, the operation is performed to increase the reference voltage to be applied to the gate of the first NMOS 26, and the output voltage Vout is further stabilized.

  FIG. 2 is a diagram illustrating characteristics of the output current Iout and the output voltage Vout of the power supply circuit 1 according to the first embodiment. The characteristic indicated by the solid line is the characteristic of the power supply circuit 1 in the first embodiment. Even when the output current Iout decreases, the substantially constant output voltage Vout is maintained. On the other hand, the characteristic indicated by the broken line is a characteristic of a circuit in which the voltage input to the gate of the first NMOS 26 is fixed without providing the DC stabilizing unit 10. That is, the output voltage Vout is stabilized only by the high frequency response unit 20. In this circuit, as the output current Iout decreases, the output voltage Vout increases and is not stable.

  As described above, according to the first embodiment, the voltage input to the gate of the first NMOS 26 is adaptively changed in accordance with the change in the output current Iout, so that the output independent of the output current Iout is obtained. A voltage Vout can be generated. In addition, the current consumption can be reduced without having to constantly pass a current through the transistors for boosting and stepping down. Furthermore, the dependence of the output current Iout on the frequency can be reduced. Furthermore, since the reference voltage is changed according to the change amount of the output current Iout, the phase change is small and the oscillation can be suppressed.

(Embodiment 2)
FIG. 3 is a diagram illustrating a configuration of the power supply circuit 2 according to the second embodiment. The power supply voltage Vdd line is connected to the drains of the second PMOS 42, the third PMOS 44 and the fourth PMOS 46. The drive capability of the fourth PMOS 46 is set to twice the drive capability of the third PMOS 44. The third constant current source circuit 40 supplies a starting current to the gates of the second PMOS 42, the third PMOS 44, and the fourth PMOS 46. This starting current is necessary only at the time of starting, and is not necessary after starting.

  The source of the second PMOS 42 is connected to the drain of the second NMOS 50, and the source of the second NMOS 50 is connected to the output voltage Vout line. A first load 70 and a fourth constant current source circuit 72 are connected in parallel between the output voltage Vout line and the ground line. The source of the fourth PMOS 46 is connected to the drain and gate of the pair of third NMOS 52 and fourth NMOS 54 and the gate of the second NMOS 50. The sources of the pair of third NMOS 52 and fourth NMOS 54 are connected to the drains of the pair of fifth NMOS 56 and sixth NMOS 58, respectively. The drive capabilities of these four NMOSs are set to be the same as the drive capability of the third PMOS 44. If the driving capability of each NMOS is the same as that of the third PMOS 44, the driving capability of the fourth PMOS 46 is set to be twice that of the third PMOS 44, so that it is necessary to receive the output current of the fourth PMOS 46 through two rows of current paths. is there. These two columns are set to have the same characteristics.

  A target voltage Vref serving as a target value for the output voltage Vout is input to the gate of the fifth NMOS 56. The gate of the sixth NMOS 58 forming the pair is connected to the source of the fourth NMOS 54. A common source of the pair of fifth NMOS 56 and sixth NMOS 58 is connected to the drain of the seventh NMOS 60.

  The source of the third PMOS 44 is connected to the drain of the eighth NMOS 62 that forms a pair with the seventh NMOS 60 and forms the current mirror circuit, and to the gates of the seventh NMOS 60 and the eighth NMOS 62. The drive capability of the eighth NMOS 62 is set to be the same as that of the third PMOS 44, and the drive capability of the seventh NMOS 60 is set to be twice that of the third PMOS 44. This corresponds to the relationship between the third PMOS 44 and the fourth PMOS 46.

Next, the operation of the power supply circuit 2 in the second embodiment will be described. First, considering a state in which no current flows through the first load 70 or no load, the current consumption Ist of the power supply circuit 2 is the idle current Iidle flowing through the fourth constant current source circuit 72 and the source current of the third PMOS 44. Ip2 is the sum of the source currents In3 flowing into the common source of the fifth NMOS 56 and the sixth NMOS 58.
That is,
Ist = Iidle + Ip2 + In3 (Formula 1)
It becomes.

The relationship between the drain current Id and the gate voltage Vgs of each transistor is
Id = β (W / L) (Vgs−Vth) ² (Formula 2)
Here, β is a predetermined coefficient. W is the gate width, L is the gate length, and (W / L) is the driving capability of the transistor. Vth is the threshold voltage of the transistor. If the drain current Id and the driving capability (W / L) of the transistor are made constant, the gate voltage Vgs becomes constant.

The output voltage Vout of the power supply circuit 2 is a value obtained by boosting the target voltage Vref by the gate voltage Vgs52 of the third NMOS 52 and reducing the target voltage Vref by the gate voltage Vgs50 of the second NMOS 50.
That is,
Vout = Vref + Vgs52−Vgs50 (Formula 3)
It becomes.

The drain current Id52 of the third NMOS 52 is
Id52 = β (W / L) (Vgs52−Vth) ² (Formula 4)
The drain current Id50 of the second NMOS 50 is assumed that the drive capability of the second NMOS 50 and the second PMOS 42 is set to m times that of the third PMOS 44.
Id50 = βm (W / L) (Vgs50−Vth) ² (Formula 5)
It becomes.

Id50 = mId52 = βm (W / L) (Vgs50−Vth) ² (Formula 6)
And
From (Expression 4) and (Expression 6), Vgs52 = Vgs50, and when this is substituted into (Expression 3), Vout = Vref. Here, by setting m to a large value, it is possible to reduce the current consumption Ist at no load in (Equation 1).

  As described above, according to the second embodiment, the drain current of the third NMOS 52 for compensating the gate voltage of the second NMOS 50 serving as the output transistor of the power supply circuit 2 is adapted according to the current flowing through the first load 70. The output voltage can be stabilized by changing the frequency. Furthermore, by setting a large ratio of the drain current of the second NMOS 50 and the drain current of the third NMOS 52, the current flowing through the second NMOS 50 can be reduced, and the current consumption of the entire power supply circuit 2 can be reduced. it can.

(Embodiment 3)
FIG. 4 is a diagram illustrating a configuration of the power supply circuit 3 according to the third embodiment. The power supply voltage Vdd line is connected to the drains of the fifth PMOS 80, the sixth PMOS 82, the seventh PMOS 84, and the eighth PMOS 86. The driving capabilities of these four PMOSs are set equal. The fifth PMOS 80 and the sixth PMOS 82 constitute a current mirror circuit, and the seventh PMOS 84 and the eighth PMOS 86 also constitute a current mirror circuit. The power supply voltage Vdd line is also connected to the drains of the sixth constant current source circuit 102 and the ninth PMOS 104.

  The source of the eighth PMOS 86 is connected to the drain and gate of the ninth NMOS 90, the gate of the fourteenth NMOS 112, and the gate of the fifteenth NMOS 106. The source of the ninth NMOS 90 is connected to the drain and gate of the eleventh NMOS 94. The eleventh NMOS 94 is paired with the tenth NMOS 92. The drain of the tenth NMOS 92 is connected to the source of the seventh PMOS 84, and the target voltage Vref serving as the target value of the output voltage Vout is input to the gate thereof. The driving capacities of the ninth NMOS 90, the tenth NMOS 92, the eleventh NMOS 94, and the fourteenth NMOS 112 are set equal, and the four PMOSs are also set equal.

  A common source of the tenth NMOS 92 and the eleventh NMOS 94 forming a pair is connected to the drain of the twelfth NMOS 96. The source of the fifth PMOS 80 is connected to the drain of the thirteenth NMOS 98. The fifth constant current source circuit 99 supplies a starting current to the gates of the twelfth NMOS 96 and the thirteenth NMOS 98 forming a pair. This starting current is also necessary only at the time of starting, and is unnecessary after starting. The driving capability of the thirteenth NMOS 98 is also set equal to that of the NMOS and PMOS described above. The driving capability of the twelfth NMOS 96 is set to be twice the driving capability of the thirteenth NMOS 98 because the common source current of the tenth NMOS 92 and the eleventh NMOS 94 forming a pair flows.

  The source of the sixth PMOS 82 is connected to the drain of the fourteenth NMOS 112, and the source of the fourteenth NMOS 112 is connected to the output voltage Vout line. The output of the sixth constant current source circuit 102 is connected to the gate of the ninth PMOS 104 and the drain of the fifteenth NMOS 106. A seventh constant current source circuit 108 and a second load 110 are connected in parallel between the output voltage Vout line and the ground line.

  Next, the operation of the power supply circuit 3 in the third embodiment will be described. First, the sixth constant current source circuit 102, the ninth PMOS 104, the fifteen NMOS 106, and the seventh constant current source circuit 108 are the same as the operation of the high frequency response unit 20 described in the first embodiment. Of course, as in the first embodiment, a series circuit of a resistor and a capacitor for phase compensation may be connected between the output voltage Vout line and the ground line.

The operation of the portion for generating the gate voltage of the fifteen NMOS 106 is basically the same as the operation of the portion for generating the gate voltage of the second NMOS 50 of the second embodiment. In other words, the output voltage Vout of the power supply circuit 3 is a value obtained by boosting the target voltage Vref by the gate voltage Vgs90 of the ninth NMOS 90 and by stepping down the gate voltage Vgs106 of the fifteenth NMOS 106.
That is,
Vout = Vref + Vgs90−Vgs106 (Expression 7)
It becomes.

  As in the second embodiment, Vgs90 = Vgs106 and Vout = Vref. Here, when the driving capability of the fifteenth NMOS 106 is set to m times that of the ninth NMOS 90, the current consumption Ist at no load can be reduced by setting this m to a large value.

  As described above, according to the third embodiment, the drain current of the ninth NMOS 90 for compensating the gate voltage of the fifteen NMOS 106 serving as the output transistor of the power supply circuit 3 is adapted according to the current flowing through the second load 110. The output voltage can be stabilized by changing the frequency. In addition, the output voltage can be further stabilized by providing a current path other than the output transistor that adjusts the amount of current flowing through the second load 110 in accordance with the fluctuation of the output voltage Vout. Furthermore, by setting a large ratio of the drain current of the ninth NMOS 90 and the drain current of the fifteenth NMOS 106, the current flowing through the ninth NMOS 90 can be reduced, and the current consumption of the entire power supply circuit 3 can be reduced. it can.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, a circuit configured with CMOS (Complementary Metal Oxide Semiconductor) has been described as an example, but may be configured with a TTL (Transistor-Transistor Logic) process using a bipolar transistor. In this case, the base current of the output transistor is adaptively changed according to the fluctuation of the output voltage Vout.

2 is a diagram illustrating a configuration of a power supply circuit in Embodiment 1. FIG. It is a figure which shows the characteristic of the output current Iout of the electric power supply circuit in Embodiment 1, and the output voltage Vout. It is a figure which shows the structure of the electric power supply circuit in Embodiment 2. FIG. It is a figure which shows the structure of the electric power supply circuit in Embodiment 3. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Power supply circuit, 10 DC stabilization part, 12 Reference voltage correction circuit, 20 High frequency response part, 22 1st constant current source circuit, 24 1st PMOS, 26 1st NMOS, 27 2nd constant current source circuit, 30 1st capacity | capacitance .

Claims (11)

A power supply circuit that steps down a predetermined fixed potential via an output transistor and supplies power to a predetermined load,
The target value of the output voltage of the power supply circuit, a reference for outputting a reference signal corresponding to the component is added to the voltage of the step-down between the control electrode and a main electrode of said output transistor, the control electrode of said output transistor A signal generation circuit,
The reference signal generation circuit includes a current path in which a current flowing in response to a change in a current flowing into the output transistor is adaptively changed.
By providing a compensation transistor for compensating the step-down amount of the output transistor in the current path, the reference signal is adaptively changed with respect to a change in current flowing into the output transistor. Power supply circuit. Power supply circuit according to claim 1, characterized in that the driving capability of the compensating transistor, to set lower than the driving capability of the output transistor. A first constant current source circuit connected between the fixed potential and the output transistor;
A second constant current source circuit connected between the output transistor and a ground potential;
A current adjustment transistor provided in parallel with the series circuit including the first constant current source circuit and the output transistor between the fixed potential and the load;
3. The power supply circuit according to claim 1, wherein the current adjustment transistor has a control electrode connected to a connection point between the output transistor and the first constant current source circuit. 4. A semiconductor device comprising: a power supply circuit according to any one of claims 1 to 3. A power supply circuit that steps down a predetermined fixed potential to a predetermined target voltage via an output transistor and outputs the voltage from a first main electrode of the output transistor,
A compensation transistor in which a first main electrode and a control electrode are connected to a control electrode of the output transistor;
A first transistor having a first main electrode connected to a second main electrode of the compensating transistor;
  A second transistor that is current-mirror connected to the first transistor and to which the target voltage is input to a control electrode;
The compensation transistor and the output transistor are connected to each other through a current mirror circuit, and the current flowing through the compensation transistor is adaptively changed according to a change in the current flowing through the output transistor. A power supply circuit. A first constant current circuit having one end connected to the fixed potential and the other end connected to a second main electrode of the output transistor;
A second constant current circuit having one end connected to the first main electrode of the output transistor and a ground connected to the other end;
A current adjusting transistor having a first main electrode connected to the fixed potential, a second main electrode connected to the first main electrode of the output transistor, and a control electrode connected to the other end of the first constant current circuit; The power supply circuit according to claim 5, further comprising: A third transistor having a first main electrode connected to the fixed potential, and a second main electrode connected to the first main electrode of the output transistor;
A fourth transistor constituting a current mirror circuit together with the third transistor;
A fifth transistor having a first main electrode connected to the second main electrode of the fourth transistor and a second main electrode connected to the ground;
6. The sixth transistor further comprising a sixth transistor that forms a current mirror circuit together with the fifth transistor, the first main electrode being connected to a connection point of the first transistor and the second transistor. The power supply circuit described. A first main electrode connected to the fixed potential, and a third transistor and a fourth transistor constituting a current mirror circuit;
An output stabilizing transistor in which a first main electrode and a control electrode are connected in common with the output transistor, and a second main electrode is connected to a second main electrode of the third transistor;
A fifth transistor having a first main electrode connected to the second main electrode of the fourth transistor and a second main electrode connected to the ground;
6. The sixth transistor further comprising a sixth transistor that forms a current mirror circuit together with the fifth transistor, the first main electrode being connected to a connection point of the first transistor and the second transistor. The power supply circuit described. The power supply circuit according to any one of claims 5 to 8, wherein a load having a variable size is connected to the first main electrode of the output transistor. 10. The power supply circuit according to claim 5, wherein the driving capability of the compensation transistor is set lower than the driving capability of the output transistor. 11. A semiconductor device comprising the power supply circuit according to claim 5.

Images