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JP4572627B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4572627B2
JP4572627B2 JP2004248844A JP2004248844A JP4572627B2 JP 4572627 B2 JP4572627 B2 JP 4572627B2 JP 2004248844 A JP2004248844 A JP 2004248844A JP 2004248844 A JP2004248844 A JP 2004248844A JP 4572627 B2 JP4572627 B2 JP 4572627B2
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resin layer
conductor
semiconductor device
solder
semiconductor chip
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JP2006066717A (en
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祐二 飯塚
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

本発明は、高周波用のスイッチングＩＣ，パワーデバイスなどに適用する半導体装置に関し、詳しくは半導体チップの主面に半田接合される相手側導電体の実装構造に係わる。   The present invention relates to a semiconductor device applied to a high-frequency switching IC, a power device, and the like, and more particularly to a mounting structure of a mating conductor that is solder-bonded to a main surface of a semiconductor chip.

まず、本発明の実施対象となる半導体装置の例として、パッケージ内に複数の半導体チップ（例えばＩＧＢＴ）を組み込んだパワースイッチングデバイスの組立構造を図４に示す。図において、１はヒートシンクとして放熱フィン１ａを備えた銅ベース、２は銅ベース１に搭載した絶縁基板（例えば、Direct Copper Bonding基板）、２ａは絶縁基板２の表裏両面に形成した導体パターン（銅箔）、３は絶縁基板２にマウントして導体パターン２ａに接合した半導体チップ、４は半導体チップ３の表面電極（主面）に接合した接続リード片（導体片）、５は外囲ケース、６は外囲ケース５を貫通して前記リード片４から外部に引き出した外部導出リードであり、絶縁基板２の導体パターン２ａおよび接続リード片４は半導体チップ３の主面に重ね合わせてその電極との間が半田接合されている。
一方、最近では環境問題から半田の鉛フリー化対策が進められており、Ｐｂ系の半田材に替えてＳｎ−Ａｇ系などのＳｎリッチな半田材が採用されるような傾向にある。 First, FIG. 4 shows an assembly structure of a power switching device in which a plurality of semiconductor chips (for example, IGBTs) are incorporated in a package as an example of a semiconductor device to be implemented by the present invention. In the figure, 1 is a copper base provided with heat radiation fins 1a as a heat sink, 2 is an insulating substrate (for example, Direct Copper Bonding substrate) mounted on the copper base 1, and 2a is a conductor pattern (copper copper) formed on both front and back surfaces of the insulating substrate 2. Foil), 3 is a semiconductor chip mounted on the insulating substrate 2 and joined to the conductor pattern 2a, 4 is a connection lead piece (conductor piece) joined to the surface electrode (main surface) of the semiconductor chip 3, and 5 is an enclosing case, Reference numeral 6 denotes an external lead that passes through the outer case 5 and is drawn out from the lead piece 4. The conductor pattern 2 a of the insulating substrate 2 and the connection lead piece 4 are superimposed on the main surface of the semiconductor chip 3 and the electrodes. Are soldered together.
On the other hand, recently, countermeasures for lead-free solder have been promoted due to environmental problems, and there is a tendency that Sn-rich solder material such as Sn-Ag type is adopted instead of Pb type solder material.

ところで、Ｓｎリッチな半田は、Ｐｂ系の半田と比べて接合性，耐久性の面で次記のような問題点がある。すなわち、
（１）接合相手材，もしくは表面メッキ材との相互拡散により金属間化合物が生じて半田接合層の脆化が進行し易い。
（２）半田材の延性がＰｂ系半田材に比べて低く、ヒートサイクルにより繰り返し応力が加わると金属疲労の進行が早まって半田接合部にクラック，破断が発生する。
特に、パワーデバイスでは、実使用中に半田接合部に前記のようなクラック，破断が生じると、半導体デバイスとしての通電，放熱機能が低下して致命的なダメージとなる。
なお、半田接合部に生じる疲労クラック，破断の発生メカニズムは次記のように進行することが実験でも確認されている。すなわち、
（１）半田接合時に、主として母材からのアウトガスにより半田層内に微小なボイドが生成し、これが半田層の上側界面付近に移動して小さな気泡核を形成する。
（２）半田接合後の通電状態でヒートサイクルなどにより繰り返し応力が加わると、先記した脆性傾向の高い金属間化合物層付近に応力が集中してその直下の延性層が過大に歪み、半田接合の当初からこの付近に存在していた気泡核がさらに成長して大きなボイドを形成するようになる。
（３）この状態になると、ボイドとボイドとの間の肉薄な層部分に応力が集中して半田接合層内に微細な疲労クラックが発生し、これが合体して巨視的なクラックに成長し、ついには半田接合部の破断発生が確認されるようになる。 By the way, Sn-rich solder has the following problems in terms of bondability and durability as compared with Pb solder. That is,
(1) An intermetallic compound is generated by mutual diffusion with the bonding partner material or the surface plating material, and the solder bonding layer tends to become brittle.
(2) The ductility of the solder material is lower than that of the Pb-based solder material, and when a stress is repeatedly applied by the heat cycle, the progress of metal fatigue is accelerated and cracks and breaks occur in the solder joint.
In particular, in a power device, if cracks or breaks such as those described above occur in a solder joint during actual use, the energization and heat dissipation functions of the semiconductor device are reduced, causing fatal damage.
In addition, it has also been confirmed in experiments that the mechanism of fatigue cracks and fractures occurring in solder joints proceeds as follows. That is,
(1) At the time of solder joining, a minute void is generated in the solder layer mainly due to outgas from the base material, and this moves to the vicinity of the upper interface of the solder layer to form a small bubble nucleus.
(2) When repeated stress is applied by heat cycle etc. in the energized state after solder bonding, stress concentrates in the vicinity of the intermetallic compound layer having a high brittle tendency as described above, and the ductile layer directly below it is excessively distorted, and solder bonding. The bubble nuclei that existed in the vicinity from this beginning grow further to form large voids.
(3) In this state, stress concentrates on the thin layer portion between the voids and fine fatigue cracks are generated in the solder joint layer, which combine to grow into macroscopic cracks, Eventually, the breakage of the solder joint is confirmed.

したがって、半田の延性層内に疲労，クラックが発生するのを防いで半田接合部の耐久性，デバイスの信頼性向上を図るには、応力が集中し易い前記の金属間化合物層に加わる応力を如何にして低減させるかが問題解決の重要な課題となる。
一方、フリップチップ接続方式の半導体装置に関して、半導体チップのウエハ表面に形成したバンプ電極の直下面域に応力緩和層（樹脂層）を被覆形成した上で、この応力緩和層の表面に電極パッドとの配線，表面保護膜を施し、この半導体チップを回路基板に実装した半導体装置の通電時に、バンプに加わる熱的応力を前記樹脂層で吸収緩和するようにした構成のものが知られている（例えば、特許文献１参照）。
特開２００２−９３９４７号公報 Therefore, in order to prevent fatigue and cracks from occurring in the ductile layer of the solder and to improve the durability of the solder joint and the reliability of the device, the stress applied to the intermetallic compound layer on which the stress tends to concentrate is applied. How to reduce it is an important issue for problem solving.
On the other hand, regarding a flip-chip connection type semiconductor device, a stress relaxation layer (resin layer) is formed on the surface immediately below the bump electrode formed on the surface of the semiconductor chip wafer, and an electrode pad is formed on the surface of the stress relaxation layer. A structure is known in which a thermal stress applied to the bump is absorbed and relaxed by the resin layer when a semiconductor device in which the semiconductor chip is mounted on a circuit board is provided with the wiring and the surface protective film. For example, see Patent Document 1).
JP 2002-93947 A

ところで、前記特許文献１に開示されている半導体装置は、フリップチップ素子を対象としたものであって、応力緩和層を半導体チップのウエハ上面に形成し、その上にバンプ電極を配して半導体チップの電極パッドとの間を配線するようにしている。
しかしながら、図４に示した半導体装置のように、半導体チップ３の主面に絶縁基板２の導体パターン２ａおよび接続リード片４の導電体接合面を重ね合わせて直接半田接合した構造の半導体装置には、特許文献１の構成がそのまま適用できず、また半導体チップの製造工程も複雑化してコスト高となる。
本発明は上記の点に鑑みなされたものであり、半導体チップの主面に重ね合わせて半田接合される相手の導電体側に応力緩和機能を付与し、半導体チップとの通電性，放熱性を損なうことなく高い半田接合強度を確保して耐久性，信頼性の向上化を図った半導体装置を提供することを目的とする。 By the way, the semiconductor device disclosed in Patent Document 1 is intended for flip chip elements, in which a stress relaxation layer is formed on a wafer upper surface of a semiconductor chip, and a bump electrode is disposed on the semiconductor chip. Wiring is made between the electrode pads of the chip.
However, as in the semiconductor device shown in FIG. 4, the semiconductor device has a structure in which the conductor pattern 2 a of the insulating substrate 2 and the conductor bonding surface of the connection lead piece 4 are superimposed on the main surface of the semiconductor chip 3 and directly soldered. However, the configuration of Patent Document 1 cannot be applied as it is, and the manufacturing process of the semiconductor chip is complicated and the cost is increased.
The present invention has been made in view of the above points, and imparts a stress relaxation function to the other conductor side to be soldered while being superimposed on the main surface of the semiconductor chip, thereby impairing the conductivity and heat dissipation with the semiconductor chip. An object of the present invention is to provide a semiconductor device in which high solder joint strength is ensured and durability and reliability are improved.

上記目的を達成するために、本発明によれば、半導体チップの主面に接合面を重ね合わせて導電体が半田接合された半導体装置において、
半導体チップの主面に対向する導電体接合面の一部領域に応力緩和用の樹脂層を被覆形成し、かつ該樹脂層の表面を含めて導電体の接合面に金属メッキ層を成層した上で半導体チップに半田接合するものとし（請求項１）、具体的には次記のような態様で構成する。
（１）前記の樹脂層を、半導体チップと対峙する接合面の中央面域を除く外周面域に被覆形成する（請求項２）。
（２）前項（１）において、導電体の接合面外周域に面取りを施した上で、その面取り面に樹脂層を被覆形成する（請求項３）。
（３）前記の絶縁層について、導電体の周縁に向けて樹脂層の層厚が厚くなるよう設定する（請求項４）。
（４）前記の樹脂層を、金属フィラーを含む導電性樹脂で形成する（請求項５）。
（５）導電体の半田接合面域を取り囲んで、半田接合面域の輪郭の外周に沿って樹脂層の露出面を形成する（請求項６）。
（６）樹脂層に半導体チップの位置決め用突起を形成する（請求項７）。 In order to achieve the above object, according to the present invention, in a semiconductor device in which a conductor is solder bonded by superimposing a bonding surface on a main surface of a semiconductor chip,
A resin layer for stress relaxation is formed on a part of the conductor bonding surface facing the main surface of the semiconductor chip, and a metal plating layer is formed on the bonding surface of the conductor including the surface of the resin layer. Thus, the semiconductor chip is solder-bonded (Claim 1), and specifically, configured as follows.
(1) The resin layer is coated on the outer peripheral surface area excluding the central surface area of the joint surface facing the semiconductor chip (claim 2).
(2) In the preceding item (1), after chamfering the outer peripheral area of the joint surface of the conductor, a resin layer is formed on the chamfered surface (Claim 3).
(3) About the said insulating layer, it sets so that the layer thickness of a resin layer may become thick toward the periphery of a conductor (Claim 4).
(4) The resin layer is formed of a conductive resin containing a metal filler.
(5) The exposed surface of the resin layer is formed along the outer periphery of the outline of the solder joint surface region so as to surround the solder joint surface region of the conductor.
(6) A semiconductor chip positioning protrusion is formed on the resin layer.

上記の構成によれば、半導体チップの接続形態に制約されることなく、半導体チップの主面に導電体（図４における絶縁基板２の導体パターン，あるいは接続リード片４）の接合面を重ね合わせて直接半田接合した構造の半導体装置で、実使用時のヒートサイクルにより半田接合部に加わる応力は導電体側の接合面一部領域に被覆形成した低剛性の樹脂層に吸収緩和され、これにより半田層の疲労クラック，破断の発生を効果的に防ぐことができる。しかも、樹脂層を含めて導電体の接合面の表面にメッキ層を施しておくことで、半導体チップとの間の通電性，放熱性を損なうことなく、高い半田接合性を確保できる。
また、この場合に発熱源となる半導体チップは主面の中央部が高温で、外周縁にいくほど低温となる傾向を示し、またヒートサイクルにより半田接合部に加わる応力は接合部の周縁エッジ部分に集中することが知られている。かかる点、樹脂層を導電体の接合面中央部分を除く外周域に形成し、さらにこの樹脂層については金属フィラーを含む導電性樹脂を採用することで、高い通電性，放熱性を確保しつつ半田接合部に加わる応力を効果的に緩和でき、さらに導電体の周域に面取りを施した上で、ここに被覆する樹脂層についても導電体の周縁に向けて樹脂層の層厚が厚くなるよう設定することで、応力緩和効果がより一層高まる。 According to the above configuration, the bonding surface of the conductor (the conductor pattern of the insulating substrate 2 or the connection lead piece 4 in FIG. 4) is superimposed on the main surface of the semiconductor chip without being restricted by the connection form of the semiconductor chip. In a semiconductor device with a direct solder joint structure, the stress applied to the solder joint due to the heat cycle during actual use is absorbed and relaxed by the low-rigidity resin layer that covers the part of the joint surface on the conductor side. It is possible to effectively prevent the occurrence of fatigue cracks and fractures in the layer. In addition, by providing a plated layer on the surface of the bonding surface of the conductor including the resin layer, high solder bonding properties can be ensured without impairing the electrical conductivity and heat dissipation between the semiconductor chips.
Further, in this case, the semiconductor chip that is a heat source has a high temperature at the center of the main surface and tends to become low as it goes to the outer periphery, and the stress applied to the solder joint by the heat cycle is the peripheral edge of the joint It is known to concentrate on. In this respect, the resin layer is formed in the outer peripheral area excluding the central portion of the joint surface of the conductor, and the resin layer is made of a conductive resin containing a metal filler, thereby ensuring high electrical conductivity and heat dissipation. The stress applied to the solder joint can be effectively relieved, and the thickness of the resin layer becomes thicker toward the periphery of the conductor even after chamfering the peripheral area of the conductor. By setting so, the stress relaxation effect is further enhanced.

また、半導体チップをマウントする側の導電体（図４における絶縁基板２の導電パターン２ａ）について、半導体チップとの半田接合面域を取り囲んで、半田接合面域の輪郭の外周に沿って樹脂層の露出面を形成してこの部分のメッキ層を欠如しておくことにより、半田接合時には前記樹脂層の露出部分がバリアとなって半田が所定の接合面域を超えて不要に外側へ拡大するのを防ぐことができ、さらにこの樹脂層の露出部分に半導体チップの位置決め用突起を形成しておくことにより、半導体装置の組立工程で半導体チップを導電体の接合面に正しく位置合わせすることができる。 Further, for the conductor on the side where the semiconductor chip is mounted (the conductive pattern 2a of the insulating substrate 2 in FIG. 4), the resin layer surrounds the solder joint surface area with the semiconductor chip and extends along the outer periphery of the outline of the solder joint surface area. The exposed portion of the resin layer is formed and the plating layer of this portion is absent, so that the exposed portion of the resin layer becomes a barrier during solder joining, and the solder unnecessarily expands beyond a predetermined joint surface area. In addition, by forming a semiconductor chip positioning protrusion on the exposed portion of the resin layer, the semiconductor chip can be correctly aligned with the bonding surface of the conductor in the assembly process of the semiconductor device. it can.

以下、図４の半導体装置に適用した本発明の実施の形態を図１〜図３に示す実施例に基づいて説明する。なお、実施例の図中で図４に対応する同一部材には同じ符号を付してその説明は省略する。   In the following, an embodiment of the present invention applied to the semiconductor device of FIG. 4 will be described based on the examples shown in FIGS. In addition, in the figure of an Example, the same code | symbol is attached | subjected to the same member corresponding to FIG. 4, and the description is abbreviate | omitted.

図１（ａ），（ｂ）は本発明の請求項１〜５に対応する実施例を示すものである。この実施例においては、半導体チップ３の主面に面接合される導電体としての絶縁基板２（図４参照）の導体パターン（銅箔）２ａ，および接続リード片（銅片）４の接合面には、応力緩和機能を付与する樹脂層７が被覆形成され、さらに該樹脂層７を含めて導電体の接合面にメッキ層８が成層されており、このメッキ層８を介して半導体チップ３の主面との間が半田層９で接合されている。
ここで、樹脂層７はＡｇ，Ａｇ−Ｐｄ，Ａｕ，Ｎｉ，Ｃｕなどの金属フィラーを含有する低剛性の導電性樹脂材が用いられており、接続リード片４の接合面に対しては、その周縁部分を面取りした上で、図1（ｂ）で表すように接合面の中央部域４ａを除いた外周面域に樹脂層７が被覆形成され、かつ樹脂層７の層厚はリード片の周縁に向けて厚くなるように設定している。なお、絶縁基板の導体パターン２ａについても、その接合面には図１ａと同様に樹脂層７がパターン形成されている。 1A and 1B show an embodiment corresponding to claims 1 to 5 of the present invention. In this embodiment, the conductor pattern (copper foil) 2a of the insulating substrate 2 (see FIG. 4) as a conductor to be surface bonded to the main surface of the semiconductor chip 3 and the bonding surface of the connection lead piece (copper piece) 4 Is coated with a resin layer 7 for imparting a stress relaxation function, and a plating layer 8 is formed on the bonding surface of the conductor including the resin layer 7, and the semiconductor chip 3 is interposed via the plating layer 8. The main surface is joined by a solder layer 9.
Here, the resin layer 7 is made of a low-rigidity conductive resin material containing a metal filler such as Ag, Ag-Pd, Au, Ni, or Cu. After chamfering the peripheral portion, as shown in FIG. 1 (b), a resin layer 7 is formed on the outer peripheral surface area excluding the central area 4a of the joint surface, and the layer thickness of the resin layer 7 is the lead piece. It is set to become thicker toward the periphery of the. As for the conductor pattern 2a of the insulating substrate, the resin layer 7 is patterned on the joint surface as in FIG. 1a.

この樹脂層７は所望の厚みに応じて次記の方法を選択して形成することができる。すなわち、厚みが例えば数μｍ〜数１０μｍ程度の樹脂層を形成するには、接続リード片４の接合面に樹脂層の形成パターンに応じてマスクした上で、熱硬化性樹脂，ＵＶ硬化性樹脂（例えばポリイミド）を膜状に塗布し、加熱，紫外線照射により硬化させて形成する。また、厚みが数１００μｍの樹脂層７を形成する場合には金型を使用し、熱硬化性樹脂を金型に注型した上で加熱硬化して形成する。
また、メッキ層８は膜厚３〜５μｍ程度のＮｉあるいはＮｉ−Ｐ膜であり、半田層９にはＳｎ−Ａｇ，Ｓｎ−Ｃｕ，Ｓｎ−Ａｇ−Ｃｕ，Ｓｎ−Ｚｎ系の鉛フリーな半田材が用いられている。なお、前記メッキ層８の表面に０．０５〜０．1μｍのＡｕ膜を成層すれば、下地層の酸化を防いで半田との良好な濡れ性を確保することができる。 The resin layer 7 can be formed by selecting the following method according to the desired thickness. That is, in order to form a resin layer having a thickness of, for example, about several μm to several tens of μm, the joint surface of the connection lead piece 4 is masked according to the resin layer formation pattern, and then a thermosetting resin or a UV curable resin (For example, polyimide) is applied in a film shape and cured by heating and irradiation with ultraviolet rays. Further, when forming the resin layer 7 having a thickness of several hundreds of μm, a mold is used, and a thermosetting resin is poured into the mold and then heated and cured.
The plated layer 8 is a Ni or Ni-P film having a thickness of about 3 to 5 μm, and the solder layer 9 is Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn based lead-free solder. The material is used. If an Au film having a thickness of 0.05 to 0.1 μm is formed on the surface of the plating layer 8, it is possible to prevent the underlying layer from being oxidized and to ensure good wettability with the solder.

そして、前記のように接合面に樹脂層７，メッキ層８を成層した導電体（導体パターン２ａ，接続リード片４）を図示のように半導体チップ３の主面に重ね合わせて半田接合した状態では、接合界面に生成されるＮｉ／Ｓｎ，Ｃｕ／Ｓｎ，Ｃｕ／Ｓｎ／Ｎｉなどの合金層（金属間化合物）の直下に剛性の低い樹脂層７が存在することから、その後の通電によるヒートサイクルに伴い脆性傾向の高い合金層付近に生じた応力が樹脂層７によって吸収緩和される。しかも、樹脂層７は応力が集中し易い導電体の周縁部分に選択的に形成されており、かつこの樹脂層７を含めて導電体の接合面全域がメッキ層８を介して半田接合されているので、半導体チップ３との間に高い通電性，放熱性と半田接合強度を確保しつつ、応力緩和機能を効果的に発揮させることができ、これにより半田接合部の疲労クラック，破断の発生を抑えて耐久性，信頼性が向上する。 Then, as described above, the conductor (conductor pattern 2a, connection lead piece 4) having the resin layer 7 and the plating layer 8 formed on the joint surface is superposed on the main surface of the semiconductor chip 3 and solder-joined as shown. Then, since the resin layer 7 having low rigidity exists immediately below the alloy layer (intermetallic compound) such as Ni / Sn, Cu / Sn, Cu / Sn / Ni generated at the bonding interface, The stress generated near the alloy layer having a high brittle tendency with the cycle is absorbed and relaxed by the resin layer 7. In addition, the resin layer 7 is selectively formed on the peripheral portion of the conductor where stress is likely to concentrate, and the entire bonding surface of the conductor including the resin layer 7 is soldered via the plating layer 8. As a result, the stress relaxation function can be effectively exerted while ensuring high electrical conductivity, heat dissipation, and solder joint strength between the semiconductor chip 3 and the occurrence of fatigue cracks and fractures in the solder joints. Improves durability and reliability.

次に、本発明の請求項６に係わる実施例を図２で説明する。この実施例においては、半導体チップ３の主面に半田接合される導電体としての絶縁基板の導体パターン２ａおよび接続リード片４に対して、その接合面には実施例１と同様に樹脂層７とメッキ層８を形成するとともに、特に半導体チップ３をマウントする導体パターン２ａについては、半導体チップ３との半田接合面域を取り囲むように、その輪郭の外周に沿ってこの部分のメッキ層８を欠如して樹脂層７が表面に露出するよう露出面７ａを形成している。
これにより、半田接合工程では前記の樹脂層露出面７ａがバリアとなって溶融半田の濡れが所定の半田接合面域から外側に広がるのを防ぎ、半田層９の広がりが図示のように露出面７ａの内側に納まって半導体チップ３が所定位置に半田接合されるようになる。 Next, an embodiment according to claim 6 of the present invention will be described with reference to FIG. In this embodiment, with respect to the conductor pattern 2a of the insulating substrate as the conductor to be soldered to the main surface of the semiconductor chip 3 and the connection lead piece 4, the resin layer 7 is provided on the bonding surface as in the first embodiment. and to form a plating layer 8, the conductor patterns 2a in particular mounting the semiconductor chip 3, so as to surround the solder joint surface area of the semiconductor chip 3, a plated layer 8 of this portion along the outer periphery of the outline The exposed surface 7a is formed so that the resin layer 7 is exposed on the surface.
Thus, in the soldering step, the resin layer exposed surface 7a serves as a barrier to prevent the molten solder from spreading outward from the predetermined soldering surface area, and the spread of the solder layer 9 is exposed as shown in the figure. The semiconductor chip 3 is placed inside 7a and soldered to a predetermined position.

図３は本発明の請求項７に対応する実施例を示すものである。この実施例においては、半導体チップ３を半田マウントする絶縁基板の導体パターン２ａについて、該導体パターンの半田接合面域の周縁部分に被覆形成した樹脂層７からメッキ層８を貫通して表面側に突き出す突起７ｂおよび７ｃが形成されている。ここで、突起７ｂは半導体チップ３の外周に沿った複数箇所に分散し、この突起７ｂの内側に半導体チップが納まるように位置に形成されている。一方、突起７ｃは半導体チップ３の半田接合面を支持するもので、前記突起７ｂよりも高さを低くしてその内側数箇所に分散して形成されている。なお、突起７ｃは突起７ｂに段差を設けて一体に形成してもよい。
また、接続リード片４側に形成した樹脂層７についても、前記突起７ｃと同様な突起７ｄを形成しておくことにより、この突起７ｄが支脚の役目を果たして半田接合の際に接続リード片４の半田接合面が傾くのを防ぐことができる。 FIG. 3 shows an embodiment corresponding to claim 7 of the present invention. In this embodiment, with respect to the conductor pattern 2a of the insulating substrate on which the semiconductor chip 3 is solder-mounted, the plating layer 8 is penetrated from the resin layer 7 formed on the periphery of the solder joint surface area of the conductor pattern to the surface side. Projecting protrusions 7b and 7c are formed. Here, the protrusions 7b are dispersed at a plurality of locations along the outer periphery of the semiconductor chip 3 , and are formed at positions so that the semiconductor chip is accommodated inside the protrusions 7b. On the other hand, the protrusions 7c support the solder joint surface of the semiconductor chip 3 , and are formed so as to be lower in height than the protrusions 7b and dispersed in several places inside thereof. The protrusion 7c may be integrally formed by providing a step on the protrusion 7b.
Further, the resin layer 7 formed on the connection lead piece 4 side is also provided with a projection 7d similar to the projection 7c, so that the projection 7d serves as a support leg and is connected to the connection lead piece 4 during soldering. It is possible to prevent the solder joint surface from tilting.

このように導体パターン２ａに形成した絶縁層７に位置決め用の突起７ｂを設けておくことにより、半導体装置の組立工程で絶縁基板（図４参照）に半導体チップ３を搭載して半田接合するする際に、前記突起７ｂを位置決めの基準として半導体チップを所定の半田接合位置定位置に正しく位置合わせすることができる。また、絶縁基板２に載置する半導体チップ３を基板側に形成した突起７ｃで支持することにより、半導体チップ３の半田接合面の傾きを抑制することができ、これによりチップ実装工程の作業性改善，および製造のばらつきを抑えて品質向上が図れる。
なお、前記の突起７ｂは、あらかじめ導体パターン２ａの表面に形成した樹脂層７の上にメッキ層８を選択的に成膜した上で、メッキ層の欠如部に熱硬化性樹脂を充填，硬化させ、最後にメッキ層の一部をエッチングにより除去して突起７ｂ，７ｃを形成することができる。また、突起７ｄについても同様な方法で形成できる。 Thus, by providing the positioning projection 7b on the insulating layer 7 formed on the conductor pattern 2a, the semiconductor chip 3 is mounted on the insulating substrate (see FIG. 4) and soldered in the assembly process of the semiconductor device. At this time, the semiconductor chip can be correctly aligned at a predetermined solder bonding position using the protrusion 7b as a positioning reference. Further, by supporting the semiconductor chip 3 placed on the insulating substrate 2 with the protrusions 7c formed on the substrate side, it is possible to suppress the inclination of the solder joint surface of the semiconductor chip 3 , thereby improving the workability of the chip mounting process. Improvement and quality improvement can be achieved while suppressing manufacturing variations.
The protrusion 7b is formed by selectively forming a plating layer 8 on the resin layer 7 previously formed on the surface of the conductor pattern 2a, and filling and curing the thermosetting resin in the lack of the plating layer. Finally, a part of the plating layer can be removed by etching to form the protrusions 7b and 7c. Further, the protrusion 7d can be formed by a similar method.

また、前記突起７ｃ，７ｄを形成することにより、半導体チップ３と接合相手部材との半田接合面の傾きを抑制しつつ、導体パターン２ａ，接続リード片４と半導体チップ３との間の半田層９を所望の厚みに保持して品質の安定化が図れる。 Further, by forming the protrusions 7c and 7d, the solder layer between the conductor pattern 2a, the connection lead piece 4 and the semiconductor chip 3 is suppressed while suppressing the inclination of the solder joint surface between the semiconductor chip 3 and the bonding partner member. 9 can be maintained at a desired thickness and quality can be stabilized.

本発明の実施例１に係わる半導体装置の要部構成図で、（ａ）は半導体チップと導電体との半田接合部の詳細構造を表す断面図、（ｂ）は（ａ）における接続リード片の接合面に被覆形成した樹脂層を模式的に表したパターン図BRIEF DESCRIPTION OF THE DRAWINGS It is principal part block diagram of the semiconductor device concerning Example 1 of this invention, (a) is sectional drawing showing the detailed structure of the solder joint part of a semiconductor chip and a conductor, (b) is a connection lead piece in (a) Pattern diagram schematically showing the resin layer coated on the joint surface 本発明の実施例２に係わる半田接合部の構造断面図Cross-sectional view of the structure of the solder joint according to the second embodiment of the present invention 本発明の実施例３に係わる半田接合部の構造断面図Sectional view of structure of solder joint according to embodiment 3 of the present invention 本発明の実施対象となる半導体装置全体の組立構造図Assembly structure diagram of entire semiconductor device to be implemented by the present invention

１ 銅ベース
２ 絶縁基板
２ａ 導体パターン
３ 半導体チップ
４ 接続リード片
７ 樹脂層
８ メッキ層
９ 半田層 DESCRIPTION OF SYMBOLS 1 Copper base 2 Insulating board 2a Conductor pattern 3 Semiconductor chip 4 Connection lead piece 7 Resin layer 8 Plating layer 9 Solder layer

Claims (7)

半導体チップの主面に接合面を重ね合わせて導電体が半田接合された半導体装置において、
半導体チップの主面に対向する導電体接合面の一部領域に応力緩和用の樹脂層を被覆形成し、かつ該樹脂層の表面を含めて導電体の接合面に金属メッキ層を成層した上で半導体チップに半田接合したことを特徴とする半導体装置。 In a semiconductor device in which a conductor is solder bonded by superimposing a bonding surface on a main surface of a semiconductor chip,
A resin layer for stress relaxation is formed on a part of the conductor bonding surface facing the main surface of the semiconductor chip, and a metal plating layer is formed on the bonding surface of the conductor including the surface of the resin layer. A semiconductor device characterized by being solder-bonded to a semiconductor chip. 請求項１記載の半導体装置において、樹脂層を導電体接合面の中央面域を除く外周面域に被覆形成したことを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the resin layer is coated on an outer peripheral surface area excluding a central surface area of the conductor bonding surface. 請求項２記載の半導体装置において、導電体の接合面外周周域に面取りを施した上で、その面取り面に樹脂層を被覆形成したことを特徴とする半導体装置。 3. The semiconductor device according to claim 2, wherein a chamfer is applied to the outer peripheral area of the joint surface of the conductor, and a resin layer is formed on the chamfered surface. 請求項２または３のいずれかの項に記載の半導体装置において、導電体の周縁に向けて樹脂層の層厚が厚くなるよう設定したことを特徴とする半導体装置。 4. The semiconductor device according to claim 2, wherein the thickness of the resin layer is set to increase toward the periphery of the conductor. 請求項１ないし４のいずれかの項に記載の半導体装置において、樹脂層が導電性樹脂であることを特徴とする半導体装置。 5. The semiconductor device according to claim 1, wherein the resin layer is a conductive resin. 請求項１ないし５のいずれかの項に記載の半導体装置において、導電体の半田接合面域を取り囲んで、半田接合面域の輪郭の外周に沿って樹脂層の露出面を形成したことを特徴とする半導体装置。 6. The semiconductor device according to claim 1, wherein an exposed surface of the resin layer is formed along an outer periphery of a contour of the solder joint surface region so as to surround the solder joint surface region of the conductor. A semiconductor device. 請求項６記載の半導体装置において、樹脂層に半導体チップの位置決め用突起を形成したことを特徴とする半導体装置。 7. The semiconductor device according to claim 6, wherein a semiconductor chip positioning protrusion is formed on the resin layer.
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JP2002093947A (en) * 2000-09-19 2002-03-29 Hitachi Ltd Semiconductor device, its manufacturing method and mounting structure of semiconductor device

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