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JP4571853B2 - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP4571853B2
JP4571853B2 JP2004360828A JP2004360828A JP4571853B2 JP 4571853 B2 JP4571853 B2 JP 4571853B2 JP 2004360828 A JP2004360828 A JP 2004360828A JP 2004360828 A JP2004360828 A JP 2004360828A JP 4571853 B2 JP4571853 B2 JP 4571853B2
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Prior art keywords
ceramic
layer
glass
substrate body
brazing material
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JP2006173222A (en
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和浩 浦島
達晴 井川
光雄 白石
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

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  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、ガラス−セラミックからなる基板本体の表面および裏面の少なくとも一方に形成したCuメタライズ層に導体ピンをロウ付けした配線基板に関する。   The present invention relates to a wiring board in which conductor pins are brazed to a Cu metallized layer formed on at least one of a front surface and a back surface of a substrate body made of glass-ceramic.

低誘電損失のガラス−セラミックからなる基板本体と、かかる基板本体の表面および裏面の少なくとも一方に形成した低抵抗のCuメタライズ層と、を含む配線基板は、高周波領域で使用される電子部品の実装用に好適である。更に、上記Cuメタライズ層に導体ピンをロウ付けすることで、MPUの実装用や、例えば光通信用素子を実装する光通信用の分野などに広く利用することができる。
ところで、例えばガラス−セラミックからなる基板本体の裏面に形成したCuメタライズ層に対し、低融点(約220℃)であるSn−Sb系のロウ材を介して、導体ピンをロウ付けすると、上記基板本体の表面に上記ロウ材よりも高融点のSn−Ag系合金を介して電子部品を実装する際のリフロー時に、上記ロウ材の軟化ないし溶融して上記導体ピンが倒れる、という問題があった。
しかも、基板本体のガラス−セラミックとCuメタライズ層との間では、密着性が低いため、基板本体の内部配線と上記メタライズ層との導電性が低下したり、上記メタライズ層が剥離して導体ピンが不用意に外れる、という問題もあった。
A wiring board including a low-dielectric loss glass-ceramic substrate body and a low-resistance Cu metallization layer formed on at least one of the front and back surfaces of the substrate body is mounted on an electronic component used in a high-frequency region. Suitable for use. Furthermore, by brazing a conductor pin to the Cu metallized layer, it can be widely used for mounting an MPU, for example, an optical communication field in which an optical communication element is mounted.
By the way, when the conductor pin is brazed to the Cu metallized layer formed on the back surface of the substrate body made of, for example, glass-ceramic via a Sn—Sb brazing material having a low melting point (about 220 ° C.), the substrate At the time of reflow when mounting an electronic component on the surface of the main body via an Sn-Ag alloy having a melting point higher than that of the brazing material, there is a problem that the brazing material softens or melts and the conductor pin falls down. .
Moreover, since the adhesion between the glass-ceramic of the substrate main body and the Cu metallized layer is low, the conductivity between the internal wiring of the substrate main body and the metallized layer is reduced, or the metallized layer is peeled off to form a conductor pin. There was also a problem that was accidentally removed.

一方、ガラスセラミック基板の表面に位置するTi/Mo/NiMoなどからなる薄膜パッドの上方に、Ag−Cu系共晶合金またはAg−Sn系合金のロウ材を介して、42アロイからなる入出力ピンをロウ付けする多層配線基板が提案されている(例えば、特許文献1参照)。
また、ガラスセラミックからなる絶縁基体の下面に位置するCu製の接続パッドに対し、Ag−Sn系またはAg−Si系合金のロウ材をNiメッキ層およびAuリッチ層を介してネールヘッド部の上に設けたリードピンを、かかるロウ材によりロウ付けしたリードピン付きセラミックパッケージも提案されている(例えば、特許文献2参照)。
On the other hand, above the thin film pad made of Ti / Mo / Ni 3 Mo or the like located on the surface of the glass ceramic substrate, it is made of 42 alloy through the brazing material of Ag—Cu eutectic alloy or Ag—Sn alloy. A multilayer wiring board in which input / output pins are brazed has been proposed (see, for example, Patent Document 1).
In addition, an Ag—Sn or Ag—Si alloy brazing material is placed on the nail head portion through the Ni plating layer and the Au rich layer on the Cu connection pad located on the lower surface of the insulating base made of glass ceramic. There has also been proposed a ceramic package with a lead pin in which the lead pin provided in is brazed with such a brazing material (see, for example, Patent Document 2).

特開平8−298381号公報(第1〜6頁、図1)JP-A-8-298381 (pages 1-6, FIG. 1) 特開2003−224224号公報(第1〜9頁、図1,2)JP 2003-224224 A (pages 1 to 9, FIGS. 1 and 2)

しかながら、前述したガラス−セラミックの基板本体に形成されたCuメタライズ層に対し、Ag−Cu系共晶合金を用いてロウ付けする場合、かかるAg−Cu系共晶合金の融点付近では、ロウ材、ガラス−セラミックの基板本体、およびCuメタライズ層の3者間の熱膨張係数の差が大きくなる。このため、前記導体ピンの取り付け部分にクラックが発生し、かかる導体ピンの取り付け強度が低下することにより、上記導体ピンが倒れるおそれがあった。   However, when brazing the above-mentioned Cu metallized layer formed on the glass-ceramic substrate body using an Ag-Cu eutectic alloy, the brazing metal is near the melting point of the Ag-Cu eutectic alloy. The difference in coefficient of thermal expansion among the three members, the material, the glass-ceramic substrate body, and the Cu metallized layer is increased. For this reason, a crack is generated in the mounting portion of the conductor pin, and the conductor pin may fall due to a decrease in the mounting strength of the conductor pin.

本発明は、前記背景技術において示した問題点を解決し、ガラス−セラミックからなる基板本体とこれに形成するCuメタライズ層との密着性を高めると共に、かかるCuメタライズ層にロウ付けする導体ピンの取り付け強度を高めた配線基板を提供する、ことを課題とする。   The present invention solves the problems shown in the background art, improves the adhesion between the substrate body made of glass-ceramic and the Cu metallized layer formed thereon, and the conductor pin brazed to the Cu metallized layer. It is an object of the present invention to provide a wiring board with increased attachment strength.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、基板本体のガラス−セラミックとCuメタライズ層との間にCu−セラミック混合層を設け、且つCuメタライズ層に導体ピンをロウ付けするロウ材に高融点の合金を適用する、ことに着想して成されたものである。
即ち、本発明の配線基板(請求項1)は、ガラス−セラミックからなり且つ表面および裏面を有する基板本体と、かかる基板本体の表面および裏面の少なくとも一方に形成され且つCu粉末とセラミック粉末とを混合してなるCu−セラミック混合層と、かかるCu−セラミック混合層の上に形成されたCuメタライズ層と、かかるCuメタライズ層の上方に融点が500℃以上のロウ材を介して立設された導体ピンと、を含む、ことを特徴とする。
In order to solve the above problems, the present invention provides a Cu-ceramic mixed layer between a glass-ceramic and a Cu metallized layer of a substrate body, and a brazing material having a high melting point for brazing a conductor pin to the Cu metallized layer. The idea is to apply an alloy.
That is, the wiring board of the present invention (Claim 1) comprises a substrate body made of glass-ceramic and having a front surface and a back surface, and formed on at least one of the front surface and the back surface of the substrate body, and Cu powder and ceramic powder. A Cu-ceramic mixed layer formed by mixing, a Cu metallized layer formed on the Cu-ceramic mixed layer, and a standing part above the Cu metallized layer via a brazing material having a melting point of 500 ° C. or more. And a conductor pin.

これによれば、前記Cu−セラミック混合層が、ガラス−セラミックの基板本体とその表面および裏面の少なくとも一方に形成されたCuメタライズ層との間に介在しているので、これら3者間での密着性が確実に高められ、且つ基板本体とCuメタライズ層と前記ロウ材との熱膨張係数の差を抑制できる。このため、前記基板本体の内部配線と上記メタライズ層との導電性が低下したり、上記メタライズ層が剥離して導体ピンが不用意に外れる事態を確実に防止できる。
しかも、前記Cuメタライズ層の上方に500℃以上の高融点のロウ材を介して導体ピンを立設しているため、例えば基板本体の表面にICチップなどの電子部品を実装する際のリフロー時に、上記導体ピンの取り付け部分にクラックの発生を防止でき、上記導体ピンの倒れを確実に防ぐことができる。
従って、上記導体ピンを介してマザーボードなどのプリント基板との導通が確実に取れると共に、電子部品の実装も確実に行える配線基板となる。
According to this, since the Cu-ceramic mixed layer is interposed between the glass-ceramic substrate body and the Cu metallized layer formed on at least one of the front surface and the back surface thereof, Adhesion can be reliably improved, and a difference in thermal expansion coefficient among the substrate body, the Cu metallized layer, and the brazing material can be suppressed. For this reason, it is possible to reliably prevent the conductivity between the internal wiring of the substrate body and the metallized layer from being lowered, or the metallized layer from being peeled off and the conductor pins being inadvertently detached.
Moreover, since the conductor pins are erected above the Cu metallization layer via a high melting point brazing material of 500 ° C. or higher, for example, at the time of reflow when mounting an electronic component such as an IC chip on the surface of the substrate body Further, it is possible to prevent the occurrence of cracks in the mounting portion of the conductor pin, and to reliably prevent the conductor pin from falling down.
Accordingly, the wiring board can be reliably connected to a printed board such as a mother board through the conductor pins, and the electronic component can be mounted reliably.

尚、前記ガラス−セラミックには、ガラス−アルミナ(Al)、ガラス−珪酸(SiO)、ガラス−窒化アルミニウム、ガラス−酸化ジルコニウム、ガラス−ムライトなどが含まれる。
また、前記Cu−セラミック混合層には、例えばCu粉末とアルミナ粉末との混合材からなり、その体積割合は、例えば約5:1のものが用いられる。
更に、前記融点が500℃以上のロウ材には、例えば融点が約780℃の72wt%Ag−28wt%Cu合金などが用いられる。
加えて、前記導体ピンには、いわゆる42アロイ(Fe−42wt%Ni)、あるいはコバール(Fe−29wt%Ni−17wt%Co)などが用いられる。
The glass-ceramic includes glass-alumina (Al 2 O 3 ), glass-silicic acid (SiO 2 ), glass-aluminum nitride, glass-zirconium oxide, glass-mullite, and the like.
The Cu-ceramic mixed layer is made of, for example, a mixed material of Cu powder and alumina powder, and the volume ratio is, for example, about 5: 1.
Furthermore, for the brazing material having a melting point of 500 ° C. or higher, for example, a 72 wt% Ag-28 wt% Cu alloy having a melting point of about 780 ° C. is used.
In addition, so-called 42 alloy (Fe-42 wt% Ni), Kovar (Fe-29 wt% Ni-17 wt% Co), or the like is used for the conductor pin.

また、本発明には、前記Cu−セラミック混合層と前記Cuメタライズ層の周囲には、これらの外周部に開口縁が覆っているガラスよりなる被覆層が形成されている、配線基板(請求項2)も含まれる。
これによれば、ガラスよりなる被覆層が、Cu−セラミック混合層およびCuメタライズ層の外周部を覆うように形成されているので、これらを物理的にも基板本体のガラス−セラミック寄りに強固に密着させることができる。従って、基板本体の内部配線とCuメタライズ層との導電性が低下したり、Cuメタライズ層が剥離して前記導体ピンとが不用意に外れる事態を、一層確実に防止することができる。
Further, in the present invention, a wiring layer made of glass with an opening edge covering the outer peripheral portion thereof is formed around the Cu-ceramic mixed layer and the Cu metallized layer. 2) is also included.
According to this, since the coating layer made of glass is formed so as to cover the outer peripheral portion of the Cu-ceramic mixed layer and the Cu metallized layer, these are physically strengthened closer to the glass-ceramic of the substrate body. It can be adhered. Therefore, it is possible to more reliably prevent a situation in which the conductivity between the internal wiring of the substrate body and the Cu metallized layer is reduced or the Cu metallized layer is peeled off and the conductor pin is inadvertently detached.

更に、本発明には、前記ガラス−セラミックは、ガラス−アルミナであり、前記セラミック粉末は、アルミナ粉末である、配線基板(請求項3)も含まれる
尚、Cuメタライズ層の表面には、予めNiメッキ層を形成した後に、前記ロウ材を介して導体ピンをロウ付けしても良い。かかるNiメッキ層により、Cuメタライズ層の耐食性およびロウ材との濡れ性を向上させることが可能となる。
また、Cuメタライズ層の上方にロウ付けされた導体ピンの表面とそのネールヘッド部寄りの前記ロウ材の表面とにも、Niメッキ層およびAuメッキ層を形成することにより、これらの耐食性を確保することが可能となる。
Further, the present invention, the glass - ceramic, glass - is alumina, the ceramic powder is alumina powder, the wiring substrate (claim 3) are also included.
In addition, after forming a Ni plating layer in advance on the surface of the Cu metallized layer, conductor pins may be brazed via the brazing material. Such a Ni plating layer makes it possible to improve the corrosion resistance of the Cu metallized layer and the wettability with the brazing material.
In addition, the Ni plating layer and the Au plating layer are formed on the surface of the conductor pin brazed above the Cu metallized layer and the surface of the brazing material near the nail head portion, thereby ensuring the corrosion resistance. It becomes possible to do.

以下において、本発明を実施するための最良の形態について説明する。
図1は、本発明の配線基板1の概略を示す断面図、図2は、図1中の一点鎖線部分Aの部分拡大図である。
基板本体2は、図1,図2に示すように、表面3および裏面4を有する基板本体2と、当該基板本体2の裏面4に形成された複数のCu−セラミック混合層20と、各Cu−セラミック混合層20ごとの上に形成された複数のCuメタライズ層22と、各Cuメタライズ層22ごとの上方にロウ材23を介して立設された導体ピン26と、を含んでいる。
基板本体2は、ガラス−アルミナ(セラミック)からなる絶縁層5〜7を一体に積層したものである。また、Cu−セラミック混合層20は、Cu粉末とアルミナ(セラミック)粉末とを所定比で混合したものである。更に、上記ロウ材23は、融点が約780℃(500℃以上)の72wt%Ag−28wt%Cu合金からなる。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a cross-sectional view showing an outline of a wiring board 1 of the present invention, and FIG. 2 is a partially enlarged view of a one-dot chain line portion A in FIG.
As shown in FIGS. 1 and 2, the substrate body 2 includes a substrate body 2 having a front surface 3 and a back surface 4, a plurality of Cu-ceramic mixed layers 20 formed on the back surface 4 of the substrate body 2, and each Cu A plurality of Cu metallized layers 22 formed on each ceramic mixed layer 20 and conductor pins 26 erected on each Cu metallized layer 22 via a brazing material 23 are included.
The substrate body 2 is formed by integrally laminating insulating layers 5 to 7 made of glass-alumina (ceramic). The Cu-ceramic mixed layer 20 is a mixture of Cu powder and alumina (ceramic) powder in a predetermined ratio. Further, the brazing material 23 is made of a 72 wt% Ag-28 wt% Cu alloy having a melting point of about 780 ° C. (500 ° C. or higher).

図1,図2に示すように、基板本体2の絶縁層5〜7間には、Cuからなる配線層9,10が形成され、基板本体2の表面3には、Cuからなる複数の接続パッド14が形成されると共に、これらの間および裏面4のCuメタライズ層22との間を、Cuからなるビア導体11〜13が接続している。
基板本体2の裏面4には、前記Cu−セラミック混合層20と前記Cuメタライズ層22との外周部に貫通孔18の開口縁19が覆っているガラスよりなる被覆層8が所要の厚みで形成されている。かかる被覆層8は、例えば、珪酸を主成分とするガラスからなり、その表面8aに複数の貫通孔18が開口している。
尚、上記ガラスよりなる被覆層8には、基板本体2と同じ成分のガラス−アルミナに、Cr、Mn、またはFeなどの色粉を混ぜたものを用いても良い。
As shown in FIGS. 1 and 2, wiring layers 9 and 10 made of Cu are formed between the insulating layers 5 to 7 of the substrate body 2, and a plurality of connections made of Cu are formed on the surface 3 of the substrate body 2. The pads 14 are formed, and via conductors 11 to 13 made of Cu are connected between these pads and the Cu metallized layer 22 on the back surface 4.
On the back surface 4 of the substrate body 2, a coating layer 8 made of glass with an opening edge 19 of the through hole 18 covering the outer peripheral portion of the Cu-ceramic mixed layer 20 and the Cu metallized layer 22 is formed with a required thickness. Has been. The covering layer 8 is made of, for example, glass mainly containing silicic acid, and a plurality of through holes 18 are opened on the surface 8a.
For the coating layer 8 made of glass, a glass-alumina having the same component as that of the substrate body 2 and a color powder such as Cr, Mn, or Fe may be used.

図2に示すように、各Cuメタライズ層22ごとの上方(図示では下方)には、例えば42アロイからなる導体ピン26がロウ材23を介して立設されている。かかる導体ピン26のネールヘッド部28は、隙間24を介してCuメタライズ層22と対向している。複数の導体ピン26は、配線基板1自体を図示しない中継基板やマザーボートの表面電極などに接続するために活用される。
尚、導体ピン26およびロウ材23の表面には、図示しないNiメッキ層およびAuメッキ層が所定の厚みで被覆されている。また、Cuメタライズ層22の表面に対し、Niメッキ層を被覆しても良い。
As shown in FIG. 2, a conductor pin 26 made of, for example, 42 alloy is erected via a brazing material 23 above each Cu metallized layer 22 (downward in the drawing). The nail head portion 28 of the conductor pin 26 faces the Cu metallized layer 22 with a gap 24 interposed therebetween. The plurality of conductor pins 26 are used to connect the wiring board 1 itself to a relay board (not shown) or a surface electrode of a mother board.
The surfaces of the conductor pins 26 and the brazing material 23 are covered with a Ni plating layer and an Au plating layer (not shown) with a predetermined thickness. Further, the surface of the Cu metallized layer 22 may be covered with a Ni plating layer.

因みに、基板本体2のサイズは、51mm×51mm×厚み2mm、ガラスよりなる被覆層8の厚みは、約20μm、導体ピン26の直径は、0.3mm、そのネールヘッド部28の直径は、0.65mmである。
図1に示すように、基板本体2の表面3上に位置する複数の接続パッド14上には、融点が約230℃の低い合金(例えば、96.5wt%Sn−3.5wt%Sb)からなるロウ材15を介して、ICチップ(電子部品)16の底面に設けた外部電極17が接続されることで、当該ICチップ16が実装される。
Incidentally, the size of the substrate body 2 is 51 mm × 51 mm × thickness 2 mm, the thickness of the coating layer 8 made of glass is about 20 μm, the diameter of the conductor pin 26 is 0.3 mm, and the diameter of the nail head portion 28 is 0. .65 mm.
As shown in FIG. 1, on the plurality of connection pads 14 located on the surface 3 of the substrate body 2, an alloy having a low melting point of about 230 ° C. (for example, 96.5 wt% Sn-3.5 wt% Sb) is used. The external chip 17 provided on the bottom surface of the IC chip (electronic component) 16 is connected via the brazing material 15 to be mounted on the IC chip 16.

前記配線基板1によれば、Cu−セラミック混合層20が、基板本体2のガラス−セラミックとその裏面4に形成されたCuメタライズ層22との間に介在しているので、これら3者間での密着性が確実に高められ、且つ基板本体2とCuメタライズ層22と前記ロウ材23との熱膨張係数の差を抑制できる。このため、前記ビア導体11〜13を介して配線層9,10とメタライズ層22との導通が確実に取れると共に、メタライズ層22が剥離し導体ピン26が不用意に外れる事態を確実に防止できる。しかも、Cuメタライズ層22の上方に500℃以上の高融点のロウ材23を介して導体ピン26を立設しているため、基板本体2の表面3にICチップ30を実装する際のリフロー時に、上記導体ピン26の取り付け部分の前記被覆層8にクラックが生じなくなり、かかる導体ピン26の倒れを確実に防ぐことができる。更に、ガラスよりなる被覆層8がCu−セラミック混合層20とCuメタライズ層22との外周部を覆うように形成されているため、これらを物理的にも基板本体2のガラス−セラミック側に強固に密着させている。従って、導体ピン26を介してマザーボードなどのプリント基板との導通が確実に取れると共に、表面3上へのICチップ16の実装も確実に行うことができる。   According to the wiring substrate 1, the Cu-ceramic mixed layer 20 is interposed between the glass-ceramic of the substrate body 2 and the Cu metallized layer 22 formed on the back surface 4. And the difference in thermal expansion coefficient among the substrate body 2, the Cu metallized layer 22, and the brazing material 23 can be suppressed. For this reason, the conduction between the wiring layers 9 and 10 and the metallized layer 22 can be surely taken via the via conductors 11 to 13, and it is possible to reliably prevent the metallized layer 22 from peeling off and the conductor pins 26 from being inadvertently detached. . Moreover, since the conductor pins 26 are erected above the Cu metallized layer 22 via a high melting point brazing material 23 having a melting point of 500 ° C. or higher, during reflow when the IC chip 30 is mounted on the surface 3 of the substrate body 2. Cracks are not generated in the covering layer 8 at the portion where the conductor pin 26 is attached, and the conductor pin 26 can be reliably prevented from falling. Furthermore, since the coating layer 8 made of glass is formed so as to cover the outer peripheral portions of the Cu-ceramic mixed layer 20 and the Cu metallized layer 22, they are physically strengthened on the glass-ceramic side of the substrate body 2. It is closely attached to. Therefore, electrical connection with a printed board such as a mother board can be ensured through the conductor pins 26, and the IC chip 16 can be mounted on the surface 3 with certainty.

以下において、前記配線基板1の製造方法について説明する。
予め、複数枚のガラス−セラミックのグリーンシートを用意する。かかるグリーンシートは、ガラス粉末、フィラであるセラミック粉末、有機バインダ、可塑剤、および有機溶剤などを混合したものからなる。
上記ガラス粉末のガラス成分には、例えばSiO−B−Al系、SiO−B−Al−MO系(但し、MはCa、Sr、Mg、Ba、またはZrを示す)、PB系ガラス、あるいはBi系ガラスなどが含まれる。
また、上記セラミック粉末には、例えばAl−SiO−ZrOとアルカリ希土類金属酸化物との複合酸化物、TiOとアルカリ希土類金属酸化物との複合酸化物、AlおよびSiOから選ばれる少なくとも1種を含む複合酸化物である例えばスピネル、ムライト・コージェライトなど、が含まれる。
上記ガラス粉末とセラミック粉末とを、重量比で40:60〜99:1の割合で混合する。
Below, the manufacturing method of the said wiring board 1 is demonstrated.
A plurality of glass-ceramic green sheets are prepared in advance. Such a green sheet is made of a mixture of glass powder, ceramic powder as a filler, an organic binder, a plasticizer, an organic solvent, and the like.
Examples of the glass component of the glass powder include SiO 2 —B 2 O 3 —Al 2 O 3 system, SiO 2 —B 2 O 3 —Al 2 O 3 —MO system (where M is Ca, Sr, Mg, Ba or Zr), PB glass, Bi glass or the like.
Examples of the ceramic powder include composite oxides of Al 2 O 3 —SiO 2 —ZrO 2 and alkali rare earth metal oxides, composite oxides of TiO 2 and alkali rare earth metal oxides, Al 2 O 3 and Examples include composite oxides containing at least one selected from SiO 2 such as spinel and mullite cordierite.
The glass powder and ceramic powder are mixed at a weight ratio of 40:60 to 99: 1.

更に、前記グリーンシートに配合する有機バインダには、例えばアクリル系、ポリビニルブチラール系、ポリビニルアルコール系、アクリル−スチレン系、ポリプロピレンカーボネート系、あるいはセルロース系の単独重合体または共重合体などが含まれる。
前記グリーンシートは、前記ガラス粉末、セラミック粉末、および有機バインダに加え、必要に応じて所要量の可塑剤、溶剤(有機溶剤または水)を更に加えてスラリとし、かかるスラリをドクターブレード法、圧延法、カレンダロール法、金型プレス法などにより、厚さ数10〜数100μmのシート状に成形することで得られる。
Furthermore, the organic binder blended in the green sheet includes, for example, acrylic, polyvinyl butyral, polyvinyl alcohol, acrylic-styrene, polypropylene carbonate, or cellulose homopolymers or copolymers.
In addition to the glass powder, the ceramic powder, and the organic binder, the green sheet further includes a necessary amount of plasticizer and solvent (organic solvent or water) to form a slurry, and the slurry is subjected to a doctor blade method, rolling It can be obtained by molding into a sheet having a thickness of several tens to several hundreds of micrometers by a method, a calender roll method, a die press method, or the like.

そして、得られた複数枚のガラス−セラミック・グリ−ンシートの表面および裏面の少なくとも一方に、Cu粉末を含む導電性ペーストをスクリーン印刷などにより、所定パターンで印刷・形成すると共に、上記グリ−ンシートを貫通するビアホールにも上記導電性ペーストを充填する。
その結果、図3で例示するように、追って前記絶縁層7となり、内部の配線層10、およびビア導体13、を有するグリーンシートs7が得られる。
次いで、図3中の一点鎖線部分Bを拡大した図4に示すように、グリーンシートs7の裏面4における所定の位置に、Cu粉末とアルミナ粉末とを体積比5:1で配合した混合材からなり且つ厚み約20μmのCu−セラミック混合層20を、スクリーン印刷などによりそれぞれ形成する。
Then, a conductive paste containing Cu powder is printed and formed in a predetermined pattern on at least one of the front and back surfaces of the obtained plurality of glass-ceramic green sheets by screen printing or the like, and the green sheet The conductive paste is also filled in the via hole penetrating through.
As a result, as illustrated in FIG. 3, a green sheet s 7 having the insulating layer 7 later and having the internal wiring layer 10 and the via conductor 13 is obtained.
Next, as shown in FIG. 4 in which the one-dot chain line portion B in FIG. 3 is enlarged, from a mixed material in which Cu powder and alumina powder are blended at a volume ratio of 5: 1 at a predetermined position on the back surface 4 of the green sheet s7. And a Cu-ceramic mixed layer 20 having a thickness of about 20 μm is formed by screen printing or the like.

更に、図5に示すように、各Cu−セラミック混合層20の表面(上)に、スクリーン印刷法により、厚み約15μmのCuメタライズ層22を形成する。かかるCuメタライズ層22は、Cu−セラミック混合層20を介して、ビア導体13の端面を含むグリーンシートs7の裏面4に形成されるため、かかる裏面4に直に形成する場合に比べ、強固に接合される。
引き続いて、Cu−セラミック混合層20とCuメタライズ層22との外周部を囲うように所定のマスキング(図示せず)を施した後、図6に示すように、基板本体2の裏面4上に、前記ガラス成分からなる軟質ガラスの被覆層8を、塗布コーティングなどにより形成する。かかる被覆層8が固化すると、図6に示すように、ガラスよりなる被覆層8の表面8aに開口する貫通孔18の開口縁19がCu−セラミック混合層20およびCuメタライズ層22の外周部を覆う形状になる。
Further, as shown in FIG. 5, a Cu metallized layer 22 having a thickness of about 15 μm is formed on the surface (upper) of each Cu-ceramic mixed layer 20 by screen printing. Since the Cu metallized layer 22 is formed on the back surface 4 of the green sheet s7 including the end surface of the via conductor 13 via the Cu-ceramic mixed layer 20, the Cu metallized layer 22 is stronger than the case where it is directly formed on the back surface 4. Be joined.
Subsequently, after applying a predetermined masking (not shown) so as to surround the outer periphery of the Cu-ceramic mixed layer 20 and the Cu metallized layer 22, as shown in FIG. The soft glass coating layer 8 made of the glass component is formed by coating or the like. When the coating layer 8 is solidified, as shown in FIG. 6, the opening edge 19 of the through-hole 18 opening on the surface 8 a of the coating layer 8 made of glass covers the outer peripheral portion of the Cu-ceramic mixed layer 20 and the Cu metallized layer 22. It becomes a covering shape.

かかる状態で、前記被覆層8を含むグリーンシートs7と追って前記絶縁層5,6となるグリーンシートとを積層し、得られた積層体を例えば100〜800℃の温度域に加熱して前記有機バインダなどの有機成分を除去し、更に約800〜1000℃の温度域に加熱して焼成する。
その結果、図7に示すように、ガラス−セラミックの絶縁層5〜7からなり、内部の配線層9,10、ビア導体11〜13、および表面3の接続パッド14を有する基板本体2と、その裏面4に形成された被覆層8とが得られる。
次いで、図7中の一点鎖線部分Cを拡大した図8に示すように、前記Cuメタライズ層22の表面に対し、厚み2〜5μmのNiメッキ層21を被覆する。
In this state, the green sheet s7 including the coating layer 8 and the green sheet to be the insulating layers 5 and 6 are stacked, and the obtained stacked body is heated to a temperature range of, for example, 100 to 800 ° C. Organic components such as a binder are removed, and further heated to a temperature range of about 800 to 1000 ° C. and fired.
As a result, as shown in FIG. 7, the substrate body 2 is composed of glass-ceramic insulating layers 5 to 7, and has internal wiring layers 9 and 10, via conductors 11 to 13, and connection pads 14 on the surface 3, The coating layer 8 formed on the back surface 4 is obtained.
Next, as shown in FIG. 8 in which the one-dot chain line portion C in FIG. 7 is enlarged, the surface of the Cu metallized layer 22 is covered with a Ni plating layer 21 having a thickness of 2 to 5 μm.

更に、図8中の矢印で示すように、ガラスよりなる被覆層8において、底面に露出するCuメタライズ層22の表面、あるいは前記Niメッキ層21が底面に露出する貫通孔18内に、例えば42アロイからなる導体ピン26を、そのネールヘッド部28が対向するようにして挿入する。かかるネールヘッド部28の上面には、融点が約780℃(500℃以上)の72wt%Ag−28wt%Cu合金からなるロウ材25がほぼ半球形状にして予め形成されている。
かかるロウ材25とCuメタライズ層22、あるいは前記Niメッキ層21とが接触し且つ導体ピン26の軸心が基板本体2の裏面4に直角に保たれた状態として、上記ロウ材25をその融点直上の温度付近に加熱(シンタリング)する。
Further, as indicated by an arrow in FIG. 8, in the coating layer 8 made of glass, for example 42 in the surface of the Cu metallized layer 22 exposed on the bottom surface or in the through hole 18 where the Ni plating layer 21 is exposed on the bottom surface. The conductor pin 26 made of alloy is inserted so that the nail head portion 28 is opposed. A brazing material 25 made of a 72 wt% Ag-28 wt% Cu alloy having a melting point of about 780 ° C. (500 ° C. or higher) is formed in a substantially hemispherical shape on the upper surface of the nail head portion 28 in advance.
With the brazing material 25 in contact with the Cu metallized layer 22 or the Ni plating layer 21 and with the axis of the conductor pin 26 kept at a right angle to the back surface 4 of the substrate body 2, the brazing material 25 is melted at its melting point. Heat (sinter) near the temperature just above.

その結果、図9に示すように、前記ロウ材25が溶融されると、前記メッキ層21との隙間24を含めて導体ピン26のネールヘッド部28を包囲するように凝固したほぼ円錐形状のロウ材23となる。このため、かかるロウ材23を介して、導体ピン26を基板本体2の裏面4上方に立設することができる。
そして、導体ピン26および上記ロウ材23の表面に対し、NiメッキおよびAuメッキを施す。その結果、図9中の一点鎖線部分Cを拡大した同図中の部分面で例示するように、ピン本体27の表面に厚み3〜7μmのNiメッキ層29aと厚み約1〜2μmのAuメッキ層29bとが被覆される。かかるAuメッキ層29bにより、導体ピン26およびロウ材23の耐食性が確保される。
以上のような各工程を経ることで、前記図1に示した配線基板1が得られる。
As a result, as shown in FIG. 9, when the brazing material 25 is melted, it has a substantially conical shape solidified so as to surround the nail head portion 28 of the conductor pin 26 including the gap 24 with the plated layer 21. The brazing material 23 is obtained. For this reason, the conductor pin 26 can be erected above the back surface 4 of the substrate body 2 through the brazing material 23.
Then, Ni plating and Au plating are applied to the surfaces of the conductor pins 26 and the brazing material 23. As a result, as illustrated in the enlarged partial surface in FIG. 9, a portion of the dotted line C in FIG. Layer 29b is coated. The Au plating layer 29b ensures the corrosion resistance of the conductor pin 26 and the brazing material 23.
The wiring substrate 1 shown in FIG. 1 is obtained through the above steps.

更に、基板本体2の表面3上方にICチップ16を実装するため、表面3に位置する複数の接続パッド14上に、低融点の前記Sn−Sb系合金からなるロウ材15を介してICチップ16の底面に設けた外部電極17を載置した状態で、上記ロウ材15をその融点付近に加熱(リフロー)する。かかるリフロー時においても、約230℃付近の温度域にあるため、基板本体2の裏面4側で導体ピン26をロウ付けしている高融点の前記Ag−Cu系合金のロウ材23は、軟化しない。このため、配線基板1では、ピン倒れを確実に防ぐことが可能となる。
尚、前記Cuメタライズ層22の表面に対し、前記Niメッキ層21を被覆する工程は、省略することも可能である。
Further, in order to mount the IC chip 16 above the surface 3 of the substrate body 2, the IC chip is disposed on the plurality of connection pads 14 located on the surface 3 via the brazing material 15 made of the Sn—Sb alloy having a low melting point. In the state where the external electrode 17 provided on the bottom surface of 16 is placed, the brazing material 15 is heated (reflowed) near its melting point. Even during such reflow, since it is in a temperature range of about 230 ° C., the high melting point Ag—Cu alloy brazing material 23 brazing the conductor pin 26 on the back surface 4 side of the substrate body 2 is softened. do not do. For this reason, in the wiring board 1, it becomes possible to prevent pin collapse reliably.
The step of coating the Ni plating layer 21 on the surface of the Cu metallized layer 22 can be omitted.

本発明は、前述した形態に限定されるものではない。
例えば、前記Cu−セラミック混合層20におけるCuとセラミックとの体積割合は、10:1〜2:1の範囲で適宜選択することが可能である。
また、前記Cu−セラミック混合層20やCuメタライズ層22を基板本体2の表面3のみに形成し、かかる表面3側に前記ロウ材23を介して導体ピン26を立設することも可能であり、あるいは、基板本体2の表面3と裏面4との双方に導体ピン26を立設することも可能である。
更に、前記基板本体2は、表面3に開口するキャビティを有する形態として良く、かかる形態では前記ICチップ16などの電子部品は、上記キャビティ内において実装される。
また、前記ロウ材25は、融点が500℃以上であれば、前記組成以外のAg−Cu系合金やその他の合金を適用することも可能である。
加えて、前記導体ピン26の材質は、42アロイに限らず、コバールやCu基合金(例えば、Cu−2.3wt%Fe−0.03wt%P)としても良い。
The present invention is not limited to the form described above.
For example, the volume ratio of Cu and ceramic in the Cu-ceramic mixed layer 20 can be appropriately selected within a range of 10: 1 to 2: 1.
It is also possible to form the Cu-ceramic mixed layer 20 or the Cu metallized layer 22 only on the surface 3 of the substrate body 2 and to erect the conductor pins 26 on the surface 3 side through the brazing material 23. Alternatively, the conductor pins 26 can be erected on both the front surface 3 and the back surface 4 of the substrate body 2.
Further, the substrate main body 2 may be configured to have a cavity opened on the surface 3, and in such a configuration, electronic components such as the IC chip 16 are mounted in the cavity.
The brazing material 25 may be made of an Ag—Cu alloy or other alloy other than the above composition as long as the melting point is 500 ° C. or higher.
In addition, the material of the conductor pin 26 is not limited to 42 alloy, and may be Kovar or a Cu-based alloy (for example, Cu-2.3 wt% Fe-0.03 wt% P).

本発明の配線基板の概略を示す断面図。Sectional drawing which shows the outline of the wiring board of this invention. 図1中の一点鎖線部分Aの部分拡大図。The elements on larger scale of the dashed-dotted line part A in FIG. 上記配線基板を得るための製造工程を示す概略図。Schematic which shows the manufacturing process for obtaining the said wiring board. 図3に続く製造工程で且つ同中の一点鎖線部分Bの部分拡大図。FIG. 4 is a partially enlarged view of a one-dot chain line portion B in the manufacturing process subsequent to FIG. 3. 図4に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図5に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図6に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図7に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図8に続く製造工程を示す概略図およびその一部の拡大図。Schematic which shows the manufacturing process following FIG. 8, and the one part enlarged view.

符号の説明Explanation of symbols

1……配線基板
2……基板本体
3……表面
4……裏面
8……ガラスよりなる被覆層
20…Cu−セラミック混合層
22…Cuメタライズ層
23…ロウ材
26…導体ピン
DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Board | substrate body 3 ... Front surface 4 ... Back surface 8 ... Coating layer which consists of glass 20 ... Cu-ceramics mixed layer 22 ... Cu metallization layer 23 ... Brazing material 26 ... Conductor pin

Claims (3)

ガラス−セラミックからなり且つ表面および裏面を有する基板本体と、
上記基板本体の表面および裏面の少なくとも一方に形成され且つCu粉末とセラミック粉末とを混合してなるCu−セラミック混合層と、
上記Cu−セラミック混合層の上に形成されたCuメタライズ層と、
上記Cuメタライズ層の上方に融点が500℃以上のロウ材を介して立設された導体ピンと、を含む、
ことを特徴とする配線基板。
A substrate body made of glass-ceramic and having a front surface and a back surface;
A Cu-ceramic mixed layer formed on at least one of the front surface and the back surface of the substrate body and formed by mixing Cu powder and ceramic powder;
A Cu metallization layer formed on the Cu-ceramic mixed layer;
A conductor pin standing above the Cu metallization layer via a brazing material having a melting point of 500 ° C. or higher,
A wiring board characterized by that.
前記Cu−セラミック混合層と前記Cuメタライズ層との周囲には、これらの外周部に開口縁が覆っているガラスよりなる被覆層が形成されている、
ことを特徴とする請求項1に記載の配線基板。
Around the Cu-ceramic mixed layer and the Cu metallized layer, a coating layer made of glass with an opening edge covering these outer peripheral portions is formed.
The wiring board according to claim 1.
前記ガラス−セラミックは、ガラス−アルミナであり、前記セラミック粉末は、アルミナ粉末である
ことを特徴とする請求項1または2に記載の配線基板
The glass-ceramic is glass-alumina, and the ceramic powder is alumina powder .
The wiring board according to claim 1 or 2, wherein
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JP2001267451A (en) * 2000-03-15 2001-09-28 Ngk Spark Plug Co Ltd Wiring board with pin

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