JP4571070B2 - Voltage generation circuit and signal processing circuit using the same - Google Patents

Description

  The present invention relates to a voltage generation circuit that generates a midpoint voltage between a power supply voltage and a ground potential in a signal processing circuit that performs signal processing on an audio signal.

  When performing audio signal processing, signal amplification is generally performed using a midpoint voltage between a power supply voltage and a ground potential as a reference voltage. As a voltage generation circuit for easily generating such a reference voltage, there is a circuit that provides two voltage dividing resistors of equal resistance connected in series between a power supply terminal and a ground terminal, and divides the power supply voltage. Widely used.

JP-A-9-190698

  In this case, generally, a capacitor having a large capacitance value is provided between the voltage dividing point of the resistor and the ground so that the reference voltage does not fluctuate even if the power supply voltage fluctuates. This capacitor and the voltage dividing resistor constitute a time constant circuit. In order to reduce the power consumption due to the voltage dividing resistor, the resistance value is set large, so that the time constant of the time constant circuit formed by the capacitor and the voltage dividing resistor becomes very large. As a result, when the power source is turned on, there is a problem that the time until the capacitor is charged becomes longer and the time until the reference voltage rises becomes longer.

  The present invention has been made in view of these problems, and an object thereof is to shorten the startup time of a voltage generation circuit that divides a power supply voltage.

  One embodiment of the present invention relates to a voltage generation circuit that divides a power supply voltage applied to a power supply terminal and a ground voltage applied to a ground terminal and outputs the divided voltage from an output terminal. The voltage generation circuit includes first and second resistors connected in series between a power supply terminal and a ground terminal, a first voltage dividing circuit in which a connection point of the two resistors is connected to the output terminal, and an output terminal An output capacitor provided between the power supply terminal and the ground terminal; a second voltage dividing circuit including third and fourth resistors connected in series between the power supply terminal and the ground terminal; and a voltage at a connection point of the third and fourth resistances Is activated when the voltage is higher than the voltage at the output terminal, and includes a charging circuit that supplies current to the output capacitor.

  According to this aspect, when the power supply voltage is raised, since the rise of the voltage at the output terminal is delayed with respect to the rise of the power supply voltage, the charging circuit becomes active. As a result, the output capacitor is supplied with the charge from the charging circuit in addition to the first resistor, so that the startup time can be shortened.

  The charging circuit may include a first switch connected in series between the power supply terminal and the output terminal, and a first comparator that compares the voltage at the connection point of the third and fourth resistors with the voltage of the output terminal. . The first switch may be turned on / off according to the output signal of the first comparator.

The charging circuit may further include a fifth resistor connected in series with the first switch. The resistance value of the fifth resistor may be set in a range of 1/1000 times to 1/10 times the resistance value of the first, second, third, and fourth resistors.
By setting the resistance value of the fifth resistor low, the time constant can be set small and the output voltage can be raised in a short time.

  The first comparator may have an input offset voltage. By setting an offset voltage at the input of the first comparator, it is possible to prevent the first switch of the charging circuit from repeatedly turning on and off due to slight fluctuations in the power supply voltage and the output voltage.

The voltage generation circuit may further include a discharge circuit that becomes active when the voltage at the connection point of the third and fourth resistors is lower than the voltage at the output terminal and draws current from the output capacitor.
In this case, the activation time can be further shortened.

  The discharge circuit includes a second switch connected in series between the ground terminal and the output terminal, and a second comparator that compares the voltage at the connection point of the third and fourth resistors with the voltage of the output terminal. The two switches may be turned on / off according to the output signal of the second comparator.

  The discharge circuit may further include a sixth resistor connected in series with the second switch. The resistance value of the sixth resistor may be set in a range from 1/1000 times to 1/10 of the resistance value of the first, second, third, and fourth resistors.

  The second comparator may have an input offset voltage.

  The first resistor and the second resistor of the first voltage dividing circuit, and the third resistor and the fourth resistor of the second voltage dividing circuit may be formed by pairing, respectively.

  Another aspect of the present invention is a signal processing circuit. The signal processing circuit includes a voltage generation circuit, and performs predetermined signal processing using the voltage output from the voltage generation circuit as a reference voltage.

  According to this aspect, since the reference voltage rises immediately after the power supply voltage rises, signal processing can be started immediately.

  The signal processing circuit described above includes a stereo modulator that converts an audio signal into a stereo composite signal, a frequency modulator that generates a modulated signal that is frequency-modulated by the stereo composite signal output from the stereo modulator, and a frequency modulator. And a power amplifier that amplifies the modulated signal generated by. At least one of the stereo modulator and the frequency modulator may operate based on a voltage output from the voltage generation circuit.

  The signal processing circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the signal processing circuit as one LSI, the circuit area can be reduced.

  It should be noted that any combination of the above-described constituent elements, and those obtained by replacing constituent elements and expressions of the present invention with each other among methods, apparatuses, systems, etc. are also effective as embodiments of the present invention.

  According to the voltage generation circuit of the present invention, the startup time can be shortened.

  FIG. 1 is a circuit diagram showing a configuration of a voltage generation circuit 100 according to an embodiment of the present invention. The voltage generation circuit 100 divides the power supply voltage Vdd applied to the power supply terminal 102 and the ground voltage (0 V) applied to the ground terminal GND, and outputs them from the output terminal 104. In the present embodiment, it is assumed that voltage generation circuit 100 generates midpoint voltage Vdd / 2 of the power supply voltage.

  The voltage generation circuit 100 includes a first voltage dividing circuit 10, a second voltage dividing circuit 20, and a charging circuit 30. The first voltage dividing circuit 10 includes a first resistor R1 and a second resistor R2 connected in series between the power supply terminal 102 and the ground terminal GND. In the present embodiment, the first resistor R1 and the second resistor R2 are formed by pairing, and the resistance values are designed to be equal. The resistance values of the first resistor R1 and the second resistor R2 are preferably set large in order to reduce current consumption. For example, the resistance values are set in the range of several tens of kΩ to 1 MΩ.

  A connection point between the first resistor R 1 and the second resistor R 2 is connected to the output terminal 104. An output capacitor C1 is provided between the output terminal 104 and the ground terminal GND. The voltage generation circuit 100 outputs a voltage (hereinafter referred to as a reference voltage Vref) appearing at the output capacitor C1 from the output terminal 104. In order to stabilize the reference voltage Vref, it is desirable that the capacitance value of the output capacitor C1 is large. For example, it is preferable to set the capacitance in the range of 0.01 μF to 1 μF.

  The second voltage dividing circuit 20 includes a third resistor R3 and a fourth resistor R4 connected in series between the power supply terminal 102 and the ground terminal GND. The third resistor R3 and the fourth resistor R4 are formed by pairing, and their resistance values are designed to be equal. The resistance values of the third resistor R3 and the fourth resistor R4 are preferably set large in order to reduce current consumption. For example, the resistance values are set in the range of several tens of kΩ to 1 MΩ. The first resistor R1 to the fourth resistor R4 may all be set to the same resistance value, and all may be paired.

  The charging circuit 30 compares the voltage at the connection point of the third resistor R3 and the fourth resistor R4 (hereinafter referred to as the detection voltage Vdet) with the reference voltage Vref of the output terminal 104, and is active when Vdet> Vref, Vdet <Vref It becomes inactive at. The charging circuit 30 supplies the charging current Ic1 to the output capacitor C1 when active, and stops supplying the current when inactive.

  The charging circuit 30 includes a fifth resistor R5, a first switch SW1, and a first comparator 32. The fifth resistor R5 and the first switch SW1 are connected in series between the power supply terminal 102 and the output terminal 104. The first comparator 32 compares the detection voltage Vdet with the reference voltage Vref of the output terminal 104. The first switch SW1 is turned on / off according to the output signal of the first comparator 32. That is, the first switch SW1 is turned on when Vdet> Vref, and turned off when Vdet <Vref. The charging circuit 30 is active when the first switch SW1 is on and inactive when the first switch SW1 is off. The first switch SW1 can be configured using a MOS transistor or a bipolar transistor.

  The resistance value of the fifth resistor R5 is desirably set in a range of 1/1000 times to 1/10 of the resistance value of the first resistor R1 to the fourth resistor R4. For example, when the first resistor R1 to the fourth resistor R4 are 500 kΩ, the fifth resistor R5 is about 1 kΩ.

  In the embodiment, the first comparator 32 desirably has the input offset voltage Vofs1. The value of the input offset voltage Vofs1 is preferably set to about several tens to several hundred mV, more specifically, about 10 mV to 300 mV. When the input offset voltage Vofs1 is set in the first comparator 32, the first switch SW1 is turned on when Vdet> Vref + Vofs1, and turned off when Vdet <Vref + Vofs1.

  According to the voltage generation circuit 100 configured as described above, a reference voltage given by Vref = Vdd × R2 / (R1 + R2) = Vdd / 2 is generated from the output terminal 104 in a steady state. The reference voltage Vref output from the output terminal 104 is supplied to other circuit blocks via the buffer circuits BUF1 and BUF2.

  The operation of the voltage generation circuit 100 configured as described above when the power supply voltage fluctuates will be described. Hereinafter, a case where the power supply voltage rises will be described as an example of the power supply voltage fluctuation.

  First, in order to clarify the effect of the present invention, the operation when the charging circuit 30 is not provided will be described. FIG. 2 is an operation waveform diagram of the voltage generation circuit when the charging circuit 30 is not provided. In FIG. 2 and FIG. 3 described later, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  The power is turned on at time t0, the power supply voltage Vdd rises, and reaches a predetermined voltage Vdd1 at time t1. When the charging circuit 30 is not provided, the charging path for the output capacitor C1 is only the first resistor R1. Here, the output capacitor C1 and the first resistor R1 form a time constant circuit. As described above, the capacitance value of the output capacitor C1 is set large for voltage stabilization, and the resistance of the first resistor R1. The value is also set large for low power consumption. Accordingly, since the time constants of the output capacitor C1 and the first resistor R1 become very large, the rising of the reference voltage Vref rises behind the power supply voltage Vdd as shown in FIG. 2, and at a time t2, the predetermined voltage Vdd1 / 2 is reached.

  Next, the operation of the voltage generation circuit 100 according to the present embodiment provided with the charging circuit 30 will be described. FIG. 3 is an operation waveform diagram of the voltage generation circuit 100 according to the present embodiment in which the charging circuit 30 is provided.

  When the power supply voltage Vdd increases, the detection voltage Vdet obtained by dividing the power supply voltage Vdd increases following the power supply voltage Vdd. At time t0, Vdet <Vref + Vofs1 is established, and the charging circuit 30 is inactive. At this time, since the output capacitor C1 is charged via the first resistor R1, the reference voltage Vref starts to rise gently.

  When Vdet> Vref + Vofs1 at time t1, the first switch SW1 is turned on and the charging circuit 30 is activated. When the charging circuit 30 becomes active, the output capacitor C1 is charged through a path including the first switch SW1 and the fifth resistor R5. As described above, since the resistance value of the fifth resistor R5 is set lower than the resistance value of the first resistor R1, the time constant decreases and the reference voltage Vref starts to rise rapidly.

  When the power supply voltage Vdd reaches the predetermined value Vdd1 at time t2, and then the reference voltage Vdet reaches the voltage (Vdd1 / 2−Vofs1) at time t3, Vdet <Vref + Vofs1, and the first switch SW1 is turned off. Become. After time t3, the output capacitor C1 is charged by the first resistor R1, and the reference voltage Vref gradually rises and reaches Vdd1 / 2 at time t4.

  Thus, according to the voltage generation circuit 100 according to the present embodiment, when the power supply voltage Vdd rises, the rise of the reference voltage Vref of the output terminal 104 with respect to the rise of the detection voltage Vdet that follows the power supply voltage Vdd. , The charging circuit 30 becomes active. By turning on the first switch SW1 and charging via the fifth resistor R5 having a low resistance value, the reference voltage Vref can be raised in a shorter time than when charging only with the first resistor R1. .

  Further, when the input offset voltage Vofs1 is set in the first comparator 32 of the charging circuit 30, it is possible to prevent the first switch SW1 of the charging circuit 30 from being turned on and off due to slight fluctuations in the power supply voltage Vdd and the reference voltage Vref. Can do. In particular, the ripple of the power supply voltage Vdd can prevent the first switch SW1 from being repeatedly turned on and off, and the reference voltage Vref can be further stabilized.

  Furthermore, the charging circuit 30 becomes active when the detected voltage Vdet becomes Vdet> Vref (when the offset voltage is set, Vdet> Vref + Vofs1) even if the difference between the reference voltages Vref becomes small. Therefore, the reference voltage Vref can be raised by the charging circuit 30 until the reference voltage Vref becomes substantially equal to the midpoint voltage Vdd / 2 of the power supply voltage Vdd.

  Next, a modification of the voltage generation circuit will be described. FIG. 4 is a circuit diagram showing a configuration of a modified example of the voltage generation circuit 100. In FIG. 4, the same or equivalent components as in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Hereinafter, the difference will be mainly described.

  The voltage generation circuit 100b of FIG. 4 is characterized in that a discharge circuit 40 is added to the voltage generation circuit 100 of FIG. The discharge circuit 40 becomes active when the detection voltage Vdet appearing at the connection point of the third resistor R3 and the fourth resistor R4 is lower than the reference voltage Vref appearing at the output terminal 104, and draws current from the output capacitor C1.

The discharge circuit 40 is configured similarly to the second voltage dividing circuit 20. The discharge circuit 40 includes a sixth resistor R6, a second switch SW2, and a second comparator 42.
The sixth resistor R6 and the second switch SW2 are connected in series between the ground terminal GND and the output terminal 104. The second comparator 42 compares the detection voltage Vdet appearing at the connection point of the third resistor R3 and the fourth resistor R4 with the reference voltage Vref of the output terminal 104. The second switch SW2 is controlled to be turned on / off according to the output signal of the second comparator 42. The second comparator 42 may have an input offset voltage Vofs2.

  When the input offset voltage Vofs2 is set in the second comparator 42, the second switch SW2 is turned on when Vdet <Vref−Vofs, and turned off when Vdet> Vref−Vofs.

  The resistance value of the sixth resistor R6 is preferably set in the range of 1/1000 times to 1/10 of the resistance values of the first resistor R1 to the fourth resistor R4. Further, the resistance values of the sixth resistor R6 and the fifth resistor R5 may be set to be the same and paired.

  Further, by providing the discharging circuit 40 in addition to the charging circuit 30, the reference voltage Vref can be immediately reduced when the voltage generating circuit 100b is stopped.

  Further, by setting an input offset voltage in the first comparator 32 and the second comparator 42, the first switch SW1 and the second switch SW2 are alternately turned on and off in a voltage range where the reference voltage Vref and the detection voltage Vdet are substantially equal. Can be prevented.

  FIG. 5 is a block diagram illustrating a configuration example of a signal processing circuit using the voltage generation circuit 100 according to the above-described embodiment. The signal processing circuit 200 in FIG. 5 performs predetermined signal processing using the midpoint voltage Vdd / 2 output from the voltage generation circuit 100 as a reference voltage. Examples of the predetermined signal processing include audio signal amplification and filtering by an active filter.

  Hereinafter, the signal processing circuit 200 in FIG. 5 will be described as a stereo FM transmission circuit that converts an audio signal into a stereo composite signal, performs frequency modulation, amplifies it, and transmits it from an antenna. Such a signal processing circuit (hereinafter also referred to as “FM transmission circuit”) 200 is used when transmitting a signal without using a cable in in-vehicle audio, or built in a portable terminal and used in a stationary audio device. On the other hand, it can be used for the purpose of transmitting an audio signal.

  The FM transmission circuit 200 includes a voltage generation circuit 100, pre-emphasis filters 110L and 110R, a stereo modulator 120, a frequency modulator 130, and a power amplifier 140. In the FM transmitter circuit 200, each block may be integrated in one LSI, or may be divided into separate ICs. Note that the FM transmission circuit 200 in FIG. 1 is shown by simplifying only main blocks, and other circuit blocks such as filters are omitted.

  The audio signal source 210 is a CD player, MD player, memory audio, hard disk audio, etc., and generates an audio signal S 1 and outputs it to the FM transmitter circuit 200. The pre-emphasis filters 110 </ b> L and 110 </ b> R perform frequency correction on the L channel of the stereo signal and the audio signals S <b> 1 </ b> L and S <b> 1 </ b> R corresponding to the R channel, and output to the stereo modulator 120. The stereo modulator 120 converts the audio signals SL and SR output from the pre-emphasis filters 110L and 110L into a stereo composite signal Sc. The stereo composite signal Sc is input to the frequency modulator 130.

  The frequency modulator 130 uses the stereo composite signal Sc as a modulation signal, and generates a high-frequency modulated signal S3 that is frequency-modulated based on the modulation signal. The frequency modulator 130 includes, for example, a PLL (Phase Locked Loop) configured by using a VCO, a frequency divider, a phase comparator, and a loop filter, and is a direct modulation type frequency that superimposes an audio signal on an input signal of the VCO. It is a modulator. The modulated signal S3 generated by the frequency modulator 130 is amplified by the power amplifier 140 and transmitted from the antenna 220.

  The voltage generation circuit 100 uses the battery voltage Vbat output from the battery 230 as the power supply voltage Vdd, and generates the reference voltage Vref based on the power supply voltage Vdd. The battery voltage Vdd is supplied to each block in addition to the voltage generation circuit 100. The reference voltage Vref generated by the voltage generation circuit 100 is supplied to the midpoint voltage Vdd of the power supply voltage Vdd through the buffers BUF1 to BUF3, such as the pre-emphasis filter 110, the stereo modulator 120, the frequency modulator 130, and other amplifiers. Output to each block requiring / 2. That is, it is desirable that at least one of the stereo modulator 120 and the frequency modulator 130 operate based on the midpoint voltage Vdd output from the voltage generation circuit 100.

  In the FM transmitter circuit 200 of FIG. 5 configured as described above, the voltage generation circuit 100 according to the embodiment can generate the intermediate voltage Vdd / 2 in a short time after the power is turned on. The period until it can be shortened.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  In the voltage generation circuit 100 according to the embodiment, the fifth resistor R5 or the sixth resistor R6 is provided on the charging / discharging path of the charging circuit 30 or the discharging circuit 40, but is not limited thereto. For example, the charging circuit 30 and the discharging circuit 40 may not be provided with the fifth resistor R5 and the sixth resistor R6.

  The FM transmission circuit 200 of FIG. 5 has been described as being driven by a battery, but is not limited thereto, and may be driven by a voltage output from another power supply device. The application of the voltage generation circuit 100 according to the embodiment is not limited to the audio signal processing circuit, and can be widely used for other signal processing circuits using the midpoint voltage Vdd / 2.

  Although the voltage generation circuit 100 divides the power supply voltage Vdd and the ground potential, the ground potential is not limited to 0 V, and includes a negative power supply voltage -Vdd.

It is a circuit diagram which shows the structure of the voltage generation circuit which concerns on embodiment. It is an operation | movement waveform diagram of the voltage generation circuit when not providing a charging circuit. It is an operation | movement waveform diagram of the voltage generation circuit of FIG. 1 which provided the charging circuit. FIG. 6 is a circuit diagram showing a configuration of a modification of the voltage generation circuit of FIG. 1. It is a block diagram which shows the structural example of the signal processing circuit using the voltage generation circuit which concerns on embodiment.

Explanation of symbols

  100 voltage generating circuit, 10 first voltage dividing circuit, 20 second voltage dividing circuit, 30 charging circuit, 32 first comparator, 40 discharging circuit, 42 second comparator, C1 output capacitor, R1 first resistance, R2 second resistance , R3 third resistor, R4 fourth resistor, R5 fifth resistor, R6 sixth resistor, SW1 first switch, SW2 second switch, 102 power supply terminal, 104 output terminal, 110 pre-emphasis filter, 120 stereo modulator, 130 Frequency modulator, 140 power amplifier, 200 FM transmitter circuit.

Claims (14)

A voltage generation circuit that divides a power supply voltage applied to a power supply terminal and a ground voltage applied to a ground terminal and outputs the voltage from an output terminal,
A first voltage dividing circuit including first and second resistors connected in series between the power supply terminal and the ground terminal, the connection point of the two resistors being connected to the output terminal;
An output capacitor provided between the output terminal and the ground terminal;
A second voltage dividing circuit including third and fourth resistors connected in series between the power supply terminal and the ground terminal;
A charging circuit that becomes active when a voltage at a connection point of the third and fourth resistors is higher than a voltage of the output terminal and supplies a current to the output capacitor;
A voltage generation circuit comprising: The charging circuit is
A first switch connected in series between the power supply terminal and the output terminal;
A first comparator for comparing a voltage at a connection point of the third and fourth resistors with a voltage of the output terminal;
The voltage generation circuit according to claim 1, wherein the first switch is turned on / off according to an output signal of the first comparator.   The voltage generation circuit according to claim 2, wherein the charging circuit further includes a fifth resistor connected in series with the first switch.   The resistance value of the fifth resistor is set in a range of 1/1000 times to 1/10 times the resistance value of the first, second, third, and fourth resistors. Voltage generation circuit. It said first comparator is possess an input offset voltage Vofs1, the third, fourth voltage in the resistance of the connection point Vdet, when writing the Vref voltage of the output terminal,
Vdet> Vref + Vofs1
The voltage generation circuit according to claim 2 , wherein the first switch is turned on when the condition is satisfied .   6. The discharge circuit according to claim 1, further comprising a discharge circuit that becomes active when a voltage at a connection point of the third and fourth resistors is lower than a voltage of the output terminal and draws a current from the output capacitor. The voltage generation circuit described in 1. The discharge circuit is:
A second switch connected in series between the ground terminal and the output terminal;
A second comparator for comparing the voltage at the connection point of the third and fourth resistors with the voltage at the output terminal;
The voltage generation circuit according to claim 6 , wherein the second switch is turned on / off according to an output signal of the second comparator.   The voltage generation circuit according to claim 7, wherein the discharge circuit further includes a sixth resistor connected in series with the second switch.   The resistance value of the sixth resistor is set in a range of 1/1000 times to 1/10 times the resistance value of the first, second, third, and fourth resistors. Voltage generation circuit. The second comparator is possess an input offset voltage Vofs2, the third, fourth voltage in the resistance of the connection point Vdet, when writing the Vref voltage of the output terminal,
Vdet <Vref−Vofs1
The voltage generation circuit according to claim 7 , wherein when the condition is satisfied, the second switch is turned on .   The first resistor and the second resistor of the first voltage dividing circuit, and the third resistor and the fourth resistor of the second voltage dividing circuit are formed by pairing, respectively. 7. The voltage generation circuit according to 1 or 6.   A signal processing circuit comprising the voltage generation circuit according to claim 1, wherein predetermined signal processing is performed using a voltage output from the voltage generation circuit as a reference voltage. A stereo modulator that converts the audio signal into a stereo composite signal;
A frequency modulator that generates a modulated signal that is frequency-modulated by the stereo composite signal output from the stereo modulator;
A power amplifier for amplifying the modulated signal generated by the frequency modulator;
The signal processing circuit according to claim 12, wherein at least one of the stereo modulator and the frequency modulator operates based on a voltage output from the voltage generation circuit.   The signal processing circuit according to claim 12, wherein the signal processing circuit is integrated on a single semiconductor substrate.

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