JP4570935B2 - Semiconductor substrate evaluation method and semiconductor substrate evaluation element - Google Patents

Description

  The present invention relates to a method for producing and evaluating a substrate evaluation element for evaluating a semiconductor substrate having a semiconductor layer formed on a base substrate, and a semiconductor substrate evaluation element. The present invention relates to an electrical property evaluation method and an evaluation element.

  For example, there is a silicon substrate as a semiconductor substrate that is widely used as an integrated circuit. However, as the speed of the system increases, the integration becomes higher, and the development of portable terminals, the semiconductor device has a higher speed and lower power consumption and a higher breakdown voltage. In addition, there is a further demand for a large capacity. Under such circumstances, a semiconductor substrate in which a semiconductor layer for forming a semiconductor device is formed on a base substrate such as silicon may be used. Such a substrate has an advantage that a semiconductor layer such as silicon having desired characteristics suitable for forming semiconductor devices for various uses can be easily obtained. Examples of such a substrate include an epitaxial wafer and an SOI (Silicon On Insulator) wafer in which a silicon active layer is formed on an insulating layer. A silicon substrate having a heterostructure in which a semiconductor layer having a conductivity type different from that of a base substrate (for example, a heteroepitaxial wafer) is used for applications such as bipolar transistors and IGBTs (Insulated Gate Bipolar Transistors).

  On the other hand, as a quality evaluation method for a normal silicon substrate (bulk wafer), a GOI (Gate Oxide Integrity) method is widely used. In the GOI method, for example, as shown in a plan view and a cross-sectional view in FIG. 6, the surface of the silicon substrate 11 to be evaluated is oxidized to form a gate oxide film 12, and a metal electrode is formed on the gate oxide film 12. 13 (or polysilicon electrode) is formed, and a MOS capacitor having a MOS (Metal Oxide Semiconductor) structure is fabricated as an evaluation element. For the MOS capacitor thus manufactured, the back surface of the silicon substrate 11 is connected to the ground, and a voltage is applied to the metal electrode 13 so that the silicon substrate 11 is on the storage side. For example, when the conductivity type of the silicon substrate 11 is P type, the silicon substrate 11 becomes the accumulation side by applying a negative voltage. In this manner, the dielectric breakdown behavior of the gate oxide film 12 is measured by applying a voltage.

  At this time, if there is no crystal defect or impurity such as COP (Crystal Originated Particles) in the silicon substrate, the dielectric breakdown of the gate oxide film exhibits intrinsic breakdown characteristics inherent to the oxide film itself. However, when crystal defects or the like are present on the substrate, the insulating properties as the original insulating film are deteriorated, so that the oxide film breakdown electric field strength is lowered when the dielectric breakdown characteristics of the gate oxide film are measured. Therefore, the quality of the silicon substrate 11 can be evaluated by measuring the dielectric breakdown characteristics of the gate oxide film 12.

  On the other hand, in a silicon substrate in which a semiconductor layer is formed on a base substrate, there are cases where electrical contact cannot be made from the back surface of the wafer even if the conventional GOI method is applied. For example, in the above-described SOI wafer or heteroepitaxial wafer, electrical contact cannot be made from the back surface of the wafer due to the presence of a buried oxide film or a semiconductor layer of a different conductivity type, and electrical contact is made on the wafer front side. A ground must be formed separately. In order to solve such a problem, for example, in an SOI wafer, as shown in FIG. 7, a gate oxide film is formed on the surface of an SOI wafer 19 in which a buried oxide film 17 and a silicon layer 16 are sequentially formed on a support substrate 18. In addition to 12 ′ and metal electrode 13 ′, metal wiring 14 for enabling electrical contact on the wafer surface side and isolation oxide film 15 for insulating these metal wirings are formed to evaluate the MOS capacitor. A method for manufacturing the device is disclosed (for example, see Patent Document 1 and Non-Patent Document 1). However, this MOS capacitor has a very complicated structure as compared with the MOS capacitor for bulk wafer evaluation shown in FIG.

  As described above, conventionally, a long and complicated process is required to fabricate a MOS capacitor for evaluation by the GOI method by forming a ground for making electrical contact on the wafer surface side. It takes time. Also, in terms of equipment, in addition to an apparatus necessary for manufacturing an element for bulk wafer evaluation, an oxide film for element isolation (hereinafter sometimes referred to as an interlayer insulating film) is formed by a CVD (Chemical Vapor Deposition) method or the like. Equipment, metal (mainly Al) wiring technology, etc. are required, and a simpler evaluation method is desired.

JP 2002-359362 A IEEE Trans. on Electron Dev. , Vol. 48, no. 2, p307 (2001)

  When evaluating a semiconductor substrate having a semiconductor layer formed on a base substrate, the present invention eliminates the need to form an isolation oxide film, metal wiring, or the like on the surface of the substrate, and improves the quality of the semiconductor substrate easily and in a short time. An object of the present invention is to provide a method and an element for semiconductor substrate evaluation that can be evaluated by the above method.

In order to achieve the above object, the present invention provides a method for evaluating a semiconductor substrate having a semiconductor layer formed on a base substrate, wherein at least a gate oxide film is formed on the outermost surface layer of the semiconductor layer, A gate conductive film is formed on the formed gate oxide film, and at least two adjacent dielectric breakdown electrodes and one evaluation electrode are formed from the formed gate conductive film, and at least between the dielectric breakdown electrodes. An electric field is applied to the gate oxide film, and a process including a step of dielectric breakdown of the gate oxide film is performed. Thereafter, electrical characteristics of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode are evaluated. it that provides an evaluation method of a semiconductor substrate according to claim.

  Thus, when evaluating a semiconductor substrate, first, a gate oxide film and a gate conductive film are sequentially formed on the semiconductor layer, and at least two adjacent dielectric breakdown electrodes and one evaluation electrode are formed by patterning the gate conductive film. And an electrode. After that, an electric field is applied between the breakdown electrodes to perform a breakdown of a part of the gate oxide film, and then the electrical characteristics of the gate oxide film between the breakdown electrode and the evaluation electrode To evaluate. This eliminates the need for conventional processes and devices for forming metal wiring such as interlayer insulating films and aluminum, and processes necessary for patterning them. Cost is not required and the evaluation process is shortened, so that quick evaluation can be performed at low cost.

In this case, the semiconductor layer, Ru can be made to have a different conductivity type from that of the base substrate.
Thus, even if the semiconductor layer has a conductivity type different from that of the base substrate, for example, a heteroepitaxial wafer, according to the present invention, a ground for making electrical contact can be formed on the wafer surface side. Quick evaluation at low cost.

Further, the gate in the step of including a part step of breakdown of the oxide film, further wherein the semiconductor layer located between the breakdown electrodes have preferable that a step of forming a low-resistance layer.
In this way, by performing the step of forming the low resistance layer on the semiconductor layer located between the dielectric breakdown electrodes, the contact resistance between the semiconductor layer and the electrode and the electrode and electrode regardless of the resistivity and thickness of the semiconductor layer. Since the connection resistance between the two is reduced, highly accurate evaluation can be performed.
It should be noted that the effect of the present invention can be obtained by performing either the step of forming the low resistance layer or the step of dielectric breakdown of a part of the gate oxide film first.

Moreover, it is not preferable that the resistance value of the semiconductor layer or the forming a low resistance layer located between the breakdown electrode than 5 k.OMEGA.
Thus, if the resistance value of the semiconductor layer or the low resistance layer located between the dielectric breakdown electrodes is 5 kΩ or less, the contact resistance between the semiconductor layer and the electrode is sufficiently small, and complicated processes and expensive equipment are required. A highly accurate evaluation can be performed more reliably without doing so. When a low resistance layer is formed, it is desirable that the resistance value is low. However, if the resistance value is too low, the doping amount of the dopant becomes too large and affects the characteristics of the evaluation element itself. It is preferable.

Moreover, it can be evaluated a semiconductor substrate on which the semiconductor layer is made of silicon.
In this way, it is possible to evaluate a semiconductor layer made of silicon, which is a material that is widely used for the formation of semiconductor elements, so that the evaluation results can be used widely and effectively for product quality investigation and assurance of various semiconductor elements. can do.

Further, the low-resistance layer has preferably be formed by a thermal diffusion method.
Thus, if the low resistance layer is formed using a thermal diffusion method, the low resistance layer can be formed by doping with a dopant at a relatively low cost.

The present invention is also a semiconductor substrate evaluation element, comprising at least a semiconductor substrate having a semiconductor layer formed on a base substrate, a gate oxide film formed on the outermost surface layer of the semiconductor layer, and the gate formed on the oxide film, that provides a semiconductor substrate for evaluation element characterized is for and at least two adjacent dielectric breakdown electrode for one of the evaluation electrode made of a conductive film.

  As described above, the semiconductor substrate has a semiconductor layer formed on the base substrate, a gate oxide film formed on the outermost surface layer of the semiconductor layer, and at least a conductive film formed on the gate oxide film. In the case of a semiconductor substrate evaluation element having two adjacent dielectric breakdown electrodes and one evaluation electrode, a conventional process and apparatus for forming a metal wiring such as an interlayer insulating film or aluminum, In addition, since it can be manufactured without using the processes necessary for patterning, the cost for introducing and maintaining the equipment is not necessary, and the evaluation process can be shortened, so that the semiconductor substrate can be evaluated quickly at low cost. It becomes an element for evaluation.

In this case, the semiconductor layer, Ru can to have a different conductivity type from that of the base substrate.
Thus, even if the semiconductor layer is a heteroepitaxial wafer having a conductivity type different from that of the base substrate, the semiconductor substrate evaluation element of the present invention can form a ground for making electrical contact on the wafer surface side. Therefore, quick evaluation can be performed at low cost.

Further, the semiconductor layer is not preferable in which the low resistance layer is formed at least between the breakdown electrode.
As described above, if the semiconductor layer has at least a low resistance layer formed between the dielectric breakdown electrodes, the contact resistance between the semiconductor layer and the electrode, the electrode and the electrode, regardless of the resistivity and thickness of the semiconductor layer. Therefore, the semiconductor substrate evaluation element can be evaluated with high accuracy.

Further, the semiconductor layer or the low-resistance layer between the breakdown electrode, it is not preferable resistance value is of less 5 k.OMEGA.
Thus, if the resistance value of the semiconductor layer or the low resistance layer between the dielectric breakdown electrodes is 5 kΩ or less, the contact resistance between the semiconductor layer and the electrode is sufficiently small, and the connection resistance between the electrode and the electrode is also sufficient. This is a small element that can be evaluated with high accuracy. In the case where a low resistance layer is formed, it is desirable that the resistance value is low. However, if the resistance value is too low, the doping amount of the dopant becomes excessive and affects the characteristics of the evaluation element itself. It is preferable to set the degree as the lower limit.

Further, the electrode is not preferably is made of polysilicon.
Thus, if the electrode is made of polysilicon, it is easy to process and is easy to form.

Further, the semiconductor layer, have preferably be made of silicon.
In this way, if it is made of silicon that is widely used for semiconductor element manufacturing, the evaluation results of this evaluation element should be widely and effectively used for the investigation and guarantee of the product quality of various semiconductor elements. Can do.

Further, the gate oxide film is not preferable between the breakdown electrode in which dielectric breakdown portion is formed.
As described above, if the gate oxide film has a dielectric breakdown portion formed between the dielectric breakdown electrodes, the characteristic evaluation can be performed quickly and at low cost by connecting the dielectric breakdown electrode to the ground. it can.

  According to the evaluation method of the present invention, when evaluating a semiconductor substrate in which a semiconductor layer is formed on a base substrate, a conventional process and apparatus for forming a metal wiring such as an interlayer insulating film or aluminum, and a pattern are performed. Therefore, the cost required for introducing and maintaining the equipment is not necessary, and the evaluation process is shortened, so that a quick evaluation can be performed at a low cost.

  In addition, since the element for evaluating a semiconductor substrate of the present invention can be produced without using a conventional process and apparatus for forming a metal wiring such as an interlayer insulating film or aluminum, and a process necessary for patterning, Therefore, the cost for introducing and maintaining the equipment is unnecessary, and the evaluation process is shortened, so that the element for semiconductor substrate evaluation capable of rapid evaluation at low cost is obtained.

Hereinafter, the present invention will be described in detail.
As described above, when applying the conventional GOI method for evaluating the semiconductor layer formed on the base substrate of the semiconductor substrate, a ground for making electrical contact must be separately formed on the wafer surface side. If this is not the case, a long and complicated process is required to manufacture the MOS capacitor, and it takes a long time to complete the evaluation. In addition to equipment necessary for manufacturing an element for bulk wafer evaluation, equipment for forming an interlayer insulating film for element isolation, metal wiring technology, and the like are also required. Therefore, a simpler evaluation method is desired.

  Therefore, the inventors have made a gate oxide film by applying an electric field between the electrodes of two adjacent MOS capacitors after fabricating a MOS capacitor on a semiconductor substrate as a simpler, low-cost and quick evaluation method. After dielectric breakdown occurs in a part of the electrode, connect one of the electrodes to the ground, and evaluate the electrical characteristics of the gate oxide film between the other electrode and the electrode of the other MOS capacitor that was not used for dielectric breakdown And the present invention has been completed.

  In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings in the case of using a heteroepitaxial wafer in which two semiconductor layers having different conductivity types from the base substrate are formed on the base substrate. To do. However, the present invention is not limited to this. For example, a heteroepitaxial wafer in which one semiconductor layer having a conductivity type different from that of the base substrate is formed on the base substrate may be used. A wafer or the like on which one or more semiconductor layers having the same conductivity type as the base substrate are formed may be used.

  FIG. 1 is a schematic sectional view showing an example of a semiconductor substrate evaluation element according to an embodiment of the present invention. In this semiconductor substrate evaluation element 1, for example, an N + layer 3 and an N− layer 4 which are N-type silicon layers having different conductivity types are sequentially laminated on a base silicon substrate 2 having a conductivity type of P-type. The formed heteroepitaxial wafer 5, the gate oxide film 6 formed on the N− layer 4, which is the outermost surface layer of the heteroepitaxial wafer 5, and two adjacent two formed on the gate oxide film 6 At least the dielectric breakdown electrodes 7a and 7b and one evaluation electrode 8 are provided. Here, the dielectric breakdown electrode is an electrode used for applying an electric field for dielectric breakdown of a part of the gate oxide film before the evaluation of the wafer, and the evaluation electrode is evaluated during the evaluation of the wafer. It is an electrode used in order to apply the electric field for. Evaluation terminals 10a and 10b are connected to the evaluation electrode 8 and one dielectric breakdown electrode, for example, the dielectric breakdown electrode 7a, and the other dielectric breakdown electrode 7b is connected to the ground. Alternatively, the dielectric breakdown electrode 7b may be connected to the evaluation terminal 10b, and the dielectric breakdown electrode 7a may be connected to the ground. Three or more dielectric breakdown electrodes may be formed as long as they are adjacent to each other, and two or more evaluation electrodes may be formed. In this case, since the N-layer 4 made of silicon, which is a material generally used for manufacturing semiconductor elements, can be evaluated, the evaluation results of the evaluation elements are used to investigate and guarantee the product quality of various semiconductor elements. It can be used widely and effectively.

If the resistance value of the N-layer 4 between the dielectric breakdown electrodes 7a and 7b is 5 kΩ or less, the contact resistance between the N-layer 4 and the electrodes 7a and 7b is sufficiently small, The connection resistance between the electrodes for destruction (7a, 7b) and between the electrodes for evaluation (8, 7a) is sufficiently small, and the element can be evaluated with high accuracy.
The electrodes 7a, 7b, and 8 are not particularly limited as long as they are made of a conductive film. However, if they are made of polysilicon, they can be easily processed and are easily formed.

  When the N-layer 4 is evaluated using the semiconductor substrate evaluation element 1, an electric field is applied to the dielectric breakdown electrodes 7a and 7b to cause dielectric breakdown of a part of the gate oxide film between the electrodes. It is assumed that a dielectric breakdown portion is formed. An element in which a dielectric breakdown portion is formed in this manner can easily obtain an electrical contact without forming an interlayer insulating film or a metal wiring by using expensive equipment or complicated processes, and can be obtained quickly and at low cost. Characteristic evaluation can be performed.

  FIG. 2 is a schematic cross-sectional explanatory view showing another example of a semiconductor substrate evaluation element according to an embodiment of the present invention. The semiconductor substrate evaluation element 1 is the same as the semiconductor substrate evaluation element of FIG. 1 except that the N-layer 4 is formed by forming a low resistance layer 9 between at least the dielectric breakdown electrodes 7a and 7b. belongs to. The low resistance layer 9 may be formed at a place other than between the dielectric breakdown electrodes 7 a and 7 b, for example, between the dielectric breakdown electrode 7 b and the evaluation electrode 8. If the low resistance layer 9 is formed in this way, the contact resistance between the N− layer 4 and the electrodes 7a, 7b, 8 is reduced, and between the dielectric breakdown electrodes (7a, 7b) and for evaluation purposes. The connection resistance between the electrodes (8, 7a) is sufficiently small, and the element can be evaluated with high accuracy. Further, it is preferable that the low resistance layer 9 has a resistance value of 5 kΩ or less because more accurate evaluation can be performed. The resistance value of the low resistance layer 9 is preferably lower. However, if the resistance value is too low, the doping amount of the dopant will increase and affect the characteristics of the evaluation element itself. preferable.

  Next, a method for producing such a semiconductor substrate evaluation element and evaluating the semiconductor substrate will be described. 3A to 3F are process diagrams illustrating an example of a semiconductor substrate evaluation method according to the present invention.

  First, for example, a heteroepitaxial wafer 5 is prepared as a pre-process. As described above, the heteroepitaxial wafer 5 is formed by sequentially laminating the N + layer 3 and the N− layer 4 which are N-type silicon layers having different conductivity types on the P-type base silicon substrate 2. Is formed. As described above, since the heteroepitaxial wafer having the semiconductor layer made of silicon can be evaluated, the evaluation result can be widely and effectively used for investigation and guarantee of product quality of various semiconductor elements.

Next, as shown in FIG. 3A, the heteroepitaxial wafer 5 is oxidized by a normal method such as thermal oxidation to form a gate oxide film 6 on the N-layer 4 which is the outermost surface layer. The thickness of the gate oxide film is not particularly limited, but is usually about 5 to 30 nm.
Next, as shown in FIG. 3B, a gate conductive film is formed over the gate oxide film. The gate conductive film is generally a polysilicon film, and is deposited using, for example, a CVD method. This polysilicon film is generally doped with phosphorus to lower the resistance value. The phosphorus doping method is not particularly limited, and may be performed by a thermal diffusion method or the like after deposition of the polysilicon film, but a Doped Poly-Si method in which phosphorus is also doped at the time of deposition of the polysilicon film can be used.

  Next, as shown in FIG. 3C, an electrode pattern is formed from this polysilicon film by photolithography and etching. At this time, at least two adjacent dielectric breakdown electrodes 7a and 7b and one evaluation electrode 8 are formed. Thus, a plurality of MOS capacitors having a MOS structure in which a gate oxide film and a polysilicon electrode are sequentially stacked on the N− layer are formed.

  Next, as shown in FIG. 3D, an electric field is applied between the two adjacent dielectric breakdown electrodes 7a and 7b to cause a partial breakdown of the gate oxide film 6 so as to make an electrical contact. . The application of this electric field is not particularly limited as long as a part of the gate oxide film can be broken down, and a method of applying a constant voltage or current until a part of the gate oxide film is broken may be used. It is preferable to apply an electrical stress so that the resistance between the two electrodes is 1 kΩ or less. Thus, the influence on the measurement can be reduced by setting the resistance to 1 kΩ or less.

If the resistance does not drop sufficiently at this time, for example, if the resistance of the N-layer 4 which is the outermost surface layer is high, as shown in FIG. 3E, at least insulation is performed using the formed electrode as a mask. A low resistance layer may be formed by doping a dopant into the N-layer located between the breakdown electrodes. If the resistance value of the N-layer located between the dielectric breakdown electrodes or the low resistance layer formed thereon is set to 5 kΩ or less, the contact resistance between the N-layer and the electrode is sufficiently small, and high-accuracy evaluation is more reliably performed. Can be done. For example, the lower limit of the resistance value of the low resistance layer is preferably about 100Ω. The method for forming the low resistance layer is not particularly limited. For example, if a thermal diffusion method in which phosphorus glass (POCl ₃ ) is deposited on the wafer surface and annealed in a nitrogen gas atmosphere is performed, the dopant is also applied to the portion immediately below the electrode periphery. Therefore, the contact resistance between the electrode and the semiconductor layer can be surely reduced, and the cost is low and the productivity is high as compared with the ion implantation method, for example.
Although a gate oxide film is formed between the MOS capacitors, it is an oxide film as thin as, for example, about 25 nm. Therefore, even if phosphorus glass is deposited on the oxide film by annealing, a sufficient N− layer is obtained. It is possible to diffuse the dopant.

After the diffusion of the dopant, the deposited phosphorus glass is removed with, for example, a 2.5% HF aqueous solution. At this time, care must be taken not to etch the gate oxide film around the electrode in order to perform highly accurate measurement.
Note that the step of forming the low resistance layer shown in FIG. 3E may be performed before or after the step of dielectric breakdown of the gate oxide film shown in FIG.

  Next, as shown in FIG. 3F, the electrical characteristics of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode are evaluated. In this evaluation, GOI measurement is performed using one of the MOS capacitors having breakdown and an undestructed MOS capacitor. A MOS capacitor that has already been destroyed has a sufficiently low resistance, and one electrode of this MOS capacitor is connected to the ground to enable highly accurate measurement.

  At this time, when the outermost surface layer is an N-type wafer as in the present embodiment, a positive voltage is applied to the wafer surface side, that is, a voltage is applied to the accumulation side, but when a low resistance layer is formed, A negative voltage, that is, a voltage is applied to the depletion / inversion side on the wafer surface side. On the other hand, when the outermost surface layer is a P-type wafer, a negative voltage is applied to the wafer surface side, that is, a voltage is applied to the accumulation side, but when a low resistance layer is formed, a positive voltage is applied to the wafer surface side. That is, a voltage is applied so as to be on the depletion / inversion side.

  When evaluating the quality of semiconductor layers such as heteroepitaxial wafers by the evaluation method described above, it is necessary for conventional processes and devices for forming metal wiring such as interlayer insulation films and aluminum, and for patterning. Therefore, the cost for introducing and maintaining the equipment is not required, and the evaluation process is shortened, so that a quick evaluation can be performed at a low cost.

EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, it cannot be overemphasized that this invention is not limited to this.
Example 1
As a sample for characteristic evaluation, an IGBT heteroepitaxial wafer having a conductivity type of P type and a diameter of 150 mm was used. This wafer has a buried layer (N + layer) in which N + and N− layers are sequentially deposited (epitaxial growth) on a P-type substrate. At this time, the P-type dopant is boron, and the N-type dopant is arsenic. At this time, the thicknesses of the N + layer and the N− layer were about 6 μm, respectively.

  Next, the wafer is subjected to a thermal oxidation treatment in a dry oxygen atmosphere at 900 ° C. for about 90 minutes to form a gate oxide film having a thickness of 25 nm on the N− layer, and phosphorous is formed on the gate oxide film by a CVD method. A polysilicon layer doped with was deposited. At this time, the thickness of the polysilicon layer was set to about 300 nm, and the phosphorus doping amount was set to about 25Ω / □ in terms of sheet resistance.

Next, after photolithography was performed on this polysilicon layer, wet etching was performed using hydrofluoric acid to form two adjacent dielectric breakdown electrodes and one evaluation electrode, thereby producing a MOS capacitor. All the electrodes had an electrode area of 8 mm ² . In order to remove the oxide film formed on the back surface of the wafer, a resist is applied to the gate oxide film and the electrode on the front surface side of the wafer for protection, and the back surface treatment is performed by wet etching with a dilute HF aqueous solution on the back surface of the wafer. went.

Next, using a tester connected to a full auto prober, a stress current was applied between the dielectric breakdown electrodes to cause dielectric breakdown of the gate oxide film. The stress current was constant at 50 mA, and the application time was 3 seconds. Each electrode had an electrode area of 8 mm ² and a resistance between the electrodes of about 1 kΩ. In this example, it is considered that the resistance can be reduced by the presence of the N + layer. In addition, the prober and wiring which used the measure against noise were used.

Finally, one of the dielectric breakdown electrodes was connected to the ground, a voltage was applied between the evaluation electrode and the other of the dielectric breakdown electrodes, and the N-layer of the outermost surface layer was evaluated by the GOI method. A voltage ramp-up method was used for the voltage application at this time. The application conditions at that time were an averaging time of 20 msec and a step voltage height of 0.25 MV / cm, and the averaging after the voltage step increase. The time was 200 msec.
Such measurement was performed on two heteroepitaxial wafers manufactured under the same conditions. A graph of the IV characteristic obtained at this time is shown in FIG. The IV characteristic curves of the two wafers almost coincided, and it was confirmed that the characteristic evaluation was performed with high reproducibility and high accuracy.

(Example 2)
A heteroepitaxial wafer for bipolar transistor having a P-type conductivity and a diameter of 150 mm was used as a sample for characteristic evaluation. This wafer is obtained by depositing (epitaxial growth) an N-layer on a P-type substrate. At this time, the P-type dopant is boron, and the N-type dopant is arsenic. At this time, the thickness of the N− layer was 6 μm.

  Next, the wafer is subjected to a thermal oxidation treatment in a dry oxygen atmosphere at 900 ° C. for about 90 minutes to form a gate oxide film having a thickness of 25 nm on the N− layer, and phosphorous is formed on the gate oxide film by a CVD method. A polysilicon layer doped with was deposited. At this time, the thickness of the polysilicon layer was set to about 300 nm, and the phosphorus doping amount was set to about 25Ω / □ in terms of sheet resistance.

Next, after photolithography was performed on this polysilicon layer, wet etching was performed using hydrofluoric acid to form two adjacent dielectric breakdown electrodes and one evaluation electrode, thereby producing a MOS capacitor. All the electrodes had an electrode area of 8 mm ² . In order to remove the oxide film formed on the back surface of the wafer, a resist is applied to the gate oxide film and the electrode on the front surface side of the wafer for protection, and the back surface treatment is performed by wet etching with a dilute HF aqueous solution on the back surface of the wafer. went.

Thereafter, phosphorus glass is deposited on the wafer surface at 750 ° C. for 30 minutes, and subsequently annealed at 1000 ° C. for 1 hour in a nitrogen gas atmosphere. A resistance layer was formed.
Next, the phosphorus glass deposited using 2.5% HF aqueous solution was removed. The etching rate at this time was 0.3 nm / sec, and etching was carefully performed using a monitor wafer so that the gate oxide film around the electrode was not etched.

Next, using a tester connected to a full auto prober, a stress current was applied between the dielectric breakdown electrodes to cause dielectric breakdown of the gate oxide film. The stress current was constant at 50 mA, and the application time was 3 seconds. Each electrode had an electrode area of 8 mm ² and a resistance between the electrodes of about 400Ω. In addition, the prober and wiring which used the measure against noise were used.

Finally, one of the dielectric breakdown electrodes was connected to the ground, a voltage was applied between the evaluation electrode and the other of the dielectric breakdown electrodes, and the N-layer of the outermost surface layer was evaluated by the GOI method. A voltage ramp-up method was used for the voltage application at this time. The application conditions at that time were an averaging time of 20 msec and a step voltage height of 0.25 MV / cm, and the averaging after the voltage step increase. The time was 200 msec.
Such measurement was performed on two heteroepitaxial wafers manufactured under the same conditions. FIG. 5 shows a graph of the IV characteristics obtained at this time. The IV characteristic curves of the two wafers almost coincided, and it was confirmed that the characteristic evaluation was performed with high reproducibility and high accuracy.

  In addition, this invention is not limited to the said embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

  For example, in the above embodiment, the case where a heteroepitaxial wafer in which a semiconductor layer having a conductivity type different from that of the base substrate is used on the base substrate has been described. However, the semiconductor layer having the same conductivity type as the base substrate is formed on the base substrate. One or more epitaxial wafers may be used, or a wafer formed with a semiconductor layer on a base substrate may be used without using an epitaxial method.

It is a cross-sectional schematic explanatory drawing which shows an example of the element for semiconductor substrate evaluation according to embodiment of this invention. It is a cross-sectional schematic explanatory drawing which shows another example of the element for semiconductor substrate evaluation according to embodiment of this invention. It is process drawing which shows an example of the evaluation method of the semiconductor substrate according to this invention. 2 is a grab showing IV characteristics of a heteroepitaxial wafer in Example 1. FIG. 6 is a grab showing IV characteristics of a heteroepitaxial wafer in Example 2. It is explanatory explanatory drawing explaining GOI method, (a) is a top view, (b) shows sectional drawing. It is the cross-sectional schematic explaining the method of evaluating an SOI wafer by the conventional GOI method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate evaluation element, 2 ... Base substrate, 3 ... N + layer, 4 ... N- layer,
5 ... heteroepitaxial wafer, 6 ... gate oxide film,
7a, 7b ... dielectric breakdown electrode, 8 ... evaluation electrode, 9 ... low resistance layer,
10a, 10b ... evaluation terminals,
DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12, 12 '... Gate oxide film, 13, 13' ... Metal electrode,
14 ... Metal wiring, 15 ... Isolation oxide film, 16 ... Silicon layer,
17 ... buried oxide film, 18 ... support substrate, 19 ... SOI wafer.

Claims (13)

A method for evaluating a semiconductor substrate in which a semiconductor layer is formed on a base substrate that is a semiconductor, wherein a gate oxide film is formed at least on the outermost surface layer of the semiconductor layer, and a gate is formed on the formed gate oxide film. A conductive film is formed, and at least two adjacent dielectric breakdown electrodes and one evaluation electrode are formed from the formed gate conductive film, and then an electric field is applied between at least the dielectric breakdown electrodes to form the gate. Performing a step including a step of dielectric breakdown of a part of the oxide film, and thereafter evaluating an electrical characteristic of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode. Evaluation methods.   The semiconductor substrate evaluation method according to claim 1, wherein the semiconductor layer has a conductivity type different from that of the base substrate.   2. The method according to claim 1, further comprising the step of forming a low resistance layer in the semiconductor layer located between the dielectric breakdown electrodes in the step including the step of dielectric breakdown of a part of the gate oxide film. 2. The method for evaluating a semiconductor substrate according to 2. Evaluation method of a semiconductor substrate according to 請 Motomeko 3 you, characterized in that the resistance value of the semiconductor layer or the forming a low resistance layer located between the breakdown electrode less than 100 [Omega 5 k.OMEGA.   The semiconductor substrate evaluation method according to claim 1, wherein the semiconductor layer is a semiconductor substrate made of silicon.   The semiconductor substrate evaluation method according to claim 3, wherein the low resistance layer is formed by a thermal diffusion method. A semiconductor substrate evaluation element comprising at least a semiconductor substrate having a semiconductor layer formed on a base substrate which is a semiconductor, a gate oxide film formed on an outermost surface layer of the semiconductor layer, and the gate oxide film A semiconductor substrate evaluation element, comprising: at least two adjacent dielectric breakdown electrodes made of a conductive film and one evaluation electrode.   The semiconductor substrate evaluation element according to claim 7, wherein the semiconductor layer has a conductivity type different from that of the base substrate.   The element for evaluating a semiconductor substrate according to claim 7 or 8, wherein the semiconductor layer is a layer in which a low resistance layer is formed at least between the dielectric breakdown electrodes. The breakdown electrode between the semiconductor layer or the low-resistance layer of a semiconductor substrate evaluation device according to 請 Motomeko 9 you, wherein the resistance value is of less than 100 [Omega 5 k.OMEGA.   The element for evaluating a semiconductor substrate according to any one of claims 7 to 10, wherein the electrode is made of polysilicon.   The element for evaluating a semiconductor substrate according to claim 7, wherein the semiconductor layer is made of silicon.   13. The element for evaluating a semiconductor substrate according to claim 7, wherein the gate oxide film has a dielectric breakdown portion formed between the dielectric breakdown electrodes.

Images