JP4568118B2 - Power semiconductor element - Google Patents

Description

  The present invention relates to a power semiconductor element used for power control. In particular, the present invention relates to a lateral power FET using a nitride semiconductor, a Schottky barrier diode (SBD), and the like.

  In power control circuits such as switching power supplies and inverter circuits, power semiconductor elements such as switching elements and diodes are used. The characteristics required for the power semiconductor element are a high breakdown voltage characteristic and a low on-resistance characteristic. There is a trade-off relationship determined by the element material between the breakdown voltage and the on-resistance in the power semiconductor element. Due to the progress of technological development so far, low on-resistance of power semiconductor elements has been realized to the limit of silicon, which is the main element material. In order to further reduce the on-resistance, it is necessary to change the element material. A wide band gap semiconductor such as a nitride semiconductor such as GaN or AlGaN or silicon carbide (SiC) is used as the switching element material. In this way, the trade-off relationship determined by these materials can be improved, and a low on-resistance can be achieved. A HEMT (High Electron Mobility Transistor) using a nitride semiconductor such as GaN or AlGaN is disclosed in the following document. This document is `` p-Capped GaN-AlGaN-GaN High-Electron Mobility Transistors (HEMTs) '' by R. Coffie et al, IEEE ELECTRON DEVICE LETTERS, VOL.23, No.10.OCTOBER 2002, pp. 598-590. It is.

  Currently, research on power semiconductor devices using wide band gap semiconductors is actively conducted. In nitride semiconductor elements such as GaN, low on-resistance is realized. However, a design that takes into consideration the characteristics unique to the power element such as avalanche resistance has not been performed. This is because GaN-based elements are designed based on radio frequency (RF) elements.

  In the FET, the field voltage can be increased by providing a field plate electrode. Such a technique is described in JP-A-5-21793, JP-A-2001-230263, Japanese Patent No. 3271613, and the like.

  An object of the present invention is to provide a power semiconductor device having a high avalanche resistance and an ultra-low on-resistance.

According to the present invention, a first semiconductor layer made of non-doped Al _X Ga _1-X N (0 ≦ X ≦ 1), and a non-doped or n-type Al formed on one surface of the first semiconductor layer. _A second semiconductor layer made of _Y Ga _1-Y N (0 ≦ Y ≦ 1, X <Y), and a p-type Al _Z Ga _1-Z N selectively formed on the second semiconductor layer. A third semiconductor layer made of (0 ≦ Z ≦ 1), a drain electrode formed on the second semiconductor layer located on one side of both sides of the third semiconductor layer, and the third semiconductor layer A source electrode formed on the second semiconductor layer located on the other side of both sides of the semiconductor layer and adjacent to the third semiconductor layer at least between the third semiconductor layer and the drain electrode An insulating film formed on the second semiconductor layer at a position, and formed on the insulating film A field plate electrode, and a gate electrode formed on the third semiconductor layer. The field plate electrode is electrically connected to a source electrode, and is disposed on the drain electrode side of the third semiconductor layer. The end portion extends from the drain electrode side end portion of the gate electrode to the drain electrode side, and the third semiconductor layer is formed so that the end portion on the drain electrode side is located below the field plate electrode, The thickness of the insulating film located below the field plate electrode is t, the relative dielectric constant of the insulating film is ε _i , the relative dielectric constant of the second semiconductor layer is ε _s , and the drain electrode side of the third semiconductor layer is the distance from end to end of the drain electrode side of the field plate electrode when is L, the thickness t of the insulating film is set so that the relationship shown below, satisfy the ε _{s t>} ε _{i L} Half the power Body element is provided.

  The power semiconductor device according to the present invention generates a two-dimensional electron gas having high mobility by combining an AlGaN heterojunction structure, and lowers the on-resistance by using this as a carrier during conduction. Further, a nitride semiconductor having a large band gap is used, and a field plate structure is used, thereby realizing a high breakdown voltage. In addition, by forming a p-type AlGaN layer on the surface of the semiconductor region, holes generated during avalanche breakdown can be quickly discharged, and a high avalanche resistance can be obtained. The point where the avalanche breakdown occurs is in the semiconductor, that is, the pn junction surface, and is not the interface between the semiconductor and the passivation film such as the end of the field plate electrode. Thereby, there is no instability of the interface due to heat, and a highly reliable element can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected and demonstrated to the location corresponding over all the figures.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a configuration of a junction type power HEMT (High Electron Mobility Transistor) according to a first embodiment of the present invention.

The HEMT is provided with a channel layer 1 made of a GaN layer (X = 0) as non-doped Al _X Ga _1-X N (0 ≦ X ≦ 1). The thickness of the channel layer 1 is set to about 1 to 2 μm in order to obtain a withstand voltage of 600V. On the surface (one side) of the channel layer 1, a barrier layer 2 having a thickness of 0.02 μm is formed as n-type Al _Y Ga _1-Y N (0 ≦ Y ≦ 1, X <Y). Yes. The barrier layer 2 includes an Al _0.2 Ga _0.8 N layer (Y = 0.2) doped with Si at a dose of about 10 ¹³ (atom / cm ² ) as an impurity. Further, on the barrier layer 2, a semiconductor layer 3 having a thickness of 0.01 μm is formed as a p-type Al _Z Ga _1-Z N (0 ≦ Z ≦ 1) layer. The semiconductor layer 3 includes an Al _0.1 Ga _0.9 N layer (Z = 0.1) doped with Mg as an impurity.

  On the barrier layer 2 on both sides of the semiconductor layer 3, a drain electrode (D: first electrode) 4 and a source electrode (S: second electrode) 5 made of Ti / Al / Ni / Au are provided. They are formed separately from each other. The drain and source electrodes 4 and 5 are electrically connected to the surface of the barrier layer 2, respectively.

  A gate electrode (G: control electrode) 6 made of Pt or Ni / Au is formed on the semiconductor layer 3. The gate electrode 6 is electrically connected to the surface of the semiconductor layer 3.

  An insulating film 7 is formed so as to continuously cover the gate electrode 6 and the surrounding barrier layer 2. A field plate electrode 8 made of Ti / Al / Ni / Au is formed on the insulating film 7 so as to be positioned between the gate electrode 6 and the drain electrode 4. The field plate electrode 8 is electrically connected to the source electrode 5.

  The HEMT configured as described above operates as a junction type FET in which the depth of a depletion layer formed in the surface region of the channel layer 1 is controlled according to the voltage applied to the gate electrode 6. Therefore, the current flowing between the source and drain electrodes 5 and 4 is controlled according to the depth of the depletion layer.

In the HEMT of the first embodiment, a nitride semiconductor such as Al _X Ga _1-X N, Al _Y Ga _1-Y N, or Al _Z Ga _1-Z N having a wide band gap is used as an element material. For this reason, the critical electric field can be increased, and a high breakdown voltage of the element can be realized. A field plate electrode 8 is formed between the gate and the drain that determine the breakdown voltage. For this reason, the electric field applied between the gate electrode 6 and the drain electrode 4 at the time of voltage application can be relieved, and the fall of a proof pressure can be suppressed. Since a two-dimensional electron gas with high mobility is formed at the AlGaN / GaN hetero interface composed of the barrier layer 2 and the channel layer 1, low on-resistance is realized.

  A p-type semiconductor layer 3 is further formed on the n-type barrier layer 2. For this reason, when an avalanche breakdown occurs in the device, the generated holes promptly flow into the p-type semiconductor layer 3, thereby realizing a high avalanche resistance.

  In addition, since the p-type semiconductor layer 3 is formed on the barrier layer 2, the following effects can be obtained, that is, the gate leakage current is reduced.

  In a normal HEMT structure, the breakdown voltage is determined by the electric field applied to the Schottky junction in the gate portion. In contrast, in the HEMT structure of the above embodiment, the breakdown voltage is determined by the electric field applied to the pn junction between the p-type semiconductor layer 3 and the n-type barrier layer. That is, the breakdown point is in the semiconductor layer as compared with the case where the characteristic variation of the element such as the Schottky junction is likely to increase. For this reason, the following effects, that is, the effect that the variation in breakdown voltage is suppressed can be obtained.

  Further, in a normal HEMT structure or the like, a high electric field is generated at a semiconductor-passivation film or metal interface, such as a gate Schottky interface or a field plate edge. Therefore, if a design in which avalanche breakdown occurs at these points is performed, characteristic fluctuations due to heat tend to occur. However, in the HEMT structure of the above embodiment, the breakdown point is a pn junction in the semiconductor layer. For this reason, the stability of the avalanche breakdown is increased, and a highly reliable device can be realized.

  By connecting the field plate electrode 8 to the source electrode 5, the gate / drain capacitance is reduced, and a high-speed switching operation can be realized.

The semiconductor layer 3 made of a p-type Al _0.1 Ga _0.9 N layer is formed uniformly by crystal growth together with the channel layer 1 and the barrier layer 2. Thereafter, the semiconductor layer 3 may be formed by patterning by etching. Alternatively, the semiconductor layer 3 may be formed by crystal growth and then selectively oxidized. Alternatively, after crystal growth of the channel layer 1 and the barrier layer 2, the semiconductor layer 3 may be formed on the surface by selective growth.

(First modification of the first embodiment)
FIG. 2 is a cross-sectional view schematically showing a configuration according to a first modification of the power HEMT shown in FIG. In the power HEMT of FIG. 1, the insulating film 7 is continuously formed on the gate electrode 6 and the surrounding barrier layer 2, and the field plate electrode 8 is electrically connected to the source electrode 5.

  In contrast, the power HEMT of FIG. 2 has the following structure. That is, the insulating film 7 is formed so as to be located between the semiconductor layer 3 and the drain electrode 4 and adjacent to the semiconductor layer 3. The gate electrode 6 is formed not only on the semiconductor layer 3 but also on the insulating film 7. That is, in the first modification, the gate electrode 6 also serves as the field plate electrode 8 shown in FIG.

  In the power HEMT of this modification, the same effect as in FIG. 1 can be obtained, and the field plate electrode and the gate electrode can be formed at a time. For this reason, the following effects are acquired. That is, the manufacturing process can be simplified as compared with FIG.

(Second modification of the first embodiment)
FIG. 3 is a cross-sectional view schematically showing a configuration according to a second modification of the power HEMT shown in FIG. The power HEMT in FIG. 3 is different from that in FIG. 1 in that the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3.

  That is, in the power HEMT of FIG. 3, the gate electrode 6 forms a Schottky junction with the barrier layer 2.

  In the second modification, the gate electrode 6 is Schottky connected to the barrier layer 2. However, since the semiconductor layer 3 is connected to the gate electrode 6, hole discharge at the time of avalanche breakdown is performed through the semiconductor layer 3, and a high avalanche resistance is realized as in the case of FIG. 1. In addition, the same effect as in FIG. 1 can be obtained.

(Third Modification of First Embodiment)
FIG. 4 is a cross-sectional view schematically showing a configuration according to a third modification of the power HEMT shown in FIG. In the power HEMT of FIG. 3, the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3. On the other hand, in the power HEMT of FIG. 4, the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the source electrode 5 side of the semiconductor layer 3.

  Also in the case of the third modification, the gate electrode 6 is Schottky connected to the barrier layer 2. However, since the semiconductor layer 3 is connected to the gate electrode 6, hole discharge at the time of avalanche breakdown is performed through the semiconductor layer 3, and a high avalanche resistance is realized as in the case of FIG. 1. In addition, the same effect as in FIG. 1 can be obtained.

(Second Embodiment)
FIG. 5 is a cross-sectional view schematically showing a configuration of a junction type power HEMT according to the second embodiment of the present invention. In the power HEMT of FIG. 1, the semiconductor layer 3 made of a p-AlGaN layer has the same length as the gate electrode 6. That is, the position of the end of the semiconductor layer 3 on the drain electrode 4 side and the end of the gate electrode 6 on the drain electrode 4 side coincide with each other.

  On the other hand, in the power HEMT of the second embodiment, the end of the semiconductor layer 3 made of the p-AlGaN layer on the drain electrode 4 side extends from the end of the gate electrode 6 on the drain electrode 4 side to the drain electrode 4 side. It has been extended. Further, the semiconductor layer 3 is formed so that the end on the drain electrode 4 side is located below the field plate electrode 8.

  6A is a cross-sectional view showing the vicinity of the end of the semiconductor layer 3 of the power HEMT in FIG. 5, and FIG. 6B is an electric field in the barrier layer 2 when the power HEMT in FIG. 5 is operated. It is a characteristic view which shows the mode of distribution.

  As shown in FIG. 5, the end of the semiconductor layer 3 on the drain electrode 4 side is formed so as to be positioned below the field plate electrode 8. As a result, as shown in FIG. 6B, the points where the electric field concentrates become the end portion of the semiconductor layer 3 and the end portion of the field plate electrode 8. In FIG. 6B, a characteristic curve (line) 21 is when the insulating film 7 is thick to some extent, and a characteristic curve 22 is when the insulating film 7 is thin to some extent.

  That is, when the thickness of the insulating film 7 under the field plate electrode 8 is appropriately increased, the point at which the electric field is highest, which is the point at which avalanche breakdown occurs, is set at the end of the semiconductor layer 3. As a result, holes are discharged quickly at the time of avalanche breakdown, and sufficient avalanche resistance is ensured.

A method for setting the thickness of the insulating film 7 so that the electric field at the end of the semiconductor layer 3 is the highest will be described below. FIG. 7A is a cross-sectional view showing the vicinity of the end of the semiconductor layer 3 of the power HEMT of FIG. FIG. 7B is a characteristic diagram showing the state of electric field distribution in the plane direction when the power HEMT of FIG. 5 is operated. FIG. 7C is a characteristic diagram showing a state of electric field distribution in the vertical direction when the power HEMT of FIG. 5 is operated. 7B and 7C, the point at the end of the semiconductor layer 3 on the drain electrode 4 side is the point A, the point of the barrier layer 2 immediately below the end of the field plate electrode 8 is the point B, and the field plate electrode The point at the end of 8 is designated as point C. The electric fields at points A to C are defined as E _A , E _B , and E _C , respectively. Further, the distance between the points A and B, that is, the length of the field plate electrode 8 is L, and the thickness of the insulating film 7 is t.

From the magnitude of the electric field at each point and the dimensions of each part, the voltage V _AB between the points A and B and the V _CB between the points C and B are expressed by the following equations (1) and (2), respectively. Is done.

V _AB = (E _A + E _B ) L / 2 (1)
V _CB = E _C t (2)
Since the potential of the field plate electrode 8 is substantially equal to the potential of the semiconductor layer 3, V _AB is equal to V _CB . Since the electric flux density is continuous, the relationship between E _B and E _C is expressed by the following equation (3).

ε _i · E _C = ε _s E _B (3)
Here, ε _i is the relative dielectric constant of the insulating film 7, and ε _s is the relative dielectric constant of the barrier layer 2. By modifying the above equation (1) to (3), obtaining the relationship between _{E A} and _{E B.} This relationship is expressed by the following equation (4).

_{E A / E B = 2ε s} t / ε i L-1 ... (4)
The E _A is set to be larger than E _B becomes to increase the avalanche resistance. Therefore, the ratio of E _A and E _B expressed by the equation (4) only needs to be larger than 1. Thus, the following equation (5) can be obtained by modifying equation (4).

_{ε s t> ε i L ...} (5)
It is desirable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so as to satisfy the relationship of the expression (5).

If the length L of the field plate electrode is 2 μm, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 made of an AlGaN layer is 0.2, the relative dielectric constant ε _i is 3.9 and ε _s is 9.3. It becomes. Therefore, the thickness t of the insulating film 7 is desirably 0.83 μm or more.

In a wide band gap semiconductor such as AlGaN or GaN, the critical electric field is close to the dielectric breakdown electric field of the insulating film. When the dielectric breakdown voltage of the insulating film 7 is smaller than the avalanche breakdown voltage, the element breakdown voltage is determined by the dielectric breakdown voltage. In this case, when a voltage corresponding to the element withstand voltage is applied to the element, the element is destroyed. If the critical electric field of the semiconductor layer and the dielectric breakdown electric field of the insulating film are equal, the electric field E _C at the point C shown in FIG. 7C is made smaller than the electric field E _{A at the} point A shown in FIG. Thus, dielectric breakdown can be avoided.

By modifying the above (1) to (3), when determining the relationship between E _A and E _C, this relationship is expressed by the following equation (6).

E _A / E _C = 2t / L−ε _i / ε _s (6)
Since the ratio expressed by the above equation (6) is larger than 1, dielectric breakdown can be avoided. Accordingly, it is desirable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so as to satisfy the following expression (7).

2t / L> (1 + ε _i / ε _s ) (7)
Similarly to the above, when the length of the field plate electrode is 2 μm, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 made of the AlGaN layer is 0.2, the relative dielectric constant ε _i is 3.9, ε _s is 9.3. Therefore, the thickness t of the insulating film 7 is desirably 1.4 μm or more.

(Third embodiment)
FIG. 8 is a cross-sectional view schematically showing a configuration of a junction type power HEMT according to the third embodiment of the present invention. Since the breakdown voltage of the lateral power element as shown in FIG. 1 is determined by the distance between the gate and the drain, it is desirable to increase the breakdown voltage. Then, the interval between the source and the gate not related to the withstand voltage is reduced. This leads to a reduction in on-resistance. In the power HEMT of the third embodiment, the distance between the gate and the drain is made wider than the distance between the gate and the source in order to achieve a high breakdown voltage and a low on-resistance. That is, the interval Lgd is made wider than the interval Lgs. The interval Lgd is the distance between the end of the gate electrode 6 on the drain electrode 4 side and the end of the drain electrode 4 on the gate electrode 4 side. The interval Lgs is the distance between the end of the gate electrode 6 on the source electrode 5 side and the end of the source electrode 5 on the gate electrode 6 side.

  FIG. 8 shows a case where the end of the semiconductor layer 3 on the drain electrode 4 side is located below the field plate electrode 8. However, the third embodiment is not limited to this, and the semiconductor layer 3 is formed so that the end on the drain electrode 4 side coincides with the end of the gate electrode 6 as shown in FIG. It may be. As shown in FIGS. 3 and 4, the gate electrode 6 extends to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3 or the barrier layer 2 adjacent to the source electrode 5 side of the semiconductor layer 3. It may be formed extending to the surface.

(Fourth embodiment)
FIG. 9 is a cross-sectional view schematically showing the structure of a junction type power HEMT according to the fourth embodiment of the present invention. The power HEMT shown in FIG. 9 differs from that of FIG. 1 in the following points. That is, the semiconductor layer 9 made of a GaN layer (W = 0) doped with, for example, Mg as an impurity as P-type AlwGa _1-w N (0 ≦ W ≦ 1) is formed on the back surface (the other surface) of the channel layer 1. Formed on top. A back electrode 10 made of Pt is formed on the surface of the semiconductor layer 9. In this case, the back electrode 10 is electrically connected to the source electrode 5.

  In the power HEMT having such a structure, holes generated when avalanche breakdown occurs are also discharged through the semiconductor layer 9 and the back electrode 10, so that the avalanche resistance can be further increased.

(Modification of the fourth embodiment)
FIG. 10 shows a cross-sectional view of a modification of the fourth embodiment. As shown in FIG. 10, the thickness td of the channel layer 1 is made smaller than the distance Lgd between the gate electrode 6 and the drain electrode 4. This makes it difficult for avalanche breakdown to occur at the junction between the channel layer 1 and the semiconductor layer 9, and the breakdown voltage is determined by the thickness of the channel layer 1. In this case, since the thickness of the channel layer 1 can be controlled during crystal growth, an element with little variation in breakdown voltage can be manufactured. In addition, since the concentration of impurities contained in the semiconductor layer 9 is high, it is possible to quickly discharge holes, and high avalanche resistance can be expected.

  In the HEMT according to the fourth embodiment and its modification, the contact with the semiconductor layer 9 formed on the back surface side of the channel layer 1 is taken out from the back surface of the substrate. However, the contact with the semiconductor layer 9 may be taken out from the same surface as the source electrode 5. In this case, a conductive substrate is not necessary.

  The p-type semiconductor layer 9 desirably has the same band gap as the channel layer 1 or a narrower band gap than the channel layer 1 in order to quickly discharge holes generated in the channel layer 1. Therefore, the composition ratio W of the semiconductor layer 9 is desirably the same as or smaller than the composition ratio X of the channel layer 1.

(Fifth embodiment)
FIG. 11 is a cross-sectional view schematically showing the structure of a lateral GaN-MISFET according to the fifth embodiment of the present invention.

  In the MISFET of this embodiment, a gate insulating film 11 is added to the HEMT shown in FIG. That is, the gate insulating film 11 is formed so as to continuously cover the semiconductor layer 3 and the surrounding barrier layer 2. The gate electrode 6 is formed on the gate insulating film 11 located on the semiconductor layer 3. In this case, an opening is opened in a part of the gate insulating film 11, and the semiconductor layer 3 is electrically connected to the gate electrode 6 through the opening.

  In the MISFET having such a structure, an inversion channel portion is formed in the surface region of the channel layer 1 in accordance with the voltage applied to the gate electrode 6. The current flowing between the source electrode 5 and the drain electrode 4 is controlled according to the formation state of the inversion channel portion.

In the MISFET of the above-described embodiment, a nitride semiconductor such as Al _X Ga _1-X N, Al _Y Ga _1-Y N, or Al _Z Ga _1-Z N having a wide band gap is used as an element material. For this reason, the critical electric field can be increased, and a high breakdown voltage of the element can be realized. Further, a field plate electrode 8 is formed between the gate and the drain that determine the breakdown voltage. For this reason, the electric field applied between the gate electrode 6 and the drain electrode 4 at the time of voltage application can be relieved, and the fall of a proof pressure can be suppressed. In addition, since a two-dimensional electron gas having high mobility is formed at the AlGaN / GaN hetero interface composed of the barrier layer 2 and the channel layer 1, low on-resistance can be realized.

  A p-type semiconductor layer 3 is formed on the n-type barrier layer 2. For this reason, when an avalanche breakdown occurs in the device, the generated holes promptly flow into the p-type semiconductor layer 3, thereby realizing a high avalanche resistance.

  Further, since the p-type semiconductor layer 3 is formed on the barrier layer 2, an effect that the gate leakage current is reduced can be obtained.

  In the structure of the above embodiment, the withstand voltage is determined by the electric field at the pn junction between the p-type semiconductor layer 3 and the n-type barrier layer 2. As a result, since the breakdown point is in the semiconductor layer, the effect of suppressing variations in breakdown voltage can be obtained.

  Furthermore, in the structure of the above embodiment, the breakdown point is a pn junction in the semiconductor layer. For this reason, the stability of the avalanche breakdown is increased, and a highly reliable device can be realized.

  Further, since the field plate electrode 8 is connected to the source electrode 5, the capacitance between the gate and the drain is reduced, and a high-speed switching operation can be realized.

  Since the semiconductor layer 3 is electrically connected to the gate electrode 6, an effect that the gate leakage current can be reduced is also obtained.

(First Modification of Fifth Embodiment)
FIG. 12 shows a MISFET according to a first modification of the fifth embodiment. As shown in the MISFET of FIG. 12, the semiconductor layer 3 may be isolated from the gate electrode 6 without opening an opening in the gate insulating film 11. In the MISFET having such a structure, the gate leakage current can be extremely reduced.

  In this case, since the semiconductor layer 3 is not electrically connected to the gate electrode 6, the semiconductor layer 3 is in a floating state in terms of potential, and holes cannot be discharged to the semiconductor layer 3. For this reason, in the MISFET of this modification, a part of the source electrode 5 is formed to extend to the upper part of the semiconductor layer 3. By doing so, the semiconductor layer 3 is electrically connected to the source electrode 5. Thereby, the avalanche current flows into the source electrode 5 through the semiconductor layer 3 and does not flow into the gate electrode 6. This reduces the burden on the gate drive circuit that drives the gate electrode 6.

Note that it is desirable that the gate insulating film 11 has few interface states with the semiconductor layer 3. Therefore, it is desirable to use the following insulating film as the gate insulating film 11. The insulating film includes an oxide film and, _Al 2 _O 3 deposited by a CVD method, an insulating film such as SiN, such as _Al x _{Ga 2-x O 3} film obtained by oxidizing the AlGaN layer.

  If the impurity concentration of the semiconductor layer 3 is too high, the controllability of the inversion channel portion generated by the voltage applied to the gate electrode 6 is deteriorated, that is, the mutual conductance of the gate electrode 6 is reduced. On the contrary, if the impurity concentration of the semiconductor layer 3 is too low, the discharge resistance when holes are discharged increases. Therefore, from both viewpoints, it is desirable that the impurity concentration of the semiconductor layer 3 is approximately the same as that of the barrier layer 2.

(Second Modification of Fifth Embodiment)
13A and 13B are a cross-sectional view and a top view schematically showing the configuration of the power MISFET shown in FIG. 12 according to the second modification. In the power MISFET of FIG. 12, the semiconductor layer 3 is formed on the entire surface in the gate width direction.

  On the other hand, in the power MISFET of FIGS. 13A and 13B, the semiconductor layer 3 is formed in a strip shape in the gate width direction. With the semiconductor layer 3 having such a shape, the gate threshold voltage and the on-resistance can be controlled.

  When the semiconductor layer 3 is formed in a strip shape, both a portion where the semiconductor layer 3 is formed and a portion where the semiconductor layer 3 is not formed are formed under the gate. The portion where the semiconductor layer 3 is formed under the gate has a high gate threshold voltage, and the channel resistance and the offset resistance between the gate and the source are large. Conversely, the portion where the semiconductor layer 3 is not formed under the gate has a low gate threshold voltage, and the channel resistance and the gate-source offset resistance are small.

  Since the entire element is the same as that both parts operate in parallel, the threshold voltage and the on-resistance can be controlled by changing the interval and density of the strips of the semiconductor layer 3. .

(Sixth embodiment)
FIG. 14 is a cross-sectional view schematically showing the structure of a lateral GaN-Schottky barrier diode (SBD) according to the sixth embodiment of the present invention.

In this SBD, a channel layer 1 made of a non-doped GaN layer is provided as in the case of the FET shown in FIG. On the surface of the channel layer 1, a barrier layer 2 composed of an n-type Al _0.2 Ga _0.8 N layer (Y = 0.2) is formed. Furthermore, a plurality of semiconductor layers 3 made of p-type Al _0.1 Ga _0.9 N layers are selectively formed on the barrier layer 2.

  An anode electrode (A: second electrode) 12 made of Ni / Au is formed on the plurality of semiconductor layers 3 and the surrounding barrier layer 2 so as to continuously cover them. An insulating film 7 is formed on the barrier layer 2 so as to be in contact with the anode electrode 12. A field plate electrode 8 made of Ni / Au is formed on the insulating film 7. The field plate electrode 8 is electrically connected to the anode electrode 12. Further, a cathode electrode (K: first electrode) 13 made of Ti / Al / Ni / Au and separated from the anode electrode 12 is formed on the barrier layer 2.

  In the SBD of the sixth embodiment, an n-AlGaN / GaN heterostructure including a barrier layer 2 and a channel layer 1 is used as in the HEMT described above. As a result, high breakdown voltage and ultra-low on-resistance can be realized.

  A semiconductor layer 3 made of a p-AlGaN layer is formed on the barrier layer 2 made of an n-AlGaN layer. Thereby, the hole discharge at the time of avalanche breakdown can be secured, and high voltage withstand capability can be expected. Further, since the semiconductor layer 3 is formed as described above, the Schottky junction area where the anode electrode 12 and the barrier layer 2 are in direct contact with each other can be reduced, and the reverse leakage current can be reduced.

(Seventh embodiment)
FIG. 15 is a cross-sectional view schematically showing the structure of a Schottky barrier diode (SBD) according to the seventh embodiment.

  In the SBD of the seventh embodiment, the semiconductor layer 3 is formed at the end of the Schottky junction. In this case, the end of the semiconductor layer 3 on the cathode electrode 13 side is located between the end of the field plate electrode 8 on the cathode electrode 13 side and the end of the anode electrode 12 on the cathode electrode 13 side.

  16A is an enlarged cross-sectional view showing the vicinity of the end of the semiconductor layer 3 of the SBD of FIG. 15, and FIG. 16B is an electric field distribution in the barrier layer 2 when the SBD of FIG. 15 is operated. It is a characteristic view which shows the mode of.

  As shown in FIG. 15, the semiconductor layer 3 is formed so that the end portion on the cathode electrode 13 side is positioned below the field plate electrode 8. In this case, as shown in FIG. 16B, the points where the electric field concentrates are the end of the semiconductor layer 3 and the end of the field plate electrode 8. In FIG. 16B, the characteristic curve 23 is when the film thickness of the insulating film 7 is thick to some extent, and the characteristic curve 24 is when the film thickness of the insulating film 7 is thin to some extent.

  That is, also in the SBD, the film thickness t of the insulating film 7 is set so as to satisfy the relationships of the expressions (5) and (7) as in the case of the HEMT of the second embodiment. As a result, it is possible to ensure avalanche resistance and avoid breakdown of the insulating film.

  The present invention has been described with reference to the first to seventh embodiments. However, the present invention is not limited to the above embodiment, and all other modifications that can easily be considered by those skilled in the art can be applied.

  For example, the semiconductor layer 3 made of a p-AlGaN layer used for hole discharge desirably has a narrower band gap than the barrier layer 2 made of an n-AlGaN layer from the viewpoint of hole discharge. That is, it is desirable that the Al composition ratio is small, and a p-GaN layer can also be used. Further, in order to reduce the contact resistance with respect to the semiconductor layer 3, a semiconductor layer having a narrow band gap such as an InGaN layer is used as the contact layer. This contact layer may be formed between the gate electrode 6 or the anode electrode 12 and the semiconductor layer 3.

  In each of the above embodiments, a combination of AlGaN / GaN is used as the element material. In this case, a combination of GaN / InGaN or AlN / AlGaN may be used.

  Further, the present invention is not limited to a junction type FET unipolar element. In this case, the present invention can be easily implemented as long as it is a lateral element even if it is a bipolar element such as an IGBT in which a p layer is provided on the drain side of a pin diode or MISFET.

  As described above, according to the present invention, a lateral GaN power device having a high avalanche resistance, a high breakdown voltage and an ultra-low on-resistance can be obtained.

Sectional drawing which shows typically the power semiconductor element of the 1st Embodiment of this invention. Sectional drawing which shows typically the power semiconductor element of the 1st modification of 1st Embodiment. Sectional drawing which shows typically the power semiconductor element of the 2nd modification of 1st Embodiment. Sectional drawing which shows typically the power semiconductor element of the 3rd modification of 1st Embodiment. Sectional drawing which shows typically the power semiconductor element of the 2nd Embodiment of this invention. (A) And (B) is sectional drawing and characteristic view used in order to demonstrate the said 2nd Embodiment. (A) thru | or (C) are sectional drawing and characteristic view used in order to demonstrate the said 2nd Embodiment. Sectional drawing which shows typically the power semiconductor element of the 3rd Embodiment of this invention. Sectional drawing which shows typically the power semiconductor element of the 4th Embodiment of this invention. Sectional drawing which shows typically the power semiconductor element of the modification of 4th Embodiment. Sectional drawing which shows typically the power semiconductor element of the 5th Embodiment of this invention. Sectional drawing which shows typically the power semiconductor element of the 1st modification of 5th Embodiment. (A) And (B) is sectional drawing which shows typically the power semiconductor element of the 2nd modification of 5th Embodiment. Sectional drawing which shows typically the power semiconductor element of the 6th Embodiment of this invention. Sectional drawing which shows typically the power semiconductor element of the 7th Embodiment of this invention. (A) And (B) is sectional drawing and characteristic view used in order to demonstrate the said 7th Embodiment.

Claims (2)

A first semiconductor layer made of non-doped Al _X Ga _1-X N (0 ≦ X ≦ 1);
A second semiconductor layer made of non-doped or n-type Al _Y Ga _1-Y N (0 ≦ Y ≦ 1, X <Y) formed on one surface of the first semiconductor layer;
A third semiconductor layer made of the second p-type selectively formed on the semiconductor layer _{Al Z Ga 1-Z N (} 0 ≦ Z ≦ 1),
A drain electrode formed on the second semiconductor layer located on one side of both sides of the third semiconductor layer;
A source electrode formed on the second semiconductor layer located on the other side of both sides of the third semiconductor layer;
An insulating film formed on the second semiconductor layer at a position adjacent to the third semiconductor layer at least between the third semiconductor layer and the drain electrode;
A field plate electrode formed on the insulating film;
A gate electrode formed on the third semiconductor layer,
The field plate electrode is electrically connected to the source electrode;
The end of the third semiconductor layer on the drain electrode side extends from the end of the gate electrode on the drain electrode side to the drain electrode side, and the end of the third semiconductor layer on the drain electrode side has a field plate electrode. Formed to be located at the bottom of the
The thickness of the insulating film located below the field plate electrode is t, the relative dielectric constant of the insulating film is ε _i , the relative dielectric constant of the second semiconductor layer is ε _s , and the drain electrode side of the third semiconductor layer from end a distance to the end of the drain electrode side of the field plate electrode when L, the relationship ε _{s t>} ε _i L of the thickness t of the insulating film is shown below
Power semiconductor elements that are set to satisfy A first semiconductor layer made of non-doped Al _X Ga _1-X N (0 ≦ X ≦ 1);
A second semiconductor layer made of non-doped or n-type Al _Y Ga _1-Y N (0 ≦ Y ≦ 1, X <Y) formed on the first semiconductor layer;
A third semiconductor layer made of the second p-type selectively formed on the semiconductor layer _{Al Z Ga 1-Z N (} 0 ≦ Z ≦ 1),
An insulating film formed on the second semiconductor layer;
A field plate electrode formed on the insulating film;
A cathode electrode formed on the second semiconductor layer located on one side of both sides of the third semiconductor layer ;
Wherein said third being the located on the other side of the both sides of the semiconductor layer on the second semiconductor layer and formed over said third semiconductor layer, positioned on the other side of said third semiconductor layer A second semiconductor layer and an anode electrode forming a Schottky junction ;
The third semiconductor layer is formed such that the cathode side end is positioned below the field plate electrode,
The thickness of the insulating film positioned below the field plate electrode is t, the relative dielectric constant of the insulating film is ε _i , the relative dielectric constant of the second semiconductor layer is ε _s , and the cathode side of the third semiconductor layer is from end when the distance L to the end of the cathode electrode side of the field plate electrode, the relationship ε _{s t>} ε _i L of the thickness t of the insulating film is shown below
Power semiconductor elements that are set to satisfy

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