JP4557689B2 - DRAM controller - Google Patents

Description

  The present invention relates to a DRAM (Dynamic Random Access Memory) controller, and more particularly to a DRAM controller for AMBA AHB (Advanced High-performance Bus: hereinafter referred to as “AHB bus”) proposed by ARM.

FIG. 2 is a schematic configuration diagram of a conventional DRAM controller.
This DRAM controller controls access between a CPU (Central Processing Unit) 1 and an SDRAM (Synchronous DRAM) 2 having an AHB bus. The CPU 1 and the DRAM controller are connected by an AHB bus, and the DRAM controller and the SDRAM 2 are connected by an external memory bus.

  The AHB bus has a 32-bit address signal HADDR output from the CPU side, a 2-bit transfer signal HTRANS, a 3-bit burst signal HBURST, a write control signal HWRITE, and a clock signal HCLK, and a ready signal HREADY input by the CPU side. The control signal of the response signal HRESP and signal lines for transferring data signals of the write data HWDATA and the read data HRDATA of 32 bits each.

  Among them, the transfer signal HTRANS notifies four transfer states of an initial transfer (nSEQ), a subsequent transfer (SEQ), a busy state (BUSY), and an invalid transfer (IDLE). The burst signal HBURST indicates the number of transfers.

  The DRAM controller is roughly composed of an address control unit 10, an address generation unit 20, a memory control unit 30, and a data transfer unit 40.

  The address control unit 10 includes a transfer signal holding unit 11 that holds a transfer control signal given from the CPU 1, a ready signal output unit 12 that outputs a ready signal HREADY to the CPU 1, and a response signal output unit 13 that outputs a response signal HRESP. ing. The address generation unit 20 generates a row address and a column address from the address signal HADDR supplied from the CPU 1 and generates a time-division multiplexed address signal XA supplied to the SDRAM 2. An address generation unit 22 is included.

  The memory control unit 30 generates and outputs various control signals CS, RAS, CAS, WE, CLK, and the like for the SDRAM 2 according to the state, and includes a sequencer 31 and a terminal control unit 32. The data transfer unit 40 has a write register 41 and a read register 42 for controlling transfer between the write data HWDATA and read data HRDATA on the CPU 1 side and the bidirectional data XD on the SDRAM 2 side. ing.

FIG. 3 is an operation waveform diagram during the burst transfer of FIG.
When the address signal HADDR of the AHB bus in FIG. 2 indicates the address space of the SDRAM 2, the transfer signal HTRANS is nSEQ, and the ready signal HREADY is “H”, the address control unit 10 issues a memory request to the memory control unit 30. Output. The memory control unit 30 receives the memory request, activates the sequencer 31, controls the SDRAM 2 via the external memory bus by a control signal according to each state, and exchanges data.

  As shown in FIG. 3, in the case of WRAP4 burst read transfer, the SRED cycle occurs four times, data is read from SDRAM2 through the external memory bus four times, and transferred to the AHB bus.

JP 2000-298614 A

  However, the DRAM controller has a problem that it cannot cope with busy transfer (hereinafter referred to as “busy”) or early burst termination (hereinafter referred to as “EBT”).

  FIG. 4 is an operation waveform diagram of the burst read transfer at the time of busy in FIG. 2. Although it is originally in a transfer waiting state due to the influence of the busy occurring at the 10th cycle, the read data HRDATA to the AHB bus continues to be transferred. It is done. As a result, data different from the expected address data on the AHB bus is output.

  This is because a command indicating burst transfer is output to the SDRAM 2, and then the AHB bus is stopped due to busy or an EBT occurs to access the area other than the DRAM area while continuing the data transfer. This is because an operation mismatch between the AHB bus and the external memory bus occurs.

In order to prevent the occurrence of such a state, there is a method in which the operation of the SDRAM 2 is stopped by monitoring the transfer signal HTRANS of the AHB bus and stopping the clock of the SDRAM 2. In this case, There was a problem.
(A) The sequencer 31 becomes complicated, and many verification patterns are required.
(B) The sequencer 31 becomes complicated and the number of circuits increases.
(C) The sequencer 31 may become complicated and the speed may be reduced.
(D) Since the transfer signal HTRANS is monitored, the number of AHB bus cycles may increase.

  An object of the present invention is to prevent inconsistency in operation between the AHB bus and the external memory bus when a busy or EBT occurs by adding a simple circuit without changing the sequencer 31.

  The present invention provides a busy detection means for outputting a detection signal when a control signal indicating a busy state is given from the CPU during burst transfer of data in a DRAM controller for controlling reading and writing of data between the CPU and DRAM. And a ready signal masking means for stopping the output of a ready signal for notifying the CPU of a transmit / receive enabled state when the detection signal is given, and the detection signal during data write operation to the DRAM. Write stop means for stopping output of a write control signal to the DRAM when given, and data output to the CPU when the detection signal is given during a data read operation from the DRAM Reading stop means for stopping the address and the state of the address for the DRAM when the detection signal is given An address phase holding means for holding and an access resuming means for restarting transfer of the data in accordance with the state of the address held in the address phase holding means after the detection signal is released are provided. .

  The present invention has a busy detection means for detecting the busy state of the CPU and an address phase holding means for holding the address state for the DRAM when the busy state is detected. Thereby, after the busy state is released, there is an effect that data transfer can be continuously performed by the access resuming means.

  A busy detection means, an address phase holding means, an access restart means, a ready signal mask means, a write stop means, a read stop means, etc. are added to a conventional DRAM controller having a sequencer that does not support busy or EBT. Thereby, it becomes possible to correspond to busy and EBT without changing the sequencer function.

  FIG. 1 is a schematic configuration diagram of a DRAM controller showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  This DRAM controller controls access between the CPU 1 and the SDRAM 2 having an AHB bus, as in FIG. The CPU 1 and the DRAM controller are connected by an AHB bus, and the DRAM controller and the SDRAM 2 are connected by an external memory bus corresponding to the SDRAM 2.

  This DRAM controller is roughly composed of an address control unit 10A, an address generation unit 20, a memory control unit 30A, and a data transfer unit 40A.

  The address control unit 10A includes a transfer signal holding unit 11 that holds a transfer control signal supplied from the CPU 1, a ready signal output unit 12 that outputs a ready signal HREADY to the CPU 1, and a response signal output unit 13 that outputs a response signal HRESP. , Busy detection means (for example, early burst detection section) 14 for detecting busy and EBT, address phase holding means (for example, address phase holding section) 15 for holding the fetched address phase, and stop the output of the ready signal HREADY A ready signal masking means (for example, a ready signal masking part) 16 is provided, and an access resuming means (for example, an access resuming part) 17 for restarting data transfer access after the busy is released.

  Similarly to FIG. 2, the address generation unit 20 generates a row address and a column address from the address signal HADDR supplied from the CPU 1 and generates a time division multiplexed address signal XA to be supplied to the SDRAM 2. An address generation unit 21 and a column address generation unit 22 are included.

  The memory control unit 30A generates and outputs various control signals CS, RAS, CAS, WE, CLK, DQM and the like for the SDRAM 2 according to the state. In addition to the sequencer 31 and the terminal control unit 32, the busy control Write stop means (for example, a mask unit) 33 for stopping the control signals DQM and CAS for the SDRAM 2 according to the mask information at the time of EBT is provided.

  In addition to the write register 41 and the read register 42 for controlling the transfer between the write data HWDATA and read data HRDATA on the CPU 1 side and the bidirectional data XD on the SDRAM 2 side, the data transfer unit 40A. Read stop means (for example, a write mask information section) 43 is provided for generating mask information for writing at the time of busy or EBT and stopping output of read data HRDATA.

FIG. 5 is a circuit diagram of an additional portion in the address control unit 10A in FIG.
The early burst detection unit 14 includes a determination unit 14a to which signals hsizex [1] and hburstx [2: 0] are input. The determination unit 14a outputs “L” in the case of single transfer, and outputs “H” in other cases. The output side of the determination unit 14a is connected to the first input side of the three-input AND gate 14b. The second and third input sides of the AND gate 14b are connected to a signal hfnsplse, which indicates the last transfer of the burst. htransx [1] is given respectively.

  Further, the transfer signal HTRANS [1: 0] is supplied to the NAND gate 14c, and the output side of the NAND gate 14c is connected to the first input side of the AND gate 14d. A ready signal HREADY is supplied to the second input side of the AND gate 14d. The output signals of the AND gates 14b and 14d are ANDed by the AND gate 14e, and output as a detection signal ebdetect.

  The address phase holding unit 15 includes a set-reset type flip-flop (hereinafter referred to as “FF”) 15 a, and a detection signal “ebdetect” is given to the set terminal S of the FF 15 a. A signal hfnsplse is supplied to the reset terminal R of the FF 15a, and a mask signal hreadymsk is output from the output side of the FF 15a.

  Further, the address phase holding unit 15 has an FF 15b to which a transfer signal HTRANS is given, and an output side of the FF 15b is connected to a first input side of the selector 15c. The output side of the selector 15c is connected to the input side of the FF 15d and the first input side of the selectors 15e and 15g. The output side of the FF 15d is connected to the second input side of the selector 15c. The output side of the selector 15e is connected to the input side of the FF 15f, and the output side of the FF 15f is connected to the second input side of the selectors 15e and 15g. The output side of the selector 15g is connected to the first input side of the selector 15h, and a fixed value 2b10 (binary number “10”) is given to the second input side of the selector 15h. The signal htransx output from the selector 15h is supplied to the memory control unit 30A.

  The selector 15c is supplied with a signal “hreadyiff”, and the selectors 15e and 15g are supplied with a mask signal “headymsk” as selection signals. The selection signal of the selector 15h is given a signal snglsct described later.

  The ready signal mask unit 16 includes an OR gate 16a to which a detection signal ebdetect detected from the early burst detection unit 14 and a mask signal hreadymsk output from the address phase holding unit 16 are provided. An output of the OR gate 16a This side is connected to the first input side of the AND gate 16b which is a mask circuit. The signal hreadommc is given to the second input side of the AND gate 16b. The output side of the AND gate 16b is supplied to the OR gate 16c together with signals idleresp, serr, and eerr for generating other ready signals. The output side of the OR gate 16c is connected to the FF 16d, and a ready signal HREADY is output from the FF 16c.

  The access resuming unit 17 includes a determination unit 17a to which the signal burstexec output from the determination unit 14a of the early burst detection unit 14 and the detection signal ebdetect detected from the AND gate 14e are input. The determination unit 17a outputs “H” when the detection signal “ebdetect” becomes “H” during the period when the signal burstexec is “H”. The output signal of the determination unit 17a is given to the first input side of the selector 17b, and a fixed value 1'b0 (binary number "0") is given to the second input side of the selector 17b. . A mask signal hrdymsk is given to the selection signal of the selector 17b, a signal snglslct is outputted from the output side of the selector 17b, and is given to the selector 15h of the address phase holding unit 15.

FIG. 6 is a circuit diagram of the write mask information unit 43 in FIG.
The mask signal hrdymsk and the signal hfnsplse indicating the last transfer of the burst are ORed and input to the FF for each byte. The output signals of each FF are input to selectors (SEL0 to 3) for each byte, and the output signals of these selectors (SEL3 to 0) are given to the FF (TAG0 to 3) and the OR gate. The output side of each FF (TAG0-3) is connected to the other input side of the selector (SEL3-0). A mask signal dqmcasmsk is output from the OR gate.

FIG. 7 is a mask logic diagram of the memory control unit 30A in FIG.
The mask signal dqmcasmsk output from the OR gate in FIG. 6 is ANDed with the signal arch indicating that it is not SDRAM by the AND gate 33a, and is given to the input side of the AND gate 33b which is a mask circuit.

FIG. 8 is an output mask logic diagram of the data transfer unit 40A in FIG.
The detection signal btdetect and the mask signal hrdymsk are ORed by the OR gate 43a and provided to the input side of the AND gate 43b which is a mask circuit.

Next, the operation will be described.
FIG. 9 is a signal waveform diagram when busy is present during burst read transfer.

  Signals hfpulse and hreadommc are output signals from the memory control unit 30A, the signal hfpulse indicates the end of burst transfer, and the signal hreadommc indicates the output value of the ready signal HREADY to the AHB bus.

  The detection signal btdetect output from the early burst detection unit 14 is asserted by the busy generated in the 10th cycle. The ready signal mask unit 16 asserts the detection signal ebdetect to assert the mask signal hrdymsk at the next clock, takes the logical product of the signal readyomc and the mask signal to hrdymsk, and negates the ready signal HREADY and outputs it on the AHB bus. Is done. When the ready signal HREADY is negated, the address signal HADDR does not change.

  When the signal hfnshpulse is asserted, the detection signal btdetect is negated, and the mask signal hrdmsk is negated at the next clock after the signal hfnshpulse is asserted. Since the signal hreadommc output from the memory control unit 30A is a transfer end cycle, the ready signal HREADY remains negated and stops in a data transfer waiting state indicated by ADDR2.

  The signal snglslct is generated in the state of the mask signal hrdymsk generated by the ready signal mask unit 16 and the state of the access resuming unit 17 after busy.

  When busy is input during the burst operation, the state shifts from the idle state to the operation state. Thereafter, when SEQ is input, the signal snglslct is asserted, and the process proceeds to SRCD.

  When the signal snglslct is asserted, the transfer signal HTRANS in the address phase holding unit 15 is changed to nSEQ and the burst signal HBURST is changed to SINGLE, so that a memory request is generated in ADD2 and nSEQ, and normal single transfer is performed. Do. At the end of the single transfer, the ready signal HREADY is asserted to complete the transfer cycle.

  When the transfer signal HTRANS at the 10th cycle is idle, the above state does not change from SNOT, so the signal snglslct is not asserted and the transfer cycle is terminated.

  FIG. 10 shows a signal waveform in the case where busy is present during burst write transfer. Like the burst read transfer in FIG. 9, the detection signal ebdetect is asserted by the busy generated in the fourth cycle. A similar operation is performed. Since the DQM has a value masked by the mask signal hrdymsk, the busy transition write is not actually performed.

  As described above, the DRAM controller of this embodiment includes the early burst detection unit 14 that detects the busy / EBT and the address phase holding unit 15 that holds the address state according to the detection signal. As a result, the data up to the occurrence of busy / EBT is made valid, the data after the occurrence of busy / EBT is made invalid, the number of transfers according to the burst length are performed once, and after the busy, the data in single transfer is subsequently performed. I have to. Thereby, normal data transfer corresponding to busy / EBT can be performed without causing a transfer delay in burst transfer in which busy / EBT does not occur.

  Further, since the sequencer 31 of the memory control unit 30A can use a conventional one without changing the function, there are advantages that the verification is easy, the circuit area is small, and the speed is not lowered.

In addition, this invention is not limited to this Example, The following various deformation | transformation are possible.
(1) The target DRAM is not limited to SDRAM.
(2) The circuit diagrams of FIGS. 5 to 8 are examples, and the present invention is not limited to these.
(3) The target CPU1 side bus is not limited to the AHB bus.

1 is a schematic configuration diagram of a DRAM controller showing an embodiment of the present invention. It is a schematic block diagram of the conventional DRAM controller. FIG. 3 is an operation waveform diagram during burst transfer of FIG. 2. FIG. 3 is an operation waveform diagram of burst read transfer at the time of busy in FIG. 2. It is a circuit diagram of the additional part in 10 A of address control parts in FIG. FIG. 2 is a circuit diagram of a write mask information unit 43 in FIG. 1. FIG. 2 is a mask logic diagram of a memory control unit 30A in FIG. It is an output mask logic diagram of the data transfer unit 40A in FIG. It is a signal waveform diagram in case busy exists during burst read transfer. It is a signal waveform diagram when busy exists during burst write transfer.

Explanation of symbols

1 CPU
2 SDRAM
DESCRIPTION OF SYMBOLS 10A Address control part 11 Transfer control signal holding part 12 Ready signal output part 14 Early burst detection part 15 Address phase holding part 16 Ready signal mask part 17 Access restart part 20 Address generation part 30A Memory control part 31 Sequencer 32 Mask part 40A Data transfer Part 43 Write mask information part

Claims (1)

In a DRAM controller that controls reading and writing of data between a central processing unit and dynamic random access memory,
Busy detection means for outputting a detection signal when a control signal indicating a busy state is given from the central processing unit during burst transfer of data;
Ready signal masking means for stopping output of a ready signal for notifying the central processing unit of a state in which transmission and reception is possible when the detection signal is given;
Write stopping means for stopping output of a write control signal to the dynamic random access memory when the detection signal is given during a data write operation to the dynamic random access memory;
Read stop means for stopping output of data to the central processing unit when the detection signal is given during a read operation of data from the dynamic random access memory;
Address phase holding means for holding the state of an address for the dynamic random access memory when the detection signal is given;
After the detection signal is released, an access resuming unit that resumes the transfer of the data according to the state of the address held in the address phase holding unit,
A DRAM controller characterized by being provided.

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