JP4553428B2 - Phase-locked loop (PLL) clock generator with programmable offset and frequency - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to clock generators, and more particularly to a phase-locked loop (PLL) clock generator having programmable offset and frequency.
[0002]
[Prior art]
With advances in semiconductor technology, the operating frequency of digital circuit systems is becoming higher and higher. Therefore, the issue of clock synchronization is an important issue for designers. Clock synchronization includes not only a single clock signal but also multiple clock signals. In general, clock signal skew is determined by a clock generator or loading based on an open loop configuration. When the trace length from the clock generator to the load becomes longer or the load increases, the problem of signal deviation of the clock signal becomes more serious. For example, many devices shared a single clock generator on a computer motherboard. Also, the memory scale can be dynamically changed according to the user's request. In addition, there are many interface slots for connecting to peripheral devices depending on practical requirements. Therefore, the loading on the clock signal is changed according to the change in the memory scale and the amount of peripheral devices. It's no wonder that the open loop configuration can't solve the signal drift. On the other hand, there is a need to change the frequency of the clock signal. If all clock signals are provided by an external clock generator, it is difficult to arbitrarily change the clock frequency because the frequency of the clock signal is fixed.
[0003]
FIG. 1 is a schematic block diagram of a computer motherboard using a conventional clock generator, in which a single clock generator 150 provides clock signals CPU-CLK and SYS-CLK. Clock signal CPU-CLK provides a signal to CPU 110 and chipset 120, while clock signal SYS-CLK provides a signal to chipset 120 and devices 141-14N via bus 130. is doing. Since the chipset 120 is responsible for controlling the operation of the computer / motherboard, it is necessary to refer to both the clock signal SYS-CLK and the clock signal CPU-CLK. The devices 141 to 14N are peripheral devices. Since various numbers of peripheral devices can be connected to the computer motherboard, therefore the loading on the clock signal SYS-CLK varies depending on the number of connected devices. Changing the loading on the clock signal SYS-CLK affects the deviation of the clock signal and consequently the stability of the entire system.
[0004]
If multiple clock signals are provided from the chipset 120 to the devices in the system, the designer has better control of the clock signal deviation to give the system greater stability and durability. it can. Furthermore, the frequency of the clock signal can be changed dynamically by a computer program.
[0005]
[Problems to be solved by the invention]
In summary, the conventional clock generator has the following disadvantages.
1. If the clock signal is provided by an external clock generator, the frequency of the clock signal can be easily changed, especially by a computer program.
2. The clock signal provided based on the open loop configuration is affected by loading changes and the resulting stability of the system, which is very difficult to control clock signal drift.
[0006]
It is therefore an object of the present invention to provide a phase-locked loop (PLL) clock generator having a programmable frequency that dynamically changes the generated clock frequency.
[0007]
Another object of the present invention is to provide a PLL clock generator having a programmable offset that dynamically adjusts the offset of the clock signal.
[0008]
[Means for Solving the Problems]
In accordance with the above-described objectives of the present invention, a phase-locked loop (PLL) clock generator having programmable frequency and offset is provided, according to which a clock signal is generated based on a reference signal. . The clock generator includes a plurality of first delay devices each having a first terminal and a second terminal, a first multiplex communication device, a plurality of second delay devices each having a first terminal and a second terminal, It includes a device for two multiplex communications and a PLL signal generator.
[0009]
The plurality of first delay devices are connected in cascade by sequentially connecting the second terminal of one first delay device and the first terminal of the adjacent first delay device. A first terminal of one of the plurality of first delay devices is connected to a reference signal.
[0010]
The first multiplex communication device includes a plurality of input terminals, an output terminal, and a first selection input. The plurality of input terminals of the first multiplex communication device are respectively connected to the reference signal and the second terminals of the plurality of first delay devices, and one of the plurality of input signals to the first multiplex communication device is Connected by the first selection input and coupled to the output terminal of the first multiplex communication device.
[0011]
The plurality of second delay devices are sequentially connected in cascade by connecting the second terminal of one second delay device and the first terminal of the adjacent second delay device. The first terminal of one of the plurality of second delay devices is connected to the feedback signal.
[0012]
The second multiplex communication device includes a plurality of input terminals, an output terminal, and a second selection input. The plurality of input terminals of the second multiplex communication device are respectively connected to the feedback signal and the second terminals of the second delay devices, and one of the plurality of input signals to the second multiplex communication device is: Selected by the second selection input and coupled to the output terminal of the second multiplex communication device.
[0013]
The PLL signal generator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the PLL signal generator is connected to the output terminal of the first multiplex communication apparatus, and the second input terminal of the PLL signal generator is connected to the output terminal of the second multiplex communication apparatus. The clock signal is generated from the output terminal of the PLL signal generator and fed back to function as a feedback signal via the conductive line.
[0014]
In accordance with a preferred embodiment of the present invention, a clock signal is fed back at the midpoint of the conductive line to function as a feedback signal, providing a clock signal required by an external device.
[0015]
The PLL signal generator in the PLL clock generator described above includes a plurality of first dividers each having an input terminal and an output terminal, a third multiplex communication device, and a plurality of second dividers each having an input terminal and an output terminal. , A fourth multiplex communication device, a PLL core circuit, a plurality of third dividers each having an input terminal and an output terminal, and a fifth multiplex communication device.
[0016]
The input terminals of the plurality of first dividers are connected to the output terminals of the first multiplex communication device.
[0017]
The third multiplex communication device includes a plurality of input terminals, an output terminal, and a third selection input. The input terminals of the third multiplex communication device are respectively connected to the output terminals of the plurality of first dividers, and one of the plurality of input signals to the third multiplex communication device is selected by the third selection input, and the third multiplex communication is performed. Coupled to the output terminal of the communication device.
[0018]
The input terminals of the plurality of second dividers are connected to the output terminals of the second multiplex communication device.
[0019]
The fourth multiplex communication device includes a plurality of input terminals, an output terminal, and a fourth selection input. The plurality of input terminals of the fourth multiplex communication device are respectively connected to the output terminals of the plurality of second dividers, and one of the plurality of input signals to the fourth multiplex communication device is selected by the fourth selection input. It is coupled to the output terminal of the 4-multiplex communication device.
[0020]
The PLL core circuit includes a reference input terminal, a feedback input terminal, and an output terminal. The PLL core circuit generates a signal at the output terminal based on the phase difference between the signal at the reference input terminal and the feedback input terminal. The reference input terminal is connected to the output terminal of the third multiplex communication apparatus, and the feedback input terminal is connected to the output terminal of the fourth multiplex communication apparatus.
[0021]
The input terminals of the plurality of third dividers are connected to the output terminal of the PLL core circuit.
[0022]
The fifth multiplex communication device has a plurality of input terminals and output terminals. The plurality of input terminals of the fifth multiplex communication device are connected to the output terminals of the plurality of third dividers, respectively, and the clock signal is generated from the output terminal of the fifth multiplex communication device.
[0023]
The foregoing general description and the following detailed description are exemplary and are intended to further illustrate the claimed invention.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
The accompanying drawings provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the disclosure of the invention, serve to explain the principles.
[0025]
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or substantially the same parts.
[0026]
FIG. 2 is a block diagram of a phase-locked loop (PLL) signal generator 200 having a programmable frequency in accordance with a preferred embodiment of the present invention. As shown in FIG. 2, the PLL signal generator 200 generates a clock signal CLK2 having a variable frequency based on the reference signal REF-CLK. The PLL signal generator 200 includes a divider 211 to 21N, a multiplex communication device 220, a divider 231 to 23N, a multiplex communication device 240, a PLL core circuit 250, a divider 261 to 26N, a multiplex communication device 270, and a multiplex communication device. A communication device 280 is provided.
[0027]
The reference signal REF-CLK is connected to the input terminals of the dividers 211 to 21N. The dividers 211 to 21N divide the frequency of the reference signal REF-CLK by different numbers and obtain signals of different frequencies as outputs of the dividers 211 to 21N. Yes. Then, output signals from the dividers 211 to 21N are connected to the input terminal of the multiplex communication device 220 controlled by the selection input REF-SEL. Therefore, one of the plurality of inputs to the multiplex communication device 220 is selected as the output signal REF-CLK ′. The ratio between the reference signal REF-CLK and the output signal REF-CLK ′ from the multiplex communication device 220 can be determined by the selection input REF-SEL.
[0028]
The feedback signal FB-CLK is connected to the input terminals of the dividers 231 to 23N, and the dividers 231 to 23N divide the frequency of the feedback signal FB-CLK by different numbers and obtain signals of different frequencies as outputs of the dividers 231 to 23N. Yes. Then, output signals from the dividers 231 to 23N are connected to an input terminal of the multiplex communication apparatus 240 controlled by the selection input FB-SEL. Therefore, one of the plurality of inputs to the multiplex communication apparatus 240 is selected as the output signal FB-CLK ′. The ratio between the feedback signal FB-CLK and the output signal FB-CLK ′ from the multiplex communication device 240 can be determined by the selection input FB-SEL.
[0029]
The PLL core circuit 250 is responsible for performing the main functions of the PLL signal generator 200. The PLL signal generator 200 is connected to the reference input terminal R-IN connected to the output signal REF-CLK ′ from the multiplex communication device 220 and to the output signal FB-CLK ′ from the multiplex communication device 240. It includes a feedback input terminal F-IN and an output terminal PO that produces an output signal CLK. The PLL core circuit 250 determines the frequency and phase of the output signal CLK based on the phase difference between the output signal REF-CLK ′ from the multiplex communication device 220 and the output signal FB-CLK ′ from the multiplex communication device 240. Can be adjusted. Therefore, the phase difference between the signal REF-CLK ′ and the signal REF-CLK ′ can be minimized.
[0030]
The output signal CLK from the output terminal PO of the PLL core circuit 250 is connected to the input terminals of the dividers 261 to 26N. The dividers 261 to 26N divide the frequency of the signal CLK by different numbers, and obtain signals having different frequencies as outputs of the dividers 261 to 26N. Output signals from the dividers 261 to 26N are connected to input terminals of the multiplex communication device 270 and the multiplex communication device 280. One of the plurality of inputs to the multiplex communication apparatus 280 controlled by the selection input SEL is selected as the output clock signal CLK2 required by an external circuit.
[0031]
The multiplex communication apparatus 270 generates an output signal CLK1 that functions as a feedback signal FB-CLK. Then, the feedback signal FB-CLK proceeds to the feedback input terminal F-IN of the PLL core circuit 250 via the dividers 231 to 23N and the multiplex communication device 240, and forms a closed phase loop. The use of the multiplex communication device 270 is not for selecting a frequency for the feedback signal FB-CLK. Instead, the multiplex communication device 270 is used to more closely adjust the time delay between the signal CLK1 and the signal CLK2 and to further control the shift of the clock signal.
[0032]
What is understood based on the PLL signal generator 200 described above is that the clock signal CLK2 of the desired frequency is generated by selecting the selection inputs REF-SEL, FB-SEL and SEL based on the reference signal REF-CLK. Is Rukoto. When the reference signal REF-CLK is assumed to have a frequency f _r, the ratio between the reference signal REF-CLK and the signal REF-CLK 'is N, which is determined by the selected input REF-SEL, the feedback signal The ratio between FB-CLK and signal FB-CLK ′ is D determined by the selection input FB-SEL, and the ratio between signals CLK and CLK1 is fixed at 1. Therefore, the signal CLK generated by the PLL signal generator 200 has a frequency of f _r ^* N / D. The multiplex communication device 280 is used to select a clock signal CLK2 having a desired frequency. By using many multiplex communication devices, it is possible to provide clock signals with various frequencies required by different types of circuits.
[0033]
Based on the PLL signal generator 200 described above, the shift of the clock signal described in detail below can be controlled better.
[0034]
FIG. 3 is a block diagram of a phase-locked loop (PLL) clock generator 300 with programmable frequency and offset. The PLL clock generator 300 generates a clock signal CLK1 requested by an external circuit based on the reference signal REF-CLK0. As illustrated in FIG. 3, the PLL clock generator 300 includes delay devices 311 to 31N, a multiplex communication device 320, delay devices 331 to 33N, a multiplex communication device 340, and a PLL signal generator 200. The delay devices 311 to 31N are sequentially cascaded (cascaded). The reference signal REF-CLK0 is connected to the input terminal of the first delay device 311. The multiplex communication device 320 includes a plurality of input terminals, an output terminal, and a selection input. The input terminal of the multiplex communication device 320 is connected to the reference signal REF-CLK0 and the outputs of the delay devices 311 to 31N. The multiplex communication apparatus 320 is controlled by the selection input S1 in such a way that one of the plurality of inputs of the multiplex communication apparatus 320 is selected as the output signal REF-CLK. At that time, the output signal REF-CLK is connected to the PLL signal generator 200.
[0035]
Similarly, the delay devices 331 to 33N are connected in cascade. The feedback signal FB-CLK0 is connected to the input terminal of the first delay device 331. The multiplex communication device 340 includes a plurality of input terminals, an output terminal, and a selection input. A plurality of input terminals of the multiplex communication device 340 are connected to the feedback signal FB-CLK0 and the outputs of the delay devices 331 to 33N, respectively. The multiplex communication apparatus 340 is controlled by the selection input S2 in such a manner that one of the plurality of input terminals of the multiplex communication apparatus 340 is selected as the output signal FB-CLK. At that time, the output signal FB-CLK is connected to the PLL signal generator 200.
[0036]
The PLL signal generator 200 in FIG. 3 is shown in FIG. 2 and includes a reference input terminal, a feedback input terminal, and an output terminal. The reference input terminal of the PLL signal generator 200 is connected to the signal REF-CLK from the output terminal of the multiplex communication device 320, while the feedback input terminal of the PLL signal generator 200 is connected to the output terminal of the multiplex communication device 340. It is connected to the signal FB-CLK. A clock signal CLK1 is generated by the PLL signal generator 200 and functions as a feedback signal FB-CLK0 via a conductive line 350. As shown in FIG. 2, the PLL core circuit 250 in the PLL signal generator 200 adjusts the frequency and phase of the output signal CLK to minimize the phase difference between the signal REF-CLK ′ and the signal FB-CLK ′. It has become. The output signal CLK is based on the phase difference between the signal REF-CLK ′ and the signal FB-CLK ′. The PLL signal generator 200 can generate the clock signal CLK1 based on the relationship between the reference signal REF-CLK and the feedback signal FB-CLK.
[0037]
The clock signal CLK1 is fed back and functions as the feedback signal FB-CLK0 via the conductive line 350 in order to better control the signal shift in consideration of the signal delay due to the line length.
[0038]
Therefore, the PLL clock generator 300 is controlled by the selection inputs S1 and S2, and not only the delay devices 311 to 31N between the reference signal REF-CLK0 and the signal REF-CLK but also the feedback signal FB-CLK0 and the signal FB-. It is also adjusted by delay devices 331 to 33N with respect to CLK. Therefore, the shift of the clock signal CLK1 can be controlled and minimized.
[0039]
FIG. 4 is a schematic block diagram of a computer motherboard using a phase-locked loop (PLL) clock generator. As shown in FIG. 4, the chipset 420 includes PLL clock generators 421 and 422. The PLL clock generator 421 generates a clock signal CPU-CLK to the CPU 410, and the PLL clock generator 422 generates a clock signal SYS-CLK to the devices 441 to 44N via the bus 430. Bus 430 is based on the reference SREF from reference signal generator 450. PLL clock generators 421 and 422 having a structure as shown in FIG. 3 generate clock signals CPU-CLK and SYS-CLK based on the reference signal SREF from the reference signal generator 450. The frequency and deviation of the clock signals CPU-CLK and SYS-CLK generated from the PLL clock generators 421 and 422 are adjusted separately. Therefore, a clock signal having a desired frequency is obtained, and a deviation between the clock signals CPU-CLK and SYS-CLK is minimized. To indicate loading on the device, the feedback signal is taken at the midpoint of the line length from the output of the PLL clock generator to the device. Therefore, the deviation between the feedback signal and the clock signal to the device can be maintained in the same way. For example, the clock signal CPU-CLK is provided to the CPU 410 via the conductive line 461. The feedback signal is taken at an intermediate point of the conductive line 461 and connected to the PLL clock generator 421 through the conductive line 462. Similarly, the clock signal SYS-CLK is connected to the bus 430 through the conductive line 471. The feedback signal is taken at an appropriate location on the bus 430 and connected to the PLL clock generator 422 through a conductive line 472.
[0040]
Based on the above-described computer motherboard, the frequency of the clock signal CPU-CLK transmitted to the CPU 410 and the frequency of the clock signal SYS-CLK transmitted to the devices 441 to 44N is equal to the operating speed of the CPU 410 and the devices 441 to 44N. Can be adjusted based on. The deviation of the clock signal CPU-CLK can be adjusted depending on the actual distance between the CPU 410 and the chipset 420. Furthermore, the deviation of the clock signal SYS-CLK can also be adjusted depending on the actual loading on the bus 430 and the number of devices connected to the bus 430. Therefore, the deviation of the clock signal transmitted to the CPU 410 and the devices 441 to 44N can be minimized.
[0041]
Also, a PLL clock generator in a chipset on a computer motherboard according to a preferred embodiment of the present invention can provide the clock signal required by the system. In addition, clock signal drift can be better controlled through the closed loop configuration of the PLL clock generator. The deviation of the clock signal can also be adjusted by a computer program based on actual requirements. For example, if many memories or interface cards are installed, and as a result, the actual loading and clock signal lag is increased, the delay time of the signal from the reference input will be Increased to compensate for the deviation. Manual operation by the user is not required to change jumper settings on the motherboard. Conversely, the loading imposed on the clock signal is automatically detected by a basic input / output system (BIOS) program. Therefore, the deviation setting can be automatically adjusted.
[0042]
In summary, a PLL clock generator with programmable frequency and offset according to a preferred embodiment of the present invention has the following advantages.
1. The frequency of the clock signal generated by the PLL clock generator can be dynamically changed by a computer program.
2. Since the clock signal generated by the PLL clock generator can be dynamically adjusted by a computer program, the deviation of the clock signal can be better controlled.
[0043]
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In light of the above, it is intended that the present invention include modifications and variations of this invention if such modifications and variations are within the scope of the claims and their equivalents. .
[0044]
【The invention's effect】
In summary, a PLL clock generator with programmable frequency and offset according to a preferred embodiment of the present invention has the following advantages.
1. The frequency of the clock signal generated by the PLL clock generator can be dynamically changed by a computer program.
2. Since the clock signal generated by the PLL clock generator can be dynamically adjusted by a computer program, the deviation of the clock signal can be better controlled.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a computer motherboard using a conventional clock generator.
FIG. 2 is a block diagram of a phase locked loop (PLL) signal generator having a programmable frequency, in accordance with a preferred embodiment of the present invention.
FIG. 3 is a block diagram of a phase-locked loop (PLL) clock generator with programmable frequency and offset.
FIG. 4 is a schematic block diagram of a computer motherboard using a phase-locked loop (PLL) clock generator.

Claims (3)

In a phase-locked loop (PLL) clock generator with programmable frequency and offset to generate a clock signal based on a reference signal,
A plurality of first delay devices each having a first terminal and a second terminal;
A first multiplex communication device having a plurality of input terminals, an output terminal, and a first selection input;
A plurality of second delay devices each having a first terminal and a second terminal;
A second multiplex communication device having a plurality of input terminals, an output terminal, and a second selection input;
A PLL signal generator having a first input terminal, a second input terminal, and an output terminal;
The plurality of first delay devices are connected in cascade by sequentially connecting a second terminal of one first delay device and a first terminal of a first delay device adjacent thereto, and the plurality of first delay devices. A first terminal of one of the delay devices is connected to the reference signal;
An input terminal of the first multiplex communication device is connected to the reference signal and a second terminal of the plurality of first delay devices, respectively, and one of a plurality of input signals to the first multiplex communication device is the Selected by a first selection input and coupled to an output terminal of the first multiplex communication device;
The plurality of second delay devices are connected in cascade by sequentially connecting a second terminal of one second delay device and a first terminal of a second delay device adjacent thereto, and the plurality of second delay devices. A first terminal of one of the delay devices is connected to the feedback signal;
A plurality of input terminals of the second multiplex communication device are respectively connected to the feedback signal and a second terminal of the plurality of second delay devices, and one of the plurality of input signals to the second multiplex communication device. One selected by the second selection input and coupled to the output terminal of the second multiplex communication device;
The first input terminal of the PLL signal generator is connected to the output terminal of the first multiplex communication device, and the second input terminal of the PLL signal generator is connected to the output terminal of the second multiplex communication device. The clock signal requested by an external device is generated from the output terminal of the PLL signal generator, and the clock signal is fed back to function as the feedback signal through a conductive line. A PLL clock generator with programmable frequency and offset. A PLL clock generator with programmable frequency and offset as claimed in claim 1.
Programmable, wherein the clock signal functions as a feedback signal by being fed back at an intermediate point of the conductive line connecting the device to which the clock signal is provided and the PLL clock generator PLL clock generator with frequency and offset. The PLL clock generator with programmable frequency and offset of claim 1.
A plurality of first dividers each having an input terminal and an output terminal;
A third multiplex communication device having a plurality of input terminals, an output terminal, and a third selection input;
A plurality of second dividers each having an input terminal and an output terminal;
A fourth multiplex communication device having a plurality of input terminals, an output terminal, and a fourth selection input;
A PLL core circuit having a reference input terminal, a feedback input terminal, and an output terminal;
A plurality of third dividers each having an input terminal and an output terminal;
A fifth multiplex communication device having a plurality of input terminals and output terminals,
Input terminals of the plurality of first dividers are connected to output terminals of the first multiplex communication device;
Input terminals of the third multiplex communication device are respectively connected to output terminals of the plurality of first dividers, and one of a plurality of input signals to the third multiplex communication device is selected by the third selection input. Coupled to the output terminal of the third multiplex communication device,
Input terminals of the plurality of second dividers are connected to output terminals of the second multiplex communication device;
Input terminals of the fourth multiplex communication device are respectively connected to output terminals of the plurality of second dividers, and one of a plurality of input signals to the fourth multiplex communication device is selected by the fourth selection input. Coupled to the output terminal of the fourth multiplex communication device,
The reference input terminal is connected to the output terminal of the third multiplex communication device, the feedback input terminal is connected to the output terminal of the fourth multiplex communication device, and the PLL core circuit is connected to the reference input terminal. Generating a signal from the output terminal based on a phase difference between the signal and the feedback input terminal;
Input terminals of the plurality of third dividers are connected to output terminals of the PLL core circuit;
Programmable, wherein input terminals of the fifth multiplex communication device are respectively connected to output terminals of the plurality of third dividers, and the clock signal is generated from an output terminal of the fifth multiplex communication device PLL clock generator with variable frequency and offset.

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