JP4549001B2 - Information processing apparatus and semiconductor integrated circuit - Google Patents

Description

Technical field
The present invention relates to an information processing apparatus including a memory block having a plurality of memory banks shared by a plurality of masters, and relates to a semiconductor integrated circuit including a memory control circuit that receives the access from the plurality of masters and controls the memory block.
Background art
References referred to in this specification are as follows. References are referred to by their reference numbers. [Document 1]: Japanese Patent Laid-Open No. 05-181743.
[Document 2]: JP-A-10-228413.
As a typical information processing apparatus, one including a single CPU (Central Processing Unit) and a DRAM (Dynamic Random Access Memory) which is connected to the CPU via a DRAM control circuit and stores desired data is known. When data is read from the DRAM, the CPU sends a read command to the DRAM control circuit, and the DRAM control circuit decodes this command and performs read control of desired data from the DRAM. Hereinafter, the operation will be described along the command system of a known synchronous DRAM (SDRAM). In DRAM read control from the DRAM control circuit, first, a bank active command and a row address are sent to the DRAM (ACTV). The word line in the DRAM is selected by this command and the row address, and data for one row on the word line is transferred to the sense amplifier, amplified, and held. Next, a read command and a column address are sent (READ). The column switch is selected by this command and the column address, and the data held in the sense amplifier is read out. In DRAM, the word line selection operation requires a relatively long time. Once the data on the word line is held in the sense amplifier, access on the same word line, that is, access to the same page. If this occurs, the data can be read out in a short time. In addition, when data is read from a word line different from the currently selected word line, that is, when a different page is accessed, the currently selected word line is deselected and a new word line is selected. Since it is necessary to make a selection, it takes a long time to read data.
In the information processing apparatus, the subject that accesses the DRAM is not limited to the CPU described above, but may include a hard disk controller, an MPEG decoder, a graphics processing circuit, and the like. Since the hard disk controller and the like including the CPU can be a main body that accesses the DRAM, each is called a master. [Literature 1] and [Literature 2] are known as documents indicating an information processing apparatus including a plurality of masters. [Document 1] describes a technique for allocating a specific memory bank to a specific master in order to increase efficiency when a plurality of masters (CPU and input / output controller IOC) access the plurality of memory banks. [Document 2] is a method for holding data for reading / writing between a plurality of masters and a memory bank in order to mediate access competition between a plurality of masters and a plurality of memory banks. A technique for providing a buffer is described.
The inventors of the present application focused not only on arbitration of access competition but also on the importance of control in accordance with the nature of the master in order to improve access efficiency in a system having a plurality of masters and a plurality of memory banks. That is, the access from the CPU to the DRAM has locality even if it is random access. In other words, the access of the CPU has a property that the currently accessed address and the nearby addresses are likely to be accessed again frequently in the near future. Therefore, access from the CPU to the DRAM frequently occurs in the same page.
On the other hand, the access address of the hard disk controller has little locality. When data in the DRAM is stored in the hard disk, the hard disk controller accesses the DRAM by an interruption from the keyboard or mouse, and the data in the DRAM is read and stored in the hard disk. Once the data in the DRAM is saved, there is no need to read the data from the DRAM again unless an interrupt from the keyboard or mouse occurs. Therefore, in the near future, the possibility that the hard disk controller frequently accesses the same address again and reads data is very small.
In addition, the MPEG decoder decompresses the data compressed in the CD-ROM or the like in order within a certain time and writes it to the DRAM. Once the compressed data is decompressed, it is not necessary to decompress the same data again, so that the possibility that the MPEG decoder itself will frequently access the same address again in the near future is extremely small.
Thus, each access from a plurality of masters sharing a DRAM has its characteristics, and simple DRAM access control cannot cope with these accesses. When a master other than the CPU accesses a word line different from the word line already selected by the CPU, the subsequent access from the CPU, which was originally in the same page, becomes an access to a different page. Thus, it has been found that there is a problem that it takes a long time to read data from and write data to the DRAM. Accordingly, one of the objects of the present invention is to speed up the reading and writing of the DRAM with respect to accesses from a plurality of masters.
Disclosure of the invention
Representative means of the present invention are as follows. By identifying the master that accesses the memory, the control mode for controlling the memory is switched corresponding to the master, and the memory is controlled. More specifically, based on the identification signal of each master, the memory page is switched at the beginning of the access or not, and according to this, the page is opened and closed at the end of the access. To control. When the memory is a DRAM, a page means one of a plurality of word lines in a specific memory bank, and a page open means data for one page with the word line in a specific memory bank being selected. This corresponds to holding (bank active state) in the sense amplifier. On the other hand, page closing corresponds to setting a word line in a memory bank in a non-selected state so that any word line can be immediately selected when a word line selection request is made for the memory bank. (Bank precharge state).
When there is an access request from a master with local access, if the access is terminated with the page open, there is a high probability that the same page will be accessed in the next access. Is faster. On the other hand, in the case of a master with a low locality of access, the access is terminated by closing the page. In the case of such a master, it is highly probable that the next access is not the same page but a different page. Therefore, if the page is opened, it takes time to close the page and reopen another page. Therefore, for the master that cannot expect the cache hit effect, the entire access is made efficient by ending the access by closing the page.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). .
<Example 1>
FIG. 2 is a basic configuration diagram of an information processing apparatus using the present application. This is composed of a CPU 4 as a first master, a hard disk controller (HDC) 5 as a second master, an access arbitration circuit (ARB) 2 that arbitrates access from the CPU and HDC, and a plurality of banks. Memory block (MEM) 3, memory control circuit (MCTL) 1 that controls MEM by a signal from ARB, hard disk (HD) 50, and refresh control circuit (RFC) 6 that controls refresh operation of memory block 3 Consists of. The RFC becomes the third master.
The hard disk controller HDC controls data transfer between the hard disk 50 and the memory block MEM. The MEM is composed of four memory macros, a 0th memory macro 3M0 to a third memory macro 3M3. Each memory macro is composed of four memory banks, and each memory bank is provided with a sense amplifier. The information processing apparatus operates in synchronization with the clock CLK.
Although there is no particular limitation on the CPU, the address space can be managed by a 32-bit address signal, and the memory block MEM is mapped to the lower 18-bit address space of the CPU address signal.
Before explaining the operation of the information processing apparatus, the instruction set of each master shown in FIG. 3 will be explained. FIG. 3A shows the instruction set of the CPU, and instructions from the CPU to the access arbitration circuit ARB are based on CPU instruction signals RW0 [0] to RW0 [3] (corresponding to RW0 (4 bits) in FIG. 2). Is represented. The load instruction LD is an instruction for reading DRAM data. Store instruction ST is an instruction for writing data into DRAM. The set register SR is an instruction for setting data in shift registers 1a, 1b, and 1c in the DRAM control circuit 1 of FIG. The reserve RV is a reserve instruction for adding a new instruction. No operation NOP is an instruction which does nothing.
3B shows an instruction set of the hard disk controller HDC, which is represented by HDC instruction signals RW1 [0] to RW0 “2” (corresponding to RW1 (2 bits) in FIG. 2) LD, ST, NOP is a command having a role similar to that described with reference to FIG.
FIG. 3C shows an instruction set of the access arbitration circuit ARB, and instructions from the ARB to the memory control circuit MCTL correspond to the ARB instruction signals ICOM [0] to ICOM [3] (ICOM (4 bits) in FIG. 2). Represented). R and W are a read command and a write command, respectively, and are issued corresponding to the LD and ST of the CPU and HDC. The access end instruction EOA is an instruction indicating the end of access. The refresh instruction RF is an instruction for causing the MEM to refresh. RF is issued in response to a refresh request from the refresh control circuit RFC which is the third master. SR and NOP are instructions having the same role as the instruction already described with reference to FIG.
FIG. 3D shows an instruction set of the memory control circuit MCTL, and instructions from the MCTL to the MEM are based on MCTL instruction signals MCOM [0] to MCOM [2] (corresponding to MCOM (3 bits) in FIG. 2). Is represented. The bank active instruction BA is an instruction for selecting a word line of a specific memory bank of the memory block MEM. The column read command RD is a command for reading data on a selected word line in a specific memory bank of the MEM. A column write instruction WT is an instruction for writing data on a selected word line of MEM. The precharge command PRE is a command for deselecting the selected word line and closing the page. NOP is an instruction meaning that nothing is done as in FIG.
Next, the operation of the information processing apparatus in FIG. 2 will be described. When loading data into the CPU, the access request signal REQ0 is set to Low. Simultaneously with the access request, a load command is output from RW0, a CPU identification signal from MAD0, and an address from ADD0 to the access arbitration circuit ARB.
The hard disk controller HDC has a 512-byte buffer inside, and when loading data of the memory block MEM into this buffer, the access request signal REQ1 is set to Low. Simultaneously with this access request, a load command from RW1, an identification signal of HDC from MAD1, and an address from ADD1 are output to ARB.
The data stored in the memory block MEM has a property that it disappears if a refresh operation is not performed when a DRAM is used. It is necessary to periodically make a refresh request from the refresh control circuit RFC. There is. When requesting a refreg from RFC, REG2 is set to Low, and at the same time, a refresh command is output from RW2, an identification signal of RFC from MAD2 and an address ARB from ADD2.
The access arbitration circuit ARB monitors whether there is an access request from the CPU, an access request from the HDC, and an access request from the RFC, and assigns a priority to each access request from the master. Allow access from the master. The priority order can be changed according to the type and number of masters constituting the information processing apparatus. In this case, since the access from the RFC is the refresh control, the first priority is set. Further, since access from the HDC is an interrupt process, the second priority is set, and access from the CPU is set to the last third priority.
When the access arbitration circuit ARB sets ACK0 to Low and permits an access request for a load command from the CPU, it outputs the CPU identification signal from IMAD, the read command from ICOM, and the address from IADD to the memory control circuit MCTL. MCTL receives the signal from ARB and controls MEM.
FIG. 4 is a configuration example of the memory block MEM used in the present invention. Reference numerals 3M0, 3M1, 3M2, and 3M3 denote memory macros, and each memory macro includes four memory banks 3B0, 3B1, 3B2, and 3B3. In this example, it is assumed that the data input buffer circuit IBUF and the output buffer circuit OBUF are shared among four macros and are integrated on one chip, although not particularly limited. However, the MEM can also be configured by a memory module that operates by receiving a command such as a well-known SDRAM in each memory macro and uses a plurality of them. FIG. 5 shows a configuration example of the DRAM in one memory bank, and FIG. 6 shows the operation of the MEM.
Hereinafter, an example of an access operation to the memory block MEM will be described with reference to FIGS. From MCOM to bank active instruction BA and MADD, row address RW0 (10 bits of MADD [13: 4]), macro address MC0 (2 bits of MADD [1: 0]), puncture address BK0 (MADD [3: 2]) 2 bits), one of the 16 banks is selected by the macro address MC0 and the puncture address BK0, and the row address 301 in the selected memory bank is set to 1096 word lines by the row address RW0. One word line WL is selected, and 4096-bit memory cell data for one page passes through 4096 bit line pairs (BL0-0 and BLB0-0 to BL256-15 and BLB256-15). Transferred to and held by the amplifier 303. The sense amplifier is a latch-type sense amplifier in which two CMOS inverters are cross-coupled, and has an amplification and latch function. In this sense, the sense amplifier can be regarded as a data latch circuit. The sense amplifier is not limited to the above-described latch type sense amplifier, and may be a circuit that separates the amplification unit and the latch unit of the sense amplifier. In order to read the data held in the sense amplifier, the read command RD and MADD from MCOM to the column address CA0 (4 bits of MADD [7: 4]) and the macro address MC0 and the bank address BK0 in the bank active command are the same. The macro address MC0 and the bank address BK0 are input. One of the 16 banks is selected by the macro address MC0 and the bank address BK0, and the column decoder 300 selects one column address by the column address CA0. Of the 4096 column switches in the column switch group 304, 256 column switches are selected according to the selected column address, and 256-bit data in the sense amplifier 303 is output to the global bit line GBL. It passes through the output buffer 306 and is output to the outside of the MEM. Thereafter, the page is closed by the precharge signal PRE and the bank address BK0. In such a normal operation, the latency until the memory control circuit 1 receives a command from the CPU and the data is output from the MEM is 5.
FIG. 1 shows a memory control circuit MCTL of the present invention. This circuit identifies the master that accesses the memory block MEM, thereby dynamically switching the control mode for controlling the MEM corresponding to the master when an access from the master occurs. A switching circuit (CREG) 101 is included. In addition, for each memory bank, an in-page access determination circuit (PH) 102 that determines whether the row address that has already been selected matches the row address of the access that has currently occurred, and a control command is issued to the MEM. An instruction generation circuit (or command generation circuit) (CGEN) 103 and an address generation circuit (AGEN) 104 for generating an address are included. Further, an input / output data control circuit (DQB) 105 for controlling input / output data is included.
In accordance with shift registers 1a, 1b, 1c and 1d, and master identification signal IMAD, control mode switching circuit CREG outputs signal 1e from shift register 1a, output signal 1f from register 1b, and output signal 1g from register 1c. And a selection circuit 1i that selects the output signal 1h from the register 1d, and a latch circuit 1k that latches the output signal 1j of the selection circuit 1i. Each of the shift registers 1a to 1d is a shift register that sets a flag signal necessary for selecting a control mode for each master. 1a is a flag signal of the CPU, 1b is a flag signal of the hard disk controller HDC, 1c is a flag signal of the refresh control circuit RFC, and 1d is a flag signal of another master.
FIG. 7 shows the operation of setting the CREG shift registers 1a to 1d and flags. As a specific example, the CPU flag signal High is sent to the shift register 1a, the HDC flag signal Low is sent to the shift register 1b, the RFC flag signal Low is sent to the shift register 1c, and the other master flag signals Low are sent to the shift register 1d. Operation when set to. When the CPU issues a set register instruction SR and the ARB permits access, the set register instruction SR is input to the memory control circuit 1 through ICOM. In the set register instruction, as shown in FIG. 3, the 0th bit signal of ICOM becomes the flag data FLAG_D set in the shift register.
Four consecutive set register instructions are issued from ICOM. In the first set register instruction, the flag data is set to High, the second set register instruction is set to Low, the third set register instruction is set to Low, and the fourth set register instruction is set. When the set register instruction is set to Low and input to the memory control circuit, High is set to 1d at the first rise of the set register instruction clock. 1d data is transferred to 1c at the next rising edge of the clock, 1c is set to High, 1d is set to Low, 1c data is transferred to 1b at the next rising edge of the clock, and 1b is set to High. Is set, 1d data is transferred to 1c, 1c is set to Low, and 1a is set to Low. Thus, by shifting the flag data, finally, 1a is set to High, 1b is set to Low, 1c is set to Low, and 1d is set to Low.
FIG. 8 is a flowchart showing the operation of the control mode switching circuit CREG. In this figure, INPUT M_ID surrounded by four corners means a master identification number input operation, and WAIT M_ID means a master identification number input waiting operation. The description will be made assuming that the CPU identification number is 0, the hard disk controller HDC identification number is 1, the refresh control circuit RFC identification number is 2, and the other master identification numbers are 3. When access from the CPU is permitted to the access arbitration circuit and the CPU identification signal 0 is input to the memory control circuit MCTL through the IMAD, the flag signal High of the shift register 1a passes through the output signal 1e and is selected by the selection circuit 1i. 1i is output to the output signal 1j, High is latched in the latch circuit 1k, and the output LMS becomes High.
When access from the HDC is granted to the ARB and the HDC identification signal 1 is input to the MCTL through the IMAD, the flag signal Low of the shift register 1b is selected by the selection circuit 11 through the output signal 1f, and the output signal 1j of the selection circuit 1i , Low is latched in the latch circuit 1k, and its output LMS becomes Low. When access from the RFC is permitted to the access arbitration circuit and the RFC identification signal 2 is input to the MCTL through the IMAD, the lag signal Low of the shift register 1c passes through the output signal 1g and is selected by the selection circuit 1i. The output signal 1j is output, Low is latched in the latch circuit 1k, and the output LMS becomes Low.
The values of the shift registers 1a, 1b, 1c, and 1d can be set by providing a dedicated setting terminal outside. Further, the values of the shift registers 1a, 1b, 1c, and 1d can be set by being connected to a power source or a ground with a metal layer or a diffusion layer when integrated on silicon. This is a so-called metal option.
Next, the operation of the in-page access determination circuit PH will be described. FIG. 9 shows a row address selection PS signal (PS) and a row address (ROW_ADD) corresponding to each memory bank bank number (BANK NO.) Of each memory macro number (MACRO NO.) Set in PH. . When the row address selection signal PS is Low, it indicates that the row address of the bank is not selected, and when it is High, it indicates that the row address of the bank is selected. HT is an in-page access determination signal indicating whether or not a current access has occurred to a selected row address, that is, whether or not the access is within the same page. When the HT page access determination signal is High, it indicates an access within the same page as the selected row address, and when it is Low, a page access or row address different from the selected row address is selected. Indicates that the access has not been made. When HT is Low, the row address already set in the selected bank is always replaced with the row address in the current access by the current access. When HT is High, the row address does not change.
The IADD is composed of an 18-bit address and is not particularly limited. However, in the embodiment of FIG. 2, the most significant 17th to 8th bits are the MEM row address, and the 7th to 6th bit. The MEM memory bank address, the 5th to 4th bits are the MEM memory macro address, and the 3rd to 0th bits are the MEM column address.
The memory macro address, memory bank address, and row address in the IADD address are input to the in-page access determination circuit PH. In PH, first, a PS signal corresponding to one memory bank selected by the memory macro address and the memory bank address is output to the instruction generation circuit CGEN and the address generation circuit AGEN. When the PS signal is low, it is set to 1 at the rising edge of the next clock. When an access end command is input from ICOM and LMS is 0, the selected PS signal is set to 0.
Next, the operation of the in-page access determination signal HT signal will be described. When the PS signal of one memory bank selected by the IADD address is Low, HT is set to Low. When the PS signal is High, if the row address of one bank selected by the memory macro address and the memory bank address matches the current access row address, HT is set to High, and otherwise, HT is set to Low. . The HT signal is output to the instruction generation circuit CGEN and the address generation circuit AGEN.
FIG. 10 shows an example of operations of the instruction generation circuit CGEN and the address generation circuit AGEN when a read instruction is input. CGEN and AGEN are supplied with a read command from ICOM, an address from IADD, an in-page access determination signal HT and a row address selection signal PS from in-page access determination circuit 102, and an LMS from control mode switching circuit 101.
When the row address selection signal PS is Low, CGEN and AGEN first perform a row operation in normal access. Specifically, CGEN first outputs a bank active instruction BA, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM. After two cycles, the column operation is performed. Specifically, CGEN outputs a read command RD, and AGEN outputs a column address, a memory macro address, and a memory bank address to MEM, and reads the data.
When the row address selection signal PS is High and the in-page access determination circuit signal HT is Low, the current access is an access to a row address different from the already selected row address, that is, an access to a different page. Show. In accessing a different page, first, a precharge operation is performed to deselect a previously selected row address, and then a row operation is performed to select a new row address. After two cycles, column operation is performed to read data.
When the row address selection signal PS is High and the in-page access determination circuit signal HT is High, the current access indicates an access within the already selected row address, that is, an access within the same page. At this time, no row operation is required, column operation is performed, and data is read.
For an access of a page different from the normal access, when EOA indicating the end of access is input from ICOM after the end of the column operation, if LMS is Low, a precharge operation is performed and the page of the MEM memory bank is closed. . When LMS is high, the next access is performed while the page is opened without performing the precharge operation. When accessing the same page, the next access is waited with the page opened.
FIG. 11 shows an example of operations of the instruction generation circuit CGEN and the address generation circuit AGEN when a refresh instruction is input. CGEN and AGEN are supplied with a refresh command from ICOM, an address from IADD, an in-page access determination signal HT and a row address selection signal PS from in-page access determination circuit 102, and an LMS from control mode switching circuit 101.
When the row address selection signal PS is Low, CGEN and AGEN first perform a row operation in normal access. Specifically, CGEN first outputs a bank active instruction BA, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM.
When the row address selection signal PS is High and the in-page access determination circuit signal HT is Low, the current access is an access to a row address different from the already selected row address, that is, an access to a different page. Show. In accessing a different page, first, a precharge operation is performed to deselect a previously selected row address, and then a row operation is performed to select a new row address.
When the row address selection signal PS is High and the in-page access determination circuit signal HT is High, the current access indicates an access within the already selected row address, that is, an access within the same page. Do nothing at this time.
For an access to a page different from the normal access, when EOA indicating the end of access is input from ICOM after the row operation is completed, if LMS is Low, a precharge operation is performed and the page of the memory bank of MEM is closed. . When LMS is high, the next access is performed while the page is opened without performing the precharge operation.
FIG. 12 shows the latency when accessing the same page, normal access, and different pages as described above. When accessing the same page, read latency is 3, write latency is 1, normal access is read latency is 5, write latency is 3, and when accessing different pages, read latency is 7, and write latency is 5. Become.
In FIG. 13, after the power is turned on (T1 (INIT)), an access from the CPU (T2 (CPU)), an access from the hard disk controller HDC (T3 (HDC)), and an access from the CPU (T4 (CPU)) occur. Specific operation in the case of PW in the T1 (INIT) period indicates the initial operation after the power is turned on and after the power is turned on. Each of C0 to Cm in the T2 (CPU) period indicates one access from the CPU, and H0 in the T3 (HDC) period indicates one access from the HDC.
As described above, according to the present invention, the access from the CPU keeps the word line of the MEM selected at the end of the access, that is, keeps the page open, and the access from the HDC and the refresh control circuit MCTL Flag data is set in the shift registers 1a, 1b, 1c and 1d so that the page is closed at the end of access. Specific examples of the operation are shown in FIGS. 14 to 17, IMAD is a master identification number, and ICOM corresponds to the instruction of FIG. Here, the NOP instruction is abbreviated as N. IADD represents an access address, AD0 is in a state where a predetermined address signal is input, and DC (Don't Care) indicates a state in which the address is indefinite. MCOM corresponds to the instruction of FIG. MADD also represents an access address for MEM.
By the initial operation (T1 (INIT)) after power-on, the row address selection signal PS signal of each bank becomes Low. Therefore, the first access (C0) in the T2 (CPU) period from the CPU to each memory bank is a normal access, and the data read latency is 5. This operation is shown in FIG.
On the other hand, FIG. 15 shows the operation in the page hit state (HT = 1) in the second and subsequent accesses (C1 to Cn) in the T2 (CPU) period. According to the present invention, for the CPU access, the precharge operation for closing the page is not performed at the end of the access, and the page is kept open. When most of the second and subsequent accesses to the same page occur, the read latency is 3, and the MEM can be operated at a higher speed than the normal operation.
FIG. 16 shows the access of H0 in the T3 (HDC) period when the access is switched from the CPU to the hard disk controller HDC. In this access, it is assumed that a 512-byte read command is issued from the HDC to the MEM. First, the first half of FIG. 16 shows an operation when a page miss occurs in the first access of H0. Since each memory bank of the memory block MEM is in a state where a page is opened for CPU access, an access from the HDC is almost an access to a different page. In FIG. 16, the read latency of the first access is 7.
Subsequent accesses of the hard disk controller HDC occur in the same page, and a total of 16 accesses are made to read 512 bytes, resulting in a latency of 22. When EOA indicating the end of access is input, a precharge operation is performed and the page is closed. Compared with the case of normal access, the read latency of the first data is delayed by 2 latencies, that is, 20 ns, but when the HDC writes 512 bytes of data to the hard disk, it takes about several ms, so 20 ns The delay is not a problem in operation.
In the T4 (CPU) period of FIG. 13, the access of Cn + 1 when the access is switched from the HDC to the CPU is as follows. According to the present invention, the page of one memory bank that has been accessed from the HDC is closed, and the remaining pages of the memory bank remain open by CPU access. When the CPU access accesses a bank whose page is closed, it becomes a normal access and the latency is 5.
When the control mode switching circuit according to the present invention is not used, the page is kept open by the access from the hard disk controller HDC, and when the CPU accesses the bank holding this state, it is almost different. Access to the page. As a result, the read latency of access from the CPU is 7, which is delayed by two latencies from the normal access, and this latency directly affects the operation of the CPU. Therefore, according to the present invention, for an access from the HDC, by closing the page at the end of the access, even if an access from the CPU after this access occurs in the memory bank that was previously accessed by the HDC, There is no increase in latency.
FIG. 17 shows an operation timing chart at the time of a refresh request from the refresh control circuit RFC. In this case, it is assumed that the page was closed by the previous access. An access from RFC occurs interruptively to the MEM about once every 4 μs, and the page is closed at the end of the refresh operation. That is, in FIG. 17, MCOM ends with PRE. That is, since the same address is not accessed in the next RFC access after 4 μs, the page should be closed. Even if an access from the CPU occurs in the memory bank accessed by the refresh control circuit after this access, the latency does not increase.
Examples of the development form of the information processing apparatus of the present invention on a specific semiconductor chip include the following. First, as a first mode, there is a mode in which a master such as a CPU, HDC, and RFC and each of ARB, MCTL, and MEM are formed on individual semiconductor chips. Here, there are two possible types of MEMs: a case where all DRAMs are formed on one chip and a case where they are formed by a plurality of DRAM chips. A well-known SDRAM etc. can be used for a DRAM chip. Next, as a second form, there is a form in which three function blocks of RFC, ARB, and MCTL are integrated on one chip as a memory control chip. Other CPUs and the like are formed on individual semiconductor chips as in the first embodiment. As a third form, there is a form in which MCTL and MEM are formed on one chip. Others are the same as the first embodiment. Furthermore, as a fourth mode, it is also effective in a small-scale system to integrate the CPU, RFC, ARB, MTL, and MEM all in one semiconductor chip. Even in this case, although not particularly limited, a master to be an external option such as HDC is a separate chip. If HDC or the like is essential as a system, it may be integrated as necessary.
<Example 2>
FIG. 18 shows an embodiment of the memory control circuit 100 according to the present invention. In this embodiment, a refresh counter 106 for generating a refresh address is added to the embodiment shown in FIG. When a refresh command is input from the ICOM, the address selection circuit 107 selects an address from the refresh counter and outputs it to the in-page access determination circuit 102 and the address generation circuit. The refresh counter counts up the refresh address every time a refresh command is input.
FIG. 19 shows an information processing apparatus using the memory control circuit 100. This includes a CPU, an HDC, an access arbitration circuit 2 that arbitrates accesses from the CPU and the HDC, a MEM that includes a plurality of banks, and a memory control circuit 1 that controls the MEM by signals from the access arbitration circuit 2. And a hard disk 50 and a refresh control circuit 6 for controlling the refresh operation of the MEM. The CPU, HDC, and refresh control circuit 6 do not have the MAD identification signal shown in FIG. 2, and the ports of REQ0, REQ1, and REQ2 are connected to the access arbitration circuit. The access arbitration circuit identifies the master by the ports of REQ0, REQ1, and REQ2, receives a request from each master, and when access is permitted, converts the port information into a master identification signal IMAD.
Since the refresh counter 106 is provided in the memory control circuit 100, it is not necessary to input a refresh address from the refresh control circuit 6, and only the refresh request signal REQ2 and the refresh permission signal ACK0 are connected.
Accordingly, the configuration example of the information processing apparatus of FIG. 19 can also realize the present invention and reduce the number of terminals, which can contribute to cost reduction.
<Example 3>
FIG. 20 shows an embodiment in which the CPU 4, the MPEG decoder (MPEG DEC) 5001, the video interface circuit (VIF) 600, and the RFC become the master and access the memory block MEM. At this time, the MEM is shared by the CPU, MPEG DEC, and VIF.
As in the first embodiment, the CPU access opens the page even when the access is completed, and the MPEG decoder, the video interface, and the refresh control circuit 6 access the page at the end of the access. Consider the case where switching control is performed.
The MPEG decoder decompresses compressed data stored in a CD-ROM or the like and temporarily stores it in the MEM. For display, data in the MEM is read from the video interface. At this time, the data transfer rate required for the MEM in order for the MPEG decoder to decompress the data is about 160 MByte / sec.
When the memory capacity of one frame necessary for display is calculated, one frame is composed of 720 × 480 pixels in the NTSC, and the luminance signal Y is 8 bits, and the color difference signals Cr and Cb are 8 bits respectively. Then, the total number of bits in one frame is about 4 Mbit. If 60 frames are read out per second, a data transfer rate of about 30 MByte / sec is required for display. Therefore, a total transfer rate of 190 MByte / sec is required.
The MPEG decoder 501 and the display interface circuit 600 are connected to the memory block (MEM) 50 through the access arbitration circuit 201 and the memory control circuit 101 via a 512-bit data bus.
At this time, the access to the memory block 351 where the data transfer rate of the MPEG decoder 501 is the lowest is the access of different pages and only once. In this access, in order to output 512-bit data, it takes 7 latencies, that is, 70 ns, and the data transfer rate is (512/8) Byte × (1 × 1000/70) MHz = 911 MByte / sec. Considering that the MPEG decoder requires a transfer rate of about 190 MByte / sec at the maximum, the transfer rate of 911 MByte / sec is sufficient, and even if the remaining transfer rate is used for the CPU, the MPEG decoder There is no problem in the operation. Therefore, also in the second embodiment, the access from the MPEG decoder, the display interface circuit 701 and the refresh control circuit 600 according to the present invention is performed after the access by closing the page at the end of these accesses. Even if access from the CPU occurs in a memory bank that was previously accessed by either the MPEG decoder or the video interface, the latency of the DRAM does not increase and the speed can be increased.
<Example 4>
FIG. 21 shows an embodiment in which the CPU 4, the graphics processing circuit (GC) 502, and the display interface circuit (VIF) 702 access the DRAM by the master and the refresh control circuit (RFC) 602. At this time, the memory block (MEM) 352 is shared by the GC, the VIF, and the CPU.
In the same way as in the first embodiment, the CPU access opens the page even when the access is completed, and the GC, VIF, and RFC access control is performed to switch the page closed at the end of the access.
The data processing speed required for drawing by the graphics processing circuit 502 and the data transfer speed required for display by the display interface circuit 702 are as follows.
The number of bits per pixel is 24 bits for R, G, and B representing colors, 16 bits for Z values representing depth, 8 bits for α values representing transparency, a total of 48 bits, a frame rate of 60 Hz, If the frame size is 640 × 480, the transfer rate required for drawing is approximately 884 MByte / sec, the transfer rate required for display is approximately 110 MByte / sec, and a total transfer rate of 1 GByte / sec is required.
The graphics processing circuit GC and the display interface circuit 702 are connected to the access arbitration circuit 2 and the memory block 352 through the memory control circuit 102 via a 2048-bit data bus. At this time, the access to the memory block 352 having the lowest GC data transfer rate is a different page access and only once. In this access, in order to output 2048-bit data, it takes 7 latencies, that is, 70 ns, and the data transfer rate is (2048/8) Byte × (1 × 1000/70) MHz = 3.6 GByte / sec.
Considering that the graphics processing circuit 502 and the display interface circuit 602 together require a transfer rate of about 1 GByte / sec, the transfer rate of 3.6 GByte / sec has a sufficient margin, and the remaining transfer rate is Even if it is used for the CPU, no problem occurs in the operation of the graphics processing circuit. Therefore, also in the third embodiment, the operation of the DRAM can be speeded up by the present invention.
The DRAM used in the embodiment described above shows an example in which a plurality of memory macros are integrated on one chip, but this is not a limitation. The present invention can be realized by treating a DRAM of an individual chip as a memory macro.
As described above, access from a plurality of masters sharing a DRAM has its characteristics, and the present invention can control the DRAM by switching the control mode corresponding to the plurality of masters. DRAM can be operated at high speed.
Industrial applicability
The present invention can be applied to an information processing apparatus, particularly a computer apparatus typified by a personal computer apparatus. This information processing apparatus may be versatile or may be incorporated as a part of the control apparatus.
[Brief description of the drawings]
FIG. 1 shows a memory control circuit MCTL according to an embodiment of the present invention. FIG. 2 is an overall configuration diagram of an information processing apparatus to which the present invention is applied. FIG. 3 is an example of the instruction set of each master. FIG. 4 is an example of a block diagram of the memory block MEM of FIG. FIG. 5 is an example of a configuration diagram in a bank configuring the block diagram of FIG. FIG. 6 is a diagram illustrating an example of control of the memory block MEM of FIG. FIG. 7 is a diagram showing an example of control for setting data in the shift register of FIG. FIG. 8 is a flowchart showing the operation of the control mode switching circuit of FIG. FIG. 9 is an example of a diagram showing a row address selection signal and a row address corresponding to each memory bank set by the in-page access determination circuit of FIG. FIG. 10 is a flowchart showing the operation of the instruction generation circuit and address generation circuit of FIG. FIG. 11 is a flowchart showing the operation of the instruction generation circuit and address generation circuit of FIG. FIG. 12 is a diagram showing the latency of the DRAM for each access. FIG. 13 is a diagram showing an example of the temporal transition of the master accessing the DRAM. FIG. 14 is a waveform diagram showing an example of an operation for access from the CPU. FIG. 15 is a waveform diagram showing an example of an operation for access from the CPU. FIG. 16 is a waveform diagram showing an example of an operation for access from the hard disk controller HDC. FIG. 17 is a waveform diagram showing an example of an operation for an access from the refresh control circuit. FIG. 18 is a diagram showing another embodiment of the memory control circuit of the present invention. FIG. 19 is a diagram showing another embodiment of the information processing apparatus of the present invention. FIG. 20 is a diagram showing another embodiment of the information processing apparatus of the present invention. FIG. 21 is a diagram showing another embodiment of the information processing apparatus of the present invention.

Claims (9)

A memory block including a plurality of memory banks;
A first master capable of accessing the memory block;
A second master capable of accessing the memory block;
A memory control circuit for receiving an access request from the first and second masters and outputting an access command to the memory block;
The memory control circuit accesses one of the plurality of memory banks in a first procedure when there is an access request from the first master, and when there is an access request from the second master. Accesses one of the plurality of memory banks in the second procedure,
Each of the plurality of memory banks includes a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines, each including one MOS transistor and one capacitor.
When the access request is a data read request from one of the plurality of memory banks, the first procedure includes an instruction to activate the selected memory bank and end the read operation, The procedure includes an instruction to put the selected memory bank into a precharged state and end the read operation,
Each of the access requests of the first and second masters includes a bank address for designating one of the plurality of memory banks, and one of the plurality of word lines in one of the plurality of memory banks. And a master identification information indicating whether the access request is made from the first master or the second master, and
The memory control circuit includes a first determination circuit that determines whether the memory bank corresponding to the bank address is in the active state or the precharge state when the access request is made; When the corresponding memory bank is in an active state, it is determined whether one of the plurality of word lines in the selected state among the memory banks in the active state matches the row address included in the access request And a control mode switching circuit for holding information indicating whether to perform the first procedure or the second procedure for each of the first and second masters, and the access request Either the first procedure or the second procedure according to the master identification information and the information held in the control mode switching circuit The information processing apparatus characterized by determining whether to perform. In claim 1,
Each of the plurality of memory banks includes a plurality of data latch circuits,
When the access request is a data read request from one of the plurality of memory banks, the first procedure holds predetermined data read from a selected memory cell in the plurality of data latch circuits. And holding the data in the plurality of data latch circuits after the data is output to the first master, and the second procedure includes the predetermined data read from the selected memory cell as the plurality of data. An information processing apparatus comprising: an operation of clearing data held in the plurality of data latch circuits after being held in the data latch circuit and outputted to the second master. In claim 2,
The information processing apparatus further includes an access arbitration circuit inserted between the first and second masters and the memory control circuit,
When the access request of the first master and the access request of the second master conflict with each other, the access arbitration circuit preferentially transmits the access request of the second master to the memory control circuit. An information processing apparatus that transmits an access request of a first master to the memory control circuit. In claim 3,
The information processing apparatus, wherein the first master is a CPU. In claim 1,
The information processing apparatus, wherein the first master is a CPU. In claim 1,
When the access request is a data read request from a memory bank, the first procedure reads out predetermined data by selecting one of the plurality of word lines in the corresponding memory bank, and the first master And the second procedure reads out predetermined data by selecting one of the plurality of word lines in the corresponding memory bank. And an operation for outputting the selected word line to a non-selected state. In claim 1,
When the access request is a data read request from a memory bank, the first procedure activates the corresponding memory bank and outputs predetermined data to the first master and then activates the corresponding memory bank. And the second procedure includes an operation of outputting predetermined data from the corresponding memory bank to the second master and then precharging the corresponding memory bank.   In claim 1,
  The information processing apparatus further includes a hard disk device,
  The information processing apparatus according to claim 1, wherein the first master is a CPU, and the second master is a hard disk controller coupled to a hard disk device.   In claim 1,
  The information processing apparatus, wherein the first master is a CPU, and the second master is a refresh controller of the memory block.

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