JP4547984B2 - Semiconductor device - Google Patents

Description

The present invention includes a plurality of circuit units on a single semiconductor substrate, each of which is provided with a vertical zener diode for surge voltage protection such as electrostatic discharge (ESD), and is particularly used in a vehicle. Relates to the device.

In a semiconductor device in which a plurality of power semiconductor elements, control circuits, and horizontal surge protection elements are formed on the same semiconductor substrate, the power is increased by the application of external surge voltage or noise voltage and the surge voltage generated by the operation of the power semiconductor element itself. The normal operation of the semiconductor element or the control circuit may be disturbed. In order to prevent this, it is necessary to isolate the power semiconductor element, the control circuit, and the surge protection element from each other. As a method for isolation, a dielectric isolation structure or a junction using a high concentration buried epitaxial layer and a high concentration isolation diffusion layer is used. Separation structure is applied.
In semiconductor devices for automobiles, miniaturization and integration are promoted by using the dielectric isolation structure and the junction isolation structure, and an area for forming a power semiconductor element and a control circuit is reduced.
However, in semiconductor devices for automobiles, demands for surge resistance such as ESD resistance and noise resistance are particularly severe, so that the area occupied by a horizontal surge protection element increases and the chip area increases.

For this reason, power semiconductor elements and control circuits other than surge protection elements are formed on the same semiconductor substrate to reduce the chip area, and a surge protection element such as a Zener diode, resistor / capacitor, etc. is externally attached to achieve high surge resistance. There are many examples.
On the other hand, there is a method of reducing the chip area by forming a vertical Zener diode as a surge protection element on the same semiconductor substrate.
FIG. 7 is a plan view of a main part of a conventional semiconductor device having a vertical Zener diode. A large number of input terminals (cathode electrodes 58, 59, etc.) are formed in the periphery of the chip, and a vertical Zener diode, which is a surge protection element, is disposed under the input terminals. A control circuit, a power semiconductor element, and the like are disposed inside the chip. The input terminal is a bonding pad and a cathode electrode of a vertical Zener diode.

A vertical Zener diode can absorb a higher surge voltage even in a small area because it can pass a larger current per unit area than a horizontal Zener diode, and has a great protection effect. Further, the operating resistance of the vertical Zener diode can be made smaller than that of the horizontal Zener diode, the surge absorption / protection effect is further increased, and the element area can be reduced.
8A and 8B are main part configuration diagrams of a conventional semiconductor device, in which FIG. 8A is an enlarged view of a portion A in FIG. 7, and FIG. FIG. These drawings are main part configuration diagrams of two adjacent vertical diodes.
The n-type cathode regions 53 and 54 adjacent to the surface layer of the p-type semiconductor substrate 51 are formed, the cathode electrodes 58 and 59 are formed on the n-type cathode regions 53 and 54, and the back surface of the p-type semiconductor substrate 51 is common. A back electrode 61 as an electrode is formed. The n-type cathode regions 53 and 54 and the p-type semiconductor substrate 51 constitute a pn junction vertical diode, and the p-type semiconductor substrate 51 becomes a p-type anode region.

A p-type diffusion region 56 is formed so as to surround the n-type cathode regions 53 and 54 apart from the n-type cathode regions 53 and 54, respectively. The p-type diffusion region 56 functions to stop the depletion layer extending from the n-type cathode regions 53 and 54 to the surface layer of the p-type semiconductor substrate 51. The cathode electrodes 58 and 59 become input terminals IN1 and IN2 which are also bonding pads, and input signals are independently input thereto. Further, the cathode electrode is connected to the high potential side terminal Vcc (for example, about 14 V) of the power supply via the pull-up resistors 62a and 62b (for example, about 10 kΩ). Furthermore, the cathode electrodes 58 and 59 are also connected to a power semiconductor element (not shown) that is a protected element, a control circuit, and the like. The back electrode 61 is connected to the ground GND.
In addition, a structure has been reported in which a diffusion region is formed in the surface layer of the semiconductor substrate between two adjacent vertical Zener diodes, and this diffusion region is connected to the ground to prevent mutual influence between the input terminals. (For example, Patent Document 1).
Japanese Patent Laid-Open No. 6-224427 FIG.

The operation of the semiconductor device in FIG. 8 will be described. In normal operation, the forward current does not flow because the pn junction of the vertical Zener diode is in a reverse bias state. However, for example, when a negative surge voltage is applied to the input terminal IN 1, that is, a negative surge voltage is applied to the cathode electrode 58, the back electrode 61 passes through the n-type cathode region 53 to the cathode electrode 58. Excessive surge current flows. This surge current is a main current 71, which is a hole current flowing from the p-type semiconductor substrate 51 into the n-type cathode region 53 and an electron flow injected from the n-type cathode region 53 into the p-type semiconductor substrate 51. 74.
A part of this hole flow becomes a gate current of a parasitic npn transistor composed of the n-type cathode region 53, the p-type semiconductor substrate 51, and the n-type cathode region 54, and the parasitic npn transistor is operated, and the n-type cathode region is operated. An electron flow 74 flows from 53 to the n-type cathode region 54 via the p-type semiconductor substrate 51. This electron flow 74 enters the n-type cathode region 54, flows through the cathode electrode 59 and the pull-up resistor 62b, and flows into the high potential side terminal Vcc of the power source, causing a voltage drop of the pull-up resistor 62b, and the adjacent input terminal IN2 The control circuit connected thereto is made unstable or malfunctions.

  An object of the present invention is to provide a semiconductor device that solves the above-described problems and suppresses fluctuations in potential of adjacent input terminals and stabilizes circuit operation when a negative surge voltage is input. It is in.

In order to achieve the above object, a semiconductor element formed on a semiconductor substrate, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes (for example, vertical Zener diodes) that are surge protection elements are included. In a semiconductor device, a plurality of second conductivity type first diffusion regions formed in a surface layer of a first conductivity type semiconductor substrate are sandwiched between the adjacent first diffusion regions, and the first diffusion regions are separated from each other. A second diffusion region of a first conductivity type formed in a surface layer of the semiconductor substrate apart from the first diffusion region on both sides of the second diffusion region and in contact with the second diffusion region; A third diffusion region of a second conductivity type formed on a surface layer of the substrate; a first metal electrode formed on the first diffusion region; and formed on the second diffusion region and the third diffusion region. Second metal electrode and the semiconductor substrate And a back surface electrode formed on the back surface, the a semiconductor device constituting the vertical pn junction diode with the semiconductor substrate and the first diffusion region, a structure in which the second metal electrode is connected to the ground.

The second diffusion region may have a deeper diffusion depth than the third diffusion region.
Further, in a semiconductor device having a semiconductor element formed on a semiconductor substrate, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements, a surface layer of the first conductivity type semiconductor substrate is provided. A second conductive layer sandwiched between the formed first diffusion regions of the second conductivity type and the adjacent first diffusion regions, and formed on the surface layer of the semiconductor substrate away from the first diffusion regions. A fourth diffusion region of the mold, and a fifth fifth of the first conductivity type formed on the surface layer of the semiconductor substrate in contact with the fourth diffusion region on both sides of the fourth diffusion region and in contact with the fourth diffusion region. A diffusion region, a first metal electrode formed on the first diffusion region, a third metal electrode formed on the fourth diffusion region and the fifth diffusion region, and a back surface of the semiconductor substrate A back electrode, and the semiconductor substrate and the first electrode A semiconductor device constituting the vertical pn junction diode diffusion region, a structure in which the third metal electrode is connected to the ground.

  The fourth diffusion region may have a deeper diffusion depth than the fifth diffusion region.

  According to the present invention, the diffusion region formed in the surface layer of the semiconductor substrate between the adjacent vertical Zener diodes is connected to the ground, so that when a negative surge voltage is applied, the main current flowing through the vertical Zener diodes is applied. Efficiently absorbs the current that is part of the current, prevents the current that has leaked into the adjacent input terminal from flowing in, and suppresses fluctuations in the potential of the adjacent input terminal, thereby stabilizing the circuit operation. Can be planned. Further, the diffusion region is formed on the surface layer of the p-type semiconductor substrate with both sides of the p-type diffusion region sandwiched between the n-type diffusion regions, the p-type and n-type diffusion regions are short-circuited with a metal electrode, By connecting to the ground, the electrons exuded from the n-type cathode region are efficiently sucked into the n-type diffusion region, and the inflow of the electrons exuded into the adjacent n-type cathode region is suppressed, thereby stabilizing the circuit operation. Can be achieved.

By making the depth of the p-type diffusion region deeper than that of the n-type diffusion region, the p-type diffusion region becomes a potential barrier against the exuded electrons and prevents the electrons from entering the adjacent n-type cathode region. Thus, it is possible to efficiently absorb the electrons into the n-type diffusion region and suppress the inflow of the electrons exuded into the adjacent n-type cathode region, thereby stabilizing the circuit operation.
Further, by forming this diffusion region on the surface layer of the p-type semiconductor substrate with both sides of the n-type diffusion region sandwiched between the p-type diffusion regions, the p-type diffusion region functions as a stopper that suppresses the depletion layer extension. Thus, it is possible to prevent the n-type cathode region and the n-type diffusion region from being punched through by the surge voltage.
By making the depth of the n-type diffusion region deeper than that of the p-type diffusion region, the efficiency of sucking electrons is increased, and the leakage of electrons that have exuded to the adjacent n-type cathode region is suppressed, thereby stabilizing the circuit operation. Can be achieved.

In the embodiment of the present invention, when a negative surge voltage is applied, a part of the surge current flowing through the vertical Zener diode which is a surge protection element becomes a leaked current and enters an adjacent vertical Zener diode, In order to prevent the voltage at the input terminal from fluctuating, a region (diffusion region and metal electrode) for absorbing the leaked current is formed between two adjacent vertical Zener diodes, and this region is grounded. Is connected.
Embodiments of the present invention will be described below with reference to the drawings. The first conductivity type is p-type and the second conductivity type is n-type, but they may be reversed.

FIGS. 1A and 1B are main part configuration diagrams of a first embodiment of the present invention, in which FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX in FIG. is there. These figures are main part configuration diagrams of two adjacent vertical Zener diodes, and although not shown, a power semiconductor element and a control circuit which are protected elements as shown in FIG. Is formed.
N-type cathode regions 3 and 4 are formed adjacent to the surface layer of the p-type semiconductor substrate 1, cathode electrodes 8 and 9 are formed on the n-type cathode regions 3 and 4, A back electrode 11 that is a common electrode is formed. The n-type cathode regions 3 and 4 and the p-type semiconductor substrate 1 constitute a pn junction vertical Zener diode, and the p-type semiconductor substrate 1 becomes a p-type anode region.
The n-type diffusion regions 5 are formed separately from the n-type cathode regions 3 and 4 so as to individually surround the n-type cathode regions 3 and 4. A p-type diffusion region 6 is formed between the n-type diffusion regions 5 so as to be in contact with the n-type diffusion region 5. However, the n-type diffusion region 5 may not be formed outside the p-type diffusion region 6 on the chip end side. A metal electrode 10 is formed on the p-type diffusion region 6 and the n-type diffusion region 5, and the metal electrode 10 is connected to the ground GND. In the figure, reference numeral 7 denotes a LOCOS oxide film.

The cathode electrodes 8 and 9 become input terminals IN1 and IN2 which are also bonding pads, and input signals are input independently. The cathode electrodes 8 and 9 are connected to the high potential side terminal Vcc of the power supply via the pull-up resistors 12a and 12b. Further, the cathode electrodes 8 and 9 are connected to a power semiconductor element, a control circuit, and the like, which are protected elements, by metal wiring. The back electrode 11 is connected to the ground GND.
The operation of this semiconductor device will be described. In normal operation, the forward current does not flow because the pn junction of the vertical Zener diode is in a reverse bias state. However, for example, when a negative surge voltage is applied to the input terminal IN 1, that is, a negative surge voltage is applied to the cathode electrode 8, the back electrode 11 passes through the n-type cathode region 3 to the cathode electrode 8. Excessive surge current flows. This surge current is the main current 21 shown in the figure. The main current 21 is composed of a hole flow 25 flowing from the p-type semiconductor substrate 1 into the n-type cathode region 3 and an electron flow 23 flowing from the n-type cathode region 3 into the p-type semiconductor substrate 1. A part of the hole current 25 becomes a leaked hole current 26, and becomes a base current of a parasitic npn transistor 27 formed by the n-type cathode region 3, the p-type semiconductor substrate 1, and the n-type diffusion region 5, and a parasitic npn The transistor 27 is operated. When the parasitic npn transistor 27 is operated, the electron flow 24 exuded from the n-type cathode region 3 flows to the n-type diffusion region 5 at the ground potential, but does not flow to the n-type cathode region 4.

As described above, the n-type diffusion region 5 and the p-type diffusion region 6 for drawing out the current 24 that leaks between the adjacent vertical Zener diodes and the metal electrode 10 that short-circuits them are provided, and the metal electrode 10 is grounded. By connecting to, an electron flow that flows out to the n-type cathode region 4 adjacent to the n-type cathode region 3 can be prevented, and potential fluctuation of the cathode electrode 9 adjacent to the cathode electrode 8 can be suppressed. By suppressing the potential fluctuation, the operation of the circuit connected to the cathode electrode 9 serving as an adjacent input terminal is stabilized.
The p-type diffusion region 6 serves as a potential barrier that prevents electrons from flowing to the n-type cathode region 4.
1A, the n-type cathode regions 3 and 4 are not surrounded by the n-type diffusion region 5 and the p-type diffusion region 6 as shown in FIGS. Even if the n-type diffusion region 5 and the p-type diffusion region 6 are formed only between the regions, the same effect can be obtained. In FIG. 2, the n-type diffusion region 5 has a planar shape sandwiching the p-type diffusion region 6. In FIG. 3, the p-type diffusion region 6 is surrounded by the n-type diffusion region 5. Yes. In either case, the same effect as in FIG. 1 can be obtained.

  In addition, the p-type semiconductor substrate 1 may be replaced with an epitaxial substrate in which a high-resistance epitaxial layer is formed on a low-resistance p-type semiconductor substrate, and the respective diffusion regions may be formed in the epitaxial layer. When this epitaxial substrate is used, the operating resistance of the vertical Zener diode can be reduced, and the surge protection performance can be improved.

FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. This figure is a cross-sectional view of the main part of two adjacent vertical Zener diodes corresponding to FIG.
The difference from FIG. 1 is that the arrangement of the n-type diffusion region 5 and the p-type diffusion region 6 is interchanged. Again, the operation is the same as FIG. 1, an electronic flow 24 that exits viewed dyed from n-type cathode region 3 flows into the metal electrode 10 through the p-type semiconductor substrate 1, n-type semiconductor regions 5, It does not flow to the n-type cathode region 4. Further, the extension of the depletion layer is suppressed by the p-type diffusion region 6, and punch-through with a positive surge voltage can be prevented.

FIG. 5 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. This figure is a cross-sectional view of the main part of two adjacent vertical Zener diodes corresponding to FIG.
The difference from FIG. 1 is that the diffusion depth of the p-type diffusion region 6 is deeper than that of the n-type diffusion region 5. By doing so, the electron barrier 24 is blocked by the potential barrier formed in the p-type diffusion region 6, and electrons easily flow into the n-type diffusion region 5. Therefore, as shown in FIG. 1, the potential fluctuation is further suppressed, and the operation of the circuit connected to the cathode electrode 9 serving as an adjacent input terminal is stabilized.

FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the fourth embodiment of the present invention. This figure is a cross-sectional view of the main part of two adjacent vertical Zener diodes corresponding to FIG.
The difference from FIG. 4 is that the n-type diffusion region 5 has a deeper diffusion depth than the p-type diffusion region 6. By doing so, the electron flow 24 is more likely to flow into the n-type diffusion region 5. Therefore, as shown in FIG. 4, the potential fluctuation is further suppressed, and the operation of the circuit connected to the cathode electrode 9 serving as an adjacent input terminal is stabilized.
Further, by deeply diffusing the n-type diffusion region 5, the region where the impurity concentration on the p-type semiconductor substrate 1 side at the portion in contact with the p-type semiconductor substrate 1 is reduced is widened, and the region for absorbing electrons is expanded accordingly. The action of absorbing electrons in n-type diffusion region 5 is enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS It is principal part block diagram of 1st Example of this invention, (a) is a top view, (b) is sectional drawing cut | disconnected by the XX line of (a) Main part plan view different from FIG. Main part plan view different from FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Plan view of relevant parts of a conventional semiconductor device having a vertical surge protection element 8A and 8B are configuration diagrams of a main part of a conventional semiconductor device, in which FIG. 7A is an enlarged view of a portion A in FIG.

Reference Signs List 1 p-type semiconductor substrate 3, 4 n-type cathode region 5 n-type diffusion region 6 p-type diffusion region 7 LOCOS oxide film 8, 9 cathode electrode 10 metal electrode 11 back electrode 12a, 12b pull-up resistor 21 main current (surge current)
22 Exuded current 23 Electron current 24 Exuded electron current 25 Hole current 26 Exuded hole current (gate current)
27 Parasitic npn transistor Vcc High potential terminal IN1, IN2 of power supply Input terminal GND Ground e Electron h Hole

Claims (4)

In a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
The plurality of second conductivity type first diffusion regions formed in the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion regions, and separated from the first diffusion region, the semiconductor A second diffusion region of a first conductivity type formed in a surface layer of the layer, and a surface layer of the semiconductor layer separated from the first diffusion region on both sides of the second diffusion region and in contact with the second diffusion region A third diffusion region of the second conductivity type formed on the first diffusion electrode; a first metal electrode formed on the first diffusion region; and a second metal formed on the second diffusion region and the third diffusion region. An electrode and a back electrode formed on the back side of the semiconductor layer, wherein the vertical pn junction diode is configured by the semiconductor layer and the first diffusion region, wherein the second metal electrode is A semiconductor device connected to a ground. The semiconductor device according to claim 1, wherein the second diffusion region has a deeper diffusion depth than the third diffusion region. In a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
The plurality of second conductivity type first diffusion regions formed in the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion regions, and separated from the first diffusion region, the semiconductor A fourth diffusion region of a second conductivity type formed in the surface layer of the layer, and the surface layer of the semiconductor layer separated from the first diffusion region on both sides of the fourth diffusion region and in contact with the fourth diffusion region A fifth diffusion region of the first conductivity type formed on the first diffusion electrode; a first metal electrode formed on the first diffusion region; a third metal formed on the fourth diffusion region and the fifth diffusion region. An electrode and a back electrode formed on the back side of the semiconductor layer, wherein the semiconductor layer and the first diffusion region constitute the vertical pn junction diode, wherein the third metal electrode is A semiconductor device connected to a ground. The semiconductor device according to claim 3, wherein the fourth diffusion region has a deeper diffusion depth than the fifth diffusion region.

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