JP4540058B2 - Etching method and device manufacturing method - Google Patents

Description

  The present invention relates to an etching method and a device manufacturing method, and more particularly to an etching method in which a bottom surface of a trench formed in a substrate has a round cross-sectional shape and a device manufacturing method using the same.

Etching technology to round the bottom corners of holes and grooves in various devices such as semiconductor devices, liquid crystal display devices, field emission cold cathodes, microactuators, and MEMS (Micro-electro-mechanical System) Is required (for example, Patent Documents 1 and 2).
When forming such a fine device, dry etching is used. The dry etching is roughly classified into CDE (Chemical Dry Etching: hereinafter CDE) and RIE (Reactive Ionic Etching).
CDE is one of methods for performing etching by a chemical reaction between radicals generated by discharge decomposition of an etching gas and a film to be etched. The advantages of this method are: 1) selective etching of only a specific thin film due to a large etching selectivity, 2) excellent production efficiency due to relatively high etching speed, and 3) relative radical energy Therefore, it is difficult to damage the semiconductor substrate such as crystal defects.

  On the other hand, RIE can perform etching with high anisotropy by ion irradiation and sputtering. These methods are very effective methods for microfabrication of electronic devices. However, since RIE is a highly anisotropic etching method, it is not easy to form roundness at the bottom of the trench, and CDE is generally used.

However, when a mask is formed on a substrate and a trench is formed by CDE, an undercut is generated in the substrate under the mask, and the trench width is enlarged. Therefore, the dimensional tolerance of the circuit design deviates, and the device quality is not stable. . Further, when a conductive material or the like is embedded in the trench having the undercut in this way, the undercut portion is not filled, so that the device becomes a so-called “su” and the reliability of the device may be lowered.
JP 2003-174158 A JP 2000-215793 A

  The present invention provides an etching method capable of forming a trench having a precise opening size and a round bottom surface without causing an undercut, and a device manufacturing method using the etching method.

According to one aspect of the invention,
Forming a mask layer having an opening on the substrate;
On the inner wall surface and the bottom surface of the opening, a step that form a dummy layer,
Etching the dummy layer into a round shape by an isotropic etching method;
Forming a trench having a bottom surface reflecting the round shape in the base body by etching the dummy layer and the base body thereunder by an anisotropic etching method;
An etching method characterized by comprising:

According to another aspect of the present invention,
A method of manufacturing a device having a substrate with a trench formed thereon,
A device manufacturing method is provided, wherein the trench is formed in the substrate by the etching method.

  According to the present invention, it is possible to provide an etching method capable of forming a trench having a precise opening size and a rounded bottom surface without causing an undercut, and a device manufacturing method using the same. The benefits are great.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a process sectional view showing an etching method according to the present embodiment.
2 and 3 are process cross-sectional views illustrating an etching method as a comparative example.

First, these comparative examples will be briefly described.
In order to form the trench 60 having a round bottom, it is necessary to perform isotropic etching. For example, in the case of the comparative example shown in FIG. 2, as shown in FIG. 2A, the mask layer 20 is formed on the substrate 10 and the opening 30 having the opening width W is formed. Then, the substrate 10 is etched by an isotropic etching method such as CDE while the mask layer 20 is retracted. In this way, the trench 60 having a round bottom can be formed.

  However, in the case of this comparative example, both ends of the opening 30 of the mask layer 20 used as a mask are expanded by the width W1 by etching, so that the size of the opening of the trench 60 also exceeds the expected size. That is, it is not easy to precisely define the opening size of the trench 60. In particular, the deeper the trench 60, the larger the opening size.

  On the other hand, if the substrate 10 is isotropically etched under conditions where the etching selectivity is high, that is, under the condition that the mask layer 20 serving as a mask is difficult to be etched, as illustrated in FIG. In addition, an undercut 70 is generated in the substrate 10 immediately below the mask layer 20. That is, also in this case, the width of the trench 60 expands in the horizontal direction, and a desired size cannot be obtained. The deeper the trench 60 is formed, the wider the undercut 70 is. Further, when the trench in which the undercut 70 is generated in this manner is filled with a conductive material or an insulating material, the undercut portion is not completely filled, so-called “su” is formed, and reliability is lowered. May cause problems.

On the other hand, according to the etching method according to the embodiment of the present invention, the opening width can be precisely defined while making the bottom surface round. Hereinafter, the etching method of this embodiment will be described with reference to FIG.
First, as shown in FIG. 1A, a mask layer 20 made of a different material is formed on the substrate 10 to form an opening 30. When polycrystalline silicon is used as the material of the substrate 10, for example, silicon nitride can be used as the material of the mask layer 20.

  Next, as illustrated in FIG. 1B, the dummy layer 40 is formed so as to cover the inner wall surface and the bottom surface of the opening 30 formed in the mask layer 20. As a material of the dummy layer 40, as will be described in detail later, the same material as that of the base 10 may be used, or a different material may be used.

  Next, as shown in FIG. 1C, the dummy layer 40 is etched by a highly isotropic etching method such as CDE. At this time, the etching is performed under the condition that the etching rate of the mask layer 20 is lower than the etching rate of the dummy layer 40. By performing highly isotropic etching, the dummy layer 40 remains in a rounded shape at the bottom corner of the opening 30, and the round shape 50 can be formed.

  Further, as shown in FIG. 1D, etching is performed in a substantially vertical direction by an anisotropic etching method such as RIE. Then, the trench 60 can be formed in the base body 10 while maintaining the round shape 50. At this time, if the etching anisotropy is high to some extent, it is possible to form the deep trench 60 while maintaining the round shape 50. Note that the mask layer 20 used as an etching mask may be left as it is or removed as necessary.

  As described above, the mask layer 20 serving as a mask is formed on the substrate 10, the dummy layer 40 is laminated on the inner wall surface and the bottom surface of the opening 30 of the mask layer 20, and the round shape 50 is formed by highly isotropic etching. And further etching with high anisotropy allows the trench 60 to be formed to a desired depth while maintaining the round shape 50.

  The round shape 50 formed in this embodiment can be used for forming a shallow trench or a deep trench, for example, regardless of the depth of the trench 60. Further, as the material of the substrate 10, a material required for a device to be manufactured may be used, and the material of the mask layer 20 may be different from the substrate 10 and the dummy layer 40 so as to obtain an etching selectivity. That's fine.

  Furthermore, according to the present embodiment, it is easy to control the round shape formed on the bottom surface of the trench. That is, as illustrated in FIG. 1, when the dummy layer 40 is deposited relatively thin, the bottom of the trench is close to a flat surface, and a round shape with rounded corners can be formed.

On the other hand, when the dummy layer 40 is deposited thickly, it is possible to form a round shape that is rounded over the entire bottom surface of the trench.
FIG. 4 is a process cross-sectional view illustrating a specific example in which the dummy layer 40 is deposited thickly.
In this specific example, the dummy layer 40 is deposited thicker than the specific example shown in FIG. When such a thick dummy layer 40 is isotropically etched, as shown in FIG. 4C, a round shape 50 that is rounded as a whole is obtained in the opening 30. When this is etched in a substantially vertical direction by a highly anisotropic etching method, the trench 60 can be formed while maintaining this round shape as shown in FIG.

  In the case of the specific example shown in FIG. 1, the bottom surface of the formed trench 60 has a shape in which the vicinity of the center is close to a plane and the corners are rounded. Such a round shape can be realized by depositing the dummy layer 40 so as not to fill the opening 30 in the step shown in FIG. That is, when deposited so that the thickness of the dummy layer 40 does not exceed the thickness of the mask layer 20, as shown in FIG. 1 (d), the bottom shape with a rounded corner near the center is close to a flat surface. Can be formed.

On the other hand, as shown in FIG. 4B, in the case of the specific example in which the dummy layer 40 is deposited so as to fill the opening 30, the bottom surface of the trench 60 is rounded over the entire surface. Is formed. In other words, the dummy layer 40 when is deposited thicker than the mask layer 20 can form a trench having a bottom rounded over the entire body.
According to the present embodiment, the round shape of the bottom surface of the trench can be easily controlled by adjusting the thickness of the dummy layer 40 in this way.

Furthermore, in the present embodiment, the round shape of the bottom surface of the trench can also be controlled by appropriately selecting the material of the dummy layer 40.
That is, in this embodiment, the trench is formed by transferring the round shape formed in the dummy layer 40 to the substrate 10 by using anisotropic etching. In this case, the round shape of the bottom surface of the trench formed in the substrate 10 can be controlled according to the balance between the etching rates of the dummy layer 40 and the substrate 10.

5 to 7 are schematic cross-sectional views illustrating changes in the round shape due to the balance between the etching rates of the dummy layer 40 and the substrate 10.
That is, FIG. 5 shows a case where the etching rates of the dummy layer 40 and the substrate 10 are substantially the same. For example, this corresponds to the case where the dummy layer 40 is formed of the same material as that of the substrate 10. In this case, when highly anisotropic etching is performed, the round shape formed in the dummy layer 40 is transferred to the substrate 10 almost as it is. That is, a trench 60 having a round shape substantially similar to the round shape formed in the dummy layer 40 can be formed.

Next, FIG. 6 shows a case where the etching rate of the substrate 10 is lower than that of the dummy layer 40. That is, it corresponds to the case where the dummy layer 40 is formed of a material having an etching rate higher than that of the substrate 10.
In this case, when highly anisotropic etching is performed, the round shape formed in the dummy layer 40 is relaxed and transferred. That is, the round shape of the bottom surface of the trench 60 formed in the base body 10 is less round than the round shape of the dummy layer 40.

On the other hand, FIG. 7 shows a case where the etching rate of the substrate 10 is higher than that of the dummy layer 40. That is, this corresponds to the case where the dummy layer 40 is formed of a material having an etching rate lower than that of the substrate 10.
In this case, when highly anisotropic etching is performed, the round shape formed in the dummy layer 40 is emphasized and transferred. That is, the round shape of the bottom surface of the trench 60 formed in the base body 10 is more rounded than the round shape of the dummy layer 40.

  As described above, in the present embodiment, the round shape of the bottom surface of the trench can be changed depending on the balance between the etching rates of the dummy layer 40 and the substrate 10. That is, the round shape of the bottom surface of the trench 60 formed in the base body 10 can be controlled by appropriately selecting the material of the dummy layer 40 with respect to the material of the base body 10.

8 and 9 are schematic views illustrating the basic configuration of a dry etching apparatus that can be used in the present invention.
First, FIG. 8 shows a downflow type CDE apparatus that can be used in this embodiment. The CDE apparatus includes a processing chamber 80, a transmission window 84 made of a flat dielectric plate provided on the upper surface of the processing chamber 80, a microwave waveguide 82 provided outside the transmission window 84, And a stage 81 for mounting and holding a workpiece W such as a semiconductor wafer in a processing space below the transmission window 84.

  An inlet pipe 85 capable of introducing a plurality of reaction gases into the processing space is provided on the side surface of the processing chamber 80, and an exhaust pipe 86 for discharging the reaction gas after the reaction is provided on the lower surface of the chamber 80. ing. The processing chamber 80 can maintain a reduced pressure atmosphere formed by a vacuum exhaust system EG connected to the exhaust pipe 86.

The operation will be described. First, the microwave M propagates through the microwave waveguide 82, passes through the transmission window 84 from the slot antenna 83, and is introduced into the internal space of the processing chamber 80. A plasma region P is formed by the ionized gas excited by the microwave M, and active species such as radicals are generated. This active species is allowed to act on the object to be processed W provided below, and isotropic etching proceeds.
As described above, isotropic etching according to the present invention is possible by using this downflow type CDE apparatus. In the present invention, isotropic etching can also be performed by using, for example, a remote plasma type CDE apparatus instead of the downflow type CDE apparatus.

FIG. 9 is a schematic diagram showing an RIE apparatus that can be used in this embodiment.
The RIE apparatus includes a processing chamber 80, a showerhead upper electrode 95 provided at the upper part in the processing space, and a lower part connected to an RF (radio frequency) power source 90 for mounting and holding an object to be processed W such as a semiconductor wafer. And an electrode stage 96. The processing chamber 80 can maintain a reduced pressure atmosphere formed by the evacuation system EG, and introduces a reaction gas into the processing chamber 80 from a shower head upper electrode 95 provided in the upper portion of the processing space.

  The operation will be described. An RF power source 90 is applied from the lower electrode stage 96 while introducing a reaction gas from the shower head upper electrode 95 into the processing chamber 80. Then, a reactive gas plasma P is formed above the workpiece W. Then, an accelerating voltage is applied to the active species of the reaction gas excited by the plasma P, and it is caused to collide with the main surface of the workpiece W from the substantially vertical direction A to perform dry etching. Etching proceeds more due to the physical action of accelerated ions and the chemical action with the object to be etched, but etching proceeds in the direction of collision of accelerated ions, so that etching with strong anisotropy is possible. Unnecessary gas after the reaction is exhausted through the exhaust pipe 86.

The specific example of the dry etching apparatus that can be used in the present embodiment has been described above. In addition, the RIE processing according to the present invention is performed by ICP (Inducted
Similar processing can be performed using a Coupling Plasma (RIE) type RIE apparatus, an ECR (Electron Cyclotron Resonance) type RIE apparatus, or the like.

Next, a device manufacturing method according to the present embodiment will be described.
FIG. 10 is a schematic view illustrating the cross-sectional structure of the main part of a semiconductor device manufactured according to the present invention. That is, this figure shows a cross-sectional structure of a main part of an IGBT (Insulated Gate Bipolar Transistor) constituting the semiconductor integrated circuit.

  In this IGBT, an n-type buffer layer 202, a high-resistance n-type base layer 201, and a p-type base layer 207 are sequentially laminated on a high-concentration P-type collector layer 203. A plurality of trenches 204 having a round bottom surface are formed so as to penetrate the p-type base layer 207 and reach the n-type base layer 201.

  In these trenches 204, a gate electrode 206 is buried and formed via a gate insulating film 205, and n-type emitter layers 208 are selectively formed on both sides of the opening of the trench 204. Here, the n-type buffer layer 202 is provided as one means for giving a required breakdown voltage to the element. Therefore, the n-type buffer layer 202 is not necessary when the breakdown voltage can be satisfied by other means.

  On the n-type emitter layer 208 and the gate electrode 206, an interlayer insulating film 211 is provided so as to be in contact with both of them. Then, through the source / base extraction trench opened in the interlayer insulating film 211, a part of the n-type emitter layer 208 and a part of the p-type base layer 207 are contacted in common and not in contact with the gate electrode 206. Thus, an emitter electrode 209 made of, for example, aluminum or copper is provided.

  A collector electrode 210 is provided on the back surface of the p-type collector layer 203. Note that the gate electrode 206 is extended to, for example, a gate contact pad (not shown), and a gate electrode (G) is provided so as to be connected to the gate contact pad.

  With such a structure, the n-type base layer 201, the p-type base layer 207, the n-type emitter layer 208, and the gate electrode 206 are channel regions formed on the surface portion of the gate insulating film 205 of the p-type base layer 207. An IGBT is configured to inject electrons from the n-type emitter layer 208 into the n-type base layer 201 through CH.

11 to 13 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
First, as shown in FIG. 11A, the main part of the MOS transistor is formed. That is, a stacked body in which an n-type buffer layer 202, a high-resistance n-type base layer 201, and a p-type base layer 207 are sequentially formed on the high-concentration P-type collector layer 203 is formed.
Next, a hard mask 250 made of a SiN film is formed on the p-type base layer 207 by LPCVD (low pressure chemical vapor deposition). At this time, for example, the substrate temperature is 600 ° C., the pressure is 100 Pa, the dichlorosilane (SiH ₂ Cl ₂ ) gas flow rate is 10 ccm, the ammonia (NH ₃ ) gas flow rate is 1000 ccm, and the N ₂ gas flow rate is 1000 ccm.

Thereafter, in order to form a plurality of trenches 204, a resist is applied and patterned to form a resist pattern. At this time, the resist pattern can be formed, for example, by exposing to 120 nm width using an ArF exposure machine and developing.
Then, the hard mask 250 is etched by RIE using the resist as a mask, and openings for a plurality of trenches 204 are formed in the hard mask 250. Thereafter, the resist is removed by ashing, and a dummy layer 207C made of silicon of the same material as the p-type base layer 207 is formed on the hard mask 250 by thermal CVD.

Next, as shown in FIG. 12A, the dummy layer 207 </ b> C having the round shape 260 can be left on the bottom surface of the opening of the hard mask 250 by performing the CDE process on the dummy layer 207 </ b> C. Here, the CDE processing conditions can be performed, for example, under conditions of a substrate temperature: room temperature to 200 ° C., a pressure: 30 Pa, a carbon tetrafluoride (CF ₄ ) gas flow rate of 200 sccm, and an oxygen (O ₂ ) gas flow rate of 300 sccm. .
Furthermore, as shown in FIG. 12B and FIG. 13A, etching is performed by RIE to form a trench 204 that reaches the n-type base layer 201 through the p-type base layer 207. To do. At this time, by performing highly anisotropic etching, a deep trench 204 reaching the n-type base layer 201 can be formed while keeping the bottom surface of the trench 204 in a round shape 260 as shown in the figure. The RIE process at this time is, for example, a mixture of a substrate temperature of ° C, a pressure of 6.7 MPa, a carbon fluoride (C ₄ F ₆ ) gas flow rate of 50 sccm, a carbon monoxide (CO) flow rate of 50 sccm, and an oxygen (O ₂ ) gas flow rate of 50 cc. It can be performed using gas.

Thereafter, as shown in FIG. 13B, a gate insulating film 205 is formed on the inner wall of the trench 204, and polycrystalline silicon is buried in the trench 240 with thermal CDV to form a gate electrode 206. Then, the surface of the wafer is planarized using a CMP (Chemical Mechanical Polishing) method. Further, phosphorus (P) is implanted in the periphery of the opening of the trench 240, the n-type emitter layer 208 is formed, the interlayer insulating film 211 is formed, and the electrodes are appropriately formed, so that the essential elements of the semiconductor device shown in FIG. Department is completed.

  As described above, according to the present embodiment, the bottom of the trench having a round shape can be processed, and the electric field concentration at the lower end of the gate electrode can be reduced. Further, according to the present embodiment, the width of the trench 204 can be precisely formed to a predetermined size, and dimensional stability at the time of manufacturing a semiconductor device is increased. That is, the trench can be formed without causing the width expansion as described above with reference to FIGS. 2 and 3, and the dimensional stability and reliability of the semiconductor device are improved.

The embodiments of the present invention have been described above with specific examples being limited. However, the present invention is not limited to these specific examples.
For example, the type of gas, composition ratio, pressure, flow rate, type of material used as a substrate, size, CDE and RIE etching rate, dry etching apparatus, etc. used in the etching method and device manufacturing method according to the present invention The various parameters are not limited to the specific examples described above, and any changes may be made within the scope of the present invention as long as they have the gist of the present invention.

  In addition to IGBTs, devices that can be manufactured according to the present invention include, for example, various semiconductor elements including MOSFETs, diodes, thyristors, power switching elements, liquid crystal display devices, field emission type cathodes, A microactuator, a MEMS resistance element, a capacitive element, etc. can be mentioned.

It is process sectional drawing showing the etching method concerning this Embodiment. It is process sectional drawing showing the 1st comparative example showing the etching method concerning this Embodiment. It is process sectional drawing showing the 2nd comparative example showing the etching method concerning this Embodiment. It is process sectional drawing showing the specific example which deposited the dummy layer 40 thickly. 4 is a schematic cross-sectional view illustrating a change in round shape due to a balance between etching rates of a dummy layer 40 and a substrate 10. FIG. 4 is a schematic cross-sectional view illustrating a change in round shape due to a balance between etching rates of a dummy layer 40 and a substrate 10. FIG. 4 is a schematic cross-sectional view illustrating a change in round shape due to a balance between etching rates of a dummy layer 40 and a substrate 10. FIG. 1 represents a downflow CDE apparatus that can be used in the present embodiment. 1 represents a downflow type RIE apparatus that can be used in the present embodiment. It is a schematic diagram which illustrates the principal part cross-section of the semiconductor device manufactured by this invention. It is process sectional drawing of the semiconductor device manufactured by this invention (the 1) It is process sectional drawing of the semiconductor device manufactured by this invention (the 2) It is process sectional drawing of the semiconductor device manufactured by this invention (the 3)

Explanation of symbols

10 Substrate

20 Mask layer

30 opening

40 dummy layer

50 round shape

60 trench

70 undercut 80 processing chamber

81 stages

82 Microwave Waveguide

83 slot antenna

84 Transmission window

85 Introduction pipe

86 discharge pipe

90 RF power supply

95 Shower head upper electrode

96 Lower electrode stage

201 n-type base layer

202 n-type buffer layer

203 p-type collector layer

204 trench

205 Gate insulation film

206 Gate electrode

207 p-type base layer

207C p-type base layer 208 n-type emitter layer

209 Emitter electrode

210 Collector electrode

211 Interlayer insulation film

240 trench

250 hard mask

260 round shape

A substantially vertical direction C collector electrode G gate electrode E emitter electrode G reaction gas M microwave P plasma region W object CH channel region

EG vacuum exhaust system

Claims (8)

Forming a mask layer having an opening on the substrate;
On the inner wall surface and the bottom surface of the opening, a step that form a dummy layer,
Etching the dummy layer into a round shape by an isotropic etching method;
Forming a trench having a bottom surface reflecting the round shape in the base body by etching the dummy layer and the base body thereunder by an anisotropic etching method;
An etching method comprising: The thickness of the dummy layer is thinner than the thickness of the mask layer,
2. The etching method according to claim 1, wherein the bottom surface of the trench has a planar portion formed near the center thereof and a rounded portion formed at a corner. The dummy layer is thicker than the mask layer,
Said bottom surface of said trench, etching method according to claim 1, characterized in that rounded over the entire body. Etch rate of the dummy layer by the anisotropic etching method, said a etch rate and same of the by anisotropic etching methods substrate,
Said bottom surface of said trench, etching method of claim 1, wherein the a round shape and the same. The etching rate of the dummy layer by the anisotropic etching method is larger than the etching rate of the substrate by the anisotropic etching method,
The etching method according to claim 1, wherein the bottom surface of the trench has a shape whose roundness is less than that of the round shape. The etching rate of the dummy layer by the anisotropic etching method is smaller than the etching rate of the substrate by the anisotropic etching method,
The etching method according to claim 1, wherein the bottom surface of the trench has a shape in which roundness is emphasized more than the round shape.   The etching rate of the dummy layer and the substrate in the isotropic etching method and the anisotropic etching method is higher than the etching rate of the mask layer in the isotropic etching method and the anisotropic etching method. The etching method according to claim 1, wherein the etching method is also large. A method of manufacturing a device having a substrate with a trench formed thereon,
A device manufacturing method, wherein the trench is formed in the substrate by the etching method according to claim 1.

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