JP4434103B2 - Computer-assembled programmable controller - Google Patents

Description

The present invention is usually called a programmable controller with a built-in personal computer (hereinafter, the programmable controller is also abbreviated as “PLC”), connected to an expansion bus of a personal computer, for example, a PCI (Peripheral Component Interconnect) bus, This is related to a computer-assembled programmable controller as a PLC that exchanges data between the application program held by the PLC and the application program held by the PLC. In particular, the data exchange time between the application program on the personal computer side and the PLC side can be speeded up without variation. Further, the present invention relates to a computer-assembled programmable controller that can realize synchronization between application programs at a necessary timing.
In the following drawings, the same reference numerals denote the same or corresponding parts.

A programmable controller (PLC) is known as a device that automatically executes a sequence program stored in a PLC and automatically performs sequence control on an external control target device connected to the PLC. It is also known to combine a personal computer with a PLC as a man-machine interface (MMI).
Such a connection between the PLC and the personal computer was originally realized by exchanging data by serial communication. However, because the communication speed becomes a bottleneck and the cycle time of the entire apparatus cannot be shortened, the so-called PLC connected to the personal computer bus, It is also connected to a personal computer as a personal computer built-in PLC.
FIG. 9 is a block circuit diagram showing a system configuration example of such a personal computer built-in PLC. In the figure, 1 is a personal computer and 2 is a personal computer built-in PLC connected to a PCI bus (hereinafter also referred to as an expansion bus) 3 of the personal computer 1.

The personal computer built-in type PLC 2 includes units 01 to 06, M1, and M2, which are connected to each other via an internal PLC system bus 07. Here, the CPU 01, on the other hand, executes a system program stored in the system program memory 03, via the operation control of each means in the PLC 2, and a serial communication interface (hereinafter, the interface is also abbreviated as I / F) 05. Communication and control with respect to the external device 11 including a programming tool, a display, and the like are performed.
At the same time, the CPU 01, on the other hand, executes a PLC user application program (abbreviated as PLC application) stored in the PLC user application program memory 04, and performs sequence control of the external control target device 12 via the serial communication I / F 06. I do.

The system work memory 02 temporarily stores data used by the CPU 01 in the system program. The user data memory (also referred to as PLC internal memory) M2 temporarily stores data used in the PLC user application program, for example, control state data (contact information or the like) transmitted / received to / from the control target device 12.
The dual port memory (abbreviated as DP memory) M1 is composed of a dual port RAM, which is connected to the PLC system bus 07 on the one hand and connected to the local bus 08 and a signal line for the interrupt trigger signal INT on the other hand. It is connected to the PCI bus 3 of the personal computer 1 via F09.
With this configuration, the DP memory M1 can access the same memory area from both the CPU 01 side of the PLC 2 and the CPU side of the computer 1 that is not shown in the figure. Temporary data exchanged between the PLC 2 and the computer 1 is possible. Used as storage destination.

FIG. 8 shows a system configuration example related to a conventional data exchange function between the user application program (PLC application) of the personal computer built-in PLC 2 and the user application program of the personal computer 1 (also abbreviated as personal computer side application). In FIG. 8, the PLC 2 with a built-in personal computer is connected to an expansion bus 3 (in this example, a PCI bus) 3 of the personal computer 1 with the housing through its own DP memory M1, and a serial communication I / O (not shown). Connected to the device to be controlled (12 in FIG. 9) via F (06 in FIG. 9), and programming tool and display via another serial communication I / F (05 in FIG. 9). It is connected to an external device 11 such as a vessel.
The PLC 2 with built-in personal computer is written in a CPU (01) shown in FIG. 9 and a system program memory (03) shown in FIG. Firmware FW as a PLC, a PLC application SP as a sequence control program stored in a PLC user application program memory (04 in FIG. 9), a PLC internal memory M2 as a data memory for the PLC application SP, etc. The DP memory M1 for exchanging data with an application program (personal computer side application) PP of the personal computer 1 is provided.

The DP memory M1 is provided with a command request area 5 and a command response area 6 for performing this data exchange, and data can be read and written from the personal computer side application PP and from the firmware FW of the PLC2. The PLC internal memory M2 includes a write area 7 for exchanging data with the personal computer side application PP, in addition to an area outside the figure for storing control state data exchanged with the control target device outside the figure by the PLC application SP. A reading area 8 is provided.
The personal computer 1 reads and writes the command request area 5 and the command response area 6 of the DP memory M1 while executing the personal computer side application PP, so that, for example, the control status data exchanged between the personal computer built-in PLC 2 as the MMI with the control target device The desired control target device can be turned on / off by monitoring the device or operating the start button on the displayed screen.

The PLC application SP reads the control state data such as ON / OFF of each control target device into the PLC internal memory M2 via a serial communication I / F (not shown) at every predetermined sequence control cycle (for example, 10 ms), and performs a sequence calculation. The new control state data for each control target device obtained as a result of the calculation is written in the PLC internal memory M2, and the new control state data is respectively transmitted via the serial communication I / F (not shown). Each control target device is subjected to sequence control by transmitting to the corresponding control target device. Further, for data exchange with the personal computer side application PP, the writing area 7 of the PLC internal memory M2 is read and written to the reading area 8 within the sequence control period. In this case, the exchange with the command processing 10 described later is not performed.
As described in detail below, data exchange between the personal computer side application PP and the PLC application SP is performed by reading the write area 7 of the PLC internal memory M2 and writing into the read area 8 by the PLC application SP described above, The side application PP reads / writes the command request area 5 and the command response area 6 of the DP memory M1, and the command processing 10 in the firmware FW writes the command request area 5, the command response area 6 and the PLC internal memory M2 of the DP memory M1. This is performed by reading and writing the read area 7 and the read area 8.

Next, the data exchange operation between the personal computer side application PP and the PLC application SP will be described using a specific example.
Example 1) When the operation time of a desired control target device is monitored every second by the personal computer side application PP, the reading area 8 of the PLC internal memory M2 stores the control state data of the control target device The count value of the operation integration time is allocated, and the PLC application SP writes and updates the latest data to the count value of the integration time in the reading area 8 every sequence control period.
Example 2) In addition, when the PC-side application PP turns on the activation button of a desired control target device on the display screen of the personal computer to activate the device, the device in the writing area 7 of the PLC internal memory M2 A start command (control command bit data) is assigned, and the PLC application SP reads the write area 7 at each sequence control cycle to determine whether the start command is ON or OFF, and operates the device whether it is ON or OFF.

On the other hand, in order for the personal computer side application PP to write data to the PLC internal memory M2 or read data from the memory M2, the personal computer side application PP previously writes the write request command data or the read request command data to DP. Write to the command request area 5 of the memory M1 (arrow A2).
For example, in the case of Example 2, the write request command data is used as a start command for a desired control target device. Specifically, this start command is used as the address of the PLC internal memory M2 to which the start command is assigned, the start command. Data size and start command ON / OFF data.
The command request area 5 is written with a start command with the ON / OFF data turned OFF at the beginning of the startup of the personal computer application PP, and the ON / OFF data is stored when the start button on the display screen is turned ON. Write the start command set to ON. In addition, a start command with ON / OFF data OFF is written when the start button is turned OFF.

In the case of Example 1, the read request command data is used as a read command for the count value of the operation accumulated time of the desired control target device. Specifically, this read command is used as the PLC internal memory M2 to which the operation accumulated time is assigned. The read command is written in the command request area 5 at every monitor time interval (1 second in this example).
The command process 10 in the firmware FW is a process executed in the free time of the sequence control cycle of the PLC application SP. This command process 10 confirms the request command data (arrow A4), and if it is a read request, The data in the read area 8 of the corresponding address of the PLC internal memory M2 is read (arrow A7) and written as response data to the command response area 6 of the DP memory M1 (arrow A5). Write data added to the command data (ON or OFF data in the above example 2) is written to the write area 7 of the corresponding address in the PLC internal memory M2 (arrow A6), and response data indicating the completion of the write Is written in the command response area 6 of the DP memory M1 (arrow A5).

The personal computer side application PP confirms that the response data is written in the command response area 5 of the DP memory M1 (arrow A3), and recognizes that the writing to or reading from the PLC internal memory M2 has been completed. To do.
As described above, the personal computer built-in PLC 2 may be connected to a programming tool, a display, or the like as the external device 11 via the serial communication I / F (not shown). The external device 11 sends a command request to the command processing 10 in the firmware FW (arrow A8), receives a command response from the command processing 10 (arrow A9), and exchanges data with the PLC application SP via the PLC internal memory M2. Can do.
In this case, a read area and a write area for the external device 11 are provided in the PLC internal memory M2. However, when the personal computer side application PP also exchanges data with the PLC application SP, the read area and the write area are different addresses from the read area 8 and the write area 7 provided for the personal computer side application PP. Assigned.

In this case as well, the PLC application SP performs both writing to the reading area and reading of the writing area separately allocated to the PLC internal memory M2 for each sequence control period. Do not do.
In Patent Document 1, a high-speed serial communication interface equipped with a microcomputer, dual port memory, and high-speed serial communication IC is connected to an expansion bus of a personal computer, and a high-speed serial communication interface and a plurality of servo controllers are connected to a serial line. A servo control method and a servo control system that can easily read and write internal data of a servo controller from an application operating on a personal computer by connecting with the multi-drop method are disclosed.
JP-A-10-326107

By the way, the PLC application SP of FIG. 8 reads / writes the control state data exchanged with the control target device in the PLC internal memory M2, and the write area and the read area for data exchange with the personal computer 1 and / or the external device 11. The sequence control program is executed with the highest priority every predetermined sequence control cycle, and the command processing 10 in the firmware FW is executed during the idle time.
For this reason, if the execution time of the PLC application SP varies, the idle time also fluctuates. On the other hand, the command processing 10 generally takes time for command analysis and the like, and cannot be processed in the minimum idle time (for example, 1 ms). Since the personal computer side application PP writes the request command data to the command request area 5 of the DP memory M1 as indicated by the arrow A2, the response data is written to the command response area 6 of the DP memory M1 as indicated by the arrow A3. Therefore, the time required for data exchange until confirmation is confirmed over a range several times the sequence control period.

Thus, there is a problem that the punctuality of the data exchange of the PLC internal memory M2 between the personal computer side application PP and the PLC application SP cannot be ensured, that is, there is no guarantee that the data can be exchanged within a predetermined time.
In the system of FIG. 8, command requests from the external device 11 such as a programming tool and a display are also processed by the command processing 10, so that data is written from the external device 11 to the PLC internal memory M2 simultaneously with the personal computer side application PP. Alternatively, when reading is performed, the time required for the data exchange becomes longer, and it becomes difficult to ensure punctuality.
This problem can be tolerated when the personal computer 1 is used in a form that does not require a very fast response such as a man-machine interface. However, in recent years, with the improvement in performance of personal computers, image processing has become mainstream using personal computer software. For example, there is a demand for linking personal computer image processing and PLC positioning control in a semiconductor test apparatus or the like. . In order to meet such demands, it is necessary to allow the personal computer 1 and the PLC 2 to exchange commands and data at high speed without variation.

In the system of FIG. 8, for example, when one or a plurality of application programs PP are prepared in the personal computer 1 and a command is given from the PLC application SP to each personal computer side application PP, each personal computer side application is periodically updated. The PLC internal memory M2 is read out to check whether or not there is command data addressed to itself, or the PLC internal memory M2 is read out periodically in the personal computer 1 and a plurality of personal computers are read out. There is a problem that it is necessary to create a separate application program for confirming to which of the side application the command data is addressed, which imposes an extra burden on the creation of the personal computer side application.
The present invention solves these problems and responds to the above-mentioned demands, so that it is possible to ensure the punctuality of data exchange between the personal computer side application and the PLC application regardless of the fluctuation of the execution time of the PLC application SP and the presence or absence of the external device 11. In addition, it is possible to activate the PC side application when the PLC application is required without imposing extra burden on the creation of the PC side application (in other words, synchronizing the PLC side and the PC side application at the required timing) It is an object to provide a computer-assembled programmable controller.

In order to solve the above-described problem, a computer-assembled programmable controller according to claim 1 comprises:
Control state data received from one or a plurality of control target devices (12) are respectively stored in the corresponding areas of the internal memory (PLC internal memory M2), and a sequence calculation is performed using all the control state data, The control state data in the internal memory is updated with the new control state data obtained as a result of the calculation, and the new control state data is transmitted to the corresponding control target device in a predetermined sequence control cycle. (Ts) is repeated, and the internal memory in the programmable controller that performs sequence control of the device to be controlled is further on a bus on both the computer side and the programmable controller side, and the same memory area can be accessed from both. Port memory (DP memory M ), The input area (29) for storing the input transfer data transferred from the computer side to the programmable controller side, and the output transfer data to be transferred from the programmable controller side to the computer side via the dual port memory An output area (30) for storing
In addition to the control status data received from the control target device in the internal memory, the programmable controller further performs a sequence calculation using the input transfer data read from the input area in the internal memory for each sequence control cycle. As a result of this calculation, a computer-assembled programmable controller that obtains the output transfer data in addition to new control state data to be transmitted to the control target device and writes the output transfer data to the output area in the internal memory In a controller (PLC2 with built-in bath computer, etc.)
In the dual port memory, the size of the input transfer data (input size 24) is set in advance by the computer, and the size of the output transfer data (output size 25) is also set in advance by the computer. An output size setting area, an input area (26) where the computer transfers the input transfer data when necessary, and an output area (27) where the computer also reads the output transfer data when necessary,
In a predetermined copy cycle (Tc) shorter than the sequence control cycle, input transfer data as data having a size set in the input size setting region in the input region of the dual port memory is always input to the input region of the internal memory. Copying means for repeatedly copying the output transfer data as the data set in the output size setting area in the output area of the internal memory to the output area of the dual port memory. Assume that a copy process 31) is provided.

The computer-assembled programmable controller according to claim 2 is the computer-assembled programmable controller according to claim 1,
When the setting value for the input size setting area or / and the output size setting area of the dual port memory is set to 0 or blank, the copying means is connected between the input areas of the dual port memory and the internal memory, or ( And) the copying operation related to the output areas is omitted.
The computer-assembled programmable controller according to claim 3 is the computer-assembled programmable controller according to claim 1 or 2,
Monitoring bit position data (monitoring address addition value 34 and monitoring bit setting) is data for specifying a position where a monitoring bit as a data bit to be monitored in the output area of the dual port memory exists in the dual port memory. A monitoring bit position setting area as an area in which the value 35 or the like is preset by the computer, and an interrupt signal (interrupt trigger signal INT and interrupt flag) to the computer based on the writing of interrupt generation data 48) for generating an interrupt signal (interrupt trigger signal area 49, etc.), and the computer reads a bit (interrupt generation factor bit 39) that causes an interrupt when the interrupt signal is input. An interrupt generation factor bit area as an area,
In synchronization with the copy cycle, the monitoring bits (on the monitoring address 38) in the output area of the dual port memory, which are always specified by the monitoring bit position data set in the monitoring bit position setting area of the dual port memory. And when the monitoring bit changes to a value that should generate an interrupt, the monitoring bit position data for the monitoring bit is written into the interrupt generation factor bit area of the dual port memory. Assume that bit change monitoring means (bit change monitoring process 44 of the firmware FW) is provided for writing interrupt generation data in the interrupt signal generation area of the dual port memory and supplying an interrupt signal to the computer.

The computer-assembled programmable controller according to claim 4 is the computer-assembled programmable controller according to claim 3,
The computer reads the monitoring bit position data from the interrupt generation factor bit area of the dual port memory based on the input of the interrupt signal (via the interrupt detection management unit 50), A corresponding application program is obtained from the interrupt management table (interrupt waiting management table 59) indicating the correspondence with the application program to be operated in response to the interrupt signal, and is operated.
Next, the operation of the present invention will be described. First of all, as a method of ensuring the punctuality of data exchange between the PC side application and the PLC application and realizing high-speed data exchange without variation,
Transfer to the dual port memory (DP memory) M1 that can be accessed directly from the PC side application to the PLC side, the size of the input transfer data (input size) 24 to be transferred from the PC side application to the PLC application in advance, and transfer from the PLC application to the PC side application The size (output size) 25 of the output transfer data to be set is set and notified to the PLC firmware FW, and the input transfer data is written to the input area 26 of the input size 24 provided in the DP memory M1 when necessary. Similarly, the output transfer data transferred from the PLC application is read out from the output area 27 having an output size of 25 minutes provided in the DP memory M1, when necessary.
On the other hand, in the PLC internal memory M2 as a data memory for sequence control processing executed by the PLC application, in addition to the area for storing the control state data exchanged with the control target device by the PLC application, the input transferred from the personal computer side application An input area 29 for reading the transfer data and an output area 30 for writing the output transfer data to be transferred to the personal computer side application are provided, and the control status data received from the control target device from the PLC internal memory M2 by the PLC application every sequence control cycle Ts The input transfer data in the input area 29 is read and a sequence calculation is performed. As a result of this calculation, new control state data and output transfer data are obtained, and the control state data in the PLC internal memory M2 is updated with the new control state data. New with It transmits the control status data to the control target device, also to write the output data transferred sequence operation result to the output area 30,
Further, for data transfer between the DP memory M1 and the PLC internal memory M2, the copy process 31 in the PLC firmware FW is always input to the input area 26 of the DP memory M1 with a copy cycle Tc shorter than the sequence control cycle Ts. The transfer data is copied to the input area 29 of the PLC internal memory M2, and the output transfer data of the output area 30 of the PLC internal memory M2 is copied to the output area 27 of the DP memory M1, so that data exchange between the personal computer side application and the PLC application is possible. This is to ensure that it can be performed within one or a predetermined plurality of sequence control periods Ts.

In addition, as a method of synchronizing the PC side application and the PLC application when necessary,
In the output area 27 of the DP memory M1, when the monitoring target bit at a specific position in the output transfer data changes, the PLC application interrupts the personal computer 1 to activate the desired personal computer side application.
The PC-side application sets in advance the position of the monitoring target bit in the output area 27 of the DP memory M1 in the DP memory M1 and notifies the firmware FW of the PLC, so that the bit change monitoring process 44 in the firmware FW is set to the copy cycle Tc. Monitors the monitoring target bit in the output area 27 of the DP memory M1 at the same cycle. When a bit change is detected, the interrupt signal INT is generated to the personal computer 1 and the changed monitoring target bit is notified to the personal computer 1 at the same time. The personal computer 1 searches and operates the personal computer side application to be operated from the table indicating the correspondence between the monitoring target bit whose change has been detected and the personal computer side application to be operated at this time.

  Thus, the necessary personal computer side application is operated within one or a predetermined plurality of sequence control periods Ts from the time when the change of the monitoring target bit is detected, and the personal computer side application is quickly synchronized with the PLC application.

According to the invention relating to claim 1, the size (input size) of the input transfer data transferred from the personal computer side application to the PLC application in advance to the dual port memory (DP memory) that can be directly accessed by the personal computer side application toward the PLC side, and Set the size (output size) of the output transfer data to be transferred from the PLC application to the personal computer side application, notify the PLC firmware, and then input the input transfer data to the input area of the input size provided in the DP memory when necessary. And reading the output transfer data transferred from the PLC application when necessary from the output area corresponding to the output size provided in the DP memory,
On the other hand, the PLC internal memory as a data memory for the PLC application is provided with an input area and an output area for storing the input transfer data and the output transfer data, respectively, and a sequence control process executed by the PLC application at each sequence control period. Read / write control status data to / from the control target device in the PLC internal memory, read input transfer data and write output transfer data to the input area and output area of the PLC internal memory, respectively. Firmware that always copies the input transfer data in the input area of the DP memory to the input area of the PLC internal memory and the output transfer data in the output area of the PLC internal memory to the output area of the DP memory at a copy cycle shorter than the sequence control cycle. We will provide a copy means So it was,
Data exchange between the personal computer side application and the PLC application can be reliably performed within one or a predetermined plurality of sequence control cycles, ensuring the punctuality of data exchange, and realizing high-speed data exchange without variation.

According to the invention relating to claim 2, when the set value of the input size or / and output size to the DP memory is set to 0 or blank, the copying means is connected to each of the input areas of the DP memory and the PLC internal memory. Since the copying operation related to each other and / or between the output areas is omitted, even a conventional user who uses the PLC internal memory as a normal data memory without using the input area or the output area can be used. It is possible to use the PLC of the present invention without creating a useless empty area in the memory.
According to the inventions related to claims 3 and 4, the PC-side application previously sets the position of the monitored bit in the output area of the DP memory in the DP memory and informs the PLC firmware, thereby changing the bit of the firmware. The monitoring means monitors the monitored bits in the output area of the DP memory at the same cycle as the copy cycle. When a bit change is detected, an interrupt signal is sent to the personal computer and the changed monitored bit is notified at the same time. Since the table showing the correspondence between the monitored bit that detected the change and the PC-side application to be activated at this time, the PC-side application to be activated was searched and activated.
Necessary personal computer side applications can be operated within one or a plurality of predetermined sequence control periods from the time when the change of the monitoring target bit is detected, and the personal computer side application can be quickly synchronized with the PLC application.

  Thus, since high-speed data exchange between a personal computer and a PLC and synchronization control between a plurality of personal computer applications and a PLC are possible, for example, in a control device using image processing software of a personal computer, image processing and PLC sequence control is linked at high speed, the cycle time of the apparatus is shortened, and productivity is improved.

[Embodiment 1]
First, as a first embodiment of the present invention, implementation of a computer-assembled programmable controller capable of ensuring punctuality when data is exchanged between a personal computer application and a PLC application (that is, data can be exchanged within a predetermined time) An example will be described. Specific examples of such data exchange include the following cases.
1) Transfer of switch data:
This is a case where switch data (ON / OFF information) of a switch displayed on a personal computer screen or a touch panel of a panel computer is repeatedly transferred from the personal computer side to the PLC side, and a machine tool or the like is moved by the switch. In such a case, since ON / OFF of the switch is frequently repeated while monitoring the position of the device to be moved, ON / OFF information needs to be transferred quickly.

2) Transfer of positioning control status data and command data:
When linking the image processing software of the personal computer and the positioning control by the PLC in a semiconductor inspection device, etc., the positioning status data on the PLC side is transferred from the PLC side to the personal computer side, and the command data is transferred from the personal computer side to the PLC side. This is the case.
FIG. 1 is a block diagram showing a system configuration related to a high-speed data exchange function between a PLC application and a personal computer side application as an example of Embodiment 1 of the present invention.
In FIG. 1, the application program in the personal computer 1 is replaced with PP1 as compared to FIG.
In the personal computer built-in PLC 2, input areas 26 and 29 as areas where exchange target data (referred to as input transfer data) transferred from the personal computer side application PP 1 to the PLC application SP is written in the DP memory M 1 and the PLC internal memory M 2, respectively. In addition, output areas 27 and 30 are provided as areas where exchange target data (referred to as output transfer data) transferred from the PLC application SP to the personal computer application PP1 is written,
Further, the DP memory M1 further includes an area for setting and inputting the input size 24, which is the capacity size of the input areas 26 and 29 itself, and the output area 27 and 29. An area for setting and inputting the output size 25 which is also the capacity size of each of the output areas 27 and 30 is provided.
The command processing 10 that is present in the firmware FW and is executed during the idle time of the sequence control cycle Ts is omitted. Instead, the copy processing 31 that is always executed at the predetermined cycle Tc (1 ms in this example) is performed. It differs from the point provided.

The data exchange between the external device 11 and the PLC 2 shown in FIG. 8 is performed in the present invention by the command processing 10 on the firmware FW as before, but this is not directly related to the present invention, so the command processing 10 is It is omitted.
In addition, the PLC application SP receives control state data received from a control target device outside the figure via a serial communication interface outside the figure and stored in the PLC internal memory M2 at a predetermined sequence control cycle Ts (for example, 10 ms) as in the past. And the input transfer data in the input area 29 in place of the conventional write area 7 in the PLC internal memory M2 are read and the sequence calculation is performed. As a result, the new control state data and the output transfer data to be transferred to the personal computer side Ask for.
Then, the control state data in the PLC internal memory M2 is updated with the new control state data, the new control state data is transmitted to the control target device, and the output transfer data generated as a result of the sequence calculation is stored in the PLC internal memory M2. Are written in the output area 30 instead of the conventional read area 8.

FIG. 2 is a flowchart showing a general processing procedure of the PC application PP1, and S1 to S6 indicate step numbers. Next, FIG. 2 will be described with reference to FIG. 2 is executed asynchronously with the copy process 31 described in FIG.
When the personal computer side application PP1 starts up, as indicated by an arrow A12, the data size of the input transfer data to be written to the input area 26 in the area of the input size 24 of the DP memory M1 (this is simultaneously the capacity size of the input area 26 itself). ) Is set (step S1), and the data size of the output transfer data read from the output area 27 (which simultaneously becomes the capacity size of the output area 27 itself) is set in the area of the output size 25 of the DP memory M1 (step S1). Step S2). This data size is, for example, the number of words.
Then, the personal computer side application PP1 reads the output transfer data transferred from the PLC2 side from the output area 27 of the DP memory M1 as indicated by an arrow A16, and copies it to the output area memory inside the personal computer (step S3). Then, the personal computer side application is executed (step S4).

Next, data to be transferred to the PLC 2 side (input transfer data) generated in the application process in step S4 and stored in the input area memory (not shown) inside the personal computer is input to the DP memory M1 as indicated by an arrow A15. Copy to the area 26 (step S5), wait for the execution time interval of the personal computer side application (step S6), return to step S3, and repeat the above-described processing from step S3 to S6.
FIG. 3 is a flowchart showing the procedure of the copy process 31 on the firmware FW of the PLC 2, and S11 to S14 indicate the step numbers. Next, FIG. 3 will be described with reference to FIG. The copy process 31 is always repeated at a constant cycle Tc (1 ms in this example) that is sufficiently faster than the sequence control cycle Ts (10 ms in this example), which is the execution cycle of the PLC application SP.

The copy process 31 first checks whether there is setting data in the input size 24 area of the DP memory M1 (step S11). If there is setting data (branch Yes), the data in the input area 26 of the DP memory M1 is read. As shown by the arrow A13, the set size is copied to the input area 29 of the PLC internal memory M2 (step S12).
If there is substantially no setting data in the area of the input size 24 in step S11 and the setting data is 0 or blank, the copy process 31 skips step S12 and proceeds to the next step S13.
Next, the copy process 31 checks whether there is setting data in the area of the output size 25 of the DP memory M1 (step S13). If there is setting data (branch Yes), the PLC internal memory M2 as indicated by an arrow A14. Is copied to the output area 27 of the DP memory M1 by the set size (step S14), and the process for the current time in FIG.

If there is substantially no setting data in the output size 25 area in step S13 and the setting data is 0 or blank, the copy process 31 omits the process in step S14 and performs the process for the current time in FIG. Exit.
In the copy process of FIG. 3, it is assumed that the input size 24 of the DP memory M1 is, for example, 4 words (1 word = 16 bits), and the personal computer side application PP1 has 4 words in the input area 26 of the DP memory M1. The transfer data is written. The copy process 31 copies and transfers the data in the input area 26 to the input area 29 of the PLC internal memory M2 at a fixed period Tc of 1 ms in this example irrespective of the writing of the personal computer side application PP1.
For this reason, if the copy process 31 tries to access the input area 26 while the personal computer side application PP1 is writing to the input area 26, the DP memory M1 has the following characteristics in this example. Access is not accepted until the writing of the 16-bit unit data area, that is, the data area of one word is completed. Therefore, the access is waited for a short time until the writing of data of one word is completed. To do.

Accordingly, when the personal computer application PP1 writes transfer data for 4 words in the input area 26 of the DP memory M1, the copy process 31 simultaneously accesses the DP memory M1 and transfers it to the input area 29 of the PLC internal memory M2. Of the transferred data, the latest data is worst, one word just written by the personal computer side application PP1, and the remaining three words remain unupdated old data.
However, even if such an operation is repeated, until the copy process 31 is executed four times, in this example, at least 4 words within 4 ms, which is sufficiently faster than 10 ms of one sequence control period Ts. Since the updated data is transferred from the DP memory M1 to the PLC internal memory M2, the transferred updated data is immediately reflected in the sequence control in the next sequence control cycle by the PLC application SP, and the punctuality of data exchange Is secured.

Next, with reference to FIGS. 2 and 3, an example of the specific operation of FIG. 1 will be described in the order of the following heading numbers A1) to A3). Here, it is assumed that the personal computer 1 in FIG. 1 is a panel computer having a touch panel for operating the machine tool, and the personal computer side application PP1 in FIG. 1 is incorporated in an injection molding machine as a machine tool on the PLC side. Switch status data (in this case, position data) is monitored, and switch data for ON / OFF operation of the drive device (for example, servo amplifier and servomotor) that moves the mold (in this case, inching) is sent to the PLC side. It is assumed that the monitoring operation software is transferred.
Then, it is assumed that the PLC application SP performs mold inching control via the driving device in accordance with switch data (switch operation data) sent from the monitoring operation software PP1 of the personal computer 1.

In the case of this example, the switch operation data is written to the address assigned as the input area 26 of the DP memory M1 by the monitoring operation software PP1, but this input area 26 is stored in the fixed cycle Tc (in this example) on the firmware FW. The data is copied to the input area 29 of the PLC internal memory M2 by the copy process 31 executed every 1 ms).
For this reason, the PLC application SP reads the input area 29 in the sequence control process executed every sequence control cycle Ts (10 ms in this example), confirms the switch operation data sent from the monitoring operation software PP1, and uses this operation data as the operation data. Accordingly, it is determined in advance that the mold drive unit of the injection molding machine is ON / OFF controlled.
In this example, the position data of the type to be monitored is read by the monitoring operation software PP1 from the address assigned as the output area 27 of the DP memory M1, and this position data is copied to the firmware FW in the copy process 31. Is a copy of the contents of the output area 30 of the PLC internal memory M2.

For this reason, the PLC application SP is predetermined to write the current position data of the mold in the output area 30 of the PLC internal memory M2 for each sequence control process of the sequence control cycle Ts.
A1) Initialization by the monitoring operation software PP1:
The monitoring operation software PP1 is activated simultaneously with the rise of the computer 1, and the monitoring operation software PP1 sets the data size for high-speed data exchange with the PLC application SP to each of the input size 24 and the output size 25 of the DP memory M1. Set.
In this example, the data size of the switch operation data written in the input area 26 is set as the input size 24, and the data size of the position data of the type read from the output area 27 is set as the output size 25.

A2) Transfer of switch data by the monitoring operation software PP1:
The monitoring operation software PP1 displays an inching switch for turning on / off the driving device for moving the mold on the screen of the panel computer, and the portion displaying the inching switch of the touch panel provided on the surface of the screen is pressed. If so, ON data is set as switch operation data in the input area 26, and OFF data is set when the touch panel is no longer pressed.
The PLC application SP reads the switch operation data sent from the monitoring operation software PP1 side by the copy process 31 from the input area 29 of the PLC internal memory M2 in the sequence control process. A movement command at a fixed speed is given to the drive device to move the mold at a fixed speed, and when the data becomes OFF data, a stop command is given to the drive device to stop the mold.

In these operations, the punctuality of the transmission time of the switch data from the personal computer 1 side to the PLC 2 side is secured, and the time when the person actually pushes the switch and the time when the switch data transmitted to the PLC is ON data. There is no variation between them, and variation in the amount of movement of the mold can be eliminated. That is, movement and fine adjustment to the target position of the mold can be easily performed.
A3) Monitoring of mold position data by the monitoring operation software PP1:
The monitoring operation software PP1 reads the current position data of the type of the output area 27 sent from the PLC application SP by the copy process 31 at a fixed cycle, and displays it on the screen of the panel computer.
In these operations, the transmission time of the position data of the mold from the PLC 2 side to the personal computer 1 side is ensured, and the current position data of the mold is monitored by the monitoring operation software PP1 while moving at a fixed speed of the mold. In this case, it is possible to eliminate variations in the amount of change in the position data of the mold (the amount of movement of the mold) displayed on the panel computer screen every cycle. That is, without actually confirming the mold visually, it is possible to easily move to the target position and make fine adjustments while viewing the position data of the mold monitored by the panel computer.

[Embodiment 2]
For example, in a semiconductor inspection device, etc., multi-axis conveyance and positioning control of the IC chip to be inspected are performed by the PLC, and the personal computer side is directed to the PLC side by the image processing software based on the IC chip image recognition result (position correction command) Consider a system in which IC chip movement instructions are given by transfer management software.
In such a system, the personal computer side application and the PLC application not only perform high-speed data exchange that can ensure punctuality as described in the first embodiment, but also constantly instruct many PLC side applications from the PLC application. In other words, these PC-side applications can be operated at the appropriate timing required by the PLC application without putting an extra burden on the creation of PC-side applications. (For example, it is desirable to synchronize the personal computer side application with the PLC application when necessary), and it is effective to interrupt the personal computer side when the PLC is necessary.

Therefore, in addition to the high-speed data exchange between the PLC and the personal computer as in the first embodiment, the PLC interrupts the personal computer when necessary to perform necessary operations, further reducing the cycle time of the entire device. A computer-assembled programmable controller configured as described above will be described.
FIG. 4 is a block diagram showing a system configuration related to a synchronization function between a PLC application and a personal computer side application as an example of Embodiment 2 of the present invention.
4 differs from FIG. 1 in that the application program is replaced with PP2 in the personal computer 1 and the interrupt detection management unit 50 is added. In the personal computer built-in PLC 2, the monitoring address addition value is stored in the DP memory M1. 34, a monitor bit set value 35, an interrupt flag 48, an interrupt generation factor bit 39 area, and an interrupt trigger signal area 49 are newly provided, and a monitor address (that is, the following) is output in the output area 27 of the DP memory M1. , The area of the monitored address) 38 is newly provided, the bit change monitoring process 44 executed at the same fixed cycle Tc (1 ms in this embodiment) as the copy process 31 is added on the firmware FW, and On the output area 30 of the PLC internal memory M2, the area of the monitoring address 37 which is the copy source of the monitoring address 38 is new. Is a point that has been.

Note that the processing of the PLC application SP is basically the same as that in FIG. 1, and reading and writing of control state data in the PLC internal memory M2 exchanged with a control target device not shown in the sequence at every sequence control cycle Ts. The sequence control process is executed while reading / writing each of the input area 29 and the output area 30 in the internal memory M2. However, in FIG. 4, in order to monitor the establishment of an interrupt generation condition described later in the control state data of the control target device assigned to the output area 30 to the monitoring address 37 in the output area 30 in the PLC internal memory M2. The difference is that a bit to be monitored (referred to as a monitoring bit) is included.
The personal computer side application PP2 performs the same processing as that of the personal computer side application PP1 of FIG. 1 on the areas 24 to 27 of the DP memory M1, and in addition to the DP memory M1 in advance as indicated by the arrow A25, the monitoring address addition value 34 respectively. And the monitoring bit set value 35 is written. The monitoring address 38 is an address obtained by adding the monitoring address addition value 34 minutes to the head address of the output area 27.

In the copy process 31 on the firmware FW, whether or not the transfer data sizes 24 and 25 are set in the areas of the input size 24 and the output size 25 of the DP memory M1 in the fixed cycle Tc as in the case of FIG. If the size data is set, the data corresponding to the input size 24 of the input area 26 of the DP memory M1 is input to the input area 29 of the PLC internal memory M2, and the output size of the output area 30 of the PLC internal memory M2 is set. The 25-minute data is copied to the output area 27 of the DP memory M1.
The bit change monitoring process 44 on the firmware FW also samples the data at the monitoring address 38 of the DP memory M1 at the same fixed cycle Tc, and at least one of the bits set by the monitoring bit setting value 35 changes from OFF to ON. Watch for changes.
That is, when any bit of the monitoring address 37 in the output area 30 of the PLC internal memory M2 is turned ON in the process of the PLC application SP, the corresponding of the monitoring address 38 in the output area 27 of the DP memory M1 is performed by the copy process 31. The bit to be turned on is also ON.

The bit change monitoring process 44 detects this bit change by the process shown in FIG. 5 and determines whether or not an interrupt generation condition is satisfied. Here, the processing of FIG. 5 will be described. S21 to S27 in the figure are step numbers.
The bit change monitoring process 44 first reads and inverts the previous value of the monitoring address 38 held by itself in step S21. Next, in step S22, an AND condition between the inverted value and the current value of the monitoring address 38 read from the DP memory M1 is obtained. In the next step S23, an AND condition between the calculation result of step S22 and the monitoring bit setting value 35 read from the DP memory M1 is further obtained.
In the next step S24, the bit set as the monitoring bit set value 35 (that is, the monitoring bit) and the bit changed to ON (referred to as a change bit) is checked from the calculation result. In the next step S25, it is determined whether or not there is even one change bit. If there is no change bit (branch No), the interrupt generation condition is not satisfied (step S26), and the DP memory M1 interrupts. The flag 48 is reset.

On the other hand, if there is at least one change bit in step S25 (branch Yes), it is assumed that the interrupt generation condition is satisfied (step S27), and the bit in which the change is detected in the interrupt generation factor bit 39 area of the DP memory M1 In addition, the interrupt flag 48 of the DP memory M1 is set, and the interrupt trigger data is written to the interrupt trigger signal area 49 of the DP memory M1, thereby detecting the interrupt in the personal computer 1. An interrupt trigger signal INT is generated for the management unit 50. Then, the monitoring of the bit change is suspended until the interrupt flag 48 is reset by the interrupt detection management unit 50.
FIG. 7 is a flowchart showing a processing procedure of the interrupt detection management unit 50 in the personal computer 1, and S31 to S40 are step numbers. This processing procedure is roughly divided into a part of interrupt detection processing 100 consisting of exchanges with the PLC 2 side in steps S31 to S34 and a part of interrupt management processing 200 consisting of processing in the personal computer 1 of steps S35 to S40. .

Here, the interrupt detection processing 100 will be described. When detecting the input of the interrupt trigger signal INT (step S31, branch Yes), the interrupt detection management unit 50 in the personal computer 1 performs read access to the interrupt trigger signal area 49 of the DP memory M1 as indicated by an arrow A28. As a result, the interrupt trigger signal INT is reset (step S32).
Next, the interrupt detection management unit 50 reads the interrupt factor bit 39 of the DP memory M1 as indicated by an arrow A27, and stores this data in the interrupt factor memory 60 within itself (step S33). As shown by the arrow A26, the interrupt flag 48 of the DP memory M1 is reset (step S34). The reset of the interrupt flag 48 causes the bit change monitoring process 44 on the PLC 2 side to resume monitoring the change of the monitoring bit.
FIG. 6 shows an embodiment of the configuration of the main part in the application program PP2 and the interrupt detection management unit 50 of the personal computer 1 in FIG. The personal computer side application PP2 is composed of a plurality of application programs that operate in synchronization with the PLC application SP. In this embodiment, the personal computer side application PP2 is composed of two application programs, PP2-1 and PP2-2.

The personal computer side applications PP2-1 and PP2-2 have 511-1 and 51-2 as PLC interrupt wait functions 51 each comprising a wait bit designation value 52, a wait 55, and a generated bit 56, and interrupt this function processing. This is executed with the detection management unit 50.
The interrupt detection management unit 50 includes an interrupt waiting management table 59 and an interrupt factor memory 60 as functional units corresponding to this function processing. The interruption waiting management table 59 has a plurality of areas in which waiting bit data 52a and management numbers 53 are paired so as to be compatible with a plurality of personal computer side applications PP2.
Now, when the personal computer side applications PP2-1 and PP2-2 execute the PLC interrupt wait functions 51-1 and 51-2 during the respective processes, each of the personal computer side applications PP2 first sets the wait bit designation value 52 as an arrow. The ID number is set in the area of the wait bit data 52a in the interrupt wait management table 59 as in A31, and further specifies the personal computer side application PP2 in the area of the management number 53 paired with this wait bit data 52a. Set. And it will be in the state of waiting 55, and waits for the interruption management process 200 from the interruption detection management part 50. FIG.

Next, the interrupt management process 200 of the interrupt detection management unit 50 will be described with reference to FIG. The interrupt detection management unit 50 searches the wait bit data 52a stored in the interrupt wait management table 59 (step S35), and compares it with the data in the interrupt factor memory 60 as indicated by an arrow A32. As this comparison method, an AND condition between the searched waiting bit data 52a and the interrupt factor memory 60 is obtained (step S36).
If at least one bit is ON, that is, if any of the bits indicating the interrupt factor in the interrupt factor memory 60 is ON (step S37, branch Yes), the waiting bit data 52a A wait release instruction 54 is given to the personal computer application corresponding to the management number 53 of the pair (PP2-2 in the example of FIG. 6), the wait 55 state is released (step S38), and the allocation is performed as indicated by an arrow A33. The data in the interrupt factor memory 60 is transferred to the generated bit 56 in the PLC interrupt waiting function (51-2 in this example) of the personal computer side application (PP2-2 in this example) (step S39).

The interrupt detection management unit 50 repeats the interrupt management process 200 of steps S35 to S40 until it is determined in step S40 that the search of the interrupt waiting management table 59 is the end position.
The personal computer application (PP2-2 in the example of FIG. 6) that has received the data of the generated bit 56 in step S39 as a return value of the PLC interrupt wait function determines which bit of the designated wait bit has been released from the wait state. Confirm and perform a predetermined process according to the bit.
Next, with reference to FIG. 5 and FIG. 7, embodiments of specific operations of FIG. 4 and FIG. 6 will be described in the order of heading numbers B1) to B7). In this case, the personal computer side application PP2-1 gives a positioning command (position correction command) in a predetermined direction (X-axis direction in this example) to the PLC side by image processing of the IC chip, or a semiconductor that inspects the IC chip. It is assumed that the image processing software of the inspection apparatus is the image processing software of the inspection device, and the bath-side application PP2-2 is transport management software that manages the transport of another IC direction (in this example, the Y-axis direction) to the next process of the IC chip.

Then, it is assumed that the PLC application SP performs positioning control on the respective axes of the IC chip in accordance with commands from the image processing software PP2-1 and the conveyance management software PP2-2.
In the following description, as a premise, the IC chip to be inspected as a work that has just been carried into the semiconductor inspection apparatus by another means has been recognized by the image processing software PP2-1 for the positional deviation in the X-axis direction. After that, the PLC application SP correctly positions (corrects misalignment) in the X-axis direction, and is again inspected by the image processing software PP2-1. Thereafter, it is carried out from the semiconductor inspection apparatus by the transfer management software PP2-2 in the Y-axis direction. It is assumed that a series of processes to be performed is performed each time a new IC chip is carried into the semiconductor inspection apparatus.

In the case of this example, the movement amount data and the positioning start command data are separately written in the input area 26 of the DP memory M1 by the image processing software PP2-1 and the conveyance management software PP2-2. The input area 26 is copied to the input area 29 of the PLC internal memory M2 by the copy process 31 on the firmware FW.
For this reason, the PLC application SP reads the corresponding area in the input area 29 in the sequence control process executed every sequence control cycle Ts and sends the movement amount data and positioning start command data sent from the image processing software PP2-1. It is determined in advance that the movement amount data and positioning start command data sent from the conveyance management software PP2-2 are checked and positioning control is performed according to the existing data.
In this example, both the positioning completion data related to the image processing software PP2-1 and the positioning completion data related to the conveyance management software PP2-2 are written as monitoring bits in the monitoring address 38 in the output area 27 of the DP memory M1. However, the content of the monitoring address 38 is obtained by copying the content of the monitoring address 37 in the output area 30 of the PLC internal memory M2 by the copy process 31 on the firmware FW.

For this reason, the PLC application SP performs the PLC internal memory M2 in the sequence control process at the latest sequence control cycle Ts at the time when the positioning control based on the instructions of the image processing software PP2-1 and the conveyance management software PP2-2 is completed. The positioning completion data as the monitoring bit is written in advance in the corresponding bit position of the monitoring address 37 in the output area 30.
As a result, in this example, the PLC application SP uses bit 0 (0th digit (end digit) bit of binary data) or bit 1 (1st digit of binary data (next to the end) as the positioning completion data on the monitoring address 37. Bit)) is set, an interrupt is generated from the PLC side to the personal computer side assuming that the positioning control based on the instruction of the image processing software PP2-1 or the conveyance management software PP2-2 is completed.

B1) Initialization process:
When the computer 1 is started up, first a representative computer application (in this example, image processing software PP2-1) is started up, and high-speed data exchange with the PLC application SP and an interruption to the personal computer side by the PLC are generated. For example, the initialization processing unit of the image processing software PP2-1 performs the initial setting shown in B1a) and B1b) on the DP memory M1, and then starts the transport management software PP2-2.
B1a) Setting to the input size 24 and output size 25 areas of the DP memory M1;
In this example, the input size 24 includes all of the movement amount data and the positioning start command data that the image processing software PP2-1 and the conveyance management software PP2-2 write in the input area 26 using different areas. Set the data size.

Further, the output size 25 is set to 1 word which is the data size of the monitoring address 38 in the output area 27 in which the positioning completion data handled by the image processing software and the positioning completion data handled by the conveyance management software are both written as monitoring bits. .
B1b) Setting of the monitoring address addition value 34 and the monitoring bit setting value 35 area of the DP memory M1;
In this example, the monitoring address addition value 34 is set to an address addition value that gives an address on the output area 27 of the monitoring address 38 having the positioning completion data assigned to the output area 27. In this example, since the output area 27 itself coincides with the monitoring address 38 area, the address addition value is 0.
Further, in the monitoring bit set value 35, positions of two monitoring bits for generating an interrupt from the PLC, which are handled by the image processing software PP2-1 and the conveyance management software PP2-2, are set. For example, when the image processing software uses bit 0 (0th digit bit) and the transport management software uses bit 1 (1st digit bit) as the monitoring bit position, bits 0 and 1 are set to the monitoring bit setting value 35. A binary data value “3” is set, each value “1”.

B2) Detection of IC chip position deviation by image processing software, standby processing:
The image processing software PP2-1 recognizes the image of the IC chip, measures the deviation of the IC chip from the normal position in the X-axis direction, and uses the movement amount data in the X-axis direction to correct the position of the IC chip as DP The movement amount data assigned to the image processing software side of the input area 26 of the memory M1 is set to the address for storing the movement amount data, and “start data” is set to the address for storing the positioning start command data also assigned to the image processing software side. set.
Subsequently, the PLC interrupt wait function 51-1 is executed to set a wait bit in the wait bit specified value 52 to enter a wait 55 state, and wait for an interrupt from the PLC side. That is, it waits for the completion of positioning for position correction of the IC chip.
Note that the value set in the waiting bit designation value 52 here is bit 0 when the image processing software sets bit 0 of the monitoring address 38 in the output area 27 as the copy destination of the positioning completion data by the PLC application SP as described above. The binary data value “1” is obtained by setting the value of the (0th digit bit) to “1”.

B3) Positioning control in X axis direction by PLC, interrupt generation processing:
The PLC application SP is moved from the input area 26 of the DP memory M1 to the input area 29 of the PLC internal memory M2 by the copy process 31 on the firmware FW, and the movement amount data (in the X-axis direction) and positioning start on the image processing software side Reads the “start data” of the command data, controls the X-axis direction drive device (for example, servo amplifier and servo motor) connected to the PLC 2 to execute the positioning operation, and moves only the movement amount specified by the movement amount data. Move the IC chip. That is, the positional deviation of the IC chip is corrected.
When this positioning control (position shift correction) is completed, the PLC application SP turns ON bit 0 of the last digit of the monitoring address 37 of the PLC internal memory M2 as positioning completion data. As a result, bit 0 of the monitoring address 38 of the DP memory M1 is also turned ON by the copy processing 31 on the firmware FW, and the bit change monitoring processing 44 on the firmware FW is checked against the monitoring bit set value 35 of the DP memory M1 to determine the interrupt condition. When it is determined that it is established, the bit 0 of the interrupt generation factor bit 39 of the DP memory M1 is turned ON, and an interrupt is generated in the personal computer 1 by the interrupt generation process described above.

B4) Image processing software standby release, IC chip inspection processing:
In the image processing software PP2-1, the wait 55 of the PLC interrupt wait function 51-1 is canceled by the occurrence of the interrupt, and the bit 0 of the generated bit 56 of the function 51-1 is “1”. Recognizing that the IC chip position shift correction is completed, the IC chip is inspected to determine whether it is acceptable. Then, after instructing the transport management software PP2-2 to carry out the IC chip, it waits for the arrival of the IC chip to be corrected next.
B5) IC chip unloading processing by transfer management software:
When the conveyance management software PP2-2 receives an instruction to carry out the IC chip from the image processing software PP2-1, the movement management (in the Y-axis direction) to the conveyance destination is transferred to the conveyance management in the input area 26 of the DP memory M1. The moving amount data assigned to the software side is set to the address for storing the data, and the “start data” is set to the address for storing the positioning start command data also assigned to the conveyance management software side.

Subsequently, the PLC interrupt wait function 51-2 is executed to set a wait bit in the wait bit specified value 52 to enter a wait 55 state and wait for an interrupt from the PLC side. That is, it waits for completion of positioning of the movement to the transfer destination of the IC chip.
Here, the value set to the waiting bit designation value 52 is the copy destination of the positioning completion data by the PLC application SP by the bit 1 (first digit bit) of the monitoring address 38 of the output area 27 as described above by the transport management software. In this case, the binary data value “2” with the value of bit 1 (first digit bit) as “1” is obtained.
B6) Y-axis positioning control by PLC, interrupt generation processing:
The PLC application SP starts the positioning and movement amount data (in the Y-axis direction) on the transfer management software side copied from the input area 26 of the DP memory M1 to the input area 29 of the PLC internal memory M2 by the copy process 31 on the firmware FW. Reads the “start data” of the command data, controls the Y-axis direction drive device (for example, servo amplifier and servo motor) connected to the PLC 2 to execute the positioning operation, and moves only the movement amount specified by the movement amount data. Move the IC chip.

When this positioning control (movement to the conveyance destination) is completed, the PLC application SP turns ON bit 1 of the monitoring address 37 of the PLC internal memory M2 as positioning completion data. As a result, bit 1 of the monitoring address 38 of the DP memory M1 is also turned ON by the copy processing 31 on the firmware FW, and the bit change monitoring processing 44 on the firmware FW is compared with the monitoring bit set value 35 of the DP memory M1 to determine the interrupt condition. When it is determined that it is established, the bit 1 of the interrupt generation factor bit 39 of the DP memory M1 is turned ON, and an interrupt is generated in the personal computer 1 by the interrupt generation process described above.
B7) Canceling standby of transport management software:
In the transfer management software PP2-2, the wait 55 of the PLC interrupt wait function 51-2 is canceled by the occurrence of the interrupt, and the bit 1 of the generated bit 56 of the function 51-2 is “1”. It recognizes that the movement of the IC chip to the transfer destination is completed, and waits for an instruction to carry out the next IC chip.

  However, before the IC chip is carried out to the conveyance destination by the conveyance management software, the next IC chip is carried into this semiconductor inspection apparatus, and the positional deviation is corrected by the image processing software and the PLC as described above. If the inspection is completed at this time, the IC chip unloading instruction from the image processing software to the transfer management software has already been issued or is immediately issued. The carry-out process can be resumed.

1 is a block diagram showing a system configuration related to a high-speed data exchange function between a PLC application and a personal computer side application as an example of Embodiment 1 of the present invention; The flowchart which shows the procedure of the general process of the personal computer side application in FIG. The flowchart which shows the procedure of the copy process of the PLC firmware in FIG. The block diagram which shows the system configuration regarding the synchronous function of the PLC application and personal computer side application as one Example of Embodiment 2 of this invention The flowchart which shows the procedure of the interrupt generation determination process by the bit change monitoring process of the PLC firmware in FIG. The block diagram which shows one Example of a structure of the principal part in the application program and interruption detection management part of the personal computer in FIG. The flowchart which shows the process sequence of the interruption detection management part in a personal computer in FIG. The figure which shows the system structural example regarding the data exchange function of the conventional PLC application and the personal computer side application Block circuit diagram showing a system configuration example of a PLC with a built-in personal computer

Explanation of symbols

1 PC 2 PC built-in programmable controller (PC built-in PLC)
3 Expansion bus (PCI bus)
24 Input size 25 Output size 26 Input area 27 Output area 29 Input area 30 Output area 31 Copy process 34 Monitoring address addition value 35 Monitoring bit set value 37, 38 Monitoring address 39 Interrupt generation factor bit 44 Bit change monitoring process 48 Interrupt Flag 49 Interrupt trigger signal area 50 Interrupt detection management section 51 (51-1, 51-2) PLC interrupt wait function 52 Wait bit specified value 52a Wait bit data 53 Management number 54 Wait release instruction 55 Wait 56 Generated bit 59 Interrupt wait management table 60 Interrupt factor memory 100 Interrupt detection process 200 Interrupt management process INT Interrupt trigger signal M1 Dual port memory (DP memory)
M2 PLC internal memory FW Firmware SP PLC user application program (PLC application)
PP1, PP2 (PP2-1, PP2-2) PC side user application program (PC side application)

Claims (4)

The control state data received from one or more control target devices is stored in the corresponding areas of the internal memory, and a sequence operation is performed using all the control state data, and a new result obtained as a result of the operation is obtained. The control state data in the internal memory is updated with each control state data, and the new control state data is repeatedly transmitted to the corresponding control target device at a predetermined sequence control cycle, and the control target device is sequenced. The internal memory in the programmable controller to be controlled is further connected to the programmable controller from the computer side via a dual port memory on the buses on both the computer side and the programmable controller side, and the same memory area can be accessed from both. Input region for storing input transfer data transferred to the over La side, provided the output region for storing output transfer data to be transferred through the dual port memory to the computer side from the programmable controller side,
In addition to the control status data received from the control target device in the internal memory, the programmable controller further performs a sequence calculation using the input transfer data read from the input area in the internal memory for each sequence control cycle. As a result of this calculation, a computer-assembled programmable controller that obtains the output transfer data in addition to new control state data to be transmitted to the control target device and writes the output transfer data to the output area in the internal memory In the controller
In the dual port memory, an input size setting area in which the size of the input transfer data is set in advance by the computer, an output size setting area in which the size of the output transfer data is set in advance by the computer, and the computer An input area where the input transfer data is written when necessary, and an output area where the output transfer data is also read when necessary by the computer,
In a predetermined copy cycle shorter than the sequence control cycle, input transfer data as data having a size set in the input size setting region in the input region of the dual port memory is always copied to the input region of the internal memory. And a copy unit that repeats copying output transfer data as data having a size set in the output size setting area in the output area of the internal memory to the output area of the dual port memory. A computer-assembled programmable controller. The computer-assembled programmable controller according to claim 1,
When the setting value for the input size setting area or / and the output size setting area of the dual port memory is set to 0 or blank, the copying means is connected between the input areas of the dual port memory and the internal memory, or ( And) a computer-assembled programmable controller characterized by omitting the above-described copying operation between output areas. The computer-assembled programmable controller according to claim 1 or 2,
An area in which monitor bit position data, which is data specifying a position where a monitor bit as a data bit to be monitored in the output area of the dual port memory exists in the dual port memory, is preset by the computer. Monitoring bit position setting area, an interrupt signal generation area for generating an interrupt signal to the computer based on the writing of interrupt generation data, and an interrupt generation when the computer inputs the interrupt signal An interrupt generation factor bit area is provided as an area for reading the factor bit,
In synchronization with the copy cycle, the monitoring bit in the output area of the dual port memory specified by the monitoring bit position data set in the monitoring bit position setting area of the dual port memory is constantly monitored, When the monitoring bit changes to a value to generate an interrupt, the monitoring bit position data for the monitoring bit is written in the interrupt generation factor bit area of the dual port memory, and the interrupt signal of the dual port memory A computer-assembled programmable controller comprising bit change monitoring means for writing interrupt generation data in a generation area and supplying an interrupt signal to the computer. The computer-assembled programmable controller according to claim 3,
The computer reads the monitoring bit position data from the interrupt generation factor bit area of the dual port memory based on the input of the interrupt signal, and operates according to the monitoring bit position data and the interrupt signal. What is claimed is: 1. A computer-assembled programmable controller characterized in that a corresponding application program is obtained from an interrupt management table indicating correspondence with different application programs to be operated.

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