[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP4419559B2 - Power converter - Google Patents

Power converter Download PDF

Info

Publication number
JP4419559B2
JP4419559B2 JP2003424472A JP2003424472A JP4419559B2 JP 4419559 B2 JP4419559 B2 JP 4419559B2 JP 2003424472 A JP2003424472 A JP 2003424472A JP 2003424472 A JP2003424472 A JP 2003424472A JP 4419559 B2 JP4419559 B2 JP 4419559B2
Authority
JP
Japan
Prior art keywords
voltage
reverse
semiconductor element
reverse blocking
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003424472A
Other languages
Japanese (ja)
Other versions
JP2005185039A (en
Inventor
壮章 田畑
英俊 海田
清明 笹川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Holdings Ltd filed Critical Fuji Electric Holdings Ltd
Priority to JP2003424472A priority Critical patent/JP4419559B2/en
Publication of JP2005185039A publication Critical patent/JP2005185039A/en
Application granted granted Critical
Publication of JP4419559B2 publication Critical patent/JP4419559B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Power Conversion In General (AREA)

Description

この発明は、ブリッジ構成の1アーム当たり複数個直列接続された逆阻止型IGBTを持つ電力変換装置に関する。   The present invention relates to a power conversion device having reverse blocking IGBTs connected in series per arm in a bridge configuration.

図19(a)に、電力変換装置の一般的な例を示す。
図19(a)において素子定格電圧に対して直流電圧Edが大きく高電圧になる場合には、例えば図19(b)に示すように、IGBTQ11〜23をそれぞれ複数個直列接続して用いるのが一般的である。このように、IGBTを複数個直列接続した場合には、同時にオン,オフさせるために、例えば特許文献1のようにする。
図20はその概要を説明するもので、その動作図としての図21に示すように、ターンオフ時に急峻に立ち上がるサージ電圧を揃え、ターンオフ後の漏れ電流のアンバランスによる電圧アンバランスを、図20に示すような可変抵抗回路からなる外部回路Rvar1,Rvar2により均等にバランスさせるようにしている。
FIG. 19A shows a general example of a power conversion device.
In FIG. 19A, when the DC voltage Ed is large and high with respect to the element rated voltage, for example, as shown in FIG. 19B, a plurality of IGBTs Q11 to 23 are used in series. It is common. As described above, when a plurality of IGBTs are connected in series, for example, Patent Document 1 is used in order to simultaneously turn on and off.
FIG. 20 is a diagram for explaining the outline. As shown in FIG. 21 as an operation diagram thereof, surge voltages that rise steeply at the time of turn-off are arranged, and voltage imbalance due to imbalance of leakage current after turn-off is shown in FIG. The external circuits Rvar1 and Rvar2 composed of variable resistance circuits as shown are balanced evenly.

一方、IGBTは一般に逆方向に対する耐圧がない等の理由により、IGBTに逆方向に電圧が印加されて素子破壊するのを防止するため、通常は逆方向にダイオードを接続して使用する。
ところで、近年、図22(b)に示すような逆方向に耐圧を有する特性の逆阻止IGBTが開発されていることから(非特許文献1参照)、図23(a)に示すように逆阻止IGBTQf,Qrを互いに逆並列に接続して、図24のようなマトリックスコンバータ(サイクロコンバータ:非特許文献2参照)を構成することで、大容量の電解コンデンサを不要とし、電力変換装置の小型,長寿命化を図るものがある。
On the other hand, the IGBT is generally used by connecting a diode in the reverse direction in order to prevent the device from being damaged by applying a voltage to the IGBT in the reverse direction, for the reason that there is generally no breakdown voltage in the reverse direction.
In recent years, reverse blocking IGBTs having a breakdown voltage in the reverse direction as shown in FIG. 22B have been developed (see Non-Patent Document 1), and as shown in FIG. 23A, reverse blocking is performed. IGBTQf and Qr are connected in antiparallel with each other to form a matrix converter as shown in FIG. 24 (cycloconverter: see Non-Patent Document 2), thereby eliminating the need for a large-capacity electrolytic capacitor and reducing the size of the power converter. Some have a longer life.

このようなマトリックスコンバータにおいても、装置を高電圧化するには例えば図23(b)に示すように複数個直列接続する手法をとる。このとき、逆阻止IGBTのターンオフは一般的なIGBTと同じ特性になるため、先の図20に示すように、可変抵抗からなる外部回路Rvar1,Rvar2を各素子に並列に接続することで、電圧アンバランスを抑制することができる。   Even in such a matrix converter, in order to increase the voltage of the device, for example, as shown in FIG. At this time, the turn-off of the reverse blocking IGBT has the same characteristics as that of a general IGBT. Therefore, as shown in FIG. 20, the external circuits Rvar1 and Rvar2 made of variable resistors are connected in parallel to the respective elements. Unbalance can be suppressed.

特開2003−189590号公報(第4−5頁、図1−2)JP 2003-189590 A (page 4-5, FIG. 1-2) 「新しいパワーデバイス マトリックスコンバータに適用される逆阻止IGBT」OHM,2003年4月号"Reverse blocking IGBT applied to new power device matrix converter", OHM, April 2003 「電圧型PWMサイクロコンバータの定常特性」電学論D,113巻9号,平成5年"Steady characteristics of voltage-type PWM cycloconverter" D

しかしながら、逆阻止IGBTを逆並列に接続した双方向スイッチを直列接続した回路では、図23(c)のように順方向側Qf1,Qf2,…Qfnと、逆方向側Qr1,Qr2,…Qrnに外部回路を接続しなければならず、外部回路が大型化または複雑化するという問題が発生する。
したがって、この発明で解決しようとする課題は、外部回路をできるだけ小さくして電圧バランスを図ることにある。
However, in a circuit in which bidirectional switches having reverse blocking IGBTs connected in antiparallel are connected in series, as shown in FIG. 23 (c), forward side Qf1, Qf2,. An external circuit must be connected, which causes a problem that the external circuit becomes large or complicated.
Therefore, the problem to be solved by the present invention is to make the external circuit as small as possible to achieve voltage balance.

このような課題を解決するため、逆電圧が印加されているときの漏れ電流はゲート電圧が大きいと減少すると言う逆阻止IGBTの逆電圧特性を利用するもので、請求項1の発明では、コレクタ−エミッタ間に印加される順方向の電圧はゲートに順電圧または逆電圧を与えることで制御し、コレクタ−エミッタ間に印加される逆方向の電圧は阻止する機能を有する逆阻止型半導体素子を、アーム当たり複数個直列に接続して構成される電力変換装置において、前記逆阻止型半導体素子のそれぞれにコレクタ−エミッタ間の電圧を検出する検出手段と、ゲート電圧値を調整する調整手段とを設け、逆阻止型半導体素子に逆方向に電圧が印加されているときは、前記検出手段にて検出された電圧値に応じ、前記調整手段によりゲート電圧値を調整することを特徴とする。
この請求項1の発明においては、前記逆阻止型半導体素子に順方向に電圧が印加されているときは、前記半導体素子に並列に接続された可変抵抗の抵抗値を前記調整手段を介して調整することができる(請求項2の発明)。
In order to solve such a problem, the reverse current characteristic of the reverse blocking IGBT that the leakage current when the reverse voltage is applied decreases when the gate voltage is large is used. The forward voltage applied between the emitter is controlled by applying a forward voltage or a reverse voltage to the gate, and the reverse blocking semiconductor element having a function of blocking the reverse voltage applied between the collector and the emitter is provided. In the power conversion device configured to be connected in series per arm, a detecting means for detecting a collector-emitter voltage for each of the reverse blocking semiconductor elements and an adjusting means for adjusting a gate voltage value are provided. When the voltage is applied to the reverse blocking semiconductor element in the reverse direction, the gate voltage value is adjusted by the adjusting means according to the voltage value detected by the detecting means. And wherein the Rukoto.
In the first aspect of the invention, when a voltage is applied in the forward direction to the reverse blocking semiconductor element, the resistance value of the variable resistor connected in parallel to the semiconductor element is adjusted via the adjusting means. (Invention of claim 2).

請求項3の発明では、コレクタ−エミッタ間に印加される順方向の電圧はゲートに順電圧または逆電圧を与えることで制御し、コレクタ−エミッタ間に印加される逆方向の電圧は阻止する機能を有する逆阻止型半導体素子を逆並列に接続してなる双方向スイッチを、アーム当たりn(2以上の自然数)個直列に接続して構成される電力変換装置において、
前記双方向スイッチを構成する一方の逆阻止型半導体素子のコレクタ−エミッタ間電圧と他方の逆阻止型半導体素子のエミッタ−コレクタ間電圧をそれぞれ検出する検出手段と、検出された電圧値が所定値を超えた逆阻止型半導体素子とは逆方向に電圧が印加されている方の逆阻止型半導体素子のゲート電圧値を調整する調整手段とを設けたことを特徴とする。
In the invention of claim 3, the forward voltage applied between the collector and the emitter is controlled by applying a forward voltage or a reverse voltage to the gate, and the reverse voltage applied between the collector and the emitter is blocked. In a power converter configured by connecting n (two or more natural numbers) bi-directional switches formed by connecting anti-blocking semiconductor elements having anti-parallel in parallel in series,
Detecting means for detecting the collector-emitter voltage of one reverse blocking semiconductor element and the emitter-collector voltage of the other reverse blocking semiconductor element constituting the bidirectional switch, and the detected voltage value is a predetermined value; And an adjusting means for adjusting the gate voltage value of the reverse blocking semiconductor element to which a voltage is applied in the opposite direction to the reverse blocking semiconductor element exceeding.

上記請求項3の発明においては、前記ゲート電圧値の調整は、逆方向に電圧が印加されている逆阻止型半導体素子について行なうことができ(請求項4の発明)、または、n個直列に接続された双方向スイッチの両端に印加される電圧を検出する第2の検出手段を設け、この第2の検出手段にて検出された電圧の1/nの値と前記検出手段にて検出された電圧値とを比較し、各双方向スイッチの両端に印加される電圧が第2の検出手段にて検出された電圧の1/nの値となるように、前記調整手段によりゲート電圧値を調整することができる(請求項5の発明)。     In the invention of claim 3, the gate voltage value can be adjusted for a reverse blocking semiconductor element to which a voltage is applied in the reverse direction (invention of claim 4), or in n series. There is provided a second detection means for detecting a voltage applied to both ends of the connected bidirectional switch, and a value of 1 / n of the voltage detected by the second detection means and the detection means are detected. And the gate voltage value is adjusted by the adjusting means so that the voltage applied to both ends of each bidirectional switch becomes 1 / n of the voltage detected by the second detecting means. It can be adjusted (invention of claim 5).

この発明によれば、逆阻止IGBTの静特性を利用し、逆方向に電圧が印加されている素子のゲート電圧を調整することで、電圧をバランスさせることができる。また、外部回路の電圧検出手段として抵抗の分圧比を利用するようにしたが、IGBTの直列接続時には、各IGBTに分圧抵抗を接続するのが一般的であるため、これらを利用することができる。さらに、ゲート電源の調整,駆動については電子回路化できるので、装置を小型にすることが可能となる。加えて、この発明は双方向スイッチについても適用できるため、マトリックスコンバータはもちろん一般的な電力変換装置に適用することができ、その効果は大きい。   According to the present invention, the voltage can be balanced by using the static characteristics of the reverse blocking IGBT and adjusting the gate voltage of the element to which the voltage is applied in the reverse direction. In addition, the voltage dividing ratio of the resistor is used as the voltage detecting means of the external circuit. However, since it is common to connect a voltage dividing resistor to each IGBT when the IGBTs are connected in series, these may be used. it can. Furthermore, since adjustment and driving of the gate power supply can be made into an electronic circuit, the apparatus can be miniaturized. In addition, since the present invention can also be applied to a bidirectional switch, it can be applied not only to a matrix converter but also to a general power converter, and the effect is great.

図1はこの発明の第1の実施の形態を示す概要図である。
図示のように、逆方向に耐圧をもつ逆阻止IGBTQ1,Q2,…Qnの両端に電圧検出手段11,12,…1nと、各IGBTを駆動するための可変直流電源Vg1,Vg2,…Vgnと、オン,オフ信号に追従して各IGBTのゲートを充放電させる駆動部21,22,…2nとから構成される。
FIG. 1 is a schematic diagram showing a first embodiment of the present invention.
As shown in the figure, voltage detection means 11, 12,... 1n at both ends of reverse blocking IGBTs Q1, Q2,. , 2n for charging / discharging the gate of each IGBT following the on / off signal.

図2に図1の詳細を示す。電圧検出手段は各IGBTQi(i=1,2,…n)の両端に抵抗Rdi1,Rdi2(i=1,2,…n)を接続して構成される。ゲート駆動回路GDUi(i=1,2,…n)は、IGBTQiに印加される電圧と基準電圧Vrefとを比較するための比較器Cmp、この比較器Cmpの出力に応じてオン,オフするスイッチSgl,Sgsを備え、スイッチSonを閉じているときに、スイッチSglを閉じスイッチSgsを開くと、各IGBTのゲート電圧はVglまで充電され、スイッチSglを開きスイッチSgsを閉じると、ゲート電圧はVgsまで充電される。   FIG. 2 shows details of FIG. The voltage detection means is configured by connecting resistors Rdi1, Rdi2 (i = 1, 2,... N) to both ends of each IGBT Qi (i = 1, 2,... N). The gate drive circuit GDUi (i = 1, 2,... N) includes a comparator Cmp for comparing the voltage applied to the IGBT Qi with the reference voltage Vref, and a switch that is turned on / off according to the output of the comparator Cmp. When the switch Son is closed and the switch Sgl is closed and the switch Sgs is opened, the gate voltage of each IGBT is charged to Vgl. When the switch Sgl is opened and the switch Sgs is closed, the gate voltage is Vgs. It is charged until.

図3は逆阻止IGBTの2直列接続回路を示しており、Q1とQ2の両端に交流電源Vsと負荷Lの直列回路が接続されている。
図4は図3の動作を説明する波形図である。ここで、交流電源Vsを2分した電圧をVs/2として、点線で示す。交流電源Vsが負の半波期間において、逆阻止IGBTが均等に分圧されているとすると、各IGBTQ1,Q2に印加される電圧VCE1,VCE2はVs/2に等しい。
FIG. 3 shows a two-series connection circuit of reverse blocking IGBTs. A series circuit of an AC power source Vs and a load L is connected to both ends of Q1 and Q2.
FIG. 4 is a waveform diagram for explaining the operation of FIG. Here, a voltage obtained by dividing the AC power supply Vs into two is indicated by a dotted line as Vs / 2. Assuming that the reverse blocking IGBT is equally divided during the negative half-wave period of the AC power supply Vs, the voltages VCE1 and VCE2 applied to the IGBTs Q1 and Q2 are equal to Vs / 2.

いま、図4のように、VCE1>VCE2となっていたとすると、各IGBTQ1,Q2に印加される電圧は、各電圧検出手段により図5に示すようにVCEs1,VCEs2として検出される。このVCEs1,VCEs2は電圧検出手段の各抵抗値をRd11,Rd12,Rd21,Rd22として、それぞれ次のようになる。
VCEs1=Rd11・VCE1/(Rd11+Rd12)
VCEs2=Rd21・VCE2/(Rd11+Rd12)
ここで、Rd11/(Rd11+Rd12)=Rd21/(Rd11+Rd12)=k
とすると、各IGBTに印加される電圧VCE1,VCE2に比例する電圧となる。
Assuming that VCE1> VCE2 as shown in FIG. 4, the voltages applied to the IGBTs Q1 and Q2 are detected as VCEs1 and VCEs2 by the voltage detection means as shown in FIG. The VCEs1 and VCEs2 are as follows, assuming that the resistance values of the voltage detecting means are Rd11, Rd12, Rd21, and Rd22.
VCEs1 = Rd11 · VCE1 / (Rd11 + Rd12)
VCEs2 = Rd21 · VCE2 / (Rd11 + Rd12)
Here, Rd11 / (Rd11 + Rd12) = Rd21 / (Rd11 + Rd12) = k
Then, the voltages are proportional to the voltages VCE1 and VCE2 applied to each IGBT.

今、交流電源Vsが負の半波期間において、スイッチSonを閉じ、各IGBTのゲート電圧をVglまで充電していたとする。次に、VCEs1が基準電圧Vrefを越えると、比較器Cmpの出力によりスイッチSglを開きスイッチSgsを閉じる。今Vgl>Vgsとすると、IGBTQ1のゲート電圧がVglからVgsに変化する。すなわち、VglからVgsまで放電されることとなる。IGBTQ1のゲート電圧がVgsまで放電されると、図7に示すCE間の漏れ抵抗Rce1が小さくなり、漏れ電流が図8のように大きくなる。その結果、図6のようにVCE1の電圧は減少し、VCE2の電圧は上昇して両者の電圧はバランスする方向となる。以上では、ゲート駆動回路の電源Vgl,Vgsの2つの電圧値として制御するようにしたが、スイッチング電源等により電圧を線形的に調整するようにしても良いのは言うまでもない。
また、交流電源Vsが正の半波期間、すなわちIGBTQ1が順方向の場合でスイッチングするようなときは、図20で説明した図9のような外部回路を用いることで、図10(a),(b)のように電圧分担の調整を行なうことができる。
Assume that the switch Son is closed and the gate voltage of each IGBT is charged to Vgl during the negative half-wave period of the AC power supply Vs. Next, when VCEs1 exceeds the reference voltage Vref, the switch Sgl is opened and the switch Sgs is closed by the output of the comparator Cmp. Assuming that Vgl> Vgs, the gate voltage of the IGBT Q1 changes from Vgl to Vgs. That is, the discharge is performed from Vgl to Vgs. When the gate voltage of the IGBT Q1 is discharged to Vgs, the leakage resistance Rce1 between CEs shown in FIG. 7 decreases, and the leakage current increases as shown in FIG. As a result, as shown in FIG. 6, the voltage of VCE1 decreases, the voltage of VCE2 increases, and both voltages are balanced. In the above description, the voltage is controlled as the two voltage values of the power sources Vgl and Vgs of the gate drive circuit, but it goes without saying that the voltage may be linearly adjusted by a switching power source or the like.
When the AC power source Vs is switched in the positive half-wave period, that is, when the IGBT Q1 is in the forward direction, the external circuit as shown in FIG. 9 described with reference to FIG. The voltage sharing can be adjusted as shown in (b).

図11はこの発明の第2の実施の形態を示す概要図である。
これは、図1に示すIGBTQ1〜Qnに対し、それぞれ逆並列に逆阻止IGBTを接続した点が特徴である。すなわち、各IGBTQif,IGBTQirを互いに逆並列に接続した双方向スイッチQsiをn個直列に接続する。各IGBTQif,IGBTQirに接続される電源および駆動部は、図1〜図3に示されるものと同じである。また、双方向スイッチQsiをn個直列に接続した両端には交流電源Vsと負荷Lが接続されている。
FIG. 11 is a schematic diagram showing a second embodiment of the present invention.
This is characterized in that reverse blocking IGBTs are connected in antiparallel to the IGBTs Q1 to Qn shown in FIG. That is, n bidirectional switches Qsi in which IGBTQif and IGBTQir are connected in antiparallel to each other are connected in series. The power source and the drive unit connected to each IGBT Qif and IGBT Qir are the same as those shown in FIGS. An AC power supply Vs and a load L are connected to both ends of the n bidirectional switches Qsi connected in series.

図11の動作について、図12,13を参照して説明する。
双方向スイッチQsiをn個直列に接続した両端には、図12のような交流電源Vsが印加される。交流電源Vsは正負の値をとり、例えばVsが正の期間にはQifをオン,オフさせ、Vsが負の期間にはQirをオン,オフさせる。ここで、Q1f,Q2fをスイッチングした例を図13に示す。
The operation of FIG. 11 will be described with reference to FIGS.
An AC power supply Vs as shown in FIG. 12 is applied to both ends of n bidirectional switches Qsi connected in series. The AC power supply Vs takes positive and negative values. For example, Qif is turned on and off when Vs is positive, and Qir is turned on and off when Vs is negative. Here, FIG. 13 shows an example in which Q1f and Q2f are switched.

図12の正の半波、すなわち一点鎖線の期間中に、図13(a)のようにQ1f,Q2fがターンオフする。このとき、電圧アンバランスが発生し、VCE1がVrefを越えると、Q1rのゲート電圧をオフさせ、ゲート電圧を下降させる。Q1rのゲート電圧を下降させると、Q1rの漏れ電流分が増加するため、図1〜図8の場合と同じく図13(a)に示すように、電圧バランスを図ることができる。また、Vsが負の期間においても同様に、Q1r,Q2rのターンオフ時に電圧アンバランスが発生し、VCE1がVrefを越えると、Q1fのゲート電圧を上昇させることで、図13(b)に示すように電圧をバランスさせることができる。図11〜13ではVCE1がVrefを越えた例で説明したが、VCE2の場合も同様であり、さらには、n個直列に接続した場合でも上記と同様にして電圧バランスを図ることができる。もちろん、ゲート電圧についても線形的に調整しても同様の調整を行なうことができる。   Q1f and Q2f are turned off as shown in FIG. 13A during the positive half-wave of FIG. At this time, when voltage imbalance occurs and VCE1 exceeds Vref, the gate voltage of Q1r is turned off and the gate voltage is lowered. When the gate voltage of Q1r is lowered, the amount of leakage current of Q1r increases, so that the voltage balance can be achieved as shown in FIG. 13A as in the case of FIGS. Similarly, even when Vs is negative, a voltage imbalance occurs when Q1r and Q2r are turned off. When VCE1 exceeds Vref, the gate voltage of Q1f is increased, as shown in FIG. 13B. The voltage can be balanced. 11 to 13, an example in which VCE1 exceeds Vref has been described. However, the same applies to VCE2, and even when n pieces are connected in series, voltage balance can be achieved in the same manner as described above. Of course, the same adjustment can be performed by linearly adjusting the gate voltage.

図14はこの発明の第3の実施の形態を示す概要図、図15は図14の動作モードの説明図である。
図14は図11に示すものに対し、直列接続された全双方向スイッチQs1〜Qsnの両端の電圧を検出する全素子電圧検出回路4を設けた点が特徴である。
双方向スイッチQsiがn個直列に接続された場合、電圧が各IGBTで均等に分圧されれば、各IGBTの電圧は次のようになる。
VCE1=VCE2=…=VCEn⇒Vref
したがって、この電圧を基準電圧Vrefとしてゲート電圧を調整する。
FIG. 14 is a schematic diagram showing a third embodiment of the present invention, and FIG. 15 is an explanatory diagram of the operation mode of FIG.
FIG. 14 is different from that shown in FIG. 11 in that an all-element voltage detection circuit 4 for detecting voltages at both ends of all bidirectional switches Qs1 to Qsn connected in series is provided.
When n bidirectional switches Qsi are connected in series, the voltage of each IGBT is as follows if the voltage is equally divided by each IGBT.
VCE1 = VCE2 = ... = VCEn => Vref
Therefore, the gate voltage is adjusted using this voltage as the reference voltage Vref.

図14の具体例を図16に示し、その動作モードを図17に、また、動作例を図18に示す。
図16において、全素子電圧検出回路4を抵抗Ra1,Ra2から構成し、抵抗Ra1,Ra2の接続点の電位を絶縁回路ISO−AMPで検出し、その出力を比較器Cmpで各素子の検出電圧値と比較する。図17に示す交流電源Vsが負の期間において、図18のようにQ1r,Q2rをオフさせる。このとき、例えばVCE1がVrefより高ければ、Vg11を上昇させQ1fの漏れ電流を減少させることで、図18のように電圧をバランスさせることができる。
図11の場合と比べて、全期間において各素子の電圧をバランスさせることが可能で、スイッチング時に発生する素子発生損失による熱バランスも図ることができる。
A specific example of FIG. 14 is shown in FIG. 16, its operation mode is shown in FIG. 17, and an operation example is shown in FIG.
In FIG. 16, the all-element voltage detection circuit 4 is composed of resistors Ra1 and Ra2, the potential at the connection point of the resistors Ra1 and Ra2 is detected by the insulation circuit ISO-AMP, and the output is detected by the comparator Cmp. Compare with the value. In the period in which the AC power supply Vs shown in FIG. 17 is negative, Q1r and Q2r are turned off as shown in FIG. At this time, for example, if VCE1 is higher than Vref, the voltage can be balanced as shown in FIG. 18 by increasing Vg11 and decreasing the leakage current of Q1f.
Compared to the case of FIG. 11, the voltage of each element can be balanced over the entire period, and the heat balance due to the element generation loss generated during switching can also be achieved.

この発明の第1の実施の形態を示す概要図Schematic diagram showing the first embodiment of the present invention 図1の詳細構成図Detailed configuration diagram of FIG. 図2の2直列接続の例を示す構成図The block diagram which shows the example of 2 series connection of FIG. 図3における動作モードの説明図Explanatory drawing of the operation mode in FIG. 図3の動作を説明する回路図Circuit diagram for explaining the operation of FIG. 図3の動作を説明する波形図Waveform diagram explaining the operation of FIG. 漏れ電流経路の説明図Illustration of leakage current path ゲート電圧の大小によって異なる漏れ電流の説明図Illustration of leakage current that varies depending on the gate voltage n直列接続の例を示す概要図Schematic diagram showing an example of n series connection 図9における正の半波時の動作説明図Operation explanatory diagram at the time of positive half wave in FIG. この発明の第2の実施の形態を示す概要図Schematic diagram showing a second embodiment of the present invention 図11の動作モードの説明図Explanatory drawing of the operation mode of FIG. 図11の動作説明図FIG. 11 is an operation explanatory diagram. この発明の第3の実施の形態を示す概要図Schematic diagram showing a third embodiment of the present invention 図14の動作モードの説明図Explanatory drawing of the operation mode of FIG. 図14の詳細構成図Detailed configuration diagram of FIG. 図16の動作モードの説明図Explanatory drawing of the operation mode of FIG. 図16の動作説明図Operation explanatory diagram of FIG. 一般的な電力変換装置を示す回路図Circuit diagram showing a typical power converter 図19における電圧バランス回路の例を示す概要図FIG. 19 is a schematic diagram showing an example of a voltage balance circuit 図20の電圧バランス回路の作用説明図FIG. 20 is a diagram illustrating the operation of the voltage balance circuit. 逆阻止型IGBTの特性説明図Characteristic illustration of reverse blocking IGBT 逆阻止型IGBTの逆並列接続図Reverse parallel connection diagram of reverse blocking IGBT 双方向スイッチを用いた交流−交流変換装置の概略構成図Schematic configuration diagram of an AC-AC converter using a bidirectional switch

符号の説明Explanation of symbols

11〜1n,4…電圧検出手段、21〜2n,31〜3n…駆動部、GDU1〜GDUn…ゲート駆動回路、Q1〜Qn…IGBT(絶縁ゲート型バイポーラトランジスタ)。

DESCRIPTION OF SYMBOLS 11-1n, 4 ... Voltage detection means, 21-2n, 31-3n ... Drive part, GDU1-GDUn ... Gate drive circuit, Q1-Qn ... IGBT (insulated gate type bipolar transistor).

Claims (5)

コレクタ−エミッタ間に印加される順方向の電圧はゲートに順電圧または逆電圧を与えることで制御し、コレクタ−エミッタ間に印加される逆方向の電圧は阻止する機能を有する逆阻止型半導体素子を、アーム当たり複数個直列に接続して構成される電力変換装置において、
前記逆阻止型半導体素子のそれぞれにコレクタ−エミッタ間の電圧を検出する検出手段と、ゲート電圧値を調整する調整手段とを設け、逆阻止型半導体素子に逆方向に電圧が印加されているときは、前記検出手段にて検出された電圧値に応じ、前記調整手段によりゲート電圧値を調整することを特徴とする電力変換装置。
A reverse blocking semiconductor element having a function of controlling a forward voltage applied between the collector and the emitter by applying a forward voltage or a reverse voltage to the gate and blocking a reverse voltage applied between the collector and the emitter. In a power converter configured by connecting a plurality of units in series per arm,
When each of the reverse blocking semiconductor elements is provided with a detecting means for detecting a collector-emitter voltage and an adjusting means for adjusting a gate voltage value, the voltage is applied to the reverse blocking semiconductor element in the reverse direction. Is a power converter that adjusts the gate voltage value by the adjusting means according to the voltage value detected by the detecting means.
前記逆阻止型半導体素子に順方向に電圧が印加されているときは、前記半導体素子に並列に接続された可変抵抗の抵抗値を前記調整手段を介して調整することを特徴とする請求項1に記載の電力変換装置。 2. The resistance value of a variable resistor connected in parallel to the semiconductor element is adjusted via the adjusting means when a voltage is applied in the forward direction to the reverse blocking semiconductor element. The power converter device described in 1. コレクタ−エミッタ間に印加される順方向の電圧はゲートに順電圧または逆電圧を与えることで制御し、コレクタ−エミッタ間に印加される逆方向の電圧は阻止する機能を有する逆阻止型半導体素子を逆並列に接続してなる双方向スイッチを、アーム当たりn(2以上の自然数)個直列に接続して構成される電力変換装置において、
前記双方向スイッチを構成する一方の逆阻止型半導体素子のコレクタ−エミッタ間電圧と他方の逆阻止型半導体素子のエミッタ−コレクタ間電圧をそれぞれ検出する検出手段と、検出された電圧値が所定値を超えた逆阻止型半導体素子とは逆方向に電圧が印加されている方の逆阻止型半導体素子のゲート電圧値を調整する調整手段とを設けたことを特徴とする電力変換装置。
A reverse blocking semiconductor element having a function of controlling a forward voltage applied between the collector and the emitter by applying a forward voltage or a reverse voltage to the gate and blocking a reverse voltage applied between the collector and the emitter. In a power converter configured to connect n (two or more natural numbers) series switches connected in reverse parallel to each other in series,
Detecting means for detecting the collector-emitter voltage of one reverse blocking semiconductor element and the emitter-collector voltage of the other reverse blocking semiconductor element constituting the bidirectional switch, and the detected voltage value is a predetermined value; And an adjustment means for adjusting a gate voltage value of the reverse blocking semiconductor element to which a voltage is applied in a direction opposite to that of the reverse blocking semiconductor element exceeding the above.
前記ゲート電圧値の調整は、逆方向に電圧が印加されている逆阻止型半導体素子について行なうことを特徴とする請求項3に記載の電力変換装置。   4. The power conversion device according to claim 3, wherein the adjustment of the gate voltage value is performed for a reverse blocking semiconductor element to which a voltage is applied in a reverse direction. n個直列接続された双方向スイッチの両端に印加される電圧を検出する第2の検出手段を設け、この第2の検出手段にて検出された電圧の1/nの値と前記検出手段にて検出された電圧値とを比較し、各双方向スイッチに印加される電圧が第2の検出手段にて検出された電圧の1/nの値となるように、前記調整手段によりゲート電圧値を調整することを特徴とする請求項3に記載の電力変換装置。   Second detection means for detecting a voltage applied to both ends of n bidirectional switches connected in series is provided, and a value of 1 / n of the voltage detected by the second detection means and the detection means are provided. And the voltage value applied to each of the bidirectional switches is compared with the voltage value detected by the second detecting means so that the voltage value is 1 / n of the voltage detected by the second detecting means. The power conversion device according to claim 3, wherein the power conversion device is adjusted.
JP2003424472A 2003-12-22 2003-12-22 Power converter Expired - Fee Related JP4419559B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003424472A JP4419559B2 (en) 2003-12-22 2003-12-22 Power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003424472A JP4419559B2 (en) 2003-12-22 2003-12-22 Power converter

Publications (2)

Publication Number Publication Date
JP2005185039A JP2005185039A (en) 2005-07-07
JP4419559B2 true JP4419559B2 (en) 2010-02-24

Family

ID=34784653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003424472A Expired - Fee Related JP4419559B2 (en) 2003-12-22 2003-12-22 Power converter

Country Status (1)

Country Link
JP (1) JP4419559B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007028860A (en) * 2005-07-21 2007-02-01 Hitachi Ltd Power-converting device and rolling stock equipped with the same
US7508096B1 (en) * 2007-09-20 2009-03-24 General Electric Company Switching circuit apparatus having a series conduction path for servicing a load and switching method
JP5927860B2 (en) * 2011-11-21 2016-06-01 株式会社明電舎 Drive device for semiconductor switching element
CN102931822B (en) * 2012-11-16 2014-04-16 清华大学 Main circuit pulse based active voltage-equalizing device for high voltage IGBTs (Insulated Gate Bipolar Transistors) in series connection
CN111146950B (en) * 2020-01-16 2024-11-08 同济大学 Single-drive power tube serial-type seabed high-voltage direct-current converter

Also Published As

Publication number Publication date
JP2005185039A (en) 2005-07-07

Similar Documents

Publication Publication Date Title
JP5732494B2 (en) Power converter
JP6208803B2 (en) Modular multilevel converter and voltage balancing control method for modular multilevel converter
WO2012020664A1 (en) Indirect matrix converter
US20190052187A1 (en) Dual submodule for a modular multilevel converter and modular multilevel converter including the same
JP2011135758A (en) Rectifier circuit
CN102075105A (en) Power conversion equipment
WO2016152989A1 (en) Power conversion apparatus
JP2012182974A (en) Five-level power conversion apparatus
JP2009159662A (en) Control circuit for power semiconductor devices
US20030042939A1 (en) Semiconductor power converting apparatus
JP4419559B2 (en) Power converter
US10770962B2 (en) Converter cell comprising an energy converter in parallel to a clamp inductor
Taib et al. Novel low-cost self-powered supply solution of bidirectional switch gate driver for matrix converters
US9397584B2 (en) Multi-level converter apparatus and methods using clamped node bias
JP2018170832A (en) Power conversion device
JP6666636B2 (en) Power converter
Lee et al. Active dv/dt control with turn-off gate resistance modulation for voltage balancing of series connected SiC MOSFETs
JP2020014045A (en) Bidirectional switch circuit
JP6111726B2 (en) Control method of multi-level power conversion circuit
CN108604877B (en) Sub-module of chain-link converter
JP4487604B2 (en) Power converter
JP7304322B2 (en) power converter
JPS60235522A (en) Semiconductor switching device
JP2013240161A (en) Power conversion device
JP4635587B2 (en) Power converter

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060615

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090421

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090804

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090904

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091110

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091123

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131211

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees