JP4417935B2 - Information processing apparatus, information processing method, and information processing program for communicating with outside via network - Google Patents

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing program that communicate with the outside via a network.

  Conventionally, message exchange communication is used in PC clusters and parallel computers. Particularly in parallel applications, communication using a message exchange library represented by MPI (Message Passing Interface) is frequently used.

  Conventionally, as a network interface for a PC cluster, Mellanox Technologies Infiniband HCA, Mycomy Myline, Quadrics QsNET II, etc. are used in combination with MPI in many usage forms (for example, “Non-patent Documents”). 1 ”).

  In Japan, an example in which MPI is mounted on RHiNET-2 has been reported as an example of a trial production level (see, for example, “Non-Patent Document 2”). Moreover, what mounted MPI on DIMMnet-2 with which a memory slot is mounted | worn has been reported (for example, refer to "nonpatent literature 3").

  These are structures in which data received from the network side is temporarily stored in a memory formed on the network interface board or in a buffer that is reserved in the main memory on the host computer and reserved in a non-swap-out area It has become.

  In a parallel system, there is no guarantee that the receiving side will activate the corresponding receiving function before the message arrives. Also, there is no guarantee that messages arriving from a plurality of partners over the network will arrive at the receiving side in the arrival order desired by the receiving side. For this reason, in a message exchange library such as the above-mentioned MPI (Message Passing Interface), when a reception function is executed, it is necessary to first search for a necessary message from the above-mentioned buffer. Then, messages that do not match are found in another buffer until a message that matches the reception key is found.

  A FIFO operation is performed on DIMMnet-2 by a hardware-controlled pointer called IPUSH mechanism. Also, the data is written in the reception buffer classified by the transmission source group. With this operation, firmware intervention on the receiving side is prevented. In addition, the MPI communication delay is shortened by improving the buffer search success probability (see, for example, “Non-Patent Document 4”).

“Performance comparisons of MPI implementations over InfiniBand, Myrinet and Quadrics”, IEEE Proceedings of SC'03, (November 2003) “Performance evaluation of RHiNET-2 network for distributed parallel processing”, Advanced Computing Infrastructure System Symposium SACSSIS 2003, ISSN 1344-0640 (May 2003) "Implementation of communication library MPI-2 in DIMMnet-2", IPSJ 0919-6072 (February 2006) "Implementation of packet reception mechanism to support message passing model", IPSJ Computer Architecture Study Group Report ISSN 0919-6072 (November 2005)

  However, the buffer search operation described above involves copying between large memories by software. Therefore, unless a desired message arrives in the order desired by the receiving side, the delay time required for message reception will increase.

  For example, when the memory capacity on the network interface board is small, such as Myrinet, there is not enough capacity to mount the entire MPI reception buffer there. For this reason, it is necessary to promptly discharge a message flowing from the network to the main memory of the host via an input / output bus such as a PCI bus. This is because if the message stays on the network interface board, the network side is clogged, causing congestion.

  Therefore, the message is always carried to the MPI reception buffer provided in the main memory of the host by repeating DMA several times via the PCI bus or the like. For this reason, there exists a problem that communication delay time will become large.

  In addition, when the memory on the network interface board is DRAM-based and has a capacity as large as the main memory of the host as in DIMMnet-2, data to be remotely accessed from the network side is arranged in the memory on the network interface board. be able to. Further, the entire MPI reception buffer can be arranged in a memory on the network interface board.

  For this reason, when the receiving side does not activate the corresponding receiving function before the message arrives, the received message can be stored in the MPI buffer provided on the memory on the network interface board. However, the memory on the network interface board takes longer to access from the host than the main memory of the host. For this reason, it takes time to search for a message that matches the reception key. Therefore, there is a problem that the MPI reception delay is not necessarily shortened.

  The present invention has been made in view of the above, and includes an information processing apparatus, an information processing method, and an information processing program as a network interface or a host apparatus with a short communication delay when realizing message exchange communication using a network interface. The purpose is to provide.

In order to solve the above-described problems and achieve the object, the present invention provides an information processing apparatus that communicates with an external device via a network, and that receives data from the external device via the network. And control means for performing processing in a layer lower than the transport layer of the received message, and the received message after the processing, the data to be used first in the reception processing in the host device that is the transmission destination of the received message A dividing unit that divides the received first message into a second message that includes data to be used after the first message in the reception process; and a first unit that stores the first message obtained by the dividing unit. A memory and a memory having an access delay larger than that of the first memory, the corresponding first A second memory for storing a distinguishably the second message message, and receiving a message request receiving means for receiving an incoming message request to the received message from the host device, when receiving the received message request, Receiving a first message transmitting means for burst-transferring the first message of the received message stored in the first memory to the host device; and a second message request for requesting the second message from the host device. A second message request receiving unit; and a second message transmitting unit configured to transmit the second message stored in the second memory to the host device when the second message request is received. Features.

According to another aspect of the present invention, there is provided an information processing apparatus that receives a message from outside via a network interface, and provides the network interface with a message processed in a layer lower than a transport layer. and receiving a message requesting means for requesting, said burst-transferred from the network interface, a message receiving means for receiving the message stored in the first memory of the network interface, receiving a message the received message received by the receiving means On the basis of the control information included in the check means for checking whether or not to receive the received message, and when the check means determines that the received message is received, the actual data size of the received message and the In the received message Data size comparing means for comparing the received message data size, and when the actual data size of the received message is larger than the data size described in the received message, A second message requesting means for requesting provision of two messages; and a second message held in a second memory, which is a memory of the network interface and has a larger access delay than the first memory, from the network interface. And a second message receiving means for receiving.

According to another aspect of the present invention, there is provided an information processing method for communicating with the outside via a network, the data receiving step for receiving a received message from an external device via the network, and the transport of the received message A control step for performing processing in a layer lower than the layer , a first message including data to be used first in reception processing in a host device that is a transmission destination of the reception message, and the reception A division step of dividing the second message including data to be used after the first message in the processing; a first storage step of storing the first message obtained in the division step in a first memory; A memory having a larger access delay than the first memory, A second storage step of storing distinguishably the second message a first message to the second memory, and receiving a message request receiving step of receiving the incoming message request to the received message from the host device, said received message When a request is received, a first message transmission step of burst transferring the first message of the received message stored in the first memory to the host device, and requesting the second message from the host device A second message request receiving step for receiving a second message request; and a second message transmission for transmitting the second message stored in the second memory to the host device when the second message request is received. And a step .

According to another aspect of the present invention, there is provided an information processing method for receiving a message from the outside through a network interface, and providing the network interface with a message processed in a layer lower than a transport layer. and receiving a message requesting step of requesting, from said network interface is burst transfer, and the message receiving step of receiving the message stored in the first memory of the network interface, the received message received at the receiving message receiving step A check step for checking whether or not to receive the received message based on the control information included in the check information, and when it is determined that the received message is received in the check step, A data size comparison step for comparing the data size of the received message described in the received message and the actual data size of the received message is larger than the data size described in the received message And a second message requesting step for requesting provision of a second message following the received message, and a memory of the network interface, which is held in a second memory having a larger access delay than the first memory. And a second message receiving step of receiving a second message from the network interface.

According to another aspect of the present invention, there is provided an information processing program for causing a computer to execute information processing that communicates with an external device via a network, and for receiving data received from an external device via the network. A control step for performing processing in a layer lower than the transport layer of the received message, and data to be used first in reception processing in the host device that is the transmission destination of the received message after the processing. A first message including the first message including the data and a second message including data to be used after the first message in the reception process; and the first message obtained in the dividing step is a first memory. Compared to the first storage step and the first memory A large memory access delay, a second storing step of storing the corresponding first message identifiably the second message in the second memory, the received message requests for requesting the received message from the host device A received message request receiving step for receiving, and a first message transmitting step for burst-transferring the first message of the received message stored in the first memory to the host device when the received message request is received; A second message request receiving step for receiving a second message request for requesting the second message from the host device; and the second message request stored in the second memory when the second message request is received. A second message transmission step of transmitting a message to the host device; An information processing program to be executed by a serial computer.

According to another aspect of the present invention, there is provided an information processing program for causing a computer to execute information processing for receiving a message from the outside via a network interface, wherein the network interface is provided in a layer below the transport layer. and receiving a message requesting step of requesting the provision of processing is performed message, and the message receiving step of said burst-transferred from the network interface, to receive the message stored in the first memory of the network interface, wherein Based on the control information included in the received message received in the received message receiving step, a test step for checking whether or not the received message is received, and determining that the received message is received in the test step A data size comparison step for comparing the actual data size of the received message with the data size of the received message described in the received message, and the actual data size of the received message in the received message A second message requesting step for requesting provision of a second message following the received message when the data size is larger than the described data size; and a memory of the network interface, which is accessed compared to the first memory An information processing program for causing the computer to execute a second message receiving step of receiving a second message held in a second memory having a large delay from the network interface.

According to the information processing apparatus according to the present invention, an effect that can be provided to the host device at a relatively low delay data to be utilized at the beginning in the host device.

  Embodiments of an information processing apparatus, an information processing method, and an information processing program according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  FIG. 1 is a diagram illustrating an overall configuration of an information processing system 1 including an information processing apparatus 10 according to an embodiment. The information processing system 1 includes a host device 20 in addition to the information processing device 10 as a network interface (NIC). The information processing apparatus 10 receives data from outside via a network. Then, the received data is transferred to the host device 20 in response to a request from the host device 20.

  The information processing apparatus 10 includes an LSI 100 and a high delay memory 200. The high delay memory 200 is a DRAM-based memory. The high delay memory 200 is installed outside the LSI on the NIC.

  As another example, the high delay memory 200 may be provided inside the LSI. The high delay memory 200 may be provided outside the NIC. Further, it may be formed on the main memory of the host device 20. Further, the high delay memory 200 may have a configuration other than a DRAM base.

  The LSI 100 includes a network control unit 110, a division control unit 120, a setting unit 130, a low delay memory control unit 140, a high delay memory control unit 150, a low delay memory 160, a host interface unit 170, a prefetch buffer. 180 and a second half prefetch control unit 190.

  The network control unit 110 performs processing in layers below the transport layer in the OSI reference model such as flow control and retransmission control. The network control unit 110 receives a message from the network. That is, the network control unit 110 according to the present embodiment functions as a data receiving unit. Then, the received message, that is, an error in the received message is detected and corrected, and the received message with no error is passed to the division control unit 120.

  The division control unit 120 includes a division position register 122 and a size position register 124. The division position register 122 holds division position information. The division position information is information indicating a division position when the received message is divided. Specifically, the division position information is information indicating the number of bytes from the beginning. The size position register 124 holds size position information. The size position information is information indicating a position in the received message where size information indicating the data size of the received message is stored.

  Using the division position information held in the division position register 122 and the size position information held in the size position register 124, the division control unit 120 appropriately divides the received message into the first half message and the second half message. The division control unit 120 according to the present embodiment functions as a division unit, a division control unit, a data size specifying unit, a first data size comparison unit, and an entry size holding unit.

  The division control unit 120 further passes the first half message to the low delay memory control unit 140 and passes the second half message to the high delay memory control unit 150. A received message with a relatively small capacity, that is, a small received message is passed to the low-delay memory control unit 140.

  Here, the first half message includes data that the host device 20 should use first in the reception process. Here, the reception process is a process performed when a received message is acquired from the information processing apparatus 10. For example, in MPI, it is first determined whether or not the key specified by the reception function matches the envelope in the reception process. That is, the envelope is information that is first used in the reception process. The first half message contains this envelope as data to be used first. The latter half message is a part of the received message other than the first half message. Note that the first half message and the second half message according to the present embodiment correspond to the first message and the second message, respectively.

  The setting unit 130 sets the division position information in the division position register 122 according to an instruction from the user or the like. Thereby, a division position can be adjusted. Also, the size position information is set in the size position register 124. Thereby, the format of the receivable message can be flexibly changed. That is, messages in various formats can be processed. That is, the setting unit 130 functions as a division position information setting unit and a size position information setting unit.

  The division position register 122, the size position register 124, and the setting unit 130 are not necessarily indispensable configurations. As another example, appropriate fixed values may be set in advance as the division position information and the size position information.

  The low delay memory control unit 140 controls the low delay memory 160. Specifically, the entire first half message or small received message received from the division control unit 120 is stored in the low delay memory 160. Also, the data stored in the low delay memory 160 is read and passed to the host interface unit 170. The low-latency memory control unit 140 according to the present embodiment functions as first half data extraction means.

  By storing the first half message and the small received message in the low delay memory 160 in this way, the first half message and the small received message can be provided to the host device 20 with a smaller delay compared to the case of storing in the high delay memory 200. it can.

  The high delay memory control unit 150 controls the high delay memory 200. Specifically, the latter half message received from the division control unit 120 is stored in the high delay memory 200. Further, the data stored in the high delay memory 200 is read and passed to the host interface unit 170 or the prefetch buffer 180. The high delay memory control unit 150 according to the present embodiment functions as a second message extraction unit.

  FIG. 2 is a diagram showing a data configuration of the low delay memory 160 and the high delay memory 200. The low delay memory 160 is typically a high-speed SRAM built in an LSI. Note that the low delay memory 160 and the high delay memory 200 according to the present embodiment function as a first memory and a second memory, respectively.

  The low delay memory 160 has a plurality of entries. Each entry stores the entire first half message or received message. The first half message is stored in the same entry together with the pointer. Here, the pointer is information indicating the address of the second half message following the first half message.

  A buffer composed of a plurality of entries in the low delay memory 160 is managed in a ring shape by the low delay memory control unit 140. That is, the plurality of entries is a ring buffer that functions as a first-in first-out buffer.

  The process of writing a received message or the like in the ring buffer can be realized by hardware by using an IPUSH mechanism, for example. The IPUSH mechanism is described in Non-Patent Document 4.

  The data size of each entry is predetermined. For example, the data size of the entry is 32 bytes. The data size of the entry is determined according to the CPU line size of the host device 20. From the viewpoint of sending data to the host device 20 as soon as possible, it is desirable to store as much data as possible in the low-latency memory 160. However, when the data size of each entry is increased, there is a problem with free space. It is desirable that the execution performance optimum point associated with such a trade-off be the data size of the entry.

  In addition, it is desirable that the data size always includes control information such as an envelope. Furthermore, it is desirable that the data size is such that the entire small received message having a relatively small capacity such as a message used for control or the like can be stored. As a result, at the same time when the entry including the envelope is transferred to the host device 20, the data portion of the small reception message is also transferred to the host device 20.

  Such a small reception message is often data that requires a short delay time. Even when the information processing apparatus 10 receives such a small reception message after receiving a longer message, the host apparatus 20 often requests the small reception message first. As described above, the small received message can be transferred with low delay by storing it in the low delay memory 160.

  The data size of the pointer is also predetermined. For example, 4 bytes. In this case, the data size of the first half message stored in each entry is the remaining data size obtained by subtracting the pointer data size of 4 bytes from the entry data size of 32 bytes, that is, 28 bytes. Therefore, the division position register 122 stores division position information indicating 28 bytes from the beginning as the division position. The user can set the division position information via the setting unit 130 in accordance with the data size of the first half message that can be stored in the entry of the low delay memory 160 determined as described above.

  In the small received message, the entire received message is stored in the entry. In this case, there is no need to store a pointer. Therefore, as in the message B2 shown in FIG. 2, if the data size of the entry is 32 bytes or less, even data having a data size larger than 28 bytes of the first half message can be stored.

  The high delay memory 200 is a large capacity and high delay memory compared to the low delay memory 160. The high delay memory 200 stores data that could not be stored in the low delay memory 160. Specifically, the latter half message is stored among the received messages. The high delay memory 200 has a FIFO structure, and stores the acquired second half messages in order.

  For example, it is difficult to install the entire MPI system buffer in the LSI 100 in terms of capacity. However, the low-delay memory 160 does not necessarily have to be built in an LSI. Therefore, in the information processing system 1, as described above, the two types of memories having different capacities and delays, the low delay memory 160 and the high delay memory 200, are used properly from the viewpoint of speeding up message exchange.

  The description returns to FIG. 1 again. The prefetch buffer 180 acquires the latter half message from the high delay memory 200 via the high delay memory control unit 150 and stores it. Further, the second half message is passed to the host interface unit 170. The latter half message is transferred to the host interface unit 170 and then deleted from the prefetch buffer 180.

  The prefetch buffer 180 is a kind of cache using an address as a key. If there is an empty line, data is stored in the empty line. If there is no empty line, select the line with an appropriate algorithm and overwrite it with new data. The prefetch buffer 180 according to the present embodiment functions as a third memory.

  As another example, if there is no space for writing new data in the prefetch buffer 180, it may not be written.

  The host interface unit 170 passes the received message stored in the low delay memory 160, the high delay memory 200, or the prefetch buffer 180 to the host device 20 in response to a request from the host device 20. The host interface unit 170 according to the present embodiment functions as a received message request receiving unit, a first message transmitting unit, a second message request receiving unit, and a second message transmitting unit.

  When the low-latency memory control unit 140 reads data from the low-delay memory 160, the second half prefetch control unit 190 detects the presence or absence of a corresponding pointer by the snoop function. If there is a pointer, it is passed to the high-delay memory control unit 150. The high delay memory control unit 150 reads the latter half message specified by the pointer. The high delay memory control unit 150 according to the present embodiment functions as a second half data extraction unit.

  FIG. 3 is a block diagram illustrating a functional configuration of the host device 20 as the information processing apparatus. The host device 20 includes a received message request unit 201, a second half message request unit 202, a cache memory 204, and a control information management unit 206.

  If the data at a predetermined address does not exist in the cache memory 204, the received message request unit 201 requests the information processing apparatus 10 for the received message by specifying the address. The small received message or the first half message is acquired from the information processing apparatus 10 and stored in the cache memory 204. The received message request unit 201 acquires the small received message or the first half message with the cache line size. The second half message request unit 202 requests the information processing apparatus 10 for the second half message. Then, the latter half message is acquired from the information processing apparatus 10. The received message request unit 201 according to the present embodiment functions as a received message request unit and a message receiving unit.

  The control information management unit 206 extracts control information included in the small reception message or the first half message acquired by the reception message request unit 201, that is, the envelope. Then, it is confirmed that it matches the key specified by the reception function. Thus, it is checked whether or not this message is received.

  When the data acquired by the received message request unit 201 is the first half message, the control information management unit 206 instructs the second message request unit 202 to request the second half message. Whether or not the acquired data is the first half message is determined by whether or not the data size indicated by the size information stored in the first half message is larger than the data size of the first half message. The control information management unit 206 according to the present embodiment functions as an inspection unit and a data size comparison unit.

  The second half message request unit 202 requests the information processing apparatus 10 for the second half message. Then, the latter half message is acquired from the information processing apparatus 10. The latter half message request unit 202 according to the present embodiment functions as a second message request unit and a second message reception unit.

  The host device 20 is a cache-based system. Therefore, the first-half message and the small reception message stored in the low-delay memory 160 are burst transferred to the host device 20 due to a cache miss hit of the host device 20 or an access accompanying a prefetch instruction. This enables transfer with low delay and high bandwidth.

  For example, assume that the data size of the entry in the low-latency memory 160 is 32 bytes. Further, assume that the cache line size of the cache memory 204 is 128 bytes. In this case, in the refill operation associated with a one-line cache miss in the host device 20, the first half message or the small reception message stored in the four entries is transferred to the host device 20.

  For example, it is assumed that four first half messages or small received messages are stored in the low delay memory 160 as shown in FIG. At this time, the delay time is shorter than in the case where the preceding three first half messages or small received messages are accessed one by one in order to receive the received message A2 stored fourth by the access at the cache line size. The received message A2 can be received.

  After the data stored in the cache memory 204 is used, the cache line corresponding to the used data in the cache memory 204, that is, the cache line corresponding to the address corresponding to the low-latency memory entry of the used data. Erase. Specifically, before the cache line corresponding to the used data is reused, the used line is erased by executing a command for performing a line flush on the cache line. In the low delay memory 160 that is a ring buffer, new data is overwritten at the same address. Therefore, in the host device 20, when old data corresponding to the same address remains in the cache memory 204 when trying to access a predetermined address, the cache memory 204 is accessed.

  For this reason, the new data stored at this address cannot be accessed. As described above, the desired data can be reliably accessed by flushing the data in the cache memory 204. The host device 20 is not necessarily a cache-based system.

  FIG. 4 is a flowchart showing message reception processing by the information processing apparatus 10. When the network control unit 110 receives a message via the network (step S100, Yes), the division control unit 120 specifies the received message, that is, the data size of the received message (step S102). Specifically, the position of the size information is specified by the size position information stored in the size position register 124, and the data size is specified.

  Next, the data size of the received message is compared with the data size of the entry in the low delay memory 160 (step S104). Here, the data size of the entry is preset in the division control unit 120. When the data size of the received message is larger than the data size of the entry (step S106, Yes), the entire received message cannot be stored in the low delay memory 160. In this case, the division control unit 120 divides the received message into the first half message and the second half message (step S108). Specifically, the received message is divided at the division position indicated by the division position information stored in the division position register 122. That is, data before the division position becomes the first half message, and data after the division position becomes the second half message.

  Next, the low delay memory control unit 140 stores the first half message in the entry of the low delay memory 160 (step S110). Further, the high delay memory control unit 150 stores the latter half message in the high delay memory 200 (step S112). At this time, the low-latency memory control unit 140 stores the pointer that is the address of the second half message in the same entry as the first half message.

  On the other hand, when the data size of the received message is equal to or smaller than the data size of the entry (No at Step S106), the entire received message can be stored in the low delay memory 160. In this case, the division control unit 120 stores the received message, that is, the entire small received message in the low delay memory 160 (step S120). Thus, the message reception process by the information processing apparatus 10 is completed.

  FIG. 5 is a flowchart showing a received message transfer process from the information processing apparatus 10 to the host apparatus 20. This is processing for providing a message received by the information processing apparatus 10 via the network by the message reception process shown in FIG. 4 to the host apparatus 20 in response to a request from the host apparatus 20.

  First, the received message request unit 201 of the host device 20 sends a received message request to the information processing device 10 (step S200). In the information processing apparatus 10, when the host interface unit 170 receives the received message request, the low delay memory control unit 140 reads data stored in the entry of the low delay memory 160 (step S202). Specifically, the small reception message or the first half message is read. Next, the host interface unit 170 transmits the read data to the host device 20 (step S204).

  At this time, the second half prefetch control unit 190 monitors the presence or absence of a pointer, that is, the presence or absence of the second half message for the read data. Specifically, whether or not the data size indicated by the size information stored in the envelope included in the first half message having the pointer is larger than the division position indicated by the division position information stored in the division position register 122 Is detected.

  As another example, a flag indicating that the latter half message exists together with the first half data may be stored in the entry, and the presence or absence of the second half message may be determined from the presence or absence of the flag.

  By the presence of the second half message, it is possible to know that the probability that the host apparatus 20 will request the second half message corresponding to the first half message will increase soon. If the data size of the received message is larger than the division position, there is a possibility that the latter message is requested because the latter message is present.

  If there is a second half message (step S210, Yes), the high delay memory control unit 150 reads the second half message indicated by the pointer from the high delay memory 200 according to an instruction from the second half prefetch control unit 190 (step S212). . Then, the read second half message is stored in the prefetch buffer 180 (step S214).

  In the host device 20, the received message request unit 201 acquires the small received message or the first half message and stores these data in the cache memory 204. At this time, the control information management unit 206 extracts an envelope from the data. Then, it is confirmed that it matches the key specified by the reception function. Then, it is determined whether the data for which the match has been confirmed is the first half message, that is, whether there is the second half message.

  If there is a second half message in step S202 (step S220, Yes), the second half message request unit 202 sends a second half message request to the information processing apparatus 10 (step S222).

  When the requested second half message exists in the prefetch buffer 180 (Yes in step S230), the host interface unit 170 of the information processing apparatus 10 reads the second half message from the prefetch buffer 180 (step S232). On the other hand, when the requested second half message does not exist in the prefetch buffer 180 (No in step S230), the second half message is read from the high delay memory 200 via the high delay memory control unit 150 (step S234).

  Note that when there is no latter-half message in the prefetch buffer 180, when the host cannot catch up with prefetch at high speed, or when the latter half message is once stored in the prefetch buffer 180, but the latter half message request is acquired, the free space is available. There may be a case where you want to delete it because of lack. In addition, when there is no room for the new data to be written in the prefetch buffer 180, a case where the latter half message is not written can be considered when the structure is not written.

  Next, the host interface unit 170 transmits the latter half message to the host device 20 (step S236). This completes the received message transfer process.

  As described above, when the latter half message corresponding to the data requested from the host apparatus 20 is stored in the high delay memory 200, the host apparatus 20 is requested in advance before obtaining the latter half message request from the host apparatus 20. The second half message is read out to the prefetch buffer 180 having a relatively small delay for the transfer of the message. Accordingly, it is possible to increase the probability that the latter half message exists in the prefetch buffer 180 when the host apparatus 20 requests the latter half message. Therefore, the latter half message can be transferred to the host device 20 with low delay.

  Thereby, the reception delay of the received message having the latter half message in the host device 20 can be shortened. Further, although the entire memory cannot be stored in the small-capacity low-delay memory 160, the bandwidth of a received message having a medium data size that has a large influence on the delay bandwidth can be improved.

  FIG. 6 is a diagram for explaining the message reception time. When a communication library based on a message passing model that is 2sided communication such as MPI is implemented, the message received on the receiving side does not necessarily match the message arrival order on the receiving node.

  For example, as shown in FIG. 2, it is assumed that messages arrive in the order of received messages B1, B2, A1, and A2. In this state, it is assumed that the host device 20 executes a function for receiving the received message A2. In this case, in the conventional processing, the MPI processing system searches and extracts the message A2 from the reception buffer based on the envelope of the four reception messages.

  At this time, the messages B1, B2, and A1 received in the reception buffer prior to the reception message A2 are saved to the saving buffer from the common buffer on the high delay memory 200 by software copy processing. The save buffer is usually arranged on the main memory of the host device 20. Thus, the received message received before message A2 is saved. For this reason, as shown in the upper part of FIG. 6, it takes a total time of copy time to the save buffer proportional to the data size of the received message. That is, it takes a lot of delay time to complete the reception of the received message A2.

  In contrast, in the information processing system 1 according to the present embodiment, as described above, the envelope is held in the low-delay memory 160 that can be accessed from the host device 20 with low delay. Therefore, the envelopes of the received messages B1, B2, and A1 can be acquired from the setting unit 130 with a small delay time without accessing the high delay memory 200 as shown in the lower part of FIG. Therefore, the delay time until the host device 20 receives the received message A1 can be greatly shortened. In this way, it is possible to shorten the delay required for reception when the data size is small.

  As described above, the present invention has been described using the embodiment, but various changes or improvements can be added to the above embodiment.

  As such a first modification, the high-delay memory control unit 150 may pre-fetch the second-half message into the prefetch buffer 180 only when the data size of the second-half message is smaller than a preset reference data size. . Here, the reference data size is set in advance and held by the high-delay memory control unit 150. The high delay memory control unit 150 according to this example functions as a second message size comparison unit.

  The prefetch buffer 180 is composed of a relatively small-capacity and low-delay memory so as to immediately respond to a request from the host device 20. However, the bandwidth performance of a message that is longer than a certain amount is relatively less affected by delay reduction by prefetching. Therefore, it is more effective to preferentially use the prefetch buffer 180 for messages having a medium message size that is more effective. Therefore, only the latter half message smaller than the reference data size is stored in the prefetch buffer 180 as described above.

  As a second modification, instead of operating the low-latency memory 160 as a ring buffer, it may be operated as a write-through cache memory. In this case, the first half message and the second half message are classified and stored in different areas secured in the high delay memory 200. Then, only the area corresponding to the first half message is targeted for the cache. As a result, the probability that the first half message is stored in the low delay memory 160 is increased. Further, it may be operated as a write-back cache memory. In this case, the high delay memory 200 stores the first half message when it is saved from the low delay memory 160 of the first half message.

  When the cache memory is full and overflows, the write-through cache memory appropriately selects an entry and stores new first half data in this entry. That is, the high-delay memory 200 is replaced. In the case of the write-back cache memory, the first half message of the entry is saved in the high delay memory 200 and then overwritten. That is, the high-delay memory 200 is replaced.

  The algorithm for selecting an entry is opposite to the LRU (Last Recently Used) algorithm in a normal CPU. That is, the entry stored most recently is replaced. Thereby, the hit rate can be improved by utilizing the tendency of message exchange that messages that arrive earlier are easier to be received earlier.

  Further, it is also possible to select the latter half message having a small influence of delay, that is, a relatively long message. As a result, shorter messages are accumulated in the cache, and the effect on effective performance is improved.

  By adopting the cache control as described above, even when the balance between the received message request from the host device 20 and the message arrival from the network side is lost as the low-latency memory 160 overflows, it causes congestion on the network side. A message can be received in such a manner that the load is suppressed.

  Furthermore, prefetching is also effective in this configuration. When the read access to the cache is hit, the first half message included in the hit entry is transferred as response data to the host device 20 that issued the read request. At the same time, prefetching of the second half message stored in the position designated by the pointer to the second half message to the prefetch buffer 180 is started. Thereby, the response time to the host device 20 when the host device 20 continues to request the latter half message can be shortened. As a result, it is possible to realize mainly a medium message reception delay reduction and an effective bandwidth improvement.

  As a third modification, in the present embodiment, the low-latency memory 160 stores 32-byte data including the envelope as the first half message. However, instead of this, only the envelope may be stored. Good. That is, one entry stores an envelope and a pointer indicating the address of the high-delay memory 200 that stores data including a portion other than the envelope of the received message.

  In this case, when the data size of the received message is larger than the data size of the entry, the division control unit 120 extracts only the envelope instead of the process of dividing into the first half message and the second half message. Then, the envelope is passed to the low delay memory control unit 140 and the remaining data is passed to the high delay memory control unit 150.

  Further, as a fourth modification, each control unit of the information processing apparatus 10 does not necessarily have to be realized by hard wired logic. For example, a part may be realized by the firmware of the CPU on the NIC or the software of the CPU on the host.

  FIG. 7 is a diagram illustrating a hardware configuration of the information processing apparatus 10 in this case. The information processing apparatus 10 includes, as a hardware configuration, a ROM 52 that stores an information processing program for executing the message reception process illustrated in FIG. 4 and the received message transfer process illustrated in FIG. A CPU 51 that controls each part of the information processing apparatus 10 according to a program, a RAM 53 that stores various data necessary for control of the information processing apparatus 10, and a bus 62 that connects each part are provided.

  The information processing program in the information processing apparatus 10 described above is a file in an installable or executable format and is a computer-readable recording medium such as a CD-ROM, floppy (registered trademark) disk (FD), or DVD. May be recorded and provided.

  In this case, the information processing program is loaded onto the main storage device by being read from the recording medium and executed by the information processing device 10 so that each unit described in the software configuration is generated on the main storage device. It has become.

  Further, the information processing program of the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network.

  The host device 20 may also be realized as software executed in hardware as shown in FIG.

1 is a diagram illustrating an overall configuration of an information processing system 1. FIG. 2 is a diagram illustrating a data configuration of a low delay memory 160 and a high delay memory 200. FIG. 3 is a block diagram showing a functional configuration of a host device 20. FIG. 4 is a flowchart illustrating message reception processing by the information processing apparatus 10. 4 is a flowchart illustrating received message transfer processing from the information processing apparatus 10 to the host apparatus 20. It is a figure for demonstrating the reception time of a message. 2 is a diagram illustrating a hardware configuration of the information processing apparatus 10. FIG.

Explanation of symbols

51 CPU
52 ROM
53 RAM
62 Bus 1 Information processing system 10 Information processing device 20 Host device 110 Network control unit 120 Division control unit 122 Division position register 124 Size position register 130 Setting unit 140 Low delay memory control unit 150 High delay memory control unit 160 Low delay memory 170 Host Interface unit 180 Prefetch buffer 190 Second half prefetch control unit 200 High delay memory 201 Received message request unit 202 Second half message request unit 204 Cache memory 206 Control information management unit

Claims (21)

An information processing apparatus that communicates with the outside via a network,
Data receiving means for receiving a received message from an external device via the network;
Control means for performing processing in a layer below the transport layer of the received message;
The received message after the processing includes a first message including data to be used first in a receiving process in a host device that is a transmission destination of the received message, and data to be used after the first message in the receiving process Dividing means for dividing the message into a second message including:
A first memory for storing the first message obtained by the dividing means;
A second memory that has a larger access delay than the first memory and stores the second message so that the corresponding first message can be identified;
A received message request receiving means for receiving a received message request for requesting the received message from the host device;
First message transmitting means for burst-transferring the first message of the received message stored in the first memory to the host device when the received message request is received;
Second message request receiving means for receiving a second message request for requesting the second message from the host device;
And a second message transmitting means for transmitting the second message stored in the second memory to the host device when the second message request is received. Processing equipment.   The information processing apparatus according to claim 1, wherein a capacity of the second memory is larger than a capacity of the first memory.   The information processing apparatus according to claim 1, wherein the first message includes control information that is information for controlling selection of the received message. The first message is data from the beginning to a predetermined position in the received message,
The information processing apparatus according to claim 3, wherein the second message is data other than the first message in the received message. The first memory further stores a pointer indicating the storage destination of the second message in the second memory in association with the first message ,
The second message transmitting means transmits the second message extracted based on the pointer associated with the first message to the host device by a snoop function. 5. The information processing apparatus according to any one of 4. The first memory has a plurality of fixed-length entries,
Each entry stores the first message and the pointer having a predetermined data size,
A division position information holding unit for holding division position information indicating a division position determined by a data size of the entry and a data size of the pointer;
The information processing apparatus according to claim 5, wherein the dividing unit divides the received message at the division position indicated by the division position information.   The information processing apparatus according to claim 6, further comprising a division position information setting unit that sets division position information in the division position information holding unit according to an instruction from the outside. Data size specifying means for specifying the data size of the received message;
Entry size holding means for holding the data size of the entry;
First data size comparison means for comparing the data size of the received message with the data size of the entry;
The division control means for instructing the division means to divide the received message when the data size of the received message is larger than the data size of the entry. 8. The information processing apparatus according to 7. Size position information holding means for holding size position information indicating a position where the data size is stored in the received message;
The information processing apparatus according to claim 8, wherein the data size specifying unit specifies the data size based on the size position information held by the size position information holding unit.   The information processing apparatus according to claim 9, further comprising a size position information setting unit that sets the size position information in the size position information holding unit according to an instruction from the outside.   The division control means instructs the division means not to divide the received message when the data size of the received message is smaller than the data size of the entry, and The information processing apparatus according to claim 8, wherein the entire received message is stored in an entry. When the second received message request is received, the second message is extracted from the second memory, the second message corresponding to the first message, and stored in the third memory having a lower delay than the second memory. Further comprising means,
When the second message is stored in the third memory, the second message transmission means transmits the second message stored in the third memory to the host device. The information processing apparatus according to any one of claims 1 to 11. Second data size comparison means for comparing the data size of the second message with a predetermined reference data size;
13. The apparatus according to claim 12, further comprising prefetch control means for starting prefetching of the second message into the third memory when the data size of the second message is smaller than the reference data size. The information processing apparatus described.   The information processing apparatus according to claim 1, wherein the first memory is a cache memory having the second memory as a save destination.   Each time the data receiving means receives the received message, the first message corresponding to the received message is stored in the first memory, and there is no capacity to store the first message in the first memory. Further includes first memory control means for replacing the entry of the existing first message having the largest data size of the corresponding received message among the existing first messages already stored in the first memory. The information processing apparatus according to claim 14.     Each time the data receiving means receives the received message, the first message corresponding to the received message is stored in the first memory, and there is no capacity to store the first message in the first memory. The apparatus further comprises first memory control means for replacing an entry of the existing first message written last among existing first messages already stored in the first memory. 14. The information processing apparatus according to 14. An information processing apparatus that receives a message from outside via a network interface,
A received message requesting means for requesting the network interface to provide a message processed in a layer lower than the transport layer ;
A message receiving unit which is burst transfer, to receive the message stored in the first memory of the network interface from the network interface,
Based on control information included in the received message received by the received message receiving means, an inspection means for checking whether or not to receive the received message;
A data size comparing unit that compares the actual data size of the received message with the data size of the received message described in the received message when the checking unit determines to receive the received message;
Second message requesting means for requesting provision of a second message following the received message when an actual data size of the received message is larger than a data size described in the received message;
And a second message receiving means for receiving from the network interface a second message held in a second memory having a larger access delay than the first memory. Information processing apparatus. An information processing method for communicating with the outside via a network,
A data receiving step of receiving a received message from an external device via the network;
A control step of performing processing in a layer below the transport layer of the received message;
The received message after the processing includes a first message including data to be used first in a receiving process in a host device that is a transmission destination of the received message, and data to be used after the first message in the receiving process A dividing step of dividing into a second message including:
A first storing step of storing the first message obtained in the dividing step in a first memory;
A large memory access latency than the first memory, and a second storing step of storing the corresponding first message identifiably the second message to the second memory,
A received message request receiving step for receiving a received message request for requesting the received message from the host device;
A first message transmission step of burst-transferring the first message of the received message stored in the first memory to the host device when the received message request is received;
A second message request receiving step of receiving a second message request for requesting the second message from the host device;
A second message transmission step of transmitting the second message stored in the second memory to the host device when the second message request is received. Method. An information processing method for receiving a message from outside via a network interface,
A received message requesting step for requesting the network interface to provide a message processed in a layer lower than the transport layer ;
And the message receiving step which is burst transfer, to receive the message stored in the first memory of the network interface from the network interface,
Based on the control information included in the received message received in the received message receiving step, a test step for checking whether to receive the received message;
A data size comparison step of comparing the actual data size of the received message with the data size of the received message described in the received message when it is determined that the received message is received in the checking step;
A second message requesting step for requesting provision of a second message following the received message when an actual data size of the received message is larger than a data size described in the received message;
A second message receiving step of receiving from the network interface a second message held in a second memory having a larger access delay than the first memory. Information processing method. An information processing program for causing a computer to execute information processing that communicates with the outside via a network,
A data receiving step of receiving a received message from an external device via the network;
A control step of performing processing in a layer below the transport layer of the received message;
The received message after the processing includes a first message including data to be used first in a receiving process in a host device that is a transmission destination of the received message, and data to be used after the first message in the receiving process A dividing step of dividing into a second message including:
A first storing step of storing the first message obtained in the dividing step in a first memory;
A second storage step for storing the second message in the second memory so that the corresponding first message can be identified, the access delay being larger than that of the first memory ;
A received message request receiving step for receiving a received message request for requesting the received message from the host device;
A first message transmission step of burst-transferring the first message of the received message stored in the first memory to the host device when the received message request is received;
A second message request receiving step of receiving a second message request for requesting the second message from the host device;
Information for causing the computer to execute a second message transmission step of transmitting the second message stored in the second memory to the host device when the second message request is received. Processing program . An information processing program for causing a computer to execute information processing for receiving a message from outside via a network interface,
A received message requesting step for requesting the network interface to provide a message processed in a layer lower than the transport layer ;
And the message receiving step which is burst transfer, to receive the message stored in the first memory of the network interface from the network interface,
Based on the control information included in the received message received in the received message receiving step, a test step for checking whether to receive the received message;
A data size comparison step of comparing the actual data size of the received message with the data size of the received message described in the received message when it is determined that the received message is received in the checking step;
A second message requesting step for requesting provision of a second message following the received message when an actual data size of the received message is larger than a data size described in the received message;
A memory of the network interface, to perform a second message receiving step of receiving a second message stored in the higher second memory access latency than the first memory from the network interface to the computer information processing program for.

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