JP4409550B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that controls a terminal operation unit by transmitting a control signal in the order of a main control circuit, a sub control circuit, and a terminal control circuit.

A conventionally known pachinko gaming machine includes a plurality of terminal control circuits such as a display control circuit and a payout control circuit and one main control circuit in order to control a terminal operation unit such as a display device and a payout device. Each terminal control circuit is configured to control each terminal operation unit in accordance with the main control signal output from the main control circuit (see, for example, Patent Document 1). On the other hand, in recent years, a sub control circuit is provided between the main control circuit and the end control circuit, and a control signal is transmitted in the order of the main control circuit, the sub control circuit, and the end control circuit, Controlling gaming machines have been developed.
Japanese Unexamined Patent Publication No. 2004-113692 ([0028], [0029], [0043], FIG. 3)

  By the way, in the above-described gaming machine that transmits control signals in the order of the main control circuit, the sub control circuit, and the end control circuit, the execution cycle of the processing program in the sub control circuit is usually the execution cycle of the processing program in the main control circuit. Same as or shorter than. Therefore, if the output frequency of the main control signal by the main control circuit increases due to the big hit gaming state or the like, the output frequency of the sub control signal by the sub control circuit also increases, and the sub control signal is received by the terminal control circuit. Therefore, the control load for the operation becomes large, and there is no allowance for the operation control of the end operation unit. For this reason, when a gaming machine is made more sophisticated and complicated than the present situation, the degree of freedom of control by the end control circuit is limited, or the data processing capability required for the end control circuit is increased, resulting in higher costs. The problem of becoming may have arisen.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reducing a control load for signal reception by a terminal control circuit.

A gaming machine according to the invention of claim 1, which has been made to achieve the above object, comprises an operable end action unit and repeatedly executed data processing at a predetermined execution cycle, and randomly generated game information. A main control circuit that generates and outputs a main control signal in data processing, a sub control circuit that receives the main control signal, generates and outputs a sub control signal according to the main control signal, and receives the sub control signal However, in a gaming machine including a terminal control circuit that controls the terminal operation unit according to the slave control signal, the terminal operation unit is configured to be switchable to a plurality of types of operation states, and the slave control circuit is set in advance. In addition, the sampling cycle generation means for generating a sampling cycle longer than the data processing execution cycle, and the output of the slave control signal for the main control signal received during any one of the sampling cycles, And hold means for stopping up Ryosuru, only the control information included in the main control signal received last among the main control signal of the data processing multiple cycles received during any one period of the sampling period, the newest control data And a control signal integration means that is included in the sub-control signal and is output after the end of the one cycle.

According to a second aspect of the present invention, in the gaming machine according to the first aspect, a signal line for transmitting / receiving a main control signal and a signal line for transmitting / receiving a strobe signal between the main control circuit and the sub control circuit. And the sub control circuit is characterized in that it receives the main control signal on condition that the strobe signal is received from the main control circuit.

According to a third aspect of the present invention, in the gaming machine according to the first or second aspect , the slave control circuit repeatedly executes data processing from power-on and interrupts data processing based on a predetermined trigger. The processing is executed, and the hold means and the control signal integration means are configured by the interruption process.

[Invention of Claim 1 ]
According to the configuration of claim 1, assuming that game information is frequently generated and a main control signal is output from the main control circuit each time data processing is executed, the sub control circuit is at least from the data processing execution cycle. The slave control signal is output at intervals of a long sampling period. Then, the control information included in the main control signal for a plurality of data processing cycles received during any one sampling cycle is updated to the latest control information, included in the slave control signal, and output one cycle later. As a result, the amount of control information output by the main control circuit included in the main control signal is reduced by the sub control circuit, and the control load for receiving the sub control signal by the end control circuit can be reduced. Further, terminal operation unit, when configured to be switched to a plurality of types of operating conditions, the last received among the received data processing multiple cycles of the main control signal during any one cycle of the sampling period By including only the control information of the main control signal in the sub control signal, the amount of control information output by the main control circuit included in the main control signal can be reduced by the sub control circuit, and the control load of the end control circuit is reduced. It becomes possible to do.

[Invention of claim 2 ]
According to the configuration of the second aspect , since the slave control circuit receives the main control signal on condition that the strobe signal is received from the main control circuit, even if the main control signal is output at random from the main control circuit. The slave control circuit can reliably receive the main control signal.

[Invention of claim 3 ]
According to the configuration of claim 3 , if the interrupt processing is executed by interrupting the data processing based on a predetermined trigger, and the hold means and the control signal integration means are configured by the interrupt processing, any sampling period can be set. The stop of the output of the slave control signal during one cycle and the output of the slave control signal after one cycle can be performed with priority over other processing .

  Hereinafter, one embodiment according to the pachinko gaming machine 10 of the present invention will be described with reference to FIGS. As shown in FIG. 1, the pachinko gaming machine 10 includes a game area R <b> 1 in a portion of the game board 11 surrounded by the guide rail 12. A display window 11W is formed through the game board 11 in the game area R1, and a liquid crystal display screen 24G provided in the display device 24 (specifically, a TFT-LCD module) is addressed to the display window 11W from the rear side. It has been broken. Further, the display window 11W is arranged on the upper side and on the right side in the game area R1, and a space in which the game ball can flow is secured on the upper side, the left side, and the lower side of the display window 11W in the game area R1. Yes.

  In the lower space of the display window 11W, first and second start winning ports 14A and 14B, a large winning port 15 and an out port 16 are arranged in order from the top in the center in the left-right direction. The section is provided with general winning ports 20, 21 and side lamps 22 along the guide rail 12, respectively. In the left space of the display window 11W, a start gate 18 and a windmill 19 are provided vertically. Below the windmill 19, a normal symbol display unit 17 is provided integrally with the side lamp 22. A warning lamp 39 is provided in the vicinity of the upper left corner of the liquid crystal display screen 24G. Furthermore, in addition to these various winning holes 14A, 14B, 15, 20, 21 and the display device 24, etc., the game area R1 is an obstacle that can contact the game ball and change the flow direction in various ways. The nails are distributed.

  The gaming area R1 described above can be viewed through a glass window 95W provided on the front surface of the pachinko gaming machine 10. A pair of speakers 13 and 13 are provided on the left and right of the front surface of the gaming machine 10 above the glass window 95W. In addition, a pair of bulging walls 26 and 27 projecting forward are provided below the glass window 95 </ b> W on the front surface of the game board 11. On the upper bulging wall 26, an upper dish portion 26A is recessed, and a ball removal button 26B is provided on the side of the upper dish portion 26A. On the lower bulging wall 27, a lower plate portion 27A is depressed, and a game button 27B is provided on the left side of the lower plate portion 27A, and a ball discharge button 27C and a ball lending state are provided on the right side. A display monitor 27D and a ball lending operation button 27E are provided. Further, an operation knob 28 is provided at the lower right corner of the front surface of the pachinko gaming machine 10.

  When the operation knob 28 is operated, a plurality of game balls stored in the upper plate portion 26A are sequentially driven into the upper part of the game area R1, and in the process of flowing down the game area R1, several game balls Enters any of the winning openings 14A, 14B, 15, 20, 21 and the game balls that have not entered any of the winning openings enter the out opening 16.

  Here, one “winning” is generated each time one gaming ball enters one of the winning openings 14A, 14B, 15, 20, and 21. This is hereinafter referred to as “game ball wins” as appropriate. Each time one game ball wins one of the winning holes, the number of game balls shown in Table 1 (hereinafter referred to as “prize ball” as appropriate) is paid out to the upper plate portion 26A.

  Note that the game ball can be discharged from the upper dish part 26A to the lower dish part 27A by pressing the ball removal button 26B. In addition, the game balls stored in the lower dish part 27A are placed in a receiving box (so-called dollar box) below the lower dish part 27A, and the ball discharge button 27C is pressed to the receiving box. And can be discharged. Further, when the lower dish portion 27A is filled with game balls, the lower dish full switch 27F shown in FIG. 6 detects this, and the warning lamp 39 is lit and a warning sound is output from the speaker 13. Is done.

  Details of each part required in the game area R1 are as follows. The general winning ports 20 and 21 have a so-called pocket structure, and are opened upward in such a size that only one game ball can enter. The game balls that have entered each of the general winning ports 20 and 21 are collected on the back side of the game board 11 through through holes (not shown) provided in the game board 11. In addition, each of these general winning ports 20, 21 is provided with a general winning port switch SW4 (see FIG. 6) for detecting the winning of a game ball, and each of these general winning port switches SW4 is one of the game balls. Each time a ball winning is detected, as shown in Table 1, four prize balls are paid out to the upper plate portion 26A.

  The start gate 18 has a gate-like structure through which game balls can dive, and the passed game balls are detected by a gate switch SW1 (see FIG. 6) built in the start gate 18. Based on this detection signal, the normal symbol display unit 17 displays the symbols in a variable manner. Specifically, the normal symbol display unit 17 is composed of 7-segment LEDs, and after the numeric symbols consisting of numbers from “0” to “9” are variably displayed over a predetermined period on the 7-segment LEDs. The predetermined numerical symbol is stopped and displayed.

  The first and second start winning ports 14A and 14B are arranged side by side. Each of the start winning ports 14A and 14B has a so-called pocket structure in which an opening is provided on the upper surface of a member protruding from the game board 11. The game balls that have entered the start winning ports 14A and 14B are collected on the back side of the game board 11 through through holes (not shown) provided in the game board 11.

  The first start winning opening 14A arranged on the upper side has an opening width into which only one game ball can enter. On the other hand, the second start winning port 14B disposed on the lower side is disposed directly below the first start winning port 14A, and movable wing pieces 14C and 14C are provided on both left and right sides of the opening. Both the movable wing pieces 14C and 14C are always in an upright state, and the opening width of the second start winning opening 14B sandwiched between the two movable wing pieces 14C and 14C is large enough to contain only one game ball. It has become. In addition, the space above the second start winning opening 14B is always surrounded by the members constituting the first start winning opening 14A and the movable wing pieces 14C and 14C so that no game balls can enter. Yes. When the number symbol stopped and displayed on the normal symbol display unit 17 becomes an odd number, the ordinary electric accessory solenoid 14S (see FIG. 6) provided on the back of the game board 11 is driven, and the movable wing pieces 14C and 14C are moved. Tilt down sideways for a predetermined period (eg, 0.4 seconds). Then, the upper space of the second start winning opening 14B is opened to the side, and the game ball that has passed through both sides of the first start winning opening 14A is received by the movable wing piece 14C and the second start winning opening 14B. Be guided by.

  Each of the first and second start winning openings 14A and 14B is provided with start opening switches SW2 and SW3 (see FIG. 6) for detecting the winning of a game ball, and each of these start opening switches SW2 and SW3. As shown in Table 1, four prize balls are paid out to the upper plate portion 26A and a game success / failure determination is performed each time a game ball winning is detected as shown in Table 1. This is indicated by a symbol display on the liquid crystal display screen 24G.

  On the liquid crystal display screen 24G, three special symbols 23A, 23B, and 23C on the left, middle, and right are normally displayed side by side. Each of these special symbols 23A, 23B, and 23C is composed of, for example, a plurality of types that express numbers “0” to “11”. Usually, each special symbol 23A, 23B, and 23C has a predetermined value. Kinds of things are stopped. Then, when the game ball is won at the start winning opening 14A, 14B and the winning / failing determination is made, these three special symbols 23A, 23B, 23C are scrolled up and down, and after a predetermined time, for example, left The special symbols 23A, 23B, and 23C are stopped and displayed in the order of middle and right. At this time, if the result of the game success / failure determination is “big hit”, for example, all the special symbols 23A, 23B, and 23C become the same symbol, that is, a rough eye.

  Further, when the special symbols 23A, 23B, and 23C are displayed on the liquid crystal display screen 24G while being variably displayed or in the “hit state”, a maximum of four winning balls are stored as reserved balls when the winning winning holes 14A and 14B are won. Then, the number of reserved memories (the number of reserved balls) is displayed on the number-of-holds display section 23Z provided at the lower corner of the liquid crystal display screen 24G. When the special symbols 23A, 23B, and 23C are stopped or displayed in the “hit state”, the number of reserved memories is reduced by one, and the special symbols 23A, 23B, and 23C are again displayed after being variably displayed. The game success / failure determination result is displayed.

  When the game button 27B is pressed, images (for example, character images) other than the special symbols 23A, 23B, and 23C that are variably displayed on the liquid crystal display screen 24G can be stopped at any timing of the player.

  The special winning opening 15 is formed in a horizontally long rectangle and is always closed by the movable door 15T. When the pachinko gaming machine 10 is in the “hit state”, a large winning opening solenoid 15S (see FIG. 6) provided on the back of the game board 11 is driven, and the movable door 15T falls forward for a predetermined period. Thereby, the grand prize opening 15 is opened, and a large number of game balls can be awarded to the big prize opening 15 by using the movable door 15T as a guide. In addition, the game ball that has entered the special winning opening 15 is collected on the back side of the game board 11 through a through hole (not shown) provided in the game board 11.

  Here, when the movable door 15T is opened and closed, it is referred to as “round”. In one round, the opening time of the movable door 15T has reached 30 seconds, or The process ends when any of the ten game balls is won first. Further, the “big hit state” is continued up to, for example, 15 rounds.

  Inside the big winning opening 15, a continuous winning opening and a counting winning opening are provided. More specifically, when the movable door 15T is opened, the continuous winning opening is opened, and after winning the continuous winning opening, the solenoid is driven to close the continuous winning opening, while the counting winning opening is opened. Will remain. Then, when the big winning opening first switch SW5 (see FIG. 6) provided in the continuous winning opening detects the winning of the game ball, after the round is completed by satisfying the above-mentioned end condition, the next round is continuously performed. Executed. Further, when the big winning opening second switch SW6 (see FIG. 6) provided in the counting winning opening detects the winning of the game ball, the winning balls to the big winning opening 15 are counted together with the winning balls to the continuous winning opening. Then, it is checked whether or not a total of 10 of these has been reached as described above. As shown in Table 1, for example, fifteen game balls are paid out to the upper plate portion 26A every time the big winning opening first switch SW5 or the big winning opening second switch SW6 detects one winning.

  FIG. 2 shows a state in which the pachinko gaming machine 10 is viewed from the rear. As shown in the figure, a tank 30 is provided on the upper rear surface of the pachinko gaming machine 10. A game ball is supplied to the tank 30 from a duct (not shown) provided in the game hall, and a certain amount or more of the game ball is always stored in the tank 30. A discharge port (not shown) that is always open is provided on the lower surface of the tank 30, and a game ball discharged from the discharge port is one side portion of the pachinko gaming machine 10 by a slanting basket 31 that extends in the horizontal direction and is inclined. Be guided to. On one side portion of the pachinko gaming machine 10, a flow bar 32 is provided to allow a game ball to flow down, and a payout device 33 is connected to the lower end of the flow bar 32.

  As shown in FIG. 3, the payout device 33 is provided with a pair of parallel flow-down passages 34 </ b> A that are large enough to allow only one game ball to pass therethrough. As shown in FIG. 4 (only one of the downflow passages 34A is shown in FIG. 4), the downflow passages 34A and 34A extend in the vertical direction and are bent in a crank shape in the middle. As shown in FIG. 5 (A), a rotating member 36 is provided between the lower ends of the flow-down passages 34A and 34A, and the spiral protruding wall 36A projecting laterally from the rotating member 36 is provided in each side. It enters the flow-down passages 34A, 34A to restrict the passage of game balls.

  The rotating member 36 can be driven to rotate by the stepping motor 35, and each time the rotating member 36 rotates 180 degrees, the lower end portion of the spiral projecting wall 36A passes through the flow passages 34A and 34A alternately. As a result, the game balls are alternately discharged from the flow-down passages 34A and 34A (see FIG. 5B). Further, the lower end openings of the flow-down passages 34A and 34A are communicated with the upper plate portion 26A via a flow-down rod (not shown). Thereby, the game ball discharged from the payout device 33 is paid out to the upper plate part 26A. Furthermore, payout sensors 37 and 37 are provided at the lower ends of both the downflow passages 34A and 34A, respectively, and these payout sensors 37 detect game balls discharged from the downflow passages 34A. On the other hand, a ball break switch 33F shown only in FIG. 6 is provided at the upper ends of the both downstream passages 34A and 34A, and the ball break switch 33F is activated when the supply of the game ball to the payout device 33 is interrupted. .

  FIG. 6 shows the electrical configuration of the pachinko gaming machine 10. As shown in the figure, among the plurality of control circuits provided in the pachinko gaming machine 10, the main control circuit 50, the first and second sub control circuits 51 and 52, the display control circuit 53, the voice control circuit 54, the launch control. The circuit 55 and the payout control circuit 56 are connected in a hierarchical structure. Specifically, the first and second sub control circuits 51 and 52 and the normal symbol display control circuit 57 of the second hierarchy are connected to the main control circuit 50 of the first hierarchy. In addition, a display control circuit 53 in the third hierarchy is connected to the first slave control circuit 51 in the second hierarchy, and a launch control circuit 55 in the third hierarchy is connected to the second slave control circuit 52 in the second hierarchy. A payout control circuit 56 is connected. Furthermore, a fourth level audio control circuit 54 is connected to the third level display control circuit 53. The control signals are transmitted in the order of the control circuits in the first, second, third, and fourth layers, and various solenoids 14S connected to the control circuits in the first to fourth layers. , 15S, various illumination boards 63, the normal symbol display unit 17, the display device 24, the speaker 13, the launching device 25, the payout device 33, and the like.

Here, in the present embodiment, the main control circuit 50 corresponds to a “main control circuit” according to the present invention, and the first and second sub control circuits 51 and 52 respectively correspond to the “sub control circuit” according to the present invention. The display control circuit 53 corresponds to the “terminal control circuit” according to the present invention. Furthermore, (in particular, liquid crystal display screen 24G) Viewing device 24 and a sound output unit consisting of voice control circuit 54 and a speaker 13 are controlled by respective "Terminal Control circuit" (display control circuit 53) It corresponds to the “terminal operation part” of the present invention. Furthermore, since the number-of-holds display part 23Z and the other parts (hereinafter referred to as “main display part 23X”) of the liquid crystal display screen 24G are controlled based on different control information as will be described later, Each of the number display unit 23Z and the main display unit 23X also corresponds to the “terminal operation unit” of the present invention.

  FIG. 7 shows the connection structure of the plurality of control circuits described above in detail. Each control circuit 50 to 56 shown in the figure includes a CPU as a main part, and an output terminal of the CPU included in the main control circuit 50 (hereinafter simply referred to as “output terminal of the main control circuit 50”). The first and second sub-control circuits 51 and 52 are connected in parallel (bus line connection) to the parallel signal line B1 connected to. Further, strobe lines ST1, ST1 are connected between an output terminal different from the output terminal connected to the parallel signal line B1 in the main control circuit 50 and the INT terminals of the first and second slave control circuits 51, 52. Connected at ST2. In order to output a control signal from the main control circuit 50 only to the first sub control circuit 51, a strobe signal is output only to the INT terminal of the main control circuit 50 and then the first sub control circuit 51 A control signal is output to the parallel signal line B1. The same applies to the case where the control signal is output only from the main control circuit 50 to the second sub control circuit 52.

  The second slave control circuit 52 is connected to the launch control circuit 55 and the payout control circuit 56 by a parallel signal line B3 as a bus line and strobe lines ST6 and ST5. Further, the first slave control circuit 51 and the display control circuit 53 are connected by a parallel signal line B2 and a strobe line ST3, and the display control circuit 53 and the audio control circuit 54 are connected by a parallel signal line B4. And strobe line ST4. Then, similarly to the main control circuit 50, the control circuits 51, 52, and 53 also output a control signal after outputting a strobe signal. Hereinafter, the control signal output from the main control circuit 50 is referred to as “main control signal”, and the control signals output from the first and second sub control circuits 51 and 52 are referred to as “sub control signal”.

  The main control circuit 50 generates and outputs a main control signal based on randomly generated game information. The game information includes, for example, a detection signal of the lower plate full switch 27F that is generated when the lower plate portion 27A is full, a detection signal of the gate switch SW1 that is generated when the start gate 18 is passed, and each prize. Examples thereof include detection signals of the switches SW2 to SW6 generated by winning the game balls to the mouths 14A, 14B, 15, 20, and 21, counter values to be described later determined by the winnings, and the like. In order to generate a main control signal from these game information, the detailed configuration of the main control circuit 50 is as follows.

  The main control circuit 50 is provided as a one-chip microcomputer in which the CPU described above is packaged together with a RAM and a ROM. A counter value storage area R10 shown in FIG. 8 is provided in the storage area R0 of the RAM of the main control circuit 50. Then, the main control circuit 50 sequentially updates a set of counter value groups shown in Table 2 as random numbers by processing described later, and a detection signal for winning to the start winning ports 14A and 14B is sent to the main control circuit 50. A set of counter value groups when taken in is stored (stored) in the counter value storage area R10. Further, when the winning balls to the start winning ports 14A and 14B become the holding balls, a plurality of counter value groups corresponding to the number of the holding balls (up to four sets) are acquired and stored in the counter value storage area R10. Is done. Then, each time the game success / failure determination result is displayed by the stop display after the special symbols 23A, 23B, and 23C are displayed, the number of sets of counter value groups stored in the counter value storage area R10 is reduced. Therefore, the number of pending storages is also known from the number of sets of counter value groups stored in the counter value storage area R10.

  When the power of the pachinko gaming machine 10 is turned on, the one-chip microcomputer provided in the main control circuit 50 takes out the main control circuit main program PG1 shown in FIG. 9 from the ROM and runs it. As shown in the figure, when the main control circuit main program PG1 is run, initialization is first performed (S1). In the initial setting (S1), for example, stack setting, constant setting, CPU setting, SIO, PIO, CTC (interrupt time controller) setting, various flags and counter values are reset. The initial setting (S1) is executed only when the main control circuit main program PG1 is run for the first time after power-on, and is not executed thereafter.

  Subsequent to the initial setting (S1), interrupts are prohibited (S2), and a special symbol main random number update process (S3) is executed. In the special symbol main random number update process (S3), the counter values shown in Table 2 are updated. These counter values are set to “0” when the power is turned on, and are incremented by 1 each time the special symbol main random number update process (S3) is executed. Further, it is checked whether or not each counter value exceeds the upper limit value. If the upper limit value is exceeded, the counter value is reset to the lower limit value (“0”) and incremented by 1 from the lower limit value again. Each counter value updated in this way is stored one by one in an update value storage area (not shown) provided separately from the counter value storage area R10 in the RAM storage area R0 (see FIG. 8). The special symbol main random number update process (S3) ends.

  When the special symbol main random number update process (S3) ends, an interrupt is permitted (S4), and the main control circuit 4 ms timer interrupt process (S5) can be executed. The main control circuit 4 ms timer interrupt processing (S5) corresponds to “data processing” according to the present invention, and an interrupt pulse is input to the CPU, for example, in a 4 msec cycle (corresponding to “execution cycle” according to the present invention). It is executed repeatedly. The special symbol main random number update processing (S3) is performed during the remaining processing period from the end of the main control circuit 4ms timer interrupt processing (S5) to the start of the main control circuit 4ms timer interrupt processing (S5). The process of updating various counter values according to (2) is repeatedly performed a plurality of times. When an interrupt pulse is input to the CPU in the interrupt disabled state, the main control circuit 4 ms timer interrupt process (S5) is not started immediately, but is started after the interrupt is enabled (S4).

  The main control circuit 4 ms timer interrupt process (S5) will be described. As shown in FIG. 10, in the main control circuit 4 ms timer interrupt process (S5), an output process (S10) is first executed. In this process (S10), the data set in the output buffer of the RAM in each process described below is output to the first and second slave control circuits 51, 52 and the like. This output process (S10) will be described in detail later.

  In the input process (S11) performed subsequent to the output process (S10), the detection signals of the lower pan full switch 27F, the various switches SW1 to SW6, etc. are fetched as “game information” according to the present invention. Then, the number obtained by multiplying the number of detection signals of the game balls by the switches SW2, SW3, SW4 of the start winning ports 14A, 14B and the general winning ports 20, 21 with “4”, and the switches provided in the large winning port 15 The number obtained by multiplying the number of detection signals of game balls by SW5 and SW6 by “15” is stored in the output buffer of the RAM as information on the number of payouts.

  In the next normal symbol / special symbol main random number update process (S12) to be performed, in addition to the various counter values shown in Table 2, the counter value for determining the normal symbol is the same as the special symbol main random number update process (S3). It is updated in the same way. That is, the counter value for determining the normal symbol is updated only during the main control circuit 4 ms timer interrupt process (S5), and the various counter values shown in Table 2 are stored in the remaining process period (main control circuit 4 ms timer interrupt process (S5 ) Until the next main control circuit 4 ms timer interrupt process (S5) is started).

  Next, the start switch detection process (S13) performed is shown in FIG. In this process (S13), various counter values stored in the update value storage area of the RAM are taken out and stored in the address space (see FIG. 8) corresponding to the number of reserved storages in the counter value storage area R10 of the RAM. The Specifically, first, it is checked whether or not a game ball has won the start winning ports 14A and 14B, that is, whether or not a game ball has been detected by the detection sensor provided in the start winning ports 14A and 14B (S150). ).

  Here, when the game ball has not won the start winning opening 14A, 14B (no in S150), this process (S13) is immediately exited. When a game ball wins the start winning opening 14A, 14B (Yes in S150), it is checked whether or not the number of reserved memories has reached 4 (upper limit) (S151). If the number of reserved memories has reached four (yes in S151), the process immediately exits (S13) without storing a new counter value. On the other hand, if the number of reserved memories is less than 4 (no in S151), the number of reserved memories is incremented by 1 (S152), and various counter values are stored. Specifically, the jackpot counter value (label-TRND-A) stored in the update value storage area of the RAM is read out and stored in the address space corresponding to the number of reserved storages in the counter value storage area R10 of the RAM. (S153). Next, the jackpot symbol counter value (label-TRND-AZ1) stored in the update value storage area of the RAM is read out and stored in the address space corresponding to the reserved storage number in the counter value storage area R10 (S154). ).

  In the start switch detection process (S13), although not shown, the reach counter value (label-TRND-RC) and the variation mode counter value (label-TRND-T1) are also taken out from the update value storage area, and the counter The value is stored in an address space corresponding to the number of reserved storages in the value storage area R10. In other words, various counter values (a jackpot counter value, a jackpot symbol counter value, a reach counter value, and a variation mode counter value) are acquired in response to the winning of a game ball at the start winning ports 14A and 14B. The above is the description of the start switch detection process (S13).

  As shown in FIG. 10, the normal symbol process (S14) is performed after the start switch detection process (S13). In this process (S14), when a normal symbol start sensor (not shown) provided in the start gate 18 detects the passing of the game ball, the counter value is acquired from the update area of the normal symbol determination counter value in the RAM. And stored in an acquisition area provided in the RAM.

  The special operation process (S15) performed after the normal symbol process (S14) is performed based on the various counter values stored in the counter value storage area R10 of the RAM in step S13.

  The special operation process (S15) is shown in FIG. 12, and first, a special symbol creation process (S170) is performed. The outlier special symbol creation processing (S170) is shown in detail in FIG. 13. First, the address of the updated value storage area of the RAM is set, and the left out symbol counter value (label-TRND-B1) is read ( S100). Next, the off-right symbol counter value (label-TRND-B3) is read as the determination value (S101). The left off symbol counter value (label-TRND-B1) is compared with the right off symbol counter value (label-TRND-B3) (S102). This process (S170) is exited.

  If they do not match (no in S102), the address space of the stored symbol counter values (labels-TRND-B1, B2, B3) is stored in the RAM in the counter value storage area R10 according to the number of reserved memories. The address space is set (S103), and the off symbol counter values (labels-TRND-B1, B2, B3) stored in the update value storage area are transferred and stored in the set address space (S104). .

  As shown in FIG. 12, the special action status is checked (S171, S173, S175) after the special symbol creation process (S170), and the special symbol standby process (S172) and the special symbol change are performed according to the special action status. One of the process (S174), the special symbol confirmation process (S176), and the special electric accessory process (S177) is executed.

  When the special operation status is “1” (Yes in S171), that is, when the special symbols 23A, 23B, and 23C are not in the variable display or “big hit game”, the special symbol standby process (S172) ) Is executed.

  The special symbol standby process (S172) is shown in FIG. First, it is checked whether or not the number of reserved memories is “0” (S202). When the number of reserved storage is “0” (Yes in S202), that is, when there is no storage of various counter values acquired due to winning at the start winning opening 14A, 14B, the liquid crystal display screen 24G It is checked whether the display is a standby screen (S208). If the screen is a standby screen (yes in S208), the process immediately exits (S172). On the other hand, if the screen is not a standby screen (no in S208), a process for setting the standby screen (S209) is performed, and then this process is performed. Exit (S172).

  On the other hand, when the number of reserved memories is not “0” (no in S202), that is, when there are one or more stored various counter values acquired due to winning at the winning winning openings 14A and 14B, Special symbol jackpot determination processing (S203), special symbol selection processing (S204), special symbol variation pattern creation processing (S205), special symbol random number shift processing (S206), and special symbol variation start setting (S207) described below Done.

  In the special symbol jackpot determination process (S203), whether or not the game is successful is determined, and it is determined whether or not the “jackpot game” can be executed. Specifically, as shown in FIG. 15, first, the jackpot counter value (label-TRND-A) stored in the counter value storage area R10 of the RAM is read as a determination value (S310). Next, the address of the jackpot determination value table is set (S311). As a result, as shown in Table 3, for example, “77” to “96” are set as the comparison values in the probability variation state, and the non-probability variation state For example, “77” and “78” are set as the comparison values. Next, it is checked whether or not the probability variation state (probability variation flag is ON) (S312). If the probability variation state is present (yes in S312), the value of the jackpot counter value (label -TRND-A) is " It is determined whether or not it is a big hit based on whether it matches any of 77 ”to“ 96 ”(S315). On the other hand, when the state is a non-stochastic fluctuation state (no in S312), whether or not the jackpot is based on whether or not the value of the jackpot counter value (label-TRND-A) matches “77” or “78”. Is determined (S313). In any case, if it is determined that the game is a “hit” (Yes in S313, yes in S315), the jackpot flag stored in the RAM is turned on (S314), and it is determined that it is not a “hit”. If this happens (no at S313, no at S315), do nothing (leave the jackpot flag off) and exit this process (S203). The above is the description of the special symbol jackpot determination process (S203).

  As shown in FIG. 14, a special symbol selection process (S204) is executed following the special symbol jackpot determination process (S203). The special symbol selection process (S204) is shown in FIG. 16, and first, it is checked whether or not the jackpot flag is ON (S210).

  When the jackpot flag is ON (yes in S210), that is, when the acquired jackpot counter value (label-TRND-A) matches any of the jackpot value (see Table 3) in the jackpot determination value table Is determined to be a combination in which all the special symbols 23A, 23B, and 23C on the liquid crystal display screen 24G are the same. Specifically, the jackpot symbol counter value (label-TRND-AZ1) acquired in the start switch detection process (S13) shown in FIG. 11 is set in the output buffer of the RAM (S211), and the process exits (S204). .

  On the other hand, when the jackpot flag is off (no in S210), that is, when the acquired jackpot counter value (label-TRND-A) does not match any of the hit numbers (see Table 3), 11 reach generation values (for example, 5, 17, 28, 40, 51, 63, etc.) in which the reach counter value (label-TRND-RC) acquired due to winning of the start winning openings 14A, 14B is preset. 74, 86, 97, 109, 120) is checked (S212).

  When the acquired reach counter value (label-TRND-RC) coincides with any of the reach occurrence numerical values (Yes in S212), the special symbols 23A, 23B, and 23C are set to a combination in which the stop symbols are out of reach.

  Specifically, the counterclockwise symbol counter value (label-TRND-B1) stored in the counter value storage area R10 of the RAM is forcibly changed to the same value as the counterclockwise symbol counter value (label-TRND-B3). (S213), and 1 is added to the left counter symbol counter value (label-TRND-B1) (S214), and the added value is forcibly set to the counter symbol counter value (label-TRND-B2) (S215). ). That is, the special symbols 23A, 23B, and 23C are determined so as to be displayed in a fixed stop manner such as “1 2 1” and “2 3 2”, for example. Then, the determined off symbol counter values (labels-TRND-B1, B2, B3) are set in the output buffer of the RAM, and this process (S204) is exited.

  On the other hand, if the acquired reach counter value (label-TRND-RC) does not coincide with any of the above reach generation values (no in S212), that is, if the reach is out of reach, the counter value storage area of the RAM The off symbol counter values (labels-TRND-B1, B2, B3) stored in R10 are set in the RAM output buffer as they are (S216), and the process (S204) is exited. The above is the description of the special symbol selection process (S204).

  As shown in FIG. 14, following the special symbol selection process (S204), a special symbol variation pattern creation process (S205) is executed. The special symbol variation pattern creation process (S205) is shown in FIG. 17, and it is first determined whether or not the big hit flag is ON (S240). If the jackpot flag is ON (Yes in S240), that is, if the determination result is “Win”, based on the obtained variation mode counter value (label-TRND-T1), the following Table 4 One of the variation pattern 1 and the variation pattern 2 is selected from the first variation pattern table shown in FIG. Specifically, when the obtained variation mode counter value is any value from 0 to 194, variation pattern 1 is selected, and the obtained variation mode counter value is any value from 195 to 198. If there is, the variation pattern 2 is selected.

  On the other hand, when the jackpot flag is OFF (no in S240), that is, when the determination result is “out”, based on the obtained variation mode counter value (label-TRND-T1), the following Table 5 The variation pattern 1, variation pattern 2, or variation pattern 3 is selected from the second variation pattern table shown in FIG. Specifically, when the acquired variation mode counter value (label-TRND-T1) is 0, the variation pattern 1 is selected, and the acquired variation mode counter value (label-TRND-T1) is When the value is any one of 1 to 18, the fluctuation pattern 2 is selected, and when the obtained fluctuation mode counter value (label-TRND-T1) is any one of 19 to 198 The variation pattern 3 is selected.

  When the variation pattern is selected, other processing (S242) is performed, and then this processing (S205) is exited. In the other processing (S242), a variation pattern command corresponding to the selected variation pattern is set in the output buffer of the RAM.

  As shown in FIG. 14, a special symbol random number shift process (S206) is performed after the special symbol variation pattern creation process (S205). This process (S206) is shown in FIG. 18. First, the reserved storage number (the numerical value of the reserved number storage area of the RAM) is decremented by 1 (S350). Next, the storage location of the various counter values in the counter value storage area R10 is shifted to the counter value storage area R10 on the lower side (address “0000” side in FIG. 8) (S351). Then, “0” is set in each address space of the uppermost counter value storage area R10 (S352), and this process (S206) is exited.

  As shown in FIG. 14, in the special symbol variation start setting (S207) performed after the special symbol random number shift processing (S206), the special operation status is set to “2” and the variation start command is set in the RAM output buffer. set. The above is the description of the special symbol standby process (S172) in the special operation process (S15).

  As shown in FIG. 12, when the special operation status is “2” in the special operation process (S15) (no in S171, yes in S173), the special symbol variation process (S174) is executed. This process (S174) is shown in FIG. 19. First, the variable display time (Table 4 and Table 5) corresponding to the fluctuation pattern set in the special symbol fluctuation pattern creation process (S205, see FIG. 17) is shown. It is checked whether or not (see) has elapsed, and if it has not elapsed (no in S261), the process immediately exits this process (S174) and continues to display the variation of the special symbols 23A, 23B, and 23C.

  On the other hand, when the variation display of the special symbols 23A, 23B, and 23C is performed over the variation display time set according to the variation pattern (yes in S261), the address of the variation stop table is set (S262). Then, the data storage process (S263) is performed. In these processes (S262, S263), a change stop command for stopping and displaying the special symbols 23A, 23B, and 23C during change display is set in the output buffer of the RAM. Next, the special operation status is set to “3” (S264), and other processing (S265) is performed, and then this processing (S174) is exited.

  As shown in FIG. 12, when the special operation status is “3” in the special operation process (S15) (no in S173, yes in S175), the special symbol confirmation process (S176) is executed. The special symbol confirmation process (S176) is shown in FIG. 20, and it is first checked whether or not the big hit flag is ON (whether or not big hit) (S270).

  If the jackpot flag is not ON (No in S270), that is, if the determination result is “Out”, the special action status is set to “1” (S271), and this special symbol confirmation processing Exit from (S176). On the other hand, if the jackpot flag is ON (Yes in S270), that is, if the determination result is “Win”, the round counter for “Big Jack Game” is set (S272), and the special operation status is set to “ 4 ”(S273) and, for example, the release flag stored in the RAM is switched from OFF to ON (S274), and the process goes out of the special symbol determination process (S176).

  Here, the round counter counts the number of “rounds” in the “big hit game”. In this embodiment, the initial value of the round counter is set to “15”.

  As shown in FIG. 12, in the special action process (S15), when the special action status is “4” (no in S175), that is, when the “big hit game” is being executed, the special electric accessory process ( S177) is performed. The special electric accessory processing (S177) is shown in FIG. 21, and first, the probability variation flag is switched from ON to OFF (S280). That is, when the “big hit game” is started, the probability variation state is forcibly ended.

  Next, it is checked whether or not the jackpot end flag is ON (S281). When the jackpot end flag is not ON (No in S281), that is, when the “hit game” is being executed, it is checked whether or not the jackpot 15 is being opened based on the release flag ( S282).

  When the special winning opening 15 is open (the open flag is ON) (Yes in S282), it is checked whether or not the round end condition is satisfied. Specifically, it is checked whether or not 10 game balls have been won in the grand prize opening 15 (S286) and whether or not the round end time (opening time of the big prize opening 15 is 30 seconds) has been reached (S287). The

  If the round end condition is not satisfied (both S286 and S287 are No), this process (S177) is immediately exited, whereas if the round end condition is satisfied (yes in either S286 or S287). The process at the end of the round (S289 to S293) is performed.

  That is, the excitation of the door drive solenoid 53 is stopped by the special winning opening closing process (S289). Next, after decrementing the round counter by 1 (S290), it is checked whether or not the round counter has become “0” (S291). If the round counter is not “0” (no in S291), that is, If the “big hit game” has not been played up to the maximum round (15 rounds), the process immediately exits (S177). That is, even during the big hit game, when one round is completed, the open / close door 15T is in the “closed position”, and the big prize opening 15 is temporarily closed.

  On the other hand, when the round counter becomes “0” (Yes in S291), that is, when the jackpot game is played up to the maximum round (15 rounds), the jackpot end process (S292) is performed. Then, after the jackpot end flag is turned ON (S293), the process exits (S177).

  In step S282, when the big prize opening 15 is closed (open flag is OFF) (no in S282), it is checked whether or not it is time to open the big prize opening 15 (S283). Specifically, it is checked whether a predetermined waiting period after the “big hit game” is started or whether a predetermined interval period has elapsed since the end of the previous round. When the time has not elapsed (no in S283), the process exits (S177). On the other hand, when the opening waiting period or the interval period elapses (yes in S283), the door is opened by the big prize opening opening process (S285). The drive solenoid 53 is excited. That is, when a predetermined time has elapsed since the start of the “big hit game” or the end of the previous round, the open / close door 15T moves from the “closed position” to the “open position” and the big prize opening 15 is opened.

  In step S281, if the jackpot end flag is ON (yes in S281), that is, if the jackpot game has been played up to the maximum round (15 rounds), the release flag, jackpot end flag, and jackpot flag are all Switching from ON to OFF (S294, S295, S296), it is checked whether or not the special symbols 23A, 23B, and 23C that have been stopped and displayed are probability variation symbols (odd numbers) (S297). If it is not a probability variation symbol (no in S297), the probability variation flag remains OFF. On the other hand, if it is a probability variation symbol (yes in S297), the probability variation flag is switched from OFF to ON (S298) and then the special operation status. Is set to "1" (S299), and the process exits (S177). The above is the description of the special operation process (S15).

  As shown in FIG. 10, in the main control circuit 4 ms timer interrupt process (S5), the reserved memory number process (S16) is performed after the special operation process (S15). This process (S16) is shown in FIG. 22, and the number of reserved storages is read from the number of sets of counter value groups stored in the RAM (S180), and the data of the number of reserved storages is set in the output buffer of the RAM. (S181).

  In the main control circuit 4 ms timer interrupt process (S5), after the reserved ball number process (S16), another process (S17) not deeply related to the present invention is executed, and the main control circuit 4 ms timer interrupt process (S5) is started. Exit. Then, as shown in FIG. 9, until the next interrupt pulse is input to the CPU, the processing of steps S2 to S8 is repeatedly executed, and again due to the input of the interrupt pulse (after about 4 msec), the main control circuit 4 ms again. Timer interrupt processing (S5) is executed. Then, as described above, when the main control circuit 4 ms timer interrupt process (S5) was executed last time, the data set in the output buffer of the RAM is the next executed main control circuit 4 ms timer interrupt process (S5). Is output in the output process (S10).

  Here, the output data (control information) set in the output buffer of the RAM in the main control circuit 50 is as shown in Table 6, and other than those specifically mentioned in the processing by the main control circuit 50 described above. The abnormal winning error data, the payout number data, and the like are also set in the output buffer of the RAM by a predetermined process by the main control circuit 50. These output data (control information) are included in the main control signal and output as follows. In the main control circuit 50, the contents of the RAM output buffer are updated every 4 ms, which is the execution cycle of the main control circuit 4 ms timer interrupt process (S5). In general, only a part of the data group shown in Table 6 is stored in the output buffer of the RAM, and these are included in the main control signal and output.

  The main control signal is a plurality of bits of parallel data transmitted through the parallel signal line B1 shown in FIG. Of the bits constituting the main control signal, the lower plurality of bits are used for transmitting the classification data of the control information, and the upper plurality of bits are used for transmitting the data of the contents of the control information. Further, as an agreement (protocol) between the control circuits 50, 51, 52, a classification code is set for classifying the type of data (game information) to be transmitted included in the main control signal.

  Specifically, for example, when “pending storage number data”, “game probability data”, and “payout number data” (see Table 6) are stored in the output buffer of the RAM, output processing is performed. By performing (S10), the “reserved memory number data” is extracted from the output buffer of the RAM, and the contents of the “reserved memory number data” are assigned to the upper bits of the main control signal, and the “reserved memory number data” Are assigned to the lower 8 bits of the main control signal, the strobe signal is output only to the first sub control circuit 51, and then the main control signal is output. Next, the “game probability data” is taken out, the contents of the “game probability data” are assigned to the upper multiple bits of the main control signal and the classification code is assigned to the lower multiple bits, and again only the first slave control circuit 51 After the strobe signal is output to the main control signal, the main control signal is output. Next, the “payout number data” is taken out, the contents of the “payout number data” are assigned to the upper multiple bits of the main control signal, and the classification code is assigned to the lower multiple bits. This time, only the second sub control circuit 52 is assigned. After outputting the strobe signal, the main control signal is output. As described above, in the output process (S10), the data set in the output buffer of the RAM is taken out one by one and included in the main control signal, and the first sub control circuit 51 or the second sub control circuit 51 is selected according to the content of the data. The operation of selecting and outputting the control circuit 52 is repeated until there is no more data in the output buffer.

  The process for outputting the main control signal may be as follows. That is, the constituent bits of the main control signal are divided into a plurality of data according to the type of data (control information) in the same manner as the data structure of the first sub-control signal (see FIG. 35), which will be described later. A plurality of types of data stored in the buffer may be assigned to predetermined sections and output.

  The above is the description of the configuration of the main control circuit 50. Next, the first slave control circuit 51 will be described. Similar to the main control circuit 50, the first sub control circuit 51 is also provided with a CPU as a one-chip microcomputer packaged with a RAM and a ROM. Then, when the one-chip microcomputer turns on the power of the pachinko gaming machine 10, the first slave control circuit main program PG2 shown in FIG. When the first sub-control circuit main program PG2 is run, initialization (S52) is performed. For example, stack setting, constant setting, CPU setting, SIO, PIO, CTC (interrupt time controller) setting. In addition, various flags and counter values are reset. This initial setting (S52) is executed only when the first sub-control circuit main program PG2 is run for the first time after power-on, and is not executed thereafter. In the initial setting (S52), the size of the sampling constant is set (“10” in this embodiment) and the first sampling constant is set after the power is turned on.

  When the initial setting (S52) is completed, the process of updating the random number seed is repeated infinitely (S53). Then, the strobe interrupt process (S54), the first slave control circuit 2ms timer interrupt process (S55), and the first slave control circuit 10ms timer interrupt process (S56) are interrupted and executed for the infinite loop.

  When the first slave control circuit 51 receives the strobe signal from the main control circuit 50, the strobe interrupt process (S54) is executed with priority over the other interrupt processes (S55, S56). When the strobe interrupt process (S54) is executed, the control information included in the main control signal from the main control circuit 50 is fetched after confirming the input of the strobe signal (Yes in S510), as shown in FIG. Then, it is stored (stored) in the primary storage area of the input signal provided in the storage area of the RAM (S511).

  The first slave control circuit 2 ms timer interrupt process (S55; see FIG. 23) is performed every time an interrupt pulse having a 10 ms cycle is input to the first slave control circuit 51. It is executed with priority over the interrupt process (S56). In this process (S55), as shown in FIG. 25, first, a ramp data output process (S550) is performed, and according to the lamp control data generated in the first slave control circuit 10 ms timer interrupt process (S56) described later. Then, the LED mounted on the illumination board 63 is turned on / off / flashed. In this respect, the first sub control circuit 51 plays the role of a “lamp control circuit”.

  Next, input processing (S551) is performed. In this input process (S551), when the game button 27B (see FIG. 6) connected to the first sub control circuit 51 is operated, the operation signal is captured. Finally, a watchdog timer process (S552) is performed to self-diagnose whether the program is running out of control, and the process exits the first slave control circuit 2ms timer interrupt process (S55).

  The first slave control circuit 10 ms timer interrupt process (S56, see FIG. 23) is executed each time an interrupt pulse with a 10 ms cycle is input to the first slave control circuit 51. In this process (S56), as shown in FIG. 26, first, a data acquisition process (S560) is performed, and an operation signal of the game button 27B captured in the first slave control circuit 2 ms timer interrupt process (S55) is acquired. .

  Next, a lower pan state confirmation process (S561) is performed, and it is checked whether or not the lower pan full data (see Table 6) by the lower pan full switch 27F is included in the control information stored in the input signal primary storage area. If it is included, the warning lamp 39 (see FIG. 1) blinks.

  Next, a loop scenario resetting process (S562) is performed. If no winning is made for a certain period of time, the main control circuit 50 outputs the main control signal including standby state data (see Table 6), so that the liquid crystal display is performed by this loop scenario resetting process (S562). Standby control data to be displayed on the screen 24G is generated. In the situation where the standby state data is output, the main control circuit 50 does not frequently output the main control signal, so the first sub control circuit does not wait for the output process (S566) described later. 51 outputs standby control data to the display control circuit 53. Then, a standby effect image is displayed on the liquid crystal display screen 24G by the display control circuit 53.

  Next, an illumination control data generation process (S563) is performed. In this process, the control information stored in the input signal primary storage area of the RAM is analyzed. If the control data includes presentation data (see Table 6), the lighting control corresponding to the presentation data is performed. Generate data. And based on this electrical decoration control data, LED etc. which were mounted in the electrical decoration board | substrate 63 are made to light and blink (S564).

  Next, Sw processing (S565) is performed, the control information stored in the input signal primary storage area of the RAM is analyzed, and the effective period of operation of the game button 27B is set according to the gaming state. When the game button 27B is operated within the valid period, the operation data of the game button 27B is output to the display control circuit 53 separately from the output process (S566) described later, and the character image or the like is displayed as described above. Stop at any time.

  Output processing (S566) is performed at the end of the first slave control circuit 10 ms timer interrupt processing (S56). When this output process (S566) is performed, as shown in FIG. 27, it is checked whether or not the output timer is “0” (S570). If the output timer is “0” (no in S570), Immediately, the first sub control circuit 10 ms timer interrupt process (S56) is exited. If the output timer is not “0” (Yes in S570), the value of the output timer is decremented by 1 (S571), and it is checked whether the output timer is “0” (S572). If the output timer is not “0” (no in S572), the control information combining process (S575) and signal output (S576) described below are not performed, and the process exits from this output process (S566). On the other hand, if the output timer is “0” (Yes in S572), a predetermined sampling constant (eg, “10”) is set in the output timer (S573).

  Thus, in the first slave control circuit 51, when the output timer becomes “0”, the sampling constant is set in the output timer. Then, every time the output process (S566) is executed with a period of 10 ms, the value is decremented by one. When the output timer becomes “0” again, a sampling constant is set again in the output timer. Repeat the operation. In other words, the output timer is “0” at an interval (cycle) of 100 ms in which the output process (S566) is executed for 10 cycles, and this interval (cycle) corresponds to the “sampling cycle” of the present invention. This interval (period) is referred to as a “first sampling period”. The time when the output timer reaches “100” corresponds to the start point of one cycle of the first sampling period, and the time when the output timer reaches “0” corresponds to the end point of the one cycle. As long as the output timer does not become “0”, that is, during any one period of the first sampling period, the control information combining process (S575) and signal output (S576) described below are not performed. . That is, steps S570 to S572 of the output process (S566) correspond to the “hold means” and the “sampling period generation means” according to the present invention. When the first slave control circuit 51 receives the main control signal a plurality of times during any one of the first sampling periods, the control information of these main control signals is stored in the input signal primary storage area of the RAM. Accumulate.

  When the sampling constant is set in the output timer (S573), it is checked whether or not the first slave control circuit 51 has received the main control signal (S574). If there is no main control signal (no in S574), the process exits the output process (S566). If there is a main control signal (yes in S574), the next control information combining process (S575) is performed.

  The control information combining process (S575) corresponds to the “control signal integration unit” according to the present invention, and is stored in the primary storage area of the input signal of the RAM by the strobe interrupt process (S54) during any one of the first sampling periods. The accumulated control information is combined to generate a first slave control signal. When only one piece of control information is stored in the input signal primary storage area of the RAM, the first sub control signal is generated only from the one piece of control information.

  Specifically, in order to perform this control information combination process (S575), the combined data storage area R100 shown in FIG. 33 is provided in the storage area of the RAM of the first slave control circuit 51, and the combined data storage area R100 is divided into system 1 to system 5. On the other hand, the first slave control signal is 2-byte (16 bits) parallel data transmitted to the parallel signal line B2 shown in FIG. As shown in FIG. 35, the configuration bits D0 to D15 constituting the first slave control signal are divided into a system 1 to a system 5 having a predetermined bit length corresponding to the combined data storage area R100. When the first slave control signal is output in the signal output (S576) to be described later, the data stored in the system 1 to the system 5 of the combined data storage area R100 is changed to the systems 1 to 1 of the first slave control signal. Assigned to the configuration bits D0 to D15 of the system 5 and output.

  Specifically, effect data (see Table 6) for specifying effect contents is stored in the system 1 of the combined data storage area R100. This effect data includes 2-bit classification specifying data (see FIG. 34B) for specifying four major classifications of “none”, “power-on”, “variation pattern”, and “big hit”, Under classification, it consists of, for example, 7-bit effect content specifying data (see FIG. 34A) for specifying the content of effect data. The production content specifying data is assigned to the configuration bits D0 to D6 of the first slave control signal, and the classification specifying data is assigned to the configuration bits D7 and D8 of the first slave control signal.

  In the system 2 of the combined data storage area R100, lower pan full data (see Table 6) is stored. This lower plate full data is composed of 1 bit as shown in FIG. 34 (C), and specifies either “lower plate non-full state” or “lower plate full state”. Are assigned to configuration bit D9.

  Abnormal winning error data (see Table 6) is stored in the system 3 of the combined data storage area R100. This abnormal winning error data is composed of 1 bit as shown in FIG. 34 (D) and specifies whether it is “none” or “abnormal winning error”. In the first sub control signal, Assigned to configuration bit D10.

  In the system 4 of the combined data storage area R100, game state distinguishing data for distinguishing game states is stored. This game state distinction data is composed of 2 bits as shown in FIG. 34 (E), and specifies whether it is “none”, “low probability”, “high probability”, or “short time”. In the control signal, it is assigned to the configuration bits D11 and D12.

  In the system 5 of the combined data storage area R100, reserved ball number data (see Table 6) is stored. This fixed ball number data is composed of 3 bits as shown in FIG. 34 (F), specifies the number of reserved balls, and is assigned to configuration bits D13 to D15 in the first slave control signal.

  In the control information combination process (S575), the control information accumulated in the input signal primary storage area of the RAM in any one of the first sampling periods is ordered from the previously stored control information (old). Take one by one. Then, based on the classification code included in the extracted control information, the control information is classified into any one of the systems 1 to 5, and the control content data included in the control information is stored in each system in the combined data storage area R100. (S580). Next, the control information is deleted from the input signal primary storage area (S581), and the above-described separation and storage processes are repeated until there is no control information accumulated in the input signal primary storage area (yes loop of S580). If control information of the same system is stored in the input signal primary storage area, the combined data storage area R100 is overwritten. That is, when the first sub control circuit 51 receives the main control signal including the control information of the same system during the same first sampling period, only the latest control information is stored in the combined data storage area R100. To store.

  In this way, the output processing (S566) shown in FIG. 27 summarizes the control information included in the main control signal received by the first slave control circuit 51 in a plurality of times, and one first A sub control signal is generated. Then, at the end of the output process (S566), the first slave control signal is output to the display control circuit 53 (S576). The above is the description regarding the first slave control circuit 51.

  Next, the display control circuit 53, the audio control circuit 54, and the payout control circuit 56 will be described. The display control circuit 53 includes a display control CPU, a control data ROM that stores display control data, and an image data ROM that stores image data such as special symbols, background images, character images, and character images. Then, based on the first slave control signal received from the first slave control circuit 51, the display control CPU extracts predetermined display control data from the control data ROM and reads necessary data from the image data ROM. Then, map data such as special symbols, background images, character images, and character images in the display image is created and output to the display device 24. Thereby, according to the state of the game ball, a predetermined image, a warning message, and the number of held balls are appropriately displayed on the liquid crystal display screen 24G. Further, the display control circuit 53 generates sound control data corresponding to the image to be displayed and outputs the sound control data to the sound control circuit 54.

  The audio control circuit 54 receives the audio control data from the display control circuit 53, takes out a predetermined audio signal from an audio data ROM (not shown), converts it into an analog signal, amplifies it, and outputs it to the speaker 13.

  When the payout control circuit 56 receives a second slave control signal from the second slave control circuit 52 to be described below, the payout control circuit 56 performs the rotation of the payout device 33 by the amount of rotation corresponding to the payout number data included in the second slave control signal. The stepping motor 35 is driven to pay out the game balls corresponding to the payout number data. The payout control circuit 56 also drives out the stepping motor 35 to pay out a predetermined number of game balls when receiving a ball rental operation signal by operating the ball rental operation button 27E.

  Next, the second slave control circuit 52 will be described. Similarly to the first slave control circuit 51, the second slave control circuit 52 is also provided as a one-chip microcomputer in which the CPU is packaged together with a RAM and a ROM. When the one-chip microcomputer turns on the power of the pachinko gaming machine 10, the second slave control circuit main program PG3 shown in FIG. Stack setting, constant setting, CPU setting, SIO, PIO, CTC (interrupt time controller) setting, various flags and counter values are reset. This initial setting (S60) is executed only when the second sub-control circuit main program PG3 is run for the first time after power-on, and is not executed thereafter. In the initial setting (S60), the size of the sampling constant is set ("500" in this embodiment) and the first sampling constant is set after the power is turned on.

  When the initial setting (S60) is completed, an infinite loop state is established. The strobe interrupt process (S61) and the second slave control circuit 2ms timer interrupt process (S62) are interrupted and executed for this infinite loop state.

  When the second slave control circuit 52 receives the strobe signal from the main control circuit 50, the strobe interrupt process (S61) is executed with priority over the other interrupt processes (S62). In the strobe interrupt process (S61), as shown in FIG. 30, after confirming the input of the strobe signal (yes in S610), the control information included in the main control signal from the main control circuit 50 is fetched and stored in the RAM. The input signal is stored in a primary storage area provided in the area (S611).

  The second slave control circuit 2 ms timer interrupt process (S62; see FIG. 29) is executed each time an interrupt pulse with a 2 ms period is input. In the second slave control circuit 2 ms timer interrupt process (S62), as shown in FIG. 31, first, an input signal monitoring process (S63) is performed. From the control information stored in the input signal primary storage area of the RAM, Control information such as an abnormal self-diagnosis command other than the payout number data is extracted and processed.

  Next, a payout process (S64) is performed. In this process, as shown in FIG. 32, it is checked whether or not there is a ball lending signal (S641). If there is a ball lending request signal by the operation of the ball lending operation button 27E (yes in S641), a ball lending request is made. After paying out the number of prize balls corresponding to the signal, it is checked whether or not the output timer is not “0” (S643). If there is no ball lending signal (no in S641), the process of step S642 is not performed, and it is checked whether the output timer is not “0” (S643). If the output timer is “0” (no in S643), the payout process (S64) is immediately exited. If the output timer is not “0” (Yes in S643), the value of the output timer is decremented by 1 (S644), and it is checked whether or not the output timer is “0” (S645). If the output timer is not "0" (no in S645), the payout process (S64) is performed without performing the payout number summing process (S649) and signal output (S650, S652) described below. Exit. On the other hand, if the output timer is “0” (Yes in S645), a predetermined sampling constant (eg, “500”) is set in the output timer (S646).

As described above, in the second slave control circuit 52, when the output timer becomes “0”, the sampling constant is set in the output timer. Each time the payout process (S64) is executed at a cycle of 2 ms, it is decremented by one. When the output timer becomes “0” again, a sampling constant is set again in the output timer. Repeat the operation. That is, at intervals of 1000ms the payout process (S64) is executed 500 cycles (cycle), the output timer is "0", below, this interval (period) as "the second sampling period". The time when the output timer reaches “500” corresponds to the start point of one cycle of the second sampling cycle, and the time when the output timer reaches “0” corresponds to the end point of the one cycle. As long as the output timer does not become “0”, that is, during any one period of the second sampling period, the payout number summing process (S649) and signal output (S650, S652) described below are not performed. Become . Their to, during any one cycle of the second sampling period, when the second slave control circuit 52 receives a plurality of times the main control signal, control of their main control signal to the input signal a primary storage area of the RAM Information is accumulated.

  When the sampling constant is set in the output timer (S646), next, the lower plate full switch indicates whether the lower plate portion 27A is full or the supply of the game ball to the dispensing device 33 is not interrupted. A check is made based on the detection signals of 27F and the ball break switch 33F (S647), and further, it is checked whether or not the second sub control circuit 52 has received the main control signal (S648). As shown in FIG. 6, detection signals from the ball lending operation button 27E, the lower pan full switch 27F, and the ball break switch 33F are taken into the second sub control circuit 52 without passing through the main control circuit 50. .

  In the determination of steps S645, S647, and S648, the output timer is 0 (yes in S645), the lower dish portion 27A is not full, and the supply of game balls to the payout device 33 is interrupted. If not (No in S647) and the second slave control circuit 52 is receiving the main control signal (Yes in S648), the input signal primary storage of the RAM is performed in the payout number combination processing (S649). The number-of-payout data accumulated in the area is taken out and the total number (total) of the number of award balls (number of payouts) is calculated. Then, it is checked whether or not the total number is “25” or more (S650), and when the total number is less than “25” (no in S650), the number of payout data for the total number Is generated, and the second slave control signal is output to the payout control circuit 56 (S653).

On the other hand, when the total number is “25” or more (Yes in S650), a second slave control signal including the payout number data for 25 is generated, and the second slave control signal is issued. A value obtained by subtracting “25” from the total number is output to the control circuit 56 as a new total number (S651). Then, it is checked whether or not the new total number is “0” (S652). If “0”, the payout process (S64) is skipped, and if it is not “0”, the process returns to step S650. Repeat the same process. When the payout process (S64) is exited, as shown in FIG. 31, in other processes (S65), for example, backup at the time of a power failure is performed, and the second slave control circuit 2ms timer interrupt process (S62) is exited .

  Here, in the present embodiment, one main control signal including the number-of-payout data for each winning is generated and output for each winning. And, as shown in Table 1, the number of prize balls for each winning is less than 25, 4 or 15, so with regard to the number of payouts (number of prize balls), the number of outputs of the second sub control signal is , The number of outputs of the main control signal can be suppressed below. Even if the main control circuit 50 is configured to add the payout amount data for a plurality of winnings and include it in the main control signal, the main control circuit 4ms timer interrupt process (S5) for generating the main control signal Since one cycle is short at 4 ms, the probability of a plurality of winnings occurring during that 4 ms is low. As a result, with regard to the number of payouts (the number of prize balls), the number of times of output of the second sub control signal is suppressed to be equal to or less than the number of times of output of the main control signal by the main control circuit 50. This completes the description of the second slave control circuit 52.

  This is the end of the description of the configuration of the pachinko gaming machine 10 according to the present embodiment. Next, functions and effects of the pachinko gaming machine 10 will be described.

  When a game is played by operating the operation knob 28 of the pachinko gaming machine 10, the game ball is blown out into the game area R1, and flows down the game area R1 at random. At this time, some game balls pass through the start gate 18 and enter the general winning ports 20, 21 and the starting winning ports 14A, 14B, and the various switches SW1 to SW4 are operated, and their detection signals are used as game information. It is taken into the main control circuit 50. In addition, whether or not the game is won or not is determined for the winning winning openings 14A and 14B, and at this time, a random number (counter value) is generated inside the main control circuit 50 as game information. Thus, when the power of the pachinko gaming machine 10 is turned on, various game information is generated inside and outside the main control circuit 50.

  On the other hand, the main control circuit 50 of the pachinko gaming machine 10 of the present embodiment repeatedly executes the main control circuit 4 ms timer interrupt process (S5) with an execution period of 4 ms, and the main control signal is obtained from randomly generated game information. Is generated and output. Then, the first and second slave control circuits 51 and 52 that have received the master control signal generate the first and second slave control signals and output them to the display control circuit 53 and the payout control circuit 56, Terminal operation parts such as the display device 24, the speaker 13, and the payout device 33 are driven. In this way, the main control circuit 50 controls the entire pachinko gaming machine 10 in an integrated manner.

  Here, for example, if a result of the determination of success or failure becomes a big hit state, or a plurality of abnormalities occur at once, such as the lower plate portion 27A being full or the dispensing device 33 running out of balls, the game information is frequently The main control signal is frequently output from the main control circuit 50. Each time the main control circuit 50 repeatedly executes the main control circuit 4 ms timer interrupt process (S5) with an execution period of 4 ms, a state in which the main control signal is output may occur.

  On the other hand, the first slave control circuit 51 outputs the first slave control signal every first sampling period of 100 ms which is longer than the execution period of 4 ms. At this time, the first sub control circuit 51 accumulates and stores the control information included in the plurality of main control signals received during any one of the first sampling periods in the input signal primary storage area of the RAM. . Then, after the elapse of one cycle, the accumulated control information is integrated into one first sub control signal and output to the display control circuit 53. Thereby, the output frequency of the first slave control signal can be made lower than the output frequency of the main control signal, and the control load for receiving the first slave control signal by the display control circuit 53 can be reduced. Become.

  Specifically, even if main control signals including control information for the main display unit 23X and the hold number display unit 23Z included in the liquid crystal display screen 24G are output at different timings, they are the same in the first sampling period. When it is received by the first sub control circuit 51 during one cycle, it is collected into one sub control signal and output to the display control circuit 53. Thereby, the control load of the display control circuit 53 is reduced.

  Further, when the main control signal for the hold number display unit 23Z is received a plurality of times during the same one cycle of the first sampling period, and the content of the control information included in these main control signals changes (for example, the hold memory number is “ In the case of changing from “4” to “3”), only the latest control information is included in the first slave control signal. As a result, the amount of control information output by the main control circuit 50 included in the main control signal is reduced by the first sub control circuit 51, and the control load on the display control circuit 53 is reduced.

  Now, when a big win game is opened and the big prize opening 15 is opened, and frequent wins occur in a short period of time, a main control signal including information on the number of payouts is frequently output from the main control circuit 50. Here, every time the main control circuit 50 repeatedly executes the main control circuit 4 ms timer interrupt process (S5), even if a main control signal including information on the number of payouts is output, The slave control circuit 52 outputs a second slave control signal every sampling period of 1000 ms. Then, the control information of the number of payouts included in the plurality of main control signals received during any one of the second sampling periods is accumulated and stored in the input signal primary storage area of the RAM, and after the elapse of the one period Then, information on the total number (total) of the accumulated payout number data is included in the second slave control signal and output to the payout control circuit 56. As a result, the output frequency of the second slave control signal can be made smaller than the output frequency of the main control signal, and the amount of control information itself can be reduced, so that the control load of the payout control circuit 56 is reduced. The

  Further, the payout control circuit 56 that has received the second slave control signal drives the stepping motor 35 of the payout device 33 by the amount of rotation corresponding to the payout amount data included in the second slave control signal. Here, in this embodiment, since a fixed upper limit value (25) is set in the payout amount data, the continuous rotation amount of the stepping motor 35 is also limited to a predetermined upper limit value or less. Thereby, the heat generation of the stepping motor 35 is suppressed.

  Thus, according to the pachinko gaming machine 10 of the present embodiment, the control load for receiving the slave control signal is reduced in the terminal control circuits such as the display control circuit 53 and the payout control circuit 56, and the terminal operation unit There is room for motion control. Thereby, it is possible to cope with the case where the gaming machine is highly functional and complicated from the current state. In the present invention, a new sampling constant is set based on the elapse of the sampling period. Therefore, by always setting a sampling constant for a certain period, it is possible to efficiently create a sub-control signal for a plurality of main control signals in a gaming machine that outputs a main control signal without time bias. This is possible, and the output frequency of the slave control signal can be reduced.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various other than the following can be made without departing from the scope of the invention. It can be changed and implemented.

(1) In the above embodiment, the present invention is applied to the pachinko gaming machine 10, but the present invention may be applied to a coin gaming machine, a slot machine, an arrangement ball, and the like.

(2) In the embodiment, the main control signal and the first and second slave control signals are both parallel signals. However, the main control signal and the first and second slave control signals may be serial signals. Good.

(3) In the initial setting process of the first and second slave control circuit main programs PG2 and PG3 described in the above embodiment, the length of the first and second sampling periods may be set. .

Front view of a pachinko gaming machine according to an embodiment of the present invention Rear view of pachinko machine Perspective view of dispensing device Side sectional view of dispensing device (A) Front sectional view of the payout device, (B) Front cross sectional view of a state in which game balls are paid out from the payout device Block diagram showing the electrical configuration of a pachinko machine Block diagram showing details of electrical configuration of pachinko machine RAM storage area conceptual diagram Main control circuit main program flowchart Main control circuit 4 ms timer interrupt processing flowchart Flow chart of start port switch detection processing Flow chart of special operation processing Flow chart of special symbol creation process Flow chart of special symbol waiting process Flow chart of special symbol jackpot determination process Flow chart of special symbol selection process Flow chart of special symbol variation pattern creation processing Flow chart of special symbol random number shift processing Flow chart of special symbol variation processing Flow chart of special symbol confirmation processing Flowchart of special symbol electric accessory processing Flow chart of number of held balls Flowchart of the first sub control circuit main program Strobe interrupt processing flowchart Flowchart of first slave control circuit 2 ms timer interrupt process Flowchart of first slave control circuit 10 ms timer interrupt process Output processing flowchart Flow chart of control information combination processing Flowchart of second slave control circuit main program Strobe interrupt processing flowchart Flowchart of second slave control circuit 2 ms timer interrupt process Flow-out process flowchart Conceptual diagram of combined data storage area (A) Production content specification data, (B) Classification specification data, (C) Bottom plate full data, (D) Abnormal winning error data, (E) Game state distinction data, (F) Reserved ball number data Conceptual diagram of the first slave control signal

Explanation of symbols

10 Pachinko machines 13 Speakers 24 Display device (terminal operation unit)
33 payout equipment 50 main control circuit 51 first slave control circuit 52 the second slave control circuit 53 a display control circuit (terminal control circuit)
54 Voice control circuit (terminal operation unit)
56 payout control circuits PG1 main control circuit main program PG2 first slave control circuit main program PG3 second slave control circuit main program

Claims (3)

  An operable end working part; and
  A main control circuit that repeatedly executes data processing at a predetermined execution cycle, generates a main control signal in the data processing from randomly generated game information, and outputs the main control signal;
  A slave control circuit that receives the master control signal, generates and outputs a slave control signal according to the master control signal;
  In a gaming machine comprising the terminal control circuit that receives the slave control signal and controls the terminal operation unit according to the slave control signal,
  The terminal operation unit is configured to be switchable to a plurality of types of operation states,
  The slave control circuit is configured to generate a sampling period that is set in advance and generates a sampling period longer than an execution period of the data processing;
  Holding means for stopping the output of the sub control signal for the main control signal received during any one of the sampling periods until the end of the one period;
  Only the control information included in the main control signal received last among the main control signals for the data processing multiple cycles received during any one of the sampling cycles is updated to the latest control information, and A gaming machine comprising: a control signal integration means that is included in the slave control signal and is output after the end of one cycle.   Between the main control circuit and the sub control circuit, a signal line for transmitting and receiving the main control signal and a signal line for transmitting and receiving the strobe signal are separately provided,
  The gaming machine according to claim 1, wherein the sub control circuit receives the main control signal on condition that the strobe signal is received from the main control circuit.   The slave control circuit repeatedly executes data processing from power-on, interrupts the data processing based on a predetermined trigger, executes interrupt processing, and the hold means and the control signal by the interrupt processing The gaming machine according to claim 1, wherein an integration unit is configured.

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